Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/us_ticker.c@66:fdb3f9f9a72f, 2016-02-18 (annotated)

Committer:
mbed_official
Date:
Thu Feb 18 09:45:10 2016 +0000
Revision:
66:fdb3f9f9a72f
Parent:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Synchronized with git revision b57f7d56840134d072ca567460a86b77fb7adcf8



Full URL: https://github.com/mbedmicro/mbed/commit/b57f7d56840134d072ca567460a86b77fb7adcf8/



Support of export function to the IAR.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /* mbed Microcontroller Library
bogdanm 0:9b334a45a8ff 2 * Copyright (c) 2006-2013 ARM Limited
bogdanm 0:9b334a45a8ff 3 *
bogdanm 0:9b334a45a8ff 4 * Licensed under the Apache License, Version 2.0 (the "License");
bogdanm 0:9b334a45a8ff 5 * you may not use this file except in compliance with the License.
bogdanm 0:9b334a45a8ff 6 * You may obtain a copy of the License at
bogdanm 0:9b334a45a8ff 7 *
bogdanm 0:9b334a45a8ff 8 * http://www.apache.org/licenses/LICENSE-2.0
bogdanm 0:9b334a45a8ff 9 *
bogdanm 0:9b334a45a8ff 10 * Unless required by applicable law or agreed to in writing, software
bogdanm 0:9b334a45a8ff 11 * distributed under the License is distributed on an "AS IS" BASIS,
bogdanm 0:9b334a45a8ff 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
bogdanm 0:9b334a45a8ff 13 * See the License for the specific language governing permissions and
bogdanm 0:9b334a45a8ff 14 * limitations under the License.
bogdanm 0:9b334a45a8ff 15 */
bogdanm 0:9b334a45a8ff 16 #include <stddef.h>
bogdanm 0:9b334a45a8ff 17 #include "us_ticker_api.h"
bogdanm 0:9b334a45a8ff 18 #include "PeripheralNames.h"
bogdanm 0:9b334a45a8ff 19 #include "ostm_iodefine.h"
bogdanm 0:9b334a45a8ff 20
bogdanm 0:9b334a45a8ff 21 #include "RZ_A1_Init.h"
bogdanm 0:9b334a45a8ff 22 #include "MBRZA1H.h"
bogdanm 0:9b334a45a8ff 23
bogdanm 0:9b334a45a8ff 24 #define US_TICKER_TIMER_IRQn (OSTMI1TINT_IRQn)
bogdanm 0:9b334a45a8ff 25 #define CPG_STBCR5_BIT_MSTP50 (0x01u) /* OSTM1 */
bogdanm 0:9b334a45a8ff 26
bogdanm 0:9b334a45a8ff 27 #define US_TICKER_CLOCK_US_DEV (1000000)
bogdanm 0:9b334a45a8ff 28
bogdanm 0:9b334a45a8ff 29 int us_ticker_inited = 0;
bogdanm 0:9b334a45a8ff 30 static double count_clock = 0;
bogdanm 0:9b334a45a8ff 31 static uint32_t last_read = 0;
bogdanm 0:9b334a45a8ff 32 static uint32_t wrap_arround = 0;
bogdanm 0:9b334a45a8ff 33 static uint64_t ticker_us_last64 = 0;
bogdanm 0:9b334a45a8ff 34
bogdanm 0:9b334a45a8ff 35 void us_ticker_interrupt(void) {
bogdanm 0:9b334a45a8ff 36 us_ticker_irq_handler();
bogdanm 0:9b334a45a8ff 37 }
bogdanm 0:9b334a45a8ff 38
bogdanm 0:9b334a45a8ff 39 void us_ticker_init(void) {
bogdanm 0:9b334a45a8ff 40 if (us_ticker_inited) return;
bogdanm 0:9b334a45a8ff 41 us_ticker_inited = 1;
bogdanm 0:9b334a45a8ff 42
bogdanm 0:9b334a45a8ff 43 /* set Counter Clock(us) */
bogdanm 0:9b334a45a8ff 44 if (false == RZ_A1_IsClockMode0()) {
bogdanm 0:9b334a45a8ff 45 count_clock = ((double)CM1_RENESAS_RZ_A1_P0_CLK / (double)US_TICKER_CLOCK_US_DEV);
bogdanm 0:9b334a45a8ff 46 } else {
bogdanm 0:9b334a45a8ff 47 count_clock = ((double)CM0_RENESAS_RZ_A1_P0_CLK / (double)US_TICKER_CLOCK_US_DEV);
bogdanm 0:9b334a45a8ff 48 }
bogdanm 0:9b334a45a8ff 49
bogdanm 0:9b334a45a8ff 50 /* Power Control for Peripherals */
bogdanm 0:9b334a45a8ff 51 CPGSTBCR5 &= ~(CPG_STBCR5_BIT_MSTP50); /* enable OSTM1 clock */
bogdanm 0:9b334a45a8ff 52
bogdanm 0:9b334a45a8ff 53 // timer settings
bogdanm 0:9b334a45a8ff 54 OSTM1TT = 0x01; /* Stop the counter and clears the OSTM1TE bit. */
bogdanm 0:9b334a45a8ff 55 OSTM1CTL = 0x02; /* Free running timer mode. Interrupt disabled when star counter */
bogdanm 0:9b334a45a8ff 56
bogdanm 0:9b334a45a8ff 57 OSTM1TS = 0x1; /* Start the counter and sets the OSTM0TE bit. */
bogdanm 0:9b334a45a8ff 58
bogdanm 0:9b334a45a8ff 59 // INTC settings
bogdanm 0:9b334a45a8ff 60 InterruptHandlerRegister(US_TICKER_TIMER_IRQn, (void (*)(uint32_t))us_ticker_interrupt);
bogdanm 0:9b334a45a8ff 61 GIC_SetPriority(US_TICKER_TIMER_IRQn, 5);
bogdanm 0:9b334a45a8ff 62 GIC_EnableIRQ(US_TICKER_TIMER_IRQn);
bogdanm 0:9b334a45a8ff 63 }
bogdanm 0:9b334a45a8ff 64
bogdanm 0:9b334a45a8ff 65 static uint64_t ticker_read_counter64(void) {
bogdanm 0:9b334a45a8ff 66 uint32_t cnt_val;
bogdanm 0:9b334a45a8ff 67 uint64_t cnt_val64;
bogdanm 0:9b334a45a8ff 68
bogdanm 0:9b334a45a8ff 69 if (!us_ticker_inited)
bogdanm 0:9b334a45a8ff 70 us_ticker_init();
bogdanm 0:9b334a45a8ff 71
bogdanm 0:9b334a45a8ff 72 /* read counter */
bogdanm 0:9b334a45a8ff 73 cnt_val = OSTM1CNT;
bogdanm 0:9b334a45a8ff 74 if (last_read > cnt_val) {
bogdanm 0:9b334a45a8ff 75 wrap_arround++;
bogdanm 0:9b334a45a8ff 76 }
bogdanm 0:9b334a45a8ff 77 last_read = cnt_val;
bogdanm 0:9b334a45a8ff 78 cnt_val64 = ((uint64_t)wrap_arround << 32) + cnt_val;
bogdanm 0:9b334a45a8ff 79
bogdanm 0:9b334a45a8ff 80 return cnt_val64;
bogdanm 0:9b334a45a8ff 81 }
bogdanm 0:9b334a45a8ff 82
bogdanm 0:9b334a45a8ff 83 uint32_t us_ticker_read() {
bogdanm 0:9b334a45a8ff 84 uint64_t cnt_val64;
bogdanm 0:9b334a45a8ff 85 uint64_t us_val64;
bogdanm 0:9b334a45a8ff 86 int check_irq_masked;
bogdanm 0:9b334a45a8ff 87
mbed_official 66:fdb3f9f9a72f 88 #if defined ( __ICCARM__)
mbed_official 66:fdb3f9f9a72f 89 check_irq_masked = __disable_irq_iar();
mbed_official 66:fdb3f9f9a72f 90 #else
bogdanm 0:9b334a45a8ff 91 check_irq_masked = __disable_irq();
mbed_official 66:fdb3f9f9a72f 92 #endif /* __ICCARM__ */
bogdanm 0:9b334a45a8ff 93
bogdanm 0:9b334a45a8ff 94 cnt_val64 = ticker_read_counter64();
bogdanm 0:9b334a45a8ff 95 us_val64 = (cnt_val64 / count_clock);
bogdanm 0:9b334a45a8ff 96 ticker_us_last64 = us_val64;
bogdanm 0:9b334a45a8ff 97
bogdanm 0:9b334a45a8ff 98 if (!check_irq_masked) {
bogdanm 0:9b334a45a8ff 99 __enable_irq();
bogdanm 0:9b334a45a8ff 100 }
bogdanm 0:9b334a45a8ff 101
bogdanm 0:9b334a45a8ff 102 /* clock to us */
bogdanm 0:9b334a45a8ff 103 return (uint32_t)us_val64;
bogdanm 0:9b334a45a8ff 104 }
bogdanm 0:9b334a45a8ff 105
bogdanm 0:9b334a45a8ff 106 void us_ticker_set_interrupt(timestamp_t timestamp) {
bogdanm 0:9b334a45a8ff 107 // set match value
bogdanm 0:9b334a45a8ff 108 uint64_t timestamp64;
bogdanm 0:9b334a45a8ff 109 uint64_t set_cmp_val64;
bogdanm 0:9b334a45a8ff 110 volatile uint32_t set_cmp_val;
bogdanm 0:9b334a45a8ff 111 uint64_t count_val_64;
bogdanm 0:9b334a45a8ff 112
bogdanm 0:9b334a45a8ff 113 /* calc compare mach timestamp */
bogdanm 0:9b334a45a8ff 114 timestamp64 = (ticker_us_last64 & 0xFFFFFFFF00000000) + timestamp;
bogdanm 0:9b334a45a8ff 115 if (timestamp < (ticker_us_last64 & 0x00000000FFFFFFFF)) {
bogdanm 0:9b334a45a8ff 116 /* This event is wrap arround */
bogdanm 0:9b334a45a8ff 117 timestamp64 += 0x100000000;
bogdanm 0:9b334a45a8ff 118 }
bogdanm 0:9b334a45a8ff 119
bogdanm 0:9b334a45a8ff 120 /* calc compare mach timestamp */
bogdanm 0:9b334a45a8ff 121 set_cmp_val64 = timestamp64 * count_clock;
bogdanm 0:9b334a45a8ff 122 set_cmp_val = (uint32_t)(set_cmp_val64 & 0x00000000FFFFFFFF);
bogdanm 0:9b334a45a8ff 123 count_val_64 = ticker_read_counter64();
bogdanm 0:9b334a45a8ff 124 if (set_cmp_val64 <= (count_val_64 + 500)) {
bogdanm 0:9b334a45a8ff 125 GIC_SetPendingIRQ(US_TICKER_TIMER_IRQn);
bogdanm 0:9b334a45a8ff 126 GIC_EnableIRQ(US_TICKER_TIMER_IRQn);
bogdanm 0:9b334a45a8ff 127 return;
bogdanm 0:9b334a45a8ff 128 }
bogdanm 0:9b334a45a8ff 129 OSTM1CMP = set_cmp_val;
bogdanm 0:9b334a45a8ff 130 GIC_EnableIRQ(US_TICKER_TIMER_IRQn);
bogdanm 0:9b334a45a8ff 131 }
bogdanm 0:9b334a45a8ff 132
bogdanm 0:9b334a45a8ff 133 void us_ticker_disable_interrupt(void) {
bogdanm 0:9b334a45a8ff 134 GIC_DisableIRQ(US_TICKER_TIMER_IRQn);
bogdanm 0:9b334a45a8ff 135 }
bogdanm 0:9b334a45a8ff 136
bogdanm 0:9b334a45a8ff 137 void us_ticker_clear_interrupt(void) {
bogdanm 0:9b334a45a8ff 138 GIC_ClearPendingIRQ(US_TICKER_TIMER_IRQn);
bogdanm 0:9b334a45a8ff 139 }