Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rtc.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
50:a417edff4437 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 2 * @file em_rtc.c
<> 144:ef7eb2e8f9f7 3 * @brief Real Time Counter (RTC) Peripheral API
<> 144:ef7eb2e8f9f7 4 * @version 4.2.1
<> 144:ef7eb2e8f9f7 5 *******************************************************************************
<> 144:ef7eb2e8f9f7 6 * @section License
<> 144:ef7eb2e8f9f7 7 * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
<> 144:ef7eb2e8f9f7 8 *******************************************************************************
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Permission is granted to anyone to use this software for any purpose,
<> 144:ef7eb2e8f9f7 11 * including commercial applications, and to alter it and redistribute it
<> 144:ef7eb2e8f9f7 12 * freely, subject to the following restrictions:
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * 1. The origin of this software must not be misrepresented; you must not
<> 144:ef7eb2e8f9f7 15 * claim that you wrote the original software.
<> 144:ef7eb2e8f9f7 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 144:ef7eb2e8f9f7 17 * misrepresented as being the original software.
<> 144:ef7eb2e8f9f7 18 * 3. This notice may not be removed or altered from any source distribution.
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
<> 144:ef7eb2e8f9f7 21 * obligation to support this Software. Silicon Labs is providing the
<> 144:ef7eb2e8f9f7 22 * Software "AS IS", with no express or implied warranties of any kind,
<> 144:ef7eb2e8f9f7 23 * including, but not limited to, any implied warranties of merchantability
<> 144:ef7eb2e8f9f7 24 * or fitness for any particular purpose or warranties against infringement
<> 144:ef7eb2e8f9f7 25 * of any proprietary rights of a third party.
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * Silicon Labs will not be liable for any consequential, incidental, or
<> 144:ef7eb2e8f9f7 28 * special damages, or any other relief, or for any claim by any third party,
<> 144:ef7eb2e8f9f7 29 * arising from your use of this Software.
<> 144:ef7eb2e8f9f7 30 *
<> 144:ef7eb2e8f9f7 31 ******************************************************************************/
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 #include "em_rtc.h"
<> 144:ef7eb2e8f9f7 34 #if defined(RTC_COUNT) && (RTC_COUNT > 0)
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 #include "em_assert.h"
<> 144:ef7eb2e8f9f7 37 #include "em_bus.h"
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 40 * @addtogroup EM_Library
<> 144:ef7eb2e8f9f7 41 * @{
<> 144:ef7eb2e8f9f7 42 ******************************************************************************/
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 45 * @addtogroup RTC
<> 144:ef7eb2e8f9f7 46 * @brief Real Time Counter (RTC) Peripheral API
<> 144:ef7eb2e8f9f7 47 * @{
<> 144:ef7eb2e8f9f7 48 ******************************************************************************/
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 /*******************************************************************************
<> 144:ef7eb2e8f9f7 51 ******************************* DEFINES ***********************************
<> 144:ef7eb2e8f9f7 52 ******************************************************************************/
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 /** Validation of valid comparator register for assert statements. */
<> 144:ef7eb2e8f9f7 57 #define RTC_COMP_REG_VALID(reg) (((reg) <= 1))
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /** @endcond */
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /*******************************************************************************
<> 144:ef7eb2e8f9f7 63 ************************** LOCAL FUNCTIONS ********************************
<> 144:ef7eb2e8f9f7 64 ******************************************************************************/
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 #if defined(_EFM32_GECKO_FAMILY)
<> 144:ef7eb2e8f9f7 69 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 70 * @brief
<> 144:ef7eb2e8f9f7 71 * Wait for ongoing sync of register(s) to low frequency domain to complete.
<> 144:ef7eb2e8f9f7 72 *
<> 144:ef7eb2e8f9f7 73 * @note
<> 144:ef7eb2e8f9f7 74 * This only applies to the Gecko Family, see the reference manual
<> 144:ef7eb2e8f9f7 75 * chapter about Access to Low Energy Peripherals (Asynchronos Registers)
<> 144:ef7eb2e8f9f7 76 * for details. For Tiny Gecko and Giant Gecko, the RTC supports immediate
<> 144:ef7eb2e8f9f7 77 * updates of registers, and will automatically hold the bus until the
<> 144:ef7eb2e8f9f7 78 * register has been updated.
<> 144:ef7eb2e8f9f7 79 *
<> 144:ef7eb2e8f9f7 80 * @param[in] mask
<> 144:ef7eb2e8f9f7 81 * Bitmask corresponding to SYNCBUSY register defined bits, indicating
<> 144:ef7eb2e8f9f7 82 * registers that must complete any ongoing synchronization.
<> 144:ef7eb2e8f9f7 83 ******************************************************************************/
<> 144:ef7eb2e8f9f7 84 __STATIC_INLINE void regSync(uint32_t mask)
<> 144:ef7eb2e8f9f7 85 {
<> 144:ef7eb2e8f9f7 86 /* Avoid deadlock if modifying the same register twice when freeze mode is */
<> 144:ef7eb2e8f9f7 87 /* activated. */
<> 144:ef7eb2e8f9f7 88 if (RTC->FREEZE & RTC_FREEZE_REGFREEZE)
<> 144:ef7eb2e8f9f7 89 return;
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 /* Wait for any pending previous write operation to have been completed */
<> 144:ef7eb2e8f9f7 92 /* in low frequency domain. This is only required for the Gecko Family */
<> 144:ef7eb2e8f9f7 93 while (RTC->SYNCBUSY & mask)
<> 144:ef7eb2e8f9f7 94 ;
<> 144:ef7eb2e8f9f7 95 }
<> 144:ef7eb2e8f9f7 96 #endif
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 /** @endcond */
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 /*******************************************************************************
<> 144:ef7eb2e8f9f7 101 ************************** GLOBAL FUNCTIONS *******************************
<> 144:ef7eb2e8f9f7 102 ******************************************************************************/
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 105 * @brief
<> 144:ef7eb2e8f9f7 106 * Get RTC compare register value.
<> 144:ef7eb2e8f9f7 107 *
<> 144:ef7eb2e8f9f7 108 * @param[in] comp
<> 144:ef7eb2e8f9f7 109 * Compare register to get, either 0 or 1
<> 144:ef7eb2e8f9f7 110 *
<> 144:ef7eb2e8f9f7 111 * @return
<> 144:ef7eb2e8f9f7 112 * Compare register value, 0 if invalid register selected.
<> 144:ef7eb2e8f9f7 113 ******************************************************************************/
<> 144:ef7eb2e8f9f7 114 uint32_t RTC_CompareGet(unsigned int comp)
<> 144:ef7eb2e8f9f7 115 {
<> 144:ef7eb2e8f9f7 116 uint32_t ret;
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 EFM_ASSERT(RTC_COMP_REG_VALID(comp));
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 /* Initialize selected compare value */
<> 144:ef7eb2e8f9f7 121 switch (comp)
<> 144:ef7eb2e8f9f7 122 {
<> 144:ef7eb2e8f9f7 123 case 0:
<> 144:ef7eb2e8f9f7 124 ret = RTC->COMP0;
<> 144:ef7eb2e8f9f7 125 break;
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 case 1:
<> 144:ef7eb2e8f9f7 128 ret = RTC->COMP1;
<> 144:ef7eb2e8f9f7 129 break;
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 default:
<> 144:ef7eb2e8f9f7 132 /* Unknown compare register selected */
<> 144:ef7eb2e8f9f7 133 ret = 0;
<> 144:ef7eb2e8f9f7 134 break;
<> 144:ef7eb2e8f9f7 135 }
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 return ret;
<> 144:ef7eb2e8f9f7 138 }
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 142 * @brief
<> 144:ef7eb2e8f9f7 143 * Set RTC compare register value.
<> 144:ef7eb2e8f9f7 144 *
<> 144:ef7eb2e8f9f7 145 * @note
<> 144:ef7eb2e8f9f7 146 * The setting of a compare register requires synchronization into the
<> 144:ef7eb2e8f9f7 147 * low frequency domain. If the same register is modified before a previous
<> 144:ef7eb2e8f9f7 148 * update has completed, this function will stall until the previous
<> 144:ef7eb2e8f9f7 149 * synchronization has completed. This only applies to the Gecko Family, see
<> 144:ef7eb2e8f9f7 150 * comment in the regSync() internal function call.
<> 144:ef7eb2e8f9f7 151 *
<> 144:ef7eb2e8f9f7 152 * @param[in] comp
<> 144:ef7eb2e8f9f7 153 * Compare register to set, either 0 or 1
<> 144:ef7eb2e8f9f7 154 *
<> 144:ef7eb2e8f9f7 155 * @param[in] value
<> 144:ef7eb2e8f9f7 156 * Initialization value (<= 0x00ffffff)
<> 144:ef7eb2e8f9f7 157 ******************************************************************************/
<> 144:ef7eb2e8f9f7 158 void RTC_CompareSet(unsigned int comp, uint32_t value)
<> 144:ef7eb2e8f9f7 159 {
<> 144:ef7eb2e8f9f7 160 volatile uint32_t *compReg;
<> 144:ef7eb2e8f9f7 161 #if defined(_EFM32_GECKO_FAMILY)
<> 144:ef7eb2e8f9f7 162 uint32_t syncbusy;
<> 144:ef7eb2e8f9f7 163 #endif
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 EFM_ASSERT(RTC_COMP_REG_VALID(comp)
<> 144:ef7eb2e8f9f7 166 && ((value & ~(_RTC_COMP0_COMP0_MASK
<> 144:ef7eb2e8f9f7 167 >> _RTC_COMP0_COMP0_SHIFT)) == 0));
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 /* Initialize selected compare value */
<> 144:ef7eb2e8f9f7 170 switch (comp)
<> 144:ef7eb2e8f9f7 171 {
<> 144:ef7eb2e8f9f7 172 case 0:
<> 144:ef7eb2e8f9f7 173 compReg = &(RTC->COMP0);
<> 144:ef7eb2e8f9f7 174 #if defined(_EFM32_GECKO_FAMILY)
<> 144:ef7eb2e8f9f7 175 syncbusy = RTC_SYNCBUSY_COMP0;
<> 144:ef7eb2e8f9f7 176 #endif
<> 144:ef7eb2e8f9f7 177 break;
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 case 1:
<> 144:ef7eb2e8f9f7 180 compReg = &(RTC->COMP1);
<> 144:ef7eb2e8f9f7 181 #if defined(_EFM32_GECKO_FAMILY)
<> 144:ef7eb2e8f9f7 182 syncbusy = RTC_SYNCBUSY_COMP1;
<> 144:ef7eb2e8f9f7 183 #endif
<> 144:ef7eb2e8f9f7 184 break;
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 default:
<> 144:ef7eb2e8f9f7 187 /* Unknown compare register selected, abort */
<> 144:ef7eb2e8f9f7 188 return;
<> 144:ef7eb2e8f9f7 189 }
<> 144:ef7eb2e8f9f7 190 #if defined(_EFM32_GECKO_FAMILY)
<> 144:ef7eb2e8f9f7 191 /* LF register about to be modified require sync. busy check */
<> 144:ef7eb2e8f9f7 192 regSync(syncbusy);
<> 144:ef7eb2e8f9f7 193 #endif
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 *compReg = value;
<> 144:ef7eb2e8f9f7 196 }
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 200 * @brief
<> 144:ef7eb2e8f9f7 201 * Enable/disable RTC.
<> 144:ef7eb2e8f9f7 202 *
<> 144:ef7eb2e8f9f7 203 * @note
<> 144:ef7eb2e8f9f7 204 * The enabling/disabling of the RTC modifies the RTC CTRL register which
<> 144:ef7eb2e8f9f7 205 * requires synchronization into the low frequency domain. If this register is
<> 144:ef7eb2e8f9f7 206 * modified before a previous update to the same register has completed, this
<> 144:ef7eb2e8f9f7 207 * function will stall until the previous synchronization has completed. This
<> 144:ef7eb2e8f9f7 208 * only applies to the Gecko Family, see comment in the regSync() internal
<> 144:ef7eb2e8f9f7 209 * function call.
<> 144:ef7eb2e8f9f7 210 *
<> 144:ef7eb2e8f9f7 211 * @param[in] enable
<> 144:ef7eb2e8f9f7 212 * true to enable counting, false to disable.
<> 144:ef7eb2e8f9f7 213 ******************************************************************************/
<> 144:ef7eb2e8f9f7 214 void RTC_Enable(bool enable)
<> 144:ef7eb2e8f9f7 215 {
<> 144:ef7eb2e8f9f7 216 #if defined(_EFM32_GECKO_FAMILY)
<> 144:ef7eb2e8f9f7 217 /* LF register about to be modified require sync. busy check */
<> 144:ef7eb2e8f9f7 218 regSync(RTC_SYNCBUSY_CTRL);
<> 144:ef7eb2e8f9f7 219 #endif
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 BUS_RegBitWrite(&(RTC->CTRL), _RTC_CTRL_EN_SHIFT, enable);
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 #if defined(_EFM32_GECKO_FAMILY)
<> 144:ef7eb2e8f9f7 224 /* Wait for CTRL to be updated before returning, because calling code may
<> 144:ef7eb2e8f9f7 225 depend upon that the CTRL register is updated after this function has
<> 144:ef7eb2e8f9f7 226 returned. */
<> 144:ef7eb2e8f9f7 227 regSync(RTC_SYNCBUSY_CTRL);
<> 144:ef7eb2e8f9f7 228 #endif
<> 144:ef7eb2e8f9f7 229 }
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 233 * @brief
<> 144:ef7eb2e8f9f7 234 * RTC register synchronization freeze control.
<> 144:ef7eb2e8f9f7 235 *
<> 144:ef7eb2e8f9f7 236 * @details
<> 144:ef7eb2e8f9f7 237 * Some RTC registers require synchronization into the low frequency (LF)
<> 144:ef7eb2e8f9f7 238 * domain. The freeze feature allows for several such registers to be
<> 144:ef7eb2e8f9f7 239 * modified before passing them to the LF domain simultaneously (which
<> 144:ef7eb2e8f9f7 240 * takes place when the freeze mode is disabled).
<> 144:ef7eb2e8f9f7 241 *
<> 144:ef7eb2e8f9f7 242 * @note
<> 144:ef7eb2e8f9f7 243 * When enabling freeze mode, this function will wait for all current
<> 144:ef7eb2e8f9f7 244 * ongoing RTC synchronization to LF domain to complete (Normally
<> 144:ef7eb2e8f9f7 245 * synchronization will not be in progress.) However for this reason, when
<> 144:ef7eb2e8f9f7 246 * using freeze mode, modifications of registers requiring LF synchronization
<> 144:ef7eb2e8f9f7 247 * should be done within one freeze enable/disable block to avoid unecessary
<> 144:ef7eb2e8f9f7 248 * stalling. This only applies to the Gecko Family, see the reference manual
<> 144:ef7eb2e8f9f7 249 * chapter about Access to Low Energy Peripherals (Asynchronos Registers)
<> 144:ef7eb2e8f9f7 250 * for details.
<> 144:ef7eb2e8f9f7 251 *
<> 144:ef7eb2e8f9f7 252 * @param[in] enable
<> 144:ef7eb2e8f9f7 253 * @li true - enable freeze, modified registers are not propagated to the
<> 144:ef7eb2e8f9f7 254 * LF domain
<> 144:ef7eb2e8f9f7 255 * @li false - disables freeze, modified registers are propagated to LF
<> 144:ef7eb2e8f9f7 256 * domain
<> 144:ef7eb2e8f9f7 257 ******************************************************************************/
<> 144:ef7eb2e8f9f7 258 void RTC_FreezeEnable(bool enable)
<> 144:ef7eb2e8f9f7 259 {
<> 144:ef7eb2e8f9f7 260 if (enable)
<> 144:ef7eb2e8f9f7 261 {
<> 144:ef7eb2e8f9f7 262 #if defined(_EFM32_GECKO_FAMILY)
<> 144:ef7eb2e8f9f7 263 /* Wait for any ongoing LF synchronization to complete. This is just to */
<> 144:ef7eb2e8f9f7 264 /* protect against the rare case when a user */
<> 144:ef7eb2e8f9f7 265 /* - modifies a register requiring LF sync */
<> 144:ef7eb2e8f9f7 266 /* - then enables freeze before LF sync completed */
<> 144:ef7eb2e8f9f7 267 /* - then modifies the same register again */
<> 144:ef7eb2e8f9f7 268 /* since modifying a register while it is in sync progress should be */
<> 144:ef7eb2e8f9f7 269 /* avoided. */
<> 144:ef7eb2e8f9f7 270 while (RTC->SYNCBUSY)
<> 144:ef7eb2e8f9f7 271 ;
<> 144:ef7eb2e8f9f7 272 #endif
<> 144:ef7eb2e8f9f7 273 RTC->FREEZE = RTC_FREEZE_REGFREEZE;
<> 144:ef7eb2e8f9f7 274 }
<> 144:ef7eb2e8f9f7 275 else
<> 144:ef7eb2e8f9f7 276 {
<> 144:ef7eb2e8f9f7 277 RTC->FREEZE = 0;
<> 144:ef7eb2e8f9f7 278 }
<> 144:ef7eb2e8f9f7 279 }
<> 144:ef7eb2e8f9f7 280
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 283 * @brief
<> 144:ef7eb2e8f9f7 284 * Initialize RTC.
<> 144:ef7eb2e8f9f7 285 *
<> 144:ef7eb2e8f9f7 286 * @details
<> 144:ef7eb2e8f9f7 287 * Note that the compare values must be set separately with RTC_CompareSet().
<> 144:ef7eb2e8f9f7 288 * That should probably be done prior to the use of this function if
<> 144:ef7eb2e8f9f7 289 * configuring the RTC to start when initialization is completed.
<> 144:ef7eb2e8f9f7 290 *
<> 144:ef7eb2e8f9f7 291 * @note
<> 144:ef7eb2e8f9f7 292 * The initialization of the RTC modifies the RTC CTRL register which requires
<> 144:ef7eb2e8f9f7 293 * synchronization into the low frequency domain. If this register is
<> 144:ef7eb2e8f9f7 294 * modified before a previous update to the same register has completed, this
<> 144:ef7eb2e8f9f7 295 * function will stall until the previous synchronization has completed. This
<> 144:ef7eb2e8f9f7 296 * only applies to the Gecko Family, see comment in the regSync() internal
<> 144:ef7eb2e8f9f7 297 * function call.
<> 144:ef7eb2e8f9f7 298 *
<> 144:ef7eb2e8f9f7 299 * @param[in] init
<> 144:ef7eb2e8f9f7 300 * Pointer to RTC initialization structure.
<> 144:ef7eb2e8f9f7 301 ******************************************************************************/
<> 144:ef7eb2e8f9f7 302 void RTC_Init(const RTC_Init_TypeDef *init)
<> 144:ef7eb2e8f9f7 303 {
<> 144:ef7eb2e8f9f7 304 uint32_t tmp;
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306 if (init->enable)
<> 144:ef7eb2e8f9f7 307 {
<> 144:ef7eb2e8f9f7 308 tmp = RTC_CTRL_EN;
<> 144:ef7eb2e8f9f7 309 }
<> 144:ef7eb2e8f9f7 310 else
<> 144:ef7eb2e8f9f7 311 {
<> 144:ef7eb2e8f9f7 312 tmp = 0;
<> 144:ef7eb2e8f9f7 313 }
<> 144:ef7eb2e8f9f7 314
<> 144:ef7eb2e8f9f7 315 /* Configure DEBUGRUN flag, sets whether or not counter should be
<> 144:ef7eb2e8f9f7 316 * updated when debugger is active */
<> 144:ef7eb2e8f9f7 317 if (init->debugRun)
<> 144:ef7eb2e8f9f7 318 {
<> 144:ef7eb2e8f9f7 319 tmp |= RTC_CTRL_DEBUGRUN;
<> 144:ef7eb2e8f9f7 320 }
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 /* Configure COMP0TOP, this will use the COMP0 compare value as an
<> 144:ef7eb2e8f9f7 323 * overflow value, instead of default 24-bit 0x00ffffff */
<> 144:ef7eb2e8f9f7 324 if (init->comp0Top)
<> 144:ef7eb2e8f9f7 325 {
<> 144:ef7eb2e8f9f7 326 tmp |= RTC_CTRL_COMP0TOP;
<> 144:ef7eb2e8f9f7 327 }
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 #if defined(_EFM32_GECKO_FAMILY)
<> 144:ef7eb2e8f9f7 330 /* LF register about to be modified require sync. busy check */
<> 144:ef7eb2e8f9f7 331 regSync(RTC_SYNCBUSY_CTRL);
<> 144:ef7eb2e8f9f7 332 #endif
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 RTC->CTRL = tmp;
<> 144:ef7eb2e8f9f7 335 }
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 340 * @brief
<> 144:ef7eb2e8f9f7 341 * Restore RTC to reset state
<> 144:ef7eb2e8f9f7 342 ******************************************************************************/
<> 144:ef7eb2e8f9f7 343 void RTC_Reset(void)
<> 144:ef7eb2e8f9f7 344 {
<> 144:ef7eb2e8f9f7 345 /* Restore all essential RTC register to default config */
<> 144:ef7eb2e8f9f7 346 RTC->FREEZE = _RTC_FREEZE_RESETVALUE;
<> 144:ef7eb2e8f9f7 347 RTC->CTRL = _RTC_CTRL_RESETVALUE;
<> 144:ef7eb2e8f9f7 348 RTC->COMP0 = _RTC_COMP0_RESETVALUE;
<> 144:ef7eb2e8f9f7 349 RTC->COMP1 = _RTC_COMP1_RESETVALUE;
<> 144:ef7eb2e8f9f7 350 RTC->IEN = _RTC_IEN_RESETVALUE;
<> 144:ef7eb2e8f9f7 351 RTC->IFC = _RTC_IFC_RESETVALUE;
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 #if defined(_EFM32_GECKO_FAMILY)
<> 144:ef7eb2e8f9f7 354 /* Wait for CTRL, COMP0 and COMP1 to be updated before returning, because the
<> 144:ef7eb2e8f9f7 355 calling code may depend upon that the register values are updated after
<> 144:ef7eb2e8f9f7 356 this function has returned. */
<> 144:ef7eb2e8f9f7 357 regSync(RTC_SYNCBUSY_CTRL | RTC_SYNCBUSY_COMP0 | RTC_SYNCBUSY_COMP1);
<> 144:ef7eb2e8f9f7 358 #endif
<> 144:ef7eb2e8f9f7 359 }
<> 144:ef7eb2e8f9f7 360
<> 144:ef7eb2e8f9f7 361
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 364 * @brief
<> 144:ef7eb2e8f9f7 365 * Restart RTC counter from zero
<> 144:ef7eb2e8f9f7 366 ******************************************************************************/
<> 144:ef7eb2e8f9f7 367 void RTC_CounterReset(void)
<> 144:ef7eb2e8f9f7 368 {
<> 144:ef7eb2e8f9f7 369 /* A disable/enable sequnce will start the counter at zero */
<> 144:ef7eb2e8f9f7 370 RTC_Enable(false);
<> 144:ef7eb2e8f9f7 371 RTC_Enable(true);
<> 144:ef7eb2e8f9f7 372 }
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 /** @} (end addtogroup RTC) */
<> 144:ef7eb2e8f9f7 376 /** @} (end addtogroup EM_Library) */
<> 144:ef7eb2e8f9f7 377 #endif /* defined(RTC_COUNT) && (RTC_COUNT > 0) */