Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dac.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
50:a417edff4437 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 2 * @file em_dac.c
<> 144:ef7eb2e8f9f7 3 * @brief Digital to Analog Coversion (DAC) Peripheral API
<> 144:ef7eb2e8f9f7 4 * @version 4.2.1
<> 144:ef7eb2e8f9f7 5 *******************************************************************************
<> 144:ef7eb2e8f9f7 6 * @section License
<> 144:ef7eb2e8f9f7 7 * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
<> 144:ef7eb2e8f9f7 8 *******************************************************************************
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Permission is granted to anyone to use this software for any purpose,
<> 144:ef7eb2e8f9f7 11 * including commercial applications, and to alter it and redistribute it
<> 144:ef7eb2e8f9f7 12 * freely, subject to the following restrictions:
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * 1. The origin of this software must not be misrepresented; you must not
<> 144:ef7eb2e8f9f7 15 * claim that you wrote the original software.
<> 144:ef7eb2e8f9f7 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 144:ef7eb2e8f9f7 17 * misrepresented as being the original software.
<> 144:ef7eb2e8f9f7 18 * 3. This notice may not be removed or altered from any source distribution.
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
<> 144:ef7eb2e8f9f7 21 * obligation to support this Software. Silicon Labs is providing the
<> 144:ef7eb2e8f9f7 22 * Software "AS IS", with no express or implied warranties of any kind,
<> 144:ef7eb2e8f9f7 23 * including, but not limited to, any implied warranties of merchantability
<> 144:ef7eb2e8f9f7 24 * or fitness for any particular purpose or warranties against infringement
<> 144:ef7eb2e8f9f7 25 * of any proprietary rights of a third party.
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * Silicon Labs will not be liable for any consequential, incidental, or
<> 144:ef7eb2e8f9f7 28 * special damages, or any other relief, or for any claim by any third party,
<> 144:ef7eb2e8f9f7 29 * arising from your use of this Software.
<> 144:ef7eb2e8f9f7 30 *
<> 144:ef7eb2e8f9f7 31 ******************************************************************************/
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 #include "em_dac.h"
<> 144:ef7eb2e8f9f7 34 #if defined(DAC_COUNT) && (DAC_COUNT > 0)
<> 144:ef7eb2e8f9f7 35 #include "em_cmu.h"
<> 144:ef7eb2e8f9f7 36 #include "em_assert.h"
<> 144:ef7eb2e8f9f7 37 #include "em_bus.h"
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 40 * @addtogroup EM_Library
<> 144:ef7eb2e8f9f7 41 * @{
<> 144:ef7eb2e8f9f7 42 ******************************************************************************/
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 45 * @addtogroup DAC
<> 144:ef7eb2e8f9f7 46 * @brief Digital to Analog Coversion (DAC) Peripheral API
<> 144:ef7eb2e8f9f7 47 * @{
<> 144:ef7eb2e8f9f7 48 ******************************************************************************/
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 /*******************************************************************************
<> 144:ef7eb2e8f9f7 51 ******************************* DEFINES ***********************************
<> 144:ef7eb2e8f9f7 52 ******************************************************************************/
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 /** Validation of DAC channel for assert statements. */
<> 144:ef7eb2e8f9f7 57 #define DAC_CH_VALID(ch) ((ch) <= 1)
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /** Max DAC clock */
<> 144:ef7eb2e8f9f7 60 #define DAC_MAX_CLOCK 1000000
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /** @endcond */
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 /*******************************************************************************
<> 144:ef7eb2e8f9f7 65 ************************** GLOBAL FUNCTIONS *******************************
<> 144:ef7eb2e8f9f7 66 ******************************************************************************/
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 69 * @brief
<> 144:ef7eb2e8f9f7 70 * Enable/disable DAC channel.
<> 144:ef7eb2e8f9f7 71 *
<> 144:ef7eb2e8f9f7 72 * @param[in] dac
<> 144:ef7eb2e8f9f7 73 * Pointer to DAC peripheral register block.
<> 144:ef7eb2e8f9f7 74 *
<> 144:ef7eb2e8f9f7 75 * @param[in] ch
<> 144:ef7eb2e8f9f7 76 * Channel to enable/disable.
<> 144:ef7eb2e8f9f7 77 *
<> 144:ef7eb2e8f9f7 78 * @param[in] enable
<> 144:ef7eb2e8f9f7 79 * true to enable DAC channel, false to disable.
<> 144:ef7eb2e8f9f7 80 ******************************************************************************/
<> 144:ef7eb2e8f9f7 81 void DAC_Enable(DAC_TypeDef *dac, unsigned int ch, bool enable)
<> 144:ef7eb2e8f9f7 82 {
<> 144:ef7eb2e8f9f7 83 volatile uint32_t *reg;
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 EFM_ASSERT(DAC_REF_VALID(dac));
<> 144:ef7eb2e8f9f7 86 EFM_ASSERT(DAC_CH_VALID(ch));
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 if (!ch)
<> 144:ef7eb2e8f9f7 89 {
<> 144:ef7eb2e8f9f7 90 reg = &(dac->CH0CTRL);
<> 144:ef7eb2e8f9f7 91 }
<> 144:ef7eb2e8f9f7 92 else
<> 144:ef7eb2e8f9f7 93 {
<> 144:ef7eb2e8f9f7 94 reg = &(dac->CH1CTRL);
<> 144:ef7eb2e8f9f7 95 }
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 BUS_RegBitWrite(reg, _DAC_CH0CTRL_EN_SHIFT, enable);
<> 144:ef7eb2e8f9f7 98 }
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 102 * @brief
<> 144:ef7eb2e8f9f7 103 * Initialize DAC.
<> 144:ef7eb2e8f9f7 104 *
<> 144:ef7eb2e8f9f7 105 * @details
<> 144:ef7eb2e8f9f7 106 * Initializes common parts for both channels. In addition, channel control
<> 144:ef7eb2e8f9f7 107 * configuration must be done, please refer to DAC_InitChannel().
<> 144:ef7eb2e8f9f7 108 *
<> 144:ef7eb2e8f9f7 109 * @note
<> 144:ef7eb2e8f9f7 110 * This function will disable both channels prior to configuration.
<> 144:ef7eb2e8f9f7 111 *
<> 144:ef7eb2e8f9f7 112 * @param[in] dac
<> 144:ef7eb2e8f9f7 113 * Pointer to DAC peripheral register block.
<> 144:ef7eb2e8f9f7 114 *
<> 144:ef7eb2e8f9f7 115 * @param[in] init
<> 144:ef7eb2e8f9f7 116 * Pointer to DAC initialization structure.
<> 144:ef7eb2e8f9f7 117 ******************************************************************************/
<> 144:ef7eb2e8f9f7 118 void DAC_Init(DAC_TypeDef *dac, const DAC_Init_TypeDef *init)
<> 144:ef7eb2e8f9f7 119 {
<> 144:ef7eb2e8f9f7 120 uint32_t tmp;
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 EFM_ASSERT(DAC_REF_VALID(dac));
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 /* Make sure both channels are disabled. */
<> 144:ef7eb2e8f9f7 125 BUS_RegBitWrite(&(dac->CH0CTRL), _DAC_CH0CTRL_EN_SHIFT, 0);
<> 144:ef7eb2e8f9f7 126 BUS_RegBitWrite(&(dac->CH1CTRL), _DAC_CH0CTRL_EN_SHIFT, 0);
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 /* Load proper calibration data depending on selected reference */
<> 144:ef7eb2e8f9f7 129 switch (init->reference)
<> 144:ef7eb2e8f9f7 130 {
<> 144:ef7eb2e8f9f7 131 case dacRef2V5:
<> 144:ef7eb2e8f9f7 132 dac->CAL = DEVINFO->DAC0CAL1;
<> 144:ef7eb2e8f9f7 133 break;
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 case dacRefVDD:
<> 144:ef7eb2e8f9f7 136 dac->CAL = DEVINFO->DAC0CAL2;
<> 144:ef7eb2e8f9f7 137 break;
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 default: /* 1.25V */
<> 144:ef7eb2e8f9f7 140 dac->CAL = DEVINFO->DAC0CAL0;
<> 144:ef7eb2e8f9f7 141 break;
<> 144:ef7eb2e8f9f7 142 }
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 tmp = ((uint32_t)(init->refresh) << _DAC_CTRL_REFRSEL_SHIFT)
<> 144:ef7eb2e8f9f7 145 | (((uint32_t)(init->prescale) << _DAC_CTRL_PRESC_SHIFT)
<> 144:ef7eb2e8f9f7 146 & _DAC_CTRL_PRESC_MASK)
<> 144:ef7eb2e8f9f7 147 | ((uint32_t)(init->reference) << _DAC_CTRL_REFSEL_SHIFT)
<> 144:ef7eb2e8f9f7 148 | ((uint32_t)(init->outMode) << _DAC_CTRL_OUTMODE_SHIFT)
<> 144:ef7eb2e8f9f7 149 | ((uint32_t)(init->convMode) << _DAC_CTRL_CONVMODE_SHIFT);
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 if (init->ch0ResetPre)
<> 144:ef7eb2e8f9f7 152 {
<> 144:ef7eb2e8f9f7 153 tmp |= DAC_CTRL_CH0PRESCRST;
<> 144:ef7eb2e8f9f7 154 }
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 if (init->outEnablePRS)
<> 144:ef7eb2e8f9f7 157 {
<> 144:ef7eb2e8f9f7 158 tmp |= DAC_CTRL_OUTENPRS;
<> 144:ef7eb2e8f9f7 159 }
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 if (init->sineEnable)
<> 144:ef7eb2e8f9f7 162 {
<> 144:ef7eb2e8f9f7 163 tmp |= DAC_CTRL_SINEMODE;
<> 144:ef7eb2e8f9f7 164 }
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 if (init->diff)
<> 144:ef7eb2e8f9f7 167 {
<> 144:ef7eb2e8f9f7 168 tmp |= DAC_CTRL_DIFF;
<> 144:ef7eb2e8f9f7 169 }
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 dac->CTRL = tmp;
<> 144:ef7eb2e8f9f7 172 }
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 176 * @brief
<> 144:ef7eb2e8f9f7 177 * Initialize DAC channel.
<> 144:ef7eb2e8f9f7 178 *
<> 144:ef7eb2e8f9f7 179 * @param[in] dac
<> 144:ef7eb2e8f9f7 180 * Pointer to DAC peripheral register block.
<> 144:ef7eb2e8f9f7 181 *
<> 144:ef7eb2e8f9f7 182 * @param[in] init
<> 144:ef7eb2e8f9f7 183 * Pointer to DAC initialization structure.
<> 144:ef7eb2e8f9f7 184 *
<> 144:ef7eb2e8f9f7 185 * @param[in] ch
<> 144:ef7eb2e8f9f7 186 * Channel number to initialize.
<> 144:ef7eb2e8f9f7 187 ******************************************************************************/
<> 144:ef7eb2e8f9f7 188 void DAC_InitChannel(DAC_TypeDef *dac,
<> 144:ef7eb2e8f9f7 189 const DAC_InitChannel_TypeDef *init,
<> 144:ef7eb2e8f9f7 190 unsigned int ch)
<> 144:ef7eb2e8f9f7 191 {
<> 144:ef7eb2e8f9f7 192 uint32_t tmp;
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 EFM_ASSERT(DAC_REF_VALID(dac));
<> 144:ef7eb2e8f9f7 195 EFM_ASSERT(DAC_CH_VALID(ch));
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 tmp = (uint32_t)(init->prsSel) << _DAC_CH0CTRL_PRSSEL_SHIFT;
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 if (init->enable)
<> 144:ef7eb2e8f9f7 200 {
<> 144:ef7eb2e8f9f7 201 tmp |= DAC_CH0CTRL_EN;
<> 144:ef7eb2e8f9f7 202 }
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 if (init->prsEnable)
<> 144:ef7eb2e8f9f7 205 {
<> 144:ef7eb2e8f9f7 206 tmp |= DAC_CH0CTRL_PRSEN;
<> 144:ef7eb2e8f9f7 207 }
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 if (init->refreshEnable)
<> 144:ef7eb2e8f9f7 210 {
<> 144:ef7eb2e8f9f7 211 tmp |= DAC_CH0CTRL_REFREN;
<> 144:ef7eb2e8f9f7 212 }
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 if (ch)
<> 144:ef7eb2e8f9f7 215 {
<> 144:ef7eb2e8f9f7 216 dac->CH1CTRL = tmp;
<> 144:ef7eb2e8f9f7 217 }
<> 144:ef7eb2e8f9f7 218 else
<> 144:ef7eb2e8f9f7 219 {
<> 144:ef7eb2e8f9f7 220 dac->CH0CTRL = tmp;
<> 144:ef7eb2e8f9f7 221 }
<> 144:ef7eb2e8f9f7 222 }
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 226 * @brief
<> 144:ef7eb2e8f9f7 227 * Set the output signal of a DAC channel to a given value.
<> 144:ef7eb2e8f9f7 228 *
<> 144:ef7eb2e8f9f7 229 * @details
<> 144:ef7eb2e8f9f7 230 * This function sets the output signal of a DAC channel by writing @p value
<> 144:ef7eb2e8f9f7 231 * to the corresponding CHnDATA register.
<> 144:ef7eb2e8f9f7 232 *
<> 144:ef7eb2e8f9f7 233 * @param[in] dac
<> 144:ef7eb2e8f9f7 234 * Pointer to DAC peripheral register block.
<> 144:ef7eb2e8f9f7 235 *
<> 144:ef7eb2e8f9f7 236 * @param[in] channel
<> 144:ef7eb2e8f9f7 237 * Channel number to set output of.
<> 144:ef7eb2e8f9f7 238 *
<> 144:ef7eb2e8f9f7 239 * @param[in] value
<> 144:ef7eb2e8f9f7 240 * Value to write to the channel output register CHnDATA.
<> 144:ef7eb2e8f9f7 241 ******************************************************************************/
<> 144:ef7eb2e8f9f7 242 void DAC_ChannelOutputSet( DAC_TypeDef *dac,
<> 144:ef7eb2e8f9f7 243 unsigned int channel,
<> 144:ef7eb2e8f9f7 244 uint32_t value )
<> 144:ef7eb2e8f9f7 245 {
<> 144:ef7eb2e8f9f7 246 switch(channel)
<> 144:ef7eb2e8f9f7 247 {
<> 144:ef7eb2e8f9f7 248 case 0:
<> 144:ef7eb2e8f9f7 249 DAC_Channel0OutputSet(dac, value);
<> 144:ef7eb2e8f9f7 250 break;
<> 144:ef7eb2e8f9f7 251 case 1:
<> 144:ef7eb2e8f9f7 252 DAC_Channel1OutputSet(dac, value);
<> 144:ef7eb2e8f9f7 253 break;
<> 144:ef7eb2e8f9f7 254 default:
<> 144:ef7eb2e8f9f7 255 EFM_ASSERT(0);
<> 144:ef7eb2e8f9f7 256 break;
<> 144:ef7eb2e8f9f7 257 }
<> 144:ef7eb2e8f9f7 258 }
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 262 * @brief
<> 144:ef7eb2e8f9f7 263 * Calculate prescaler value used to determine DAC clock.
<> 144:ef7eb2e8f9f7 264 *
<> 144:ef7eb2e8f9f7 265 * @details
<> 144:ef7eb2e8f9f7 266 * The DAC clock is given by: HFPERCLK / (prescale ^ 2). If the requested
<> 144:ef7eb2e8f9f7 267 * DAC frequency is low and the max prescaler value can not adjust the
<> 144:ef7eb2e8f9f7 268 * actual DAC frequency lower than the requested DAC frequency, then the
<> 144:ef7eb2e8f9f7 269 * max prescaler value is returned, resulting in a higher DAC frequency
<> 144:ef7eb2e8f9f7 270 * than requested.
<> 144:ef7eb2e8f9f7 271 *
<> 144:ef7eb2e8f9f7 272 * @param[in] dacFreq DAC frequency wanted. The frequency will automatically
<> 144:ef7eb2e8f9f7 273 * be adjusted to be below max allowed DAC clock.
<> 144:ef7eb2e8f9f7 274 *
<> 144:ef7eb2e8f9f7 275 * @param[in] hfperFreq Frequency in Hz of reference HFPER clock. Set to 0 to
<> 144:ef7eb2e8f9f7 276 * use currently defined HFPER clock setting.
<> 144:ef7eb2e8f9f7 277 *
<> 144:ef7eb2e8f9f7 278 * @return
<> 144:ef7eb2e8f9f7 279 * Prescaler value to use for DAC in order to achieve a clock value
<> 144:ef7eb2e8f9f7 280 * <= @p dacFreq.
<> 144:ef7eb2e8f9f7 281 ******************************************************************************/
<> 144:ef7eb2e8f9f7 282 uint8_t DAC_PrescaleCalc(uint32_t dacFreq, uint32_t hfperFreq)
<> 144:ef7eb2e8f9f7 283 {
<> 144:ef7eb2e8f9f7 284 uint32_t ret;
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 /* Make sure selected DAC clock is below max value */
<> 144:ef7eb2e8f9f7 287 if (dacFreq > DAC_MAX_CLOCK)
<> 144:ef7eb2e8f9f7 288 {
<> 144:ef7eb2e8f9f7 289 dacFreq = DAC_MAX_CLOCK;
<> 144:ef7eb2e8f9f7 290 }
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 /* Use current HFPER frequency? */
<> 144:ef7eb2e8f9f7 293 if (!hfperFreq)
<> 144:ef7eb2e8f9f7 294 {
<> 144:ef7eb2e8f9f7 295 hfperFreq = CMU_ClockFreqGet(cmuClock_HFPER);
<> 144:ef7eb2e8f9f7 296 }
<> 144:ef7eb2e8f9f7 297
<> 144:ef7eb2e8f9f7 298 /* Iterate in order to determine best prescale value. Only a few possible */
<> 144:ef7eb2e8f9f7 299 /* values. We start with lowest prescaler value in order to get first */
<> 144:ef7eb2e8f9f7 300 /* equal or below wanted DAC frequency value. */
<> 144:ef7eb2e8f9f7 301 for (ret = 0; ret <= (_DAC_CTRL_PRESC_MASK >> _DAC_CTRL_PRESC_SHIFT); ret++)
<> 144:ef7eb2e8f9f7 302 {
<> 144:ef7eb2e8f9f7 303 if ((hfperFreq >> ret) <= dacFreq)
<> 144:ef7eb2e8f9f7 304 break;
<> 144:ef7eb2e8f9f7 305 }
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 /* If ret is higher than the max prescaler value, make sure to return
<> 144:ef7eb2e8f9f7 308 the max value. */
<> 144:ef7eb2e8f9f7 309 if (ret > (_DAC_CTRL_PRESC_MASK >> _DAC_CTRL_PRESC_SHIFT))
<> 144:ef7eb2e8f9f7 310 {
<> 144:ef7eb2e8f9f7 311 ret = _DAC_CTRL_PRESC_MASK >> _DAC_CTRL_PRESC_SHIFT;
<> 144:ef7eb2e8f9f7 312 }
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 return (uint8_t)ret;
<> 144:ef7eb2e8f9f7 315 }
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 319 * @brief
<> 144:ef7eb2e8f9f7 320 * Reset DAC to same state as after a HW reset.
<> 144:ef7eb2e8f9f7 321 *
<> 144:ef7eb2e8f9f7 322 * @param[in] dac
<> 144:ef7eb2e8f9f7 323 * Pointer to ADC peripheral register block.
<> 144:ef7eb2e8f9f7 324 ******************************************************************************/
<> 144:ef7eb2e8f9f7 325 void DAC_Reset(DAC_TypeDef *dac)
<> 144:ef7eb2e8f9f7 326 {
<> 144:ef7eb2e8f9f7 327 /* Disable channels, before resetting other registers. */
<> 144:ef7eb2e8f9f7 328 dac->CH0CTRL = _DAC_CH0CTRL_RESETVALUE;
<> 144:ef7eb2e8f9f7 329 dac->CH1CTRL = _DAC_CH1CTRL_RESETVALUE;
<> 144:ef7eb2e8f9f7 330 dac->CTRL = _DAC_CTRL_RESETVALUE;
<> 144:ef7eb2e8f9f7 331 dac->IEN = _DAC_IEN_RESETVALUE;
<> 144:ef7eb2e8f9f7 332 dac->IFC = _DAC_IFC_MASK;
<> 144:ef7eb2e8f9f7 333 dac->CAL = DEVINFO->DAC0CAL0;
<> 144:ef7eb2e8f9f7 334 dac->BIASPROG = _DAC_BIASPROG_RESETVALUE;
<> 144:ef7eb2e8f9f7 335 /* Do not reset route register, setting should be done independently */
<> 144:ef7eb2e8f9f7 336 }
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 /** @} (end addtogroup DAC) */
<> 144:ef7eb2e8f9f7 340 /** @} (end addtogroup EM_Library) */
<> 144:ef7eb2e8f9f7 341 #endif /* defined(DAC_COUNT) && (DAC_COUNT > 0) */