Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_ONSEMI/TARGET_NCS36510/gpio_map.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file gpio_map.h
<> 144:ef7eb2e8f9f7 4 * @brief GPIO HW register map
<> 144:ef7eb2e8f9f7 5 * @internal
<> 144:ef7eb2e8f9f7 6 * @author ON Semiconductor
<> 144:ef7eb2e8f9f7 7 * $Rev: 2115 $
<> 144:ef7eb2e8f9f7 8 * $Date: 2013-07-17 18:08:17 +0530 (Wed, 17 Jul 2013) $
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 144:ef7eb2e8f9f7 10 * @copyright (c) 2012 ON Semiconductor. All rights reserved.
<> 144:ef7eb2e8f9f7 11 * ON Semiconductor is supplying this software for use with ON Semiconductor
<> 144:ef7eb2e8f9f7 12 * processor based microcontrollers only.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 15 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 17 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 144:ef7eb2e8f9f7 18 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 19 * @endinternal
<> 144:ef7eb2e8f9f7 20 *
<> 144:ef7eb2e8f9f7 21 * @ingroup gpio
<> 144:ef7eb2e8f9f7 22 *
<> 144:ef7eb2e8f9f7 23 * @details
<> 144:ef7eb2e8f9f7 24 * <p>
<> 144:ef7eb2e8f9f7 25 * GPIO HW register map description
<> 144:ef7eb2e8f9f7 26 * </p>
<> 144:ef7eb2e8f9f7 27 *
<> 144:ef7eb2e8f9f7 28 * <h1> Reference document(s) </h1>
<> 144:ef7eb2e8f9f7 29 * <p>
<> 144:ef7eb2e8f9f7 30 * <a href="../pdf/IPC7203_GPIO_APB_DS_v1P1.pdf" target="_blank">
<> 144:ef7eb2e8f9f7 31 * Reference document: IPC7203 APB GPIO Design Specification v1.2</a>
<> 144:ef7eb2e8f9f7 32 * </p>
<> 144:ef7eb2e8f9f7 33 */
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 #ifndef GPIO_MAP_H_
<> 144:ef7eb2e8f9f7 36 #define GPIO_MAP_H_
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 #include "architecture.h"
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 /** Structure overlay for GPIO control registers, see memory_map.h
<> 144:ef7eb2e8f9f7 41 * For most registers, bit lockations match GPIO numbers.*/
<> 144:ef7eb2e8f9f7 42 typedef struct {
<> 144:ef7eb2e8f9f7 43 __IO uint32_t R_STATE_W_SET; /**< Read synchronized input / Write ones to bits to set corresponding output IO's*/
<> 144:ef7eb2e8f9f7 44 __IO uint32_t R_IRQ_W_CLEAR; /**< Read state of irq / Write ones to bits to clear corresponging output IO's */
<> 144:ef7eb2e8f9f7 45 __IO uint32_t W_OUT; /**< Write ones to set direction to output */
<> 144:ef7eb2e8f9f7 46 __IO uint32_t W_IN; /**< Write ones to set direction to input */
<> 144:ef7eb2e8f9f7 47 __IO uint32_t IRQ_ENABLE_SET; /**< Read active high irq enable / Write ones to enable irq */
<> 144:ef7eb2e8f9f7 48 __IO uint32_t IRQ_ENABLE_CLEAR; /**< Read active high irq enable / Write ones to disable irq */
<> 144:ef7eb2e8f9f7 49 __IO uint32_t IRQ_EDGE; /**< Read irq configuration (edge or level) / Write ones to set irq to edge-sensitive */
<> 144:ef7eb2e8f9f7 50 __IO uint32_t IRQ_LEVEL; /**< Read irq configuration (edge or level) / Write ones to set irq to level-sensitive */
<> 144:ef7eb2e8f9f7 51 __IO uint32_t IRQ_POLARITY_SET; /**< Read irq polarity / Write ones to set irq to active high or rising edge */
<> 144:ef7eb2e8f9f7 52 __IO uint32_t IRQ_POLARITY_CLEAR; /**< Read irq polarity / Write ones to set interrupts to active low or falling edge */
<> 144:ef7eb2e8f9f7 53 __IO uint32_t ANYEDGE_SET; /**< Read irq anyedge configuration / Write ones to override irq edge selection & irq on any edge */
<> 144:ef7eb2e8f9f7 54 __IO uint32_t ANYEDGE_CLEAR; /**< Read irq anyedge configuration / Write ones to clear edge selection override */
<> 144:ef7eb2e8f9f7 55 __IO uint32_t IRQ_CLEAR; /**< Write ones to clear edge-sensitive irq */
<> 144:ef7eb2e8f9f7 56 __IO uint32_t CONTROL; /**< Controls loopback/normal mode selection */
<> 144:ef7eb2e8f9f7 57 } GpioReg_t, *GpioReg_pt;
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 #endif /* GPIO_MAP_H_ */