Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_NUVOTON/TARGET_NUC472/us_ticker.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015-2016 Nuvoton
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16
<> 144:ef7eb2e8f9f7 17 #include "us_ticker_api.h"
<> 144:ef7eb2e8f9f7 18 #include "sleep_api.h"
<> 144:ef7eb2e8f9f7 19 #include "mbed_assert.h"
<> 144:ef7eb2e8f9f7 20 #include "nu_modutil.h"
<> 144:ef7eb2e8f9f7 21 #include "nu_miscutil.h"
<> 144:ef7eb2e8f9f7 22 #include "critical.h"
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 #define US_PER_TICK 1
<> 144:ef7eb2e8f9f7 25
<> 144:ef7eb2e8f9f7 26 // NOTE: mbed-drivers-test-timeout test requires 100 us timer granularity.
<> 144:ef7eb2e8f9f7 27 // NOTE: us_ticker will alarm the system for its counting, so make the counting period as long as possible for better power saving.
<> 144:ef7eb2e8f9f7 28 #define US_PER_TMR0HIRES_INT (1000 * 1000 * 10)
<> 144:ef7eb2e8f9f7 29 #define TMR0HIRES_FIRE_FREQ (1000 * 1000 / US_PER_TMR0HIRES_INT)
<> 144:ef7eb2e8f9f7 30 #define US_PER_TMR0HIRES_CLK 1
<> 144:ef7eb2e8f9f7 31 #define TMR0HIRES_CLK_FREQ (1000 * 1000 / US_PER_TMR0HIRES_CLK)
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 #define US_PER_TMR1LORES_CLK 100
<> 144:ef7eb2e8f9f7 34 #define TMR1LORES_CLK_FREQ (1000 * 1000 / US_PER_TMR1LORES_CLK)
<> 144:ef7eb2e8f9f7 35 #define US_PER_TMR1HIRES_CLK 1
<> 144:ef7eb2e8f9f7 36 #define TMR1HIRES_CLK_FREQ (1000 * 1000 / US_PER_TMR1HIRES_CLK)
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 // Determine to use lo-res/hi-res timer according to CD period
<> 144:ef7eb2e8f9f7 39 #define CD_TMR_SEP_US 1000
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 static void tmr0_vec(void);
<> 144:ef7eb2e8f9f7 42 static void tmr1_vec(void);
<> 144:ef7eb2e8f9f7 43 static void us_ticker_arm_cd(void);
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 static int us_ticker_inited = 0;
<> 144:ef7eb2e8f9f7 46 static volatile uint32_t counter_major = 0;
<> 144:ef7eb2e8f9f7 47 static volatile uint32_t pd_comp_us = 0; // Power-down compenstaion for normal counter
<> 144:ef7eb2e8f9f7 48 static volatile int cd_major_minor_us = 0;
<> 144:ef7eb2e8f9f7 49 static volatile int cd_minor_us = 0;
<> 144:ef7eb2e8f9f7 50 static volatile int cd_hires_tmr_armed = 0; // Flag of armed or not of hi-res timer for CD counter
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 // NOTE: PCLK is set up in mbed_sdk_init(), invocation of which must be before C++ global object constructor. See init_api.c for details.
<> 144:ef7eb2e8f9f7 53 // NOTE: Choose clock source of timer:
<> 144:ef7eb2e8f9f7 54 // 1. HIRC: Be the most accurate but might cause unknown HardFault.
<> 144:ef7eb2e8f9f7 55 // 2. HXT: Less accurate and cannot pass mbed-drivers test.
<> 144:ef7eb2e8f9f7 56 // 3. PCLK(HXT): Less accurate but can pass mbed-drivers test.
<> 144:ef7eb2e8f9f7 57 // NOTE: TIMER_0 for normal counter, TIMER_1 for countdown.
<> 144:ef7eb2e8f9f7 58 static const struct nu_modinit_s timer0hires_modinit = {TIMER_0, TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_PCLK, 0, TMR0_RST, TMR0_IRQn, (void *) tmr0_vec};
<> 144:ef7eb2e8f9f7 59 static const struct nu_modinit_s timer1lores_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_LIRC, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec};
<> 144:ef7eb2e8f9f7 60 static const struct nu_modinit_s timer1hires_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_PCLK, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec};
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 #define TMR_CMP_MIN 2
<> 144:ef7eb2e8f9f7 63 #define TMR_CMP_MAX 0xFFFFFFu
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 void us_ticker_init(void)
<> 144:ef7eb2e8f9f7 66 {
<> 144:ef7eb2e8f9f7 67 if (us_ticker_inited) {
<> 144:ef7eb2e8f9f7 68 return;
<> 144:ef7eb2e8f9f7 69 }
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 counter_major = 0;
<> 144:ef7eb2e8f9f7 72 pd_comp_us = 0;
<> 144:ef7eb2e8f9f7 73 cd_major_minor_us = 0;
<> 144:ef7eb2e8f9f7 74 cd_minor_us = 0;
<> 144:ef7eb2e8f9f7 75 cd_hires_tmr_armed = 0;
<> 144:ef7eb2e8f9f7 76 us_ticker_inited = 1;
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 // Reset IP
<> 144:ef7eb2e8f9f7 79 SYS_ResetModule(timer0hires_modinit.rsetidx);
<> 144:ef7eb2e8f9f7 80 SYS_ResetModule(timer1lores_modinit.rsetidx);
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 // Select IP clock source
<> 144:ef7eb2e8f9f7 83 CLK_SetModuleClock(timer0hires_modinit.clkidx, timer0hires_modinit.clksrc, timer0hires_modinit.clkdiv);
<> 144:ef7eb2e8f9f7 84 CLK_SetModuleClock(timer1lores_modinit.clkidx, timer1lores_modinit.clksrc, timer1lores_modinit.clkdiv);
<> 144:ef7eb2e8f9f7 85 // Enable IP clock
<> 144:ef7eb2e8f9f7 86 CLK_EnableModuleClock(timer0hires_modinit.clkidx);
<> 144:ef7eb2e8f9f7 87 CLK_EnableModuleClock(timer1lores_modinit.clkidx);
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 // Timer for normal counter
<> 144:ef7eb2e8f9f7 90 uint32_t clk_timer0 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
<> 144:ef7eb2e8f9f7 91 uint32_t prescale_timer0 = clk_timer0 / TMR0HIRES_CLK_FREQ - 1;
<> 144:ef7eb2e8f9f7 92 MBED_ASSERT((prescale_timer0 != (uint32_t) -1) && prescale_timer0 <= 127);
<> 144:ef7eb2e8f9f7 93 uint32_t cmp_timer0 = US_PER_TMR0HIRES_INT / US_PER_TMR0HIRES_CLK;
<> 144:ef7eb2e8f9f7 94 MBED_ASSERT(cmp_timer0 >= TMR_CMP_MIN && cmp_timer0 <= TMR_CMP_MAX);
<> 144:ef7eb2e8f9f7 95 ((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname))->CTL = TIMER_PERIODIC_MODE | prescale_timer0 | TIMER_CTL_CNTDATEN_Msk;
<> 144:ef7eb2e8f9f7 96 ((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname))->CMP = cmp_timer0;
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 NVIC_SetVector(timer0hires_modinit.irq_n, (uint32_t) timer0hires_modinit.var);
<> 144:ef7eb2e8f9f7 99 NVIC_SetVector(timer1lores_modinit.irq_n, (uint32_t) timer1lores_modinit.var);
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 NVIC_EnableIRQ(timer0hires_modinit.irq_n);
<> 144:ef7eb2e8f9f7 102 NVIC_EnableIRQ(timer1lores_modinit.irq_n);
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
<> 144:ef7eb2e8f9f7 105 TIMER_Start((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
<> 144:ef7eb2e8f9f7 106 }
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 uint32_t us_ticker_read()
<> 144:ef7eb2e8f9f7 109 {
<> 144:ef7eb2e8f9f7 110 if (! us_ticker_inited) {
<> 144:ef7eb2e8f9f7 111 us_ticker_init();
<> 144:ef7eb2e8f9f7 112 }
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 TIMER_T * timer0_base = (TIMER_T *) NU_MODBASE(timer0hires_modinit.modname);
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 do {
<> 144:ef7eb2e8f9f7 117 uint32_t major_minor_us;
<> 144:ef7eb2e8f9f7 118 uint32_t minor_us;
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 // NOTE: As TIMER_CNT = TIMER_CMP and counter_major has increased by one, TIMER_CNT doesn't change to 0 for one tick time.
<> 144:ef7eb2e8f9f7 121 // NOTE: As TIMER_CNT = TIMER_CMP or TIMER_CNT = 0, counter_major (ISR) may not sync with TIMER_CNT. So skip and fetch stable one at the cost of 1 clock delay on this read.
<> 144:ef7eb2e8f9f7 122 do {
<> 144:ef7eb2e8f9f7 123 core_util_critical_section_enter();
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 // NOTE: Order of reading minor_us/carry here is significant.
<> 144:ef7eb2e8f9f7 126 minor_us = TIMER_GetCounter(timer0_base) * US_PER_TMR0HIRES_CLK;
<> 144:ef7eb2e8f9f7 127 uint32_t carry = (timer0_base->INTSTS & TIMER_INTSTS_TIF_Msk) ? 1 : 0;
<> 144:ef7eb2e8f9f7 128 // When TIMER_CNT approaches TIMER_CMP and will wrap soon, we may get carry but TIMER_CNT not wrapped. Hanlde carefully carry == 1 && TIMER_CNT is near TIMER_CMP.
<> 144:ef7eb2e8f9f7 129 if (carry && minor_us > (US_PER_TMR0HIRES_INT / 2)) {
<> 144:ef7eb2e8f9f7 130 major_minor_us = (counter_major + 1) * US_PER_TMR0HIRES_INT;
<> 144:ef7eb2e8f9f7 131 }
<> 144:ef7eb2e8f9f7 132 else {
<> 144:ef7eb2e8f9f7 133 major_minor_us = (counter_major + carry) * US_PER_TMR0HIRES_INT + minor_us;
<> 144:ef7eb2e8f9f7 134 }
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 core_util_critical_section_exit();
<> 144:ef7eb2e8f9f7 137 }
<> 144:ef7eb2e8f9f7 138 while (minor_us == 0 || minor_us == US_PER_TMR0HIRES_INT);
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 // Add power-down compensation
<> 144:ef7eb2e8f9f7 141 return (major_minor_us + pd_comp_us) / US_PER_TICK;
<> 144:ef7eb2e8f9f7 142 }
<> 144:ef7eb2e8f9f7 143 while (0);
<> 144:ef7eb2e8f9f7 144 }
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 void us_ticker_disable_interrupt(void)
<> 144:ef7eb2e8f9f7 147 {
<> 144:ef7eb2e8f9f7 148 TIMER_DisableInt((TIMER_T *) NU_MODBASE(timer1lores_modinit.modname));
<> 144:ef7eb2e8f9f7 149 }
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 void us_ticker_clear_interrupt(void)
<> 144:ef7eb2e8f9f7 152 {
<> 144:ef7eb2e8f9f7 153 TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer1lores_modinit.modname));
<> 144:ef7eb2e8f9f7 154 }
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 void us_ticker_set_interrupt(timestamp_t timestamp)
<> 144:ef7eb2e8f9f7 157 {
<> 144:ef7eb2e8f9f7 158 TIMER_Stop((TIMER_T *) NU_MODBASE(timer1lores_modinit.modname));
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 int delta = (int) (timestamp - us_ticker_read());
<> 144:ef7eb2e8f9f7 161 // NOTE: If this event was in the past, arm an interrupt to be triggered immediately.
<> 144:ef7eb2e8f9f7 162 cd_major_minor_us = delta * US_PER_TICK;
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 us_ticker_arm_cd();
<> 144:ef7eb2e8f9f7 165 }
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 void us_ticker_prepare_sleep(struct sleep_s *obj)
<> 144:ef7eb2e8f9f7 168 {
<> 144:ef7eb2e8f9f7 169 // Reject power-down if hi-res timer (HIRC/HXT) is now armed for CD counter.
<> 144:ef7eb2e8f9f7 170 if (obj->powerdown) {
<> 144:ef7eb2e8f9f7 171 obj->powerdown = ! cd_hires_tmr_armed;
<> 144:ef7eb2e8f9f7 172 }
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 core_util_critical_section_enter();
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 if (obj->powerdown) {
<> 144:ef7eb2e8f9f7 177 // NOTE: On entering power-down mode, HIRC/HXT will be disabled in normal mode, but not in ICE mode. This may cause confusion in development.
<> 144:ef7eb2e8f9f7 178 // To not be inconsistent due to above, always disable clock source of normal counter, and then re-enable it and make compensation on wakeup from power-down.
<> 144:ef7eb2e8f9f7 179 CLK_DisableModuleClock(timer0hires_modinit.clkidx);
<> 144:ef7eb2e8f9f7 180 }
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 core_util_critical_section_exit();
<> 144:ef7eb2e8f9f7 183 }
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 void us_ticker_wakeup_from_sleep(struct sleep_s *obj)
<> 144:ef7eb2e8f9f7 186 {
<> 144:ef7eb2e8f9f7 187 core_util_critical_section_enter();
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 if (obj->powerdown) {
<> 144:ef7eb2e8f9f7 190 // Calculate power-down compensation
<> 144:ef7eb2e8f9f7 191 pd_comp_us += obj->period_us;
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 CLK_EnableModuleClock(timer0hires_modinit.clkidx);
<> 144:ef7eb2e8f9f7 194 }
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 core_util_critical_section_exit();
<> 144:ef7eb2e8f9f7 197 }
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 static void tmr0_vec(void)
<> 144:ef7eb2e8f9f7 200 {
<> 144:ef7eb2e8f9f7 201 TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
<> 144:ef7eb2e8f9f7 202 counter_major ++;
<> 144:ef7eb2e8f9f7 203 }
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 static void tmr1_vec(void)
<> 144:ef7eb2e8f9f7 206 {
<> 144:ef7eb2e8f9f7 207 TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer1lores_modinit.modname));
<> 144:ef7eb2e8f9f7 208 cd_major_minor_us -= cd_minor_us;
<> 144:ef7eb2e8f9f7 209 cd_hires_tmr_armed = 0;
<> 144:ef7eb2e8f9f7 210 if (cd_major_minor_us <= 0) {
<> 144:ef7eb2e8f9f7 211 // NOTE: us_ticker_set_interrupt() may get called in us_ticker_irq_handler();
<> 144:ef7eb2e8f9f7 212 us_ticker_irq_handler();
<> 144:ef7eb2e8f9f7 213 }
<> 144:ef7eb2e8f9f7 214 else {
<> 144:ef7eb2e8f9f7 215 us_ticker_arm_cd();
<> 144:ef7eb2e8f9f7 216 }
<> 144:ef7eb2e8f9f7 217 }
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 static void us_ticker_arm_cd(void)
<> 144:ef7eb2e8f9f7 220 {
<> 144:ef7eb2e8f9f7 221 TIMER_T * timer1_base = (TIMER_T *) NU_MODBASE(timer1lores_modinit.modname);
<> 144:ef7eb2e8f9f7 222 uint32_t tmr1_clk_freq;
<> 144:ef7eb2e8f9f7 223 uint32_t us_per_tmr1_clk;
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 /**
<> 144:ef7eb2e8f9f7 226 * Reserve CD_TMR_SEP_US-plus alarm period for hi-res timer
<> 144:ef7eb2e8f9f7 227 * 1. period >= CD_TMR_SEP_US * 2. Divide into two rounds:
<> 144:ef7eb2e8f9f7 228 * CD_TMR_SEP_US * n (lo-res timer)
<> 144:ef7eb2e8f9f7 229 * CD_TMR_SEP_US + period % CD_TMR_SEP_US (hi-res timer)
<> 144:ef7eb2e8f9f7 230 * 2. period < CD_TMR_SEP_US * 2. Just one round:
<> 144:ef7eb2e8f9f7 231 * period (hi-res timer)
<> 144:ef7eb2e8f9f7 232 */
<> 144:ef7eb2e8f9f7 233 if (cd_major_minor_us >= CD_TMR_SEP_US * 2) {
<> 144:ef7eb2e8f9f7 234 cd_minor_us = cd_major_minor_us - cd_major_minor_us % CD_TMR_SEP_US - CD_TMR_SEP_US;
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236 CLK_SetModuleClock(timer1lores_modinit.clkidx, timer1lores_modinit.clksrc, timer1lores_modinit.clkdiv);
<> 144:ef7eb2e8f9f7 237 tmr1_clk_freq = TMR1LORES_CLK_FREQ;
<> 144:ef7eb2e8f9f7 238 us_per_tmr1_clk = US_PER_TMR1LORES_CLK;
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 cd_hires_tmr_armed = 0;
<> 144:ef7eb2e8f9f7 241 }
<> 144:ef7eb2e8f9f7 242 else {
<> 144:ef7eb2e8f9f7 243 cd_minor_us = cd_major_minor_us;
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 CLK_SetModuleClock(timer1hires_modinit.clkidx, timer1hires_modinit.clksrc, timer1hires_modinit.clkdiv);
<> 144:ef7eb2e8f9f7 246 tmr1_clk_freq = TMR1HIRES_CLK_FREQ;
<> 144:ef7eb2e8f9f7 247 us_per_tmr1_clk = US_PER_TMR1HIRES_CLK;
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 cd_hires_tmr_armed = 1;
<> 144:ef7eb2e8f9f7 250 }
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 // Reset 8-bit PSC counter, 24-bit up counter value and CNTEN bit
<> 144:ef7eb2e8f9f7 253 timer1_base->CTL |= TIMER_CTL_RSTCNT_Msk;
<> 144:ef7eb2e8f9f7 254 // One-shot mode, Clock = 1 MHz
<> 144:ef7eb2e8f9f7 255 uint32_t clk_timer1 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer1lores_modinit.modname));
<> 144:ef7eb2e8f9f7 256 uint32_t prescale_timer1 = clk_timer1 / tmr1_clk_freq - 1;
<> 144:ef7eb2e8f9f7 257 MBED_ASSERT((prescale_timer1 != (uint32_t) -1) && prescale_timer1 <= 127);
<> 144:ef7eb2e8f9f7 258 timer1_base->CTL &= ~(TIMER_CTL_OPMODE_Msk | TIMER_CTL_PSC_Msk | TIMER_CTL_CNTDATEN_Msk);
<> 144:ef7eb2e8f9f7 259 timer1_base->CTL |= TIMER_ONESHOT_MODE | prescale_timer1 | TIMER_CTL_CNTDATEN_Msk;
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 cd_minor_us = NU_CLAMP(cd_minor_us, TMR_CMP_MIN * us_per_tmr1_clk, TMR_CMP_MAX * us_per_tmr1_clk);
<> 144:ef7eb2e8f9f7 262 timer1_base->CMP = cd_minor_us / us_per_tmr1_clk;
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264 TIMER_EnableInt(timer1_base);
<> 144:ef7eb2e8f9f7 265 TIMER_Start(timer1_base);
<> 144:ef7eb2e8f9f7 266 }