Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Maxim/TARGET_MAX32620/rtc_api.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*******************************************************************************
<> 144:ef7eb2e8f9f7 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 144:ef7eb2e8f9f7 5 * copy of this software and associated documentation files (the "Software"),
<> 144:ef7eb2e8f9f7 6 * to deal in the Software without restriction, including without limitation
<> 144:ef7eb2e8f9f7 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 144:ef7eb2e8f9f7 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 144:ef7eb2e8f9f7 9 * Software is furnished to do so, subject to the following conditions:
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * The above copyright notice and this permission notice shall be included
<> 144:ef7eb2e8f9f7 12 * in all copies or substantial portions of the Software.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 144:ef7eb2e8f9f7 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 144:ef7eb2e8f9f7 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 144:ef7eb2e8f9f7 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 144:ef7eb2e8f9f7 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 144:ef7eb2e8f9f7 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * Except as contained in this notice, the name of Maxim Integrated
<> 144:ef7eb2e8f9f7 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 144:ef7eb2e8f9f7 24 * Products, Inc. Branding Policy.
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * The mere transfer of this software does not imply any licenses
<> 144:ef7eb2e8f9f7 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 144:ef7eb2e8f9f7 28 * trademarks, maskwork rights, or any other form of intellectual
<> 144:ef7eb2e8f9f7 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 144:ef7eb2e8f9f7 30 * ownership rights.
<> 144:ef7eb2e8f9f7 31 *******************************************************************************
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #include "rtc_api.h"
<> 144:ef7eb2e8f9f7 35 #include "lp_ticker_api.h"
<> 144:ef7eb2e8f9f7 36 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 37 #include "rtc_regs.h"
<> 144:ef7eb2e8f9f7 38 #include "pwrseq_regs.h"
<> 144:ef7eb2e8f9f7 39 #include "clkman_regs.h"
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 /**
<> 144:ef7eb2e8f9f7 42 * Defines clock divider for 4096Hz input clock.
<> 144:ef7eb2e8f9f7 43 */
<> 144:ef7eb2e8f9f7 44 typedef enum {
<> 144:ef7eb2e8f9f7 45 /** (4kHz) divide input clock by 2^0 = 1 */
<> 144:ef7eb2e8f9f7 46 MXC_E_RTC_PRESCALE_DIV_2_0 = 0,
<> 144:ef7eb2e8f9f7 47 /** (2kHz) divide input clock by 2^1 = 2 */
<> 144:ef7eb2e8f9f7 48 MXC_E_RTC_PRESCALE_DIV_2_1,
<> 144:ef7eb2e8f9f7 49 /** (1kHz) divide input clock by 2^2 = 4 */
<> 144:ef7eb2e8f9f7 50 MXC_E_RTC_PRESCALE_DIV_2_2,
<> 144:ef7eb2e8f9f7 51 /** (512Hz) divide input clock by 2^3 = 8 */
<> 144:ef7eb2e8f9f7 52 MXC_E_RTC_PRESCALE_DIV_2_3,
<> 144:ef7eb2e8f9f7 53 /** (256Hz) divide input clock by 2^4 = 16 */
<> 144:ef7eb2e8f9f7 54 MXC_E_RTC_PRESCALE_DIV_2_4,
<> 144:ef7eb2e8f9f7 55 /** (128Hz) divide input clock by 2^5 = 32 */
<> 144:ef7eb2e8f9f7 56 MXC_E_RTC_PRESCALE_DIV_2_5,
<> 144:ef7eb2e8f9f7 57 /** (64Hz) divide input clock by 2^6 = 64 */
<> 144:ef7eb2e8f9f7 58 MXC_E_RTC_PRESCALE_DIV_2_6,
<> 144:ef7eb2e8f9f7 59 /** (32Hz) divide input clock by 2^7 = 128 */
<> 144:ef7eb2e8f9f7 60 MXC_E_RTC_PRESCALE_DIV_2_7,
<> 144:ef7eb2e8f9f7 61 /** (16Hz) divide input clock by 2^8 = 256 */
<> 144:ef7eb2e8f9f7 62 MXC_E_RTC_PRESCALE_DIV_2_8,
<> 144:ef7eb2e8f9f7 63 /** (8Hz) divide input clock by 2^9 = 512 */
<> 144:ef7eb2e8f9f7 64 MXC_E_RTC_PRESCALE_DIV_2_9,
<> 144:ef7eb2e8f9f7 65 /** (4Hz) divide input clock by 2^10 = 1024 */
<> 144:ef7eb2e8f9f7 66 MXC_E_RTC_PRESCALE_DIV_2_10,
<> 144:ef7eb2e8f9f7 67 /** (2Hz) divide input clock by 2^11 = 2048 */
<> 144:ef7eb2e8f9f7 68 MXC_E_RTC_PRESCALE_DIV_2_11,
<> 144:ef7eb2e8f9f7 69 /** (1Hz) divide input clock by 2^12 = 4096 */
<> 144:ef7eb2e8f9f7 70 MXC_E_RTC_PRESCALE_DIV_2_12,
<> 144:ef7eb2e8f9f7 71 } mxc_rtc_prescale_t;
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 #define PRESCALE_VAL MXC_E_RTC_PRESCALE_DIV_2_0 // Set the divider for the 4kHz clock
<> 144:ef7eb2e8f9f7 74 #define SHIFT_AMT (MXC_E_RTC_PRESCALE_DIV_2_12 - PRESCALE_VAL)
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 #define WINDOW 1000
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 static int rtc_inited = 0;
<> 144:ef7eb2e8f9f7 79 static volatile uint32_t overflow_cnt = 0;
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 static uint64_t rtc_read64(void);
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 //******************************************************************************
<> 144:ef7eb2e8f9f7 84 static void overflow_handler(void)
<> 144:ef7eb2e8f9f7 85 {
<> 144:ef7eb2e8f9f7 86 MXC_RTCTMR->flags |= MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS;
<> 144:ef7eb2e8f9f7 87 overflow_cnt++;
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 // Wait for pending transactions
<> 144:ef7eb2e8f9f7 90 while (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
<> 144:ef7eb2e8f9f7 91 }
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 //******************************************************************************
<> 144:ef7eb2e8f9f7 94 void rtc_init(void)
<> 144:ef7eb2e8f9f7 95 {
<> 144:ef7eb2e8f9f7 96 if (rtc_inited) {
<> 144:ef7eb2e8f9f7 97 return;
<> 144:ef7eb2e8f9f7 98 }
<> 144:ef7eb2e8f9f7 99 rtc_inited = 1;
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 overflow_cnt = 0;
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 // Enable the clock to the synchronizer
<> 144:ef7eb2e8f9f7 104 MXC_CLKMAN->sys_clk_ctrl_1_sync = MXC_S_CLKMAN_CLK_SCALE_DIV_1;
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 // Enable the clock to the RTC
<> 144:ef7eb2e8f9f7 107 MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN;
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 // Prepare interrupt handlers
<> 144:ef7eb2e8f9f7 110 NVIC_SetVector(RTC0_IRQn, (uint32_t)lp_ticker_irq_handler);
<> 144:ef7eb2e8f9f7 111 NVIC_EnableIRQ(RTC0_IRQn);
<> 144:ef7eb2e8f9f7 112 NVIC_SetVector(RTC3_IRQn, (uint32_t)overflow_handler);
<> 144:ef7eb2e8f9f7 113 NVIC_EnableIRQ(RTC3_IRQn);
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 // Enable wakeup on RTC rollover
<> 144:ef7eb2e8f9f7 116 MXC_PWRSEQ->msk_flags &= ~MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER;
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 /* RTC registers are only reset on a power cycle. Do not reconfigure the RTC
<> 144:ef7eb2e8f9f7 119 * if it is already running.
<> 144:ef7eb2e8f9f7 120 */
<> 144:ef7eb2e8f9f7 121 if (!(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_ENABLE)) {
<> 144:ef7eb2e8f9f7 122 // Set the clock divider
<> 144:ef7eb2e8f9f7 123 MXC_RTCTMR->prescale = PRESCALE_VAL;
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 // Enable the overflow interrupt
<> 144:ef7eb2e8f9f7 126 MXC_RTCTMR->inten |= MXC_F_RTC_FLAGS_OVERFLOW;
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 // Restart the timer from 0
<> 144:ef7eb2e8f9f7 129 MXC_RTCTMR->timer = 0;
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 // Enable the RTC
<> 144:ef7eb2e8f9f7 132 MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_ENABLE;
<> 144:ef7eb2e8f9f7 133 }
<> 144:ef7eb2e8f9f7 134 }
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 //******************************************************************************
<> 144:ef7eb2e8f9f7 137 void lp_ticker_init(void)
<> 144:ef7eb2e8f9f7 138 {
<> 144:ef7eb2e8f9f7 139 rtc_init();
<> 144:ef7eb2e8f9f7 140 }
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 //******************************************************************************
<> 144:ef7eb2e8f9f7 143 void rtc_free(void)
<> 144:ef7eb2e8f9f7 144 {
<> 144:ef7eb2e8f9f7 145 if (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_ENABLE) {
<> 144:ef7eb2e8f9f7 146 // Clear and disable RTC
<> 144:ef7eb2e8f9f7 147 MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_CLEAR;
<> 144:ef7eb2e8f9f7 148 MXC_RTCTMR->ctrl &= ~MXC_F_RTC_CTRL_ENABLE;
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 // Wait for pending transactions
<> 144:ef7eb2e8f9f7 151 while (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
<> 144:ef7eb2e8f9f7 152 }
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 // Disable the clock to the RTC
<> 144:ef7eb2e8f9f7 155 MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN | MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP);
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 // Disable the clock to the synchronizer
<> 144:ef7eb2e8f9f7 158 MXC_CLKMAN->sys_clk_ctrl_1_sync = MXC_S_CLKMAN_CLK_SCALE_DISABLED;
<> 144:ef7eb2e8f9f7 159 }
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 //******************************************************************************
<> 144:ef7eb2e8f9f7 162 int rtc_isenabled(void)
<> 144:ef7eb2e8f9f7 163 {
<> 144:ef7eb2e8f9f7 164 return (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_ENABLE);
<> 144:ef7eb2e8f9f7 165 }
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 //******************************************************************************
<> 144:ef7eb2e8f9f7 168 time_t rtc_read(void)
<> 144:ef7eb2e8f9f7 169 {
<> 144:ef7eb2e8f9f7 170 uint32_t ovf_cnt_1, ovf_cnt_2, timer_cnt;
<> 144:ef7eb2e8f9f7 171 uint32_t ovf1, ovf2;
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 // Make sure RTC is setup before trying to read
<> 144:ef7eb2e8f9f7 174 if (!rtc_inited) {
<> 144:ef7eb2e8f9f7 175 rtc_init();
<> 144:ef7eb2e8f9f7 176 }
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 // Ensure coherency between overflow_cnt and timer
<> 144:ef7eb2e8f9f7 179 do {
<> 144:ef7eb2e8f9f7 180 ovf_cnt_1 = overflow_cnt;
<> 144:ef7eb2e8f9f7 181 ovf1 = MXC_RTCTMR->flags & MXC_F_RTC_FLAGS_OVERFLOW;
<> 144:ef7eb2e8f9f7 182 timer_cnt = MXC_RTCTMR->timer;
<> 144:ef7eb2e8f9f7 183 ovf2 = MXC_RTCTMR->flags & MXC_F_RTC_FLAGS_OVERFLOW;
<> 144:ef7eb2e8f9f7 184 ovf_cnt_2 = overflow_cnt;
<> 144:ef7eb2e8f9f7 185 } while ((ovf_cnt_1 != ovf_cnt_2) || (ovf1 != ovf2));
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 // Account for an unserviced interrupt
<> 144:ef7eb2e8f9f7 188 if (ovf1) {
<> 144:ef7eb2e8f9f7 189 ovf_cnt_1++;
<> 144:ef7eb2e8f9f7 190 }
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 return (timer_cnt >> SHIFT_AMT) + (ovf_cnt_1 << (32 - SHIFT_AMT));
<> 144:ef7eb2e8f9f7 193 }
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 //******************************************************************************
<> 144:ef7eb2e8f9f7 196 static uint64_t rtc_read64(void)
<> 144:ef7eb2e8f9f7 197 {
<> 144:ef7eb2e8f9f7 198 uint32_t ovf_cnt_1, ovf_cnt_2, timer_cnt;
<> 144:ef7eb2e8f9f7 199 uint32_t ovf1, ovf2;
<> 144:ef7eb2e8f9f7 200 uint64_t current_us;
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 // Make sure RTC is setup before trying to read
<> 144:ef7eb2e8f9f7 203 if (!rtc_inited) {
<> 144:ef7eb2e8f9f7 204 rtc_init();
<> 144:ef7eb2e8f9f7 205 }
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 // Ensure coherency between overflow_cnt and timer
<> 144:ef7eb2e8f9f7 208 do {
<> 144:ef7eb2e8f9f7 209 ovf_cnt_1 = overflow_cnt;
<> 144:ef7eb2e8f9f7 210 ovf1 = MXC_RTCTMR->flags & MXC_F_RTC_FLAGS_OVERFLOW;
<> 144:ef7eb2e8f9f7 211 timer_cnt = MXC_RTCTMR->timer;
<> 144:ef7eb2e8f9f7 212 ovf2 = MXC_RTCTMR->flags & MXC_F_RTC_FLAGS_OVERFLOW;
<> 144:ef7eb2e8f9f7 213 ovf_cnt_2 = overflow_cnt;
<> 144:ef7eb2e8f9f7 214 } while ((ovf_cnt_1 != ovf_cnt_2) || (ovf1 != ovf2));
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 // Account for an unserviced interrupt
<> 144:ef7eb2e8f9f7 217 if (ovf1) {
<> 144:ef7eb2e8f9f7 218 ovf_cnt_1++;
<> 144:ef7eb2e8f9f7 219 }
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 current_us = (((uint64_t)timer_cnt * 1000000) >> SHIFT_AMT) + (((uint64_t)ovf_cnt_1 * 1000000) << (32 - SHIFT_AMT));
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 return current_us;
<> 144:ef7eb2e8f9f7 224 }
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 //******************************************************************************
<> 144:ef7eb2e8f9f7 227 void rtc_write(time_t t)
<> 144:ef7eb2e8f9f7 228 {
<> 144:ef7eb2e8f9f7 229 // Make sure RTC is setup before accessing
<> 144:ef7eb2e8f9f7 230 if (!rtc_inited) {
<> 144:ef7eb2e8f9f7 231 rtc_init();
<> 144:ef7eb2e8f9f7 232 }
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 MXC_RTCTMR->ctrl &= ~MXC_F_RTC_CTRL_ENABLE; // disable the timer while updating
<> 144:ef7eb2e8f9f7 235 MXC_RTCTMR->timer = t << SHIFT_AMT;
<> 144:ef7eb2e8f9f7 236 overflow_cnt = t >> (32 - SHIFT_AMT);
<> 144:ef7eb2e8f9f7 237 MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_ENABLE; // enable the timer while updating
<> 144:ef7eb2e8f9f7 238 }
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 //******************************************************************************
<> 144:ef7eb2e8f9f7 241 void lp_ticker_set_interrupt(timestamp_t timestamp)
<> 144:ef7eb2e8f9f7 242 {
<> 144:ef7eb2e8f9f7 243 uint32_t comp_value;
<> 144:ef7eb2e8f9f7 244 uint64_t curr_ts64;
<> 144:ef7eb2e8f9f7 245 uint64_t ts64;
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 // Note: interrupts are disabled before this function is called.
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 // Disable the alarm while it is prepared
<> 144:ef7eb2e8f9f7 250 MXC_RTCTMR->inten &= ~MXC_F_RTC_INTEN_COMP0;
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 curr_ts64 = rtc_read64();
<> 144:ef7eb2e8f9f7 253 ts64 = (uint64_t)timestamp | (curr_ts64 & 0xFFFFFFFF00000000ULL);
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 // If this event is older than a recent window, it must be in the future
<> 144:ef7eb2e8f9f7 256 if ((ts64 < (curr_ts64 - WINDOW)) && ((curr_ts64 - WINDOW) < curr_ts64)) {
<> 144:ef7eb2e8f9f7 257 ts64 += 0x100000000ULL;
<> 144:ef7eb2e8f9f7 258 }
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 uint32_t timer = MXC_RTCTMR->timer;
<> 144:ef7eb2e8f9f7 261 if (ts64 <= curr_ts64) {
<> 144:ef7eb2e8f9f7 262 // This event has already occurred. Set the alarm to expire immediately.
<> 144:ef7eb2e8f9f7 263 comp_value = timer + 1;
<> 144:ef7eb2e8f9f7 264 } else {
<> 144:ef7eb2e8f9f7 265 comp_value = (ts64 << SHIFT_AMT) / 1000000;
<> 144:ef7eb2e8f9f7 266 }
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 // Ensure that the compare value is far enough in the future to guarantee the interrupt occurs.
<> 144:ef7eb2e8f9f7 269 if ((comp_value < (timer + 2)) && (comp_value > (timer - 10))) {
<> 144:ef7eb2e8f9f7 270 comp_value = timer + 2;
<> 144:ef7eb2e8f9f7 271 }
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 MXC_RTCTMR->comp[0] = comp_value;
<> 144:ef7eb2e8f9f7 274 MXC_RTCTMR->flags |= MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS;
<> 144:ef7eb2e8f9f7 275 MXC_RTCTMR->inten |= MXC_F_RTC_INTEN_COMP0; // enable the interrupt
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 // Enable wakeup from RTC
<> 144:ef7eb2e8f9f7 278 MXC_PWRSEQ->msk_flags &= ~MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0;
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 // Wait for pending transactions
<> 144:ef7eb2e8f9f7 281 while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
<> 144:ef7eb2e8f9f7 282 }
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 //******************************************************************************
<> 144:ef7eb2e8f9f7 285 inline void lp_ticker_disable_interrupt(void)
<> 144:ef7eb2e8f9f7 286 {
<> 144:ef7eb2e8f9f7 287 MXC_RTCTMR->inten &= ~MXC_F_RTC_INTEN_COMP0;
<> 144:ef7eb2e8f9f7 288 }
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 //******************************************************************************
<> 144:ef7eb2e8f9f7 291 inline void lp_ticker_clear_interrupt(void)
<> 144:ef7eb2e8f9f7 292 {
<> 144:ef7eb2e8f9f7 293 MXC_RTCTMR->flags |= MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS;
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 // Wait for pending transactions
<> 144:ef7eb2e8f9f7 296 while (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
<> 144:ef7eb2e8f9f7 297 }
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 //******************************************************************************
<> 144:ef7eb2e8f9f7 300 inline uint32_t lp_ticker_read(void)
<> 144:ef7eb2e8f9f7 301 {
<> 144:ef7eb2e8f9f7 302 return rtc_read64();
<> 144:ef7eb2e8f9f7 303 }