Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/drivers/fsl_flexbus.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125

Who changed what in which revision?

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<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 144:ef7eb2e8f9f7 3 * All rights reserved.
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 6 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 9 * of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 12 * list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 13 * other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 144:ef7eb2e8f9f7 16 * contributors may be used to endorse or promote products derived from this
<> 144:ef7eb2e8f9f7 17 * software without specific prior written permission.
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 29 */
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 #ifndef _FSL_FLEXBUS_H_
<> 144:ef7eb2e8f9f7 32 #define _FSL_FLEXBUS_H_
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #include "fsl_common.h"
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 /*!
<> 144:ef7eb2e8f9f7 37 * @addtogroup flexbus
<> 144:ef7eb2e8f9f7 38 * @{
<> 144:ef7eb2e8f9f7 39 */
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 /*! @file */
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /*******************************************************************************
<> 144:ef7eb2e8f9f7 44 * Definitions
<> 144:ef7eb2e8f9f7 45 ******************************************************************************/
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /*! @name Driver version */
<> 144:ef7eb2e8f9f7 48 /*@{*/
<> 144:ef7eb2e8f9f7 49 #define FSL_FLEXBUS_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
<> 144:ef7eb2e8f9f7 50 /*@}*/
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 /*!
<> 144:ef7eb2e8f9f7 53 * @brief Defines port size for FlexBus peripheral.
<> 144:ef7eb2e8f9f7 54 */
<> 144:ef7eb2e8f9f7 55 typedef enum _flexbus_port_size
<> 144:ef7eb2e8f9f7 56 {
<> 144:ef7eb2e8f9f7 57 kFLEXBUS_4Bytes = 0x00U, /*!< 32-bit port size */
<> 144:ef7eb2e8f9f7 58 kFLEXBUS_1Byte = 0x01U, /*!< 8-bit port size */
<> 144:ef7eb2e8f9f7 59 kFLEXBUS_2Bytes = 0x02U /*!< 16-bit port size */
<> 144:ef7eb2e8f9f7 60 } flexbus_port_size_t;
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /*!
<> 144:ef7eb2e8f9f7 63 * @brief Defines number of cycles to hold address and attributes for FlexBus peripheral.
<> 144:ef7eb2e8f9f7 64 */
<> 144:ef7eb2e8f9f7 65 typedef enum _flexbus_write_address_hold
<> 144:ef7eb2e8f9f7 66 {
<> 144:ef7eb2e8f9f7 67 kFLEXBUS_Hold1Cycle = 0x00U, /*!< Hold address and attributes one cycles after FB_CSn negates on writes */
<> 144:ef7eb2e8f9f7 68 kFLEXBUS_Hold2Cycles = 0x01U, /*!< Hold address and attributes two cycles after FB_CSn negates on writes */
<> 144:ef7eb2e8f9f7 69 kFLEXBUS_Hold3Cycles = 0x02U, /*!< Hold address and attributes three cycles after FB_CSn negates on writes */
<> 144:ef7eb2e8f9f7 70 kFLEXBUS_Hold4Cycles = 0x03U /*!< Hold address and attributes four cycles after FB_CSn negates on writes */
<> 144:ef7eb2e8f9f7 71 } flexbus_write_address_hold_t;
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 /*!
<> 144:ef7eb2e8f9f7 74 * @brief Defines number of cycles to hold address and attributes for FlexBus peripheral.
<> 144:ef7eb2e8f9f7 75 */
<> 144:ef7eb2e8f9f7 76 typedef enum _flexbus_read_address_hold
<> 144:ef7eb2e8f9f7 77 {
<> 144:ef7eb2e8f9f7 78 kFLEXBUS_Hold1Or0Cycles = 0x00U, /*!< Hold address and attributes 1 or 0 cycles on reads */
<> 144:ef7eb2e8f9f7 79 kFLEXBUS_Hold2Or1Cycles = 0x01U, /*!< Hold address and attributes 2 or 1 cycles on reads */
<> 144:ef7eb2e8f9f7 80 kFLEXBUS_Hold3Or2Cycle = 0x02U, /*!< Hold address and attributes 3 or 2 cycles on reads */
<> 144:ef7eb2e8f9f7 81 kFLEXBUS_Hold4Or3Cycle = 0x03U /*!< Hold address and attributes 4 or 3 cycles on reads */
<> 144:ef7eb2e8f9f7 82 } flexbus_read_address_hold_t;
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 /*!
<> 144:ef7eb2e8f9f7 85 * @brief Address setup for FlexBus peripheral.
<> 144:ef7eb2e8f9f7 86 */
<> 144:ef7eb2e8f9f7 87 typedef enum _flexbus_address_setup
<> 144:ef7eb2e8f9f7 88 {
<> 144:ef7eb2e8f9f7 89 kFLEXBUS_FirstRisingEdge = 0x00U, /*!< Assert FB_CSn on first rising clock edge after address is asserted */
<> 144:ef7eb2e8f9f7 90 kFLEXBUS_SecondRisingEdge = 0x01U, /*!< Assert FB_CSn on second rising clock edge after address is asserted */
<> 144:ef7eb2e8f9f7 91 kFLEXBUS_ThirdRisingEdge = 0x02U, /*!< Assert FB_CSn on third rising clock edge after address is asserted */
<> 144:ef7eb2e8f9f7 92 kFLEXBUS_FourthRisingEdge = 0x03U, /*!< Assert FB_CSn on fourth rising clock edge after address is asserted */
<> 144:ef7eb2e8f9f7 93 } flexbus_address_setup_t;
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 /*!
<> 144:ef7eb2e8f9f7 96 * @brief Defines byte-lane shift for FlexBus peripheral.
<> 144:ef7eb2e8f9f7 97 */
<> 144:ef7eb2e8f9f7 98 typedef enum _flexbus_bytelane_shift
<> 144:ef7eb2e8f9f7 99 {
<> 144:ef7eb2e8f9f7 100 kFLEXBUS_NotShifted = 0x00U, /*!< Not shifted. Data is left-justified on FB_AD */
<> 144:ef7eb2e8f9f7 101 kFLEXBUS_Shifted = 0x01U, /*!< Shifted. Data is right justified on FB_AD */
<> 144:ef7eb2e8f9f7 102 } flexbus_bytelane_shift_t;
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 /*!
<> 144:ef7eb2e8f9f7 105 * @brief Defines multiplex group1 valid signals.
<> 144:ef7eb2e8f9f7 106 */
<> 144:ef7eb2e8f9f7 107 typedef enum _flexbus_multiplex_group1_signal
<> 144:ef7eb2e8f9f7 108 {
<> 144:ef7eb2e8f9f7 109 kFLEXBUS_MultiplexGroup1_FB_ALE = 0x00U, /*!< FB_ALE */
<> 144:ef7eb2e8f9f7 110 kFLEXBUS_MultiplexGroup1_FB_CS1 = 0x01U, /*!< FB_CS1 */
<> 144:ef7eb2e8f9f7 111 kFLEXBUS_MultiplexGroup1_FB_TS = 0x02U, /*!< FB_TS */
<> 144:ef7eb2e8f9f7 112 } flexbus_multiplex_group1_t;
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 /*!
<> 144:ef7eb2e8f9f7 115 * @brief Defines multiplex group2 valid signals.
<> 144:ef7eb2e8f9f7 116 */
<> 144:ef7eb2e8f9f7 117 typedef enum _flexbus_multiplex_group2_signal
<> 144:ef7eb2e8f9f7 118 {
<> 144:ef7eb2e8f9f7 119 kFLEXBUS_MultiplexGroup2_FB_CS4 = 0x00U, /*!< FB_CS4 */
<> 144:ef7eb2e8f9f7 120 kFLEXBUS_MultiplexGroup2_FB_TSIZ0 = 0x01U, /*!< FB_TSIZ0 */
<> 144:ef7eb2e8f9f7 121 kFLEXBUS_MultiplexGroup2_FB_BE_31_24 = 0x02U, /*!< FB_BE_31_24 */
<> 144:ef7eb2e8f9f7 122 } flexbus_multiplex_group2_t;
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 /*!
<> 144:ef7eb2e8f9f7 125 * @brief Defines multiplex group3 valid signals.
<> 144:ef7eb2e8f9f7 126 */
<> 144:ef7eb2e8f9f7 127 typedef enum _flexbus_multiplex_group3_signal
<> 144:ef7eb2e8f9f7 128 {
<> 144:ef7eb2e8f9f7 129 kFLEXBUS_MultiplexGroup3_FB_CS5 = 0x00U, /*!< FB_CS5 */
<> 144:ef7eb2e8f9f7 130 kFLEXBUS_MultiplexGroup3_FB_TSIZ1 = 0x01U, /*!< FB_TSIZ1 */
<> 144:ef7eb2e8f9f7 131 kFLEXBUS_MultiplexGroup3_FB_BE_23_16 = 0x02U, /*!< FB_BE_23_16 */
<> 144:ef7eb2e8f9f7 132 } flexbus_multiplex_group3_t;
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 /*!
<> 144:ef7eb2e8f9f7 135 * @brief Defines multiplex group4 valid signals.
<> 144:ef7eb2e8f9f7 136 */
<> 144:ef7eb2e8f9f7 137 typedef enum _flexbus_multiplex_group4_signal
<> 144:ef7eb2e8f9f7 138 {
<> 144:ef7eb2e8f9f7 139 kFLEXBUS_MultiplexGroup4_FB_TBST = 0x00U, /*!< FB_TBST */
<> 144:ef7eb2e8f9f7 140 kFLEXBUS_MultiplexGroup4_FB_CS2 = 0x01U, /*!< FB_CS2 */
<> 144:ef7eb2e8f9f7 141 kFLEXBUS_MultiplexGroup4_FB_BE_15_8 = 0x02U, /*!< FB_BE_15_8 */
<> 144:ef7eb2e8f9f7 142 } flexbus_multiplex_group4_t;
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 /*!
<> 144:ef7eb2e8f9f7 145 * @brief Defines multiplex group5 valid signals.
<> 144:ef7eb2e8f9f7 146 */
<> 144:ef7eb2e8f9f7 147 typedef enum _flexbus_multiplex_group5_signal
<> 144:ef7eb2e8f9f7 148 {
<> 144:ef7eb2e8f9f7 149 kFLEXBUS_MultiplexGroup5_FB_TA = 0x00U, /*!< FB_TA */
<> 144:ef7eb2e8f9f7 150 kFLEXBUS_MultiplexGroup5_FB_CS3 = 0x01U, /*!< FB_CS3 */
<> 144:ef7eb2e8f9f7 151 kFLEXBUS_MultiplexGroup5_FB_BE_7_0 = 0x02U, /*!< FB_BE_7_0 */
<> 144:ef7eb2e8f9f7 152 } flexbus_multiplex_group5_t;
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 /*!
<> 144:ef7eb2e8f9f7 155 * @brief Configuration structure that the user needs to set.
<> 144:ef7eb2e8f9f7 156 */
<> 144:ef7eb2e8f9f7 157 typedef struct _flexbus_config
<> 144:ef7eb2e8f9f7 158 {
<> 144:ef7eb2e8f9f7 159 uint8_t chip; /*!< Chip FlexBus for validation */
<> 144:ef7eb2e8f9f7 160 uint8_t waitStates; /*!< Value of wait states */
<> 144:ef7eb2e8f9f7 161 uint32_t chipBaseAddress; /*!< Chip base address for using FlexBus */
<> 144:ef7eb2e8f9f7 162 uint32_t chipBaseAddressMask; /*!< Chip base address mask */
<> 144:ef7eb2e8f9f7 163 bool writeProtect; /*!< Write protected */
<> 144:ef7eb2e8f9f7 164 bool burstWrite; /*!< Burst-Write enable */
<> 144:ef7eb2e8f9f7 165 bool burstRead; /*!< Burst-Read enable */
<> 144:ef7eb2e8f9f7 166 bool byteEnableMode; /*!< Byte-enable mode support */
<> 144:ef7eb2e8f9f7 167 bool autoAcknowledge; /*!< Auto acknowledge setting */
<> 144:ef7eb2e8f9f7 168 bool extendTransferAddress; /*!< Extend transfer start/extend address latch enable */
<> 144:ef7eb2e8f9f7 169 bool secondaryWaitStates; /*!< Secondary wait states number */
<> 144:ef7eb2e8f9f7 170 flexbus_port_size_t portSize; /*!< Port size of transfer */
<> 144:ef7eb2e8f9f7 171 flexbus_bytelane_shift_t byteLaneShift; /*!< Byte-lane shift enable */
<> 144:ef7eb2e8f9f7 172 flexbus_write_address_hold_t writeAddressHold; /*!< Write address hold or deselect option */
<> 144:ef7eb2e8f9f7 173 flexbus_read_address_hold_t readAddressHold; /*!< Read address hold or deselect option */
<> 144:ef7eb2e8f9f7 174 flexbus_address_setup_t addressSetup; /*!< Address setup setting */
<> 144:ef7eb2e8f9f7 175 flexbus_multiplex_group1_t group1MultiplexControl; /*!< FlexBus Signal Group 1 Multiplex control */
<> 144:ef7eb2e8f9f7 176 flexbus_multiplex_group2_t group2MultiplexControl; /*!< FlexBus Signal Group 2 Multiplex control */
<> 144:ef7eb2e8f9f7 177 flexbus_multiplex_group3_t group3MultiplexControl; /*!< FlexBus Signal Group 3 Multiplex control */
<> 144:ef7eb2e8f9f7 178 flexbus_multiplex_group4_t group4MultiplexControl; /*!< FlexBus Signal Group 4 Multiplex control */
<> 144:ef7eb2e8f9f7 179 flexbus_multiplex_group5_t group5MultiplexControl; /*!< FlexBus Signal Group 5 Multiplex control */
<> 144:ef7eb2e8f9f7 180 } flexbus_config_t;
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 /*******************************************************************************
<> 144:ef7eb2e8f9f7 183 * API
<> 144:ef7eb2e8f9f7 184 ******************************************************************************/
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 #if defined(__cplusplus)
<> 144:ef7eb2e8f9f7 187 extern "C" {
<> 144:ef7eb2e8f9f7 188 #endif /* __cplusplus */
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 /*!
<> 144:ef7eb2e8f9f7 191 * @name FlexBus functional operation
<> 144:ef7eb2e8f9f7 192 * @{
<> 144:ef7eb2e8f9f7 193 */
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 /*!
<> 144:ef7eb2e8f9f7 196 * @brief Initializes and configures the FlexBus module.
<> 144:ef7eb2e8f9f7 197 *
<> 144:ef7eb2e8f9f7 198 * This function enables the clock gate for FlexBus module.
<> 144:ef7eb2e8f9f7 199 * Only chip 0 is validated and set to known values. Other chips are disabled.
<> 144:ef7eb2e8f9f7 200 * NOTE: In this function, certain parameters, depending on external memories, must
<> 144:ef7eb2e8f9f7 201 * be set before using FLEXBUS_Init() function.
<> 144:ef7eb2e8f9f7 202 * This example shows how to set up the uart_state_t and the
<> 144:ef7eb2e8f9f7 203 * flexbus_config_t parameters and how to call the FLEXBUS_Init function by passing
<> 144:ef7eb2e8f9f7 204 * in these parameters:
<> 144:ef7eb2e8f9f7 205 @code
<> 144:ef7eb2e8f9f7 206 flexbus_config_t flexbusConfig;
<> 144:ef7eb2e8f9f7 207 FLEXBUS_GetDefaultConfig(&flexbusConfig);
<> 144:ef7eb2e8f9f7 208 flexbusConfig.waitStates = 2U;
<> 144:ef7eb2e8f9f7 209 flexbusConfig.chipBaseAddress = 0x60000000U;
<> 144:ef7eb2e8f9f7 210 flexbusConfig.chipBaseAddressMask = 7U;
<> 144:ef7eb2e8f9f7 211 FLEXBUS_Init(FB, &flexbusConfig);
<> 144:ef7eb2e8f9f7 212 @endcode
<> 144:ef7eb2e8f9f7 213 *
<> 144:ef7eb2e8f9f7 214 * @param base FlexBus peripheral address.
<> 144:ef7eb2e8f9f7 215 * @param config Pointer to the configure structure
<> 144:ef7eb2e8f9f7 216 */
<> 144:ef7eb2e8f9f7 217 void FLEXBUS_Init(FB_Type *base, const flexbus_config_t *config);
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 /*!
<> 144:ef7eb2e8f9f7 220 * @brief De-initializes a FlexBus instance.
<> 144:ef7eb2e8f9f7 221 *
<> 144:ef7eb2e8f9f7 222 * This function disables the clock gate of the FlexBus module clock.
<> 144:ef7eb2e8f9f7 223 *
<> 144:ef7eb2e8f9f7 224 * @param base FlexBus peripheral address.
<> 144:ef7eb2e8f9f7 225 */
<> 144:ef7eb2e8f9f7 226 void FLEXBUS_Deinit(FB_Type *base);
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 /*!
<> 144:ef7eb2e8f9f7 229 * @brief Initializes the FlexBus configuration structure.
<> 144:ef7eb2e8f9f7 230 *
<> 144:ef7eb2e8f9f7 231 * This function initializes the FlexBus configuration structure to default value. The default
<> 144:ef7eb2e8f9f7 232 * values are:
<> 144:ef7eb2e8f9f7 233 @code
<> 144:ef7eb2e8f9f7 234 fbConfig->chip = 0;
<> 144:ef7eb2e8f9f7 235 fbConfig->writeProtect = 0;
<> 144:ef7eb2e8f9f7 236 fbConfig->burstWrite = 0;
<> 144:ef7eb2e8f9f7 237 fbConfig->burstRead = 0;
<> 144:ef7eb2e8f9f7 238 fbConfig->byteEnableMode = 0;
<> 144:ef7eb2e8f9f7 239 fbConfig->autoAcknowledge = true;
<> 144:ef7eb2e8f9f7 240 fbConfig->extendTransferAddress = 0;
<> 144:ef7eb2e8f9f7 241 fbConfig->secondaryWaitStates = 0;
<> 144:ef7eb2e8f9f7 242 fbConfig->byteLaneShift = kFLEXBUS_NotShifted;
<> 144:ef7eb2e8f9f7 243 fbConfig->writeAddressHold = kFLEXBUS_Hold1Cycle;
<> 144:ef7eb2e8f9f7 244 fbConfig->readAddressHold = kFLEXBUS_Hold1Or0Cycles;
<> 144:ef7eb2e8f9f7 245 fbConfig->addressSetup = kFLEXBUS_FirstRisingEdge;
<> 144:ef7eb2e8f9f7 246 fbConfig->portSize = kFLEXBUS_1Byte;
<> 144:ef7eb2e8f9f7 247 fbConfig->group1MultiplexControl = kFLEXBUS_MultiplexGroup1_FB_ALE;
<> 144:ef7eb2e8f9f7 248 fbConfig->group2MultiplexControl = kFLEXBUS_MultiplexGroup2_FB_CS4 ;
<> 144:ef7eb2e8f9f7 249 fbConfig->group3MultiplexControl = kFLEXBUS_MultiplexGroup3_FB_CS5;
<> 144:ef7eb2e8f9f7 250 fbConfig->group4MultiplexControl = kFLEXBUS_MultiplexGroup4_FB_TBST;
<> 144:ef7eb2e8f9f7 251 fbConfig->group5MultiplexControl = kFLEXBUS_MultiplexGroup5_FB_TA;
<> 144:ef7eb2e8f9f7 252 @endcode
<> 144:ef7eb2e8f9f7 253 * @param config Pointer to the initialization structure.
<> 144:ef7eb2e8f9f7 254 * @see FLEXBUS_Init
<> 144:ef7eb2e8f9f7 255 */
<> 144:ef7eb2e8f9f7 256 void FLEXBUS_GetDefaultConfig(flexbus_config_t *config);
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 /*! @}*/
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 #if defined(__cplusplus)
<> 144:ef7eb2e8f9f7 261 }
<> 144:ef7eb2e8f9f7 262 #endif /* __cplusplus */
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264 /*! @}*/
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 #endif /* _FSL_FLEXBUS_H_ */