Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

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targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/drivers/fsl_spi_dma.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 144:ef7eb2e8f9f7 3 * All rights reserved.
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 6 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 9 * of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 12 * list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 13 * other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 144:ef7eb2e8f9f7 16 * contributors may be used to endorse or promote products derived from this
<> 144:ef7eb2e8f9f7 17 * software without specific prior written permission.
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 29 */
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 #include "fsl_spi_dma.h"
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 /*******************************************************************************
<> 144:ef7eb2e8f9f7 34 * Definitons
<> 144:ef7eb2e8f9f7 35 ******************************************************************************/
<> 144:ef7eb2e8f9f7 36 /*<! Structure definition for spi_dma_private_handle_t. The structure is private. */
<> 144:ef7eb2e8f9f7 37 typedef struct _spi_dma_private_handle
<> 144:ef7eb2e8f9f7 38 {
<> 144:ef7eb2e8f9f7 39 SPI_Type *base;
<> 144:ef7eb2e8f9f7 40 spi_dma_handle_t *handle;
<> 144:ef7eb2e8f9f7 41 } spi_dma_private_handle_t;
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /*! @brief SPI transfer state, which is used for SPI transactiaonl APIs' internal state. */
<> 144:ef7eb2e8f9f7 44 enum _spi_dma_states_t
<> 144:ef7eb2e8f9f7 45 {
<> 144:ef7eb2e8f9f7 46 kSPI_Idle = 0x0, /*!< SPI is idle state */
<> 144:ef7eb2e8f9f7 47 kSPI_Busy /*!< SPI is busy tranferring data. */
<> 144:ef7eb2e8f9f7 48 };
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 /*<! Private handle only used for internally. */
<> 144:ef7eb2e8f9f7 51 static spi_dma_private_handle_t s_dmaPrivateHandle[FSL_FEATURE_SOC_SPI_COUNT];
<> 144:ef7eb2e8f9f7 52 /*******************************************************************************
<> 144:ef7eb2e8f9f7 53 * Prototypes
<> 144:ef7eb2e8f9f7 54 ******************************************************************************/
<> 144:ef7eb2e8f9f7 55 /*!
<> 144:ef7eb2e8f9f7 56 * @brief Get the instance for SPI module.
<> 144:ef7eb2e8f9f7 57 *
<> 144:ef7eb2e8f9f7 58 * @param base SPI base address
<> 144:ef7eb2e8f9f7 59 */
<> 144:ef7eb2e8f9f7 60 extern uint32_t SPI_GetInstance(SPI_Type *base);
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /*!
<> 144:ef7eb2e8f9f7 63 * @brief DMA callback function for SPI send transfer.
<> 144:ef7eb2e8f9f7 64 *
<> 144:ef7eb2e8f9f7 65 * @param handle DMA handle pointer.
<> 144:ef7eb2e8f9f7 66 * @param userData User data for DMA callback function.
<> 144:ef7eb2e8f9f7 67 */
<> 144:ef7eb2e8f9f7 68 static void SPI_TxDMACallback(dma_handle_t *handle, void *userData);
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 /*!
<> 144:ef7eb2e8f9f7 71 * @brief DMA callback function for SPI receive transfer.
<> 144:ef7eb2e8f9f7 72 *
<> 144:ef7eb2e8f9f7 73 * @param handle DMA handle pointer.
<> 144:ef7eb2e8f9f7 74 * @param userData User data for DMA callback function.
<> 144:ef7eb2e8f9f7 75 */
<> 144:ef7eb2e8f9f7 76 static void SPI_RxDMACallback(dma_handle_t *handle, void *userData);
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 /*******************************************************************************
<> 144:ef7eb2e8f9f7 79 * Variables
<> 144:ef7eb2e8f9f7 80 ******************************************************************************/
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 /* Dummy data used to send */
<> 144:ef7eb2e8f9f7 83 static const uint8_t s_dummyData = SPI_DUMMYDATA;
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 /*******************************************************************************
<> 144:ef7eb2e8f9f7 86 * Code
<> 144:ef7eb2e8f9f7 87 ******************************************************************************/
<> 144:ef7eb2e8f9f7 88 static void SPI_TxDMACallback(dma_handle_t *handle, void *userData)
<> 144:ef7eb2e8f9f7 89 {
<> 144:ef7eb2e8f9f7 90 spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData;
<> 144:ef7eb2e8f9f7 91 spi_dma_handle_t *spiHandle = privHandle->handle;
<> 144:ef7eb2e8f9f7 92 SPI_Type *base = privHandle->base;
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 /* Disable Tx dma */
<> 144:ef7eb2e8f9f7 95 SPI_EnableDMA(base, kSPI_TxDmaEnable, false);
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 /* Stop DMA tranfer */
<> 144:ef7eb2e8f9f7 98 DMA_StopTransfer(spiHandle->txHandle);
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 /* change the state */
<> 144:ef7eb2e8f9f7 101 spiHandle->txInProgress = false;
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 /* All finished, call the callback */
<> 144:ef7eb2e8f9f7 104 if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false))
<> 144:ef7eb2e8f9f7 105 {
<> 144:ef7eb2e8f9f7 106 spiHandle->state = kSPI_Idle;
<> 144:ef7eb2e8f9f7 107 if (spiHandle->callback)
<> 144:ef7eb2e8f9f7 108 {
<> 144:ef7eb2e8f9f7 109 (spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData);
<> 144:ef7eb2e8f9f7 110 }
<> 144:ef7eb2e8f9f7 111 }
<> 144:ef7eb2e8f9f7 112 }
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 static void SPI_RxDMACallback(dma_handle_t *handle, void *userData)
<> 144:ef7eb2e8f9f7 115 {
<> 144:ef7eb2e8f9f7 116 spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData;
<> 144:ef7eb2e8f9f7 117 spi_dma_handle_t *spiHandle = privHandle->handle;
<> 144:ef7eb2e8f9f7 118 SPI_Type *base = privHandle->base;
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 /* Disable Tx dma */
<> 144:ef7eb2e8f9f7 121 SPI_EnableDMA(base, kSPI_RxDmaEnable, false);
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 /* Stop DMA tranfer */
<> 144:ef7eb2e8f9f7 124 DMA_StopTransfer(spiHandle->rxHandle);
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 /* change the state */
<> 144:ef7eb2e8f9f7 127 spiHandle->rxInProgress = false;
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 /* All finished, call the callback */
<> 144:ef7eb2e8f9f7 130 if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false))
<> 144:ef7eb2e8f9f7 131 {
<> 144:ef7eb2e8f9f7 132 spiHandle->state = kSPI_Idle;
<> 144:ef7eb2e8f9f7 133 if (spiHandle->callback)
<> 144:ef7eb2e8f9f7 134 {
<> 144:ef7eb2e8f9f7 135 (spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData);
<> 144:ef7eb2e8f9f7 136 }
<> 144:ef7eb2e8f9f7 137 }
<> 144:ef7eb2e8f9f7 138 }
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 void SPI_MasterTransferCreateHandleDMA(SPI_Type *base,
<> 144:ef7eb2e8f9f7 141 spi_dma_handle_t *handle,
<> 144:ef7eb2e8f9f7 142 spi_dma_callback_t callback,
<> 144:ef7eb2e8f9f7 143 void *userData,
<> 144:ef7eb2e8f9f7 144 dma_handle_t *txHandle,
<> 144:ef7eb2e8f9f7 145 dma_handle_t *rxHandle)
<> 144:ef7eb2e8f9f7 146 {
<> 144:ef7eb2e8f9f7 147 assert(handle);
<> 144:ef7eb2e8f9f7 148 dma_transfer_config_t config = {0};
<> 144:ef7eb2e8f9f7 149 uint32_t instance = SPI_GetInstance(base);
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 /* Set spi base to handle */
<> 144:ef7eb2e8f9f7 152 handle->txHandle = txHandle;
<> 144:ef7eb2e8f9f7 153 handle->rxHandle = rxHandle;
<> 144:ef7eb2e8f9f7 154 handle->callback = callback;
<> 144:ef7eb2e8f9f7 155 handle->userData = userData;
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 /* Set SPI state to idle */
<> 144:ef7eb2e8f9f7 158 handle->state = kSPI_Idle;
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 /* Set handle to global state */
<> 144:ef7eb2e8f9f7 161 s_dmaPrivateHandle[instance].base = base;
<> 144:ef7eb2e8f9f7 162 s_dmaPrivateHandle[instance].handle = handle;
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 /* Compute internal state */
<> 144:ef7eb2e8f9f7 165 #if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && (FSL_FEATURE_SPI_16BIT_TRANSFERS)
<> 144:ef7eb2e8f9f7 166 handle->bytesPerFrame = ((base->C2 & SPI_C2_SPIMODE_MASK) >> SPI_C2_SPIMODE_SHIFT) + 1U;
<> 144:ef7eb2e8f9f7 167 #else
<> 144:ef7eb2e8f9f7 168 handle->bytesPerFrame = 1U;
<> 144:ef7eb2e8f9f7 169 #endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 #if defined(FSL_FEATURE_SPI_HAS_FIFO) && (FSL_FEATURE_SPI_HAS_FIFO)
<> 144:ef7eb2e8f9f7 172 /* If using DMA, disable FIFO, as the FIFO may cause data loss if the data size is not integer
<> 144:ef7eb2e8f9f7 173 times of 2bytes. As SPI cannot set watermark to 0, only can set to 1/2 FIFO size or 3/4 FIFO
<> 144:ef7eb2e8f9f7 174 size. */
<> 144:ef7eb2e8f9f7 175 if (FSL_FEATURE_SPI_FIFO_SIZEn(base) != 0)
<> 144:ef7eb2e8f9f7 176 {
<> 144:ef7eb2e8f9f7 177 base->C3 &= ~SPI_C3_FIFOMODE_MASK;
<> 144:ef7eb2e8f9f7 178 }
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 #endif /* FSL_FEATURE_SPI_HAS_FIFO */
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 /* Set the non-change attribute for Tx DMA transfer, to improve efficiency */
<> 144:ef7eb2e8f9f7 183 config.destAddr = SPI_GetDataRegisterAddress(base);
<> 144:ef7eb2e8f9f7 184 config.enableDestIncrement = false;
<> 144:ef7eb2e8f9f7 185 config.enableSrcIncrement = true;
<> 144:ef7eb2e8f9f7 186 if (handle->bytesPerFrame == 1U)
<> 144:ef7eb2e8f9f7 187 {
<> 144:ef7eb2e8f9f7 188 config.srcSize = kDMA_Transfersize8bits;
<> 144:ef7eb2e8f9f7 189 config.destSize = kDMA_Transfersize8bits;
<> 144:ef7eb2e8f9f7 190 }
<> 144:ef7eb2e8f9f7 191 else
<> 144:ef7eb2e8f9f7 192 {
<> 144:ef7eb2e8f9f7 193 config.srcSize = kDMA_Transfersize16bits;
<> 144:ef7eb2e8f9f7 194 config.destSize = kDMA_Transfersize16bits;
<> 144:ef7eb2e8f9f7 195 }
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 DMA_SubmitTransfer(handle->txHandle, &config, true);
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 /* Set non-change attribute for Rx DMA */
<> 144:ef7eb2e8f9f7 200 config.srcAddr = SPI_GetDataRegisterAddress(base);
<> 144:ef7eb2e8f9f7 201 config.destAddr = 0U;
<> 144:ef7eb2e8f9f7 202 config.enableDestIncrement = true;
<> 144:ef7eb2e8f9f7 203 config.enableSrcIncrement = false;
<> 144:ef7eb2e8f9f7 204 DMA_SubmitTransfer(handle->rxHandle, &config, true);
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /* Install callback for Tx dma channel */
<> 144:ef7eb2e8f9f7 207 DMA_SetCallback(handle->txHandle, SPI_TxDMACallback, &s_dmaPrivateHandle[instance]);
<> 144:ef7eb2e8f9f7 208 DMA_SetCallback(handle->rxHandle, SPI_RxDMACallback, &s_dmaPrivateHandle[instance]);
<> 144:ef7eb2e8f9f7 209 }
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer)
<> 144:ef7eb2e8f9f7 212 {
<> 144:ef7eb2e8f9f7 213 assert(handle && xfer);
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 dma_transfer_config_t config = {0};
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 /* Check if the device is busy */
<> 144:ef7eb2e8f9f7 218 if (handle->state == kSPI_Busy)
<> 144:ef7eb2e8f9f7 219 {
<> 144:ef7eb2e8f9f7 220 return kStatus_SPI_Busy;
<> 144:ef7eb2e8f9f7 221 }
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 /* Check if input parameter invalid */
<> 144:ef7eb2e8f9f7 224 if (((xfer->txData == NULL) && (xfer->rxData == NULL)) || (xfer->dataSize == 0U))
<> 144:ef7eb2e8f9f7 225 {
<> 144:ef7eb2e8f9f7 226 return kStatus_InvalidArgument;
<> 144:ef7eb2e8f9f7 227 }
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 /* Disable SPI and then enable it, this is used to clear S register*/
<> 144:ef7eb2e8f9f7 230 SPI_Enable(base, false);
<> 144:ef7eb2e8f9f7 231 SPI_Enable(base, true);
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 /* Configure tx transfer DMA */
<> 144:ef7eb2e8f9f7 234 config.destAddr = SPI_GetDataRegisterAddress(base);
<> 144:ef7eb2e8f9f7 235 config.enableDestIncrement = false;
<> 144:ef7eb2e8f9f7 236 if (handle->bytesPerFrame == 1U)
<> 144:ef7eb2e8f9f7 237 {
<> 144:ef7eb2e8f9f7 238 config.srcSize = kDMA_Transfersize8bits;
<> 144:ef7eb2e8f9f7 239 config.destSize = kDMA_Transfersize8bits;
<> 144:ef7eb2e8f9f7 240 }
<> 144:ef7eb2e8f9f7 241 else
<> 144:ef7eb2e8f9f7 242 {
<> 144:ef7eb2e8f9f7 243 config.srcSize = kDMA_Transfersize16bits;
<> 144:ef7eb2e8f9f7 244 config.destSize = kDMA_Transfersize16bits;
<> 144:ef7eb2e8f9f7 245 }
<> 144:ef7eb2e8f9f7 246 config.transferSize = xfer->dataSize;
<> 144:ef7eb2e8f9f7 247 /* Configure DMA channel */
<> 144:ef7eb2e8f9f7 248 if (xfer->txData)
<> 144:ef7eb2e8f9f7 249 {
<> 144:ef7eb2e8f9f7 250 config.enableSrcIncrement = true;
<> 144:ef7eb2e8f9f7 251 config.srcAddr = (uint32_t)(xfer->txData);
<> 144:ef7eb2e8f9f7 252 }
<> 144:ef7eb2e8f9f7 253 else
<> 144:ef7eb2e8f9f7 254 {
<> 144:ef7eb2e8f9f7 255 /* Disable the source increasement and source set to dummyData */
<> 144:ef7eb2e8f9f7 256 config.enableSrcIncrement = false;
<> 144:ef7eb2e8f9f7 257 config.srcAddr = (uint32_t)(&s_dummyData);
<> 144:ef7eb2e8f9f7 258 }
<> 144:ef7eb2e8f9f7 259 DMA_SubmitTransfer(handle->txHandle, &config, true);
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 /* Handle rx transfer */
<> 144:ef7eb2e8f9f7 262 if (xfer->rxData)
<> 144:ef7eb2e8f9f7 263 {
<> 144:ef7eb2e8f9f7 264 /* Set the source address */
<> 144:ef7eb2e8f9f7 265 DMA_SetDestinationAddress(handle->rxHandle->base, handle->rxHandle->channel, (uint32_t)(xfer->rxData));
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 /* Set the transfer size */
<> 144:ef7eb2e8f9f7 268 DMA_SetTransferSize(handle->rxHandle->base, handle->rxHandle->channel, xfer->dataSize);
<> 144:ef7eb2e8f9f7 269 }
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 /* Change the state of handle */
<> 144:ef7eb2e8f9f7 272 handle->transferSize = xfer->dataSize;
<> 144:ef7eb2e8f9f7 273 handle->state = kSPI_Busy;
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275 /* Start Rx transfer if needed */
<> 144:ef7eb2e8f9f7 276 if (xfer->rxData)
<> 144:ef7eb2e8f9f7 277 {
<> 144:ef7eb2e8f9f7 278 handle->rxInProgress = true;
<> 144:ef7eb2e8f9f7 279 SPI_EnableDMA(base, kSPI_RxDmaEnable, true);
<> 144:ef7eb2e8f9f7 280 DMA_StartTransfer(handle->rxHandle);
<> 144:ef7eb2e8f9f7 281 }
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 /* Always start Tx transfer */
<> 144:ef7eb2e8f9f7 284 handle->txInProgress = true;
<> 144:ef7eb2e8f9f7 285 SPI_EnableDMA(base, kSPI_TxDmaEnable, true);
<> 144:ef7eb2e8f9f7 286 DMA_StartTransfer(handle->txHandle);
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 return kStatus_Success;
<> 144:ef7eb2e8f9f7 289 }
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 status_t SPI_MasterTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count)
<> 144:ef7eb2e8f9f7 292 {
<> 144:ef7eb2e8f9f7 293 assert(handle);
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 status_t status = kStatus_Success;
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 if (handle->state != kSPI_Busy)
<> 144:ef7eb2e8f9f7 298 {
<> 144:ef7eb2e8f9f7 299 status = kStatus_NoTransferInProgress;
<> 144:ef7eb2e8f9f7 300 }
<> 144:ef7eb2e8f9f7 301 else
<> 144:ef7eb2e8f9f7 302 {
<> 144:ef7eb2e8f9f7 303 if (handle->rxInProgress)
<> 144:ef7eb2e8f9f7 304 {
<> 144:ef7eb2e8f9f7 305 *count = handle->transferSize - DMA_GetRemainingBytes(handle->rxHandle->base, handle->rxHandle->channel);
<> 144:ef7eb2e8f9f7 306 }
<> 144:ef7eb2e8f9f7 307 else
<> 144:ef7eb2e8f9f7 308 {
<> 144:ef7eb2e8f9f7 309 *count = handle->transferSize - DMA_GetRemainingBytes(handle->txHandle->base, handle->txHandle->channel);
<> 144:ef7eb2e8f9f7 310 }
<> 144:ef7eb2e8f9f7 311 }
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 return status;
<> 144:ef7eb2e8f9f7 314 }
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle)
<> 144:ef7eb2e8f9f7 317 {
<> 144:ef7eb2e8f9f7 318 assert(handle);
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320 /* Disable dma */
<> 144:ef7eb2e8f9f7 321 DMA_StopTransfer(handle->txHandle);
<> 144:ef7eb2e8f9f7 322 DMA_StopTransfer(handle->rxHandle);
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 /* Disable DMA enable bit */
<> 144:ef7eb2e8f9f7 325 SPI_EnableDMA(base, kSPI_DmaAllEnable, false);
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 /* Set the handle state */
<> 144:ef7eb2e8f9f7 328 handle->txInProgress = false;
<> 144:ef7eb2e8f9f7 329 handle->rxInProgress = false;
<> 144:ef7eb2e8f9f7 330 handle->state = kSPI_Idle;
<> 144:ef7eb2e8f9f7 331 }