Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/drivers/fsl_spi.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 144:ef7eb2e8f9f7 3 * All rights reserved.
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 6 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 9 * of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 12 * list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 13 * other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 144:ef7eb2e8f9f7 16 * contributors may be used tom endorse or promote products derived from this
<> 144:ef7eb2e8f9f7 17 * software without specific prior written permission.
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 29 */
<> 144:ef7eb2e8f9f7 30 #ifndef _FSL_SPI_H_
<> 144:ef7eb2e8f9f7 31 #define _FSL_SPI_H_
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 #include "fsl_common.h"
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 /*!
<> 144:ef7eb2e8f9f7 36 * @addtogroup spi_driver
<> 144:ef7eb2e8f9f7 37 * @{
<> 144:ef7eb2e8f9f7 38 */
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 /*******************************************************************************
<> 144:ef7eb2e8f9f7 42 * Definitions
<> 144:ef7eb2e8f9f7 43 ******************************************************************************/
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 /*! @name Driver version */
<> 144:ef7eb2e8f9f7 46 /*@{*/
<> 144:ef7eb2e8f9f7 47 /*! @brief SPI driver version 2.0.1. */
<> 144:ef7eb2e8f9f7 48 #define FSL_SPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
<> 144:ef7eb2e8f9f7 49 /*@}*/
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 #ifndef SPI_DUMMYDATA
<> 144:ef7eb2e8f9f7 52 /*! @brief SPI dummy transfer data, the data is sent while txBuff is NULL. */
<> 144:ef7eb2e8f9f7 53 #define SPI_DUMMYDATA (0xFFU)
<> 144:ef7eb2e8f9f7 54 #endif
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 /*! @brief Return status for the SPI driver.*/
<> 144:ef7eb2e8f9f7 57 enum _spi_status
<> 144:ef7eb2e8f9f7 58 {
<> 144:ef7eb2e8f9f7 59 kStatus_SPI_Busy = MAKE_STATUS(kStatusGroup_SPI, 0), /*!< SPI bus is busy */
<> 144:ef7eb2e8f9f7 60 kStatus_SPI_Idle = MAKE_STATUS(kStatusGroup_SPI, 1), /*!< SPI is idle */
<> 144:ef7eb2e8f9f7 61 kStatus_SPI_Error = MAKE_STATUS(kStatusGroup_SPI, 2) /*!< SPI error */
<> 144:ef7eb2e8f9f7 62 };
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 /*! @brief SPI clock polarity configuration.*/
<> 144:ef7eb2e8f9f7 65 typedef enum _spi_clock_polarity
<> 144:ef7eb2e8f9f7 66 {
<> 144:ef7eb2e8f9f7 67 kSPI_ClockPolarityActiveHigh = 0x0U, /*!< Active-high SPI clock (idles low). */
<> 144:ef7eb2e8f9f7 68 kSPI_ClockPolarityActiveLow /*!< Active-low SPI clock (idles high). */
<> 144:ef7eb2e8f9f7 69 } spi_clock_polarity_t;
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 /*! @brief SPI clock phase configuration.*/
<> 144:ef7eb2e8f9f7 72 typedef enum _spi_clock_phase
<> 144:ef7eb2e8f9f7 73 {
<> 144:ef7eb2e8f9f7 74 kSPI_ClockPhaseFirstEdge = 0x0U, /*!< First edge on SPSCK occurs at the middle of the first
<> 144:ef7eb2e8f9f7 75 * cycle of a data transfer. */
<> 144:ef7eb2e8f9f7 76 kSPI_ClockPhaseSecondEdge /*!< First edge on SPSCK occurs at the start of the
<> 144:ef7eb2e8f9f7 77 * first cycle of a data transfer. */
<> 144:ef7eb2e8f9f7 78 } spi_clock_phase_t;
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 /*! @brief SPI data shifter direction options.*/
<> 144:ef7eb2e8f9f7 81 typedef enum _spi_shift_direction
<> 144:ef7eb2e8f9f7 82 {
<> 144:ef7eb2e8f9f7 83 kSPI_MsbFirst = 0x0U, /*!< Data transfers start with most significant bit. */
<> 144:ef7eb2e8f9f7 84 kSPI_LsbFirst /*!< Data transfers start with least significant bit. */
<> 144:ef7eb2e8f9f7 85 } spi_shift_direction_t;
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 /*! @brief SPI slave select output mode options.*/
<> 144:ef7eb2e8f9f7 88 typedef enum _spi_ss_output_mode
<> 144:ef7eb2e8f9f7 89 {
<> 144:ef7eb2e8f9f7 90 kSPI_SlaveSelectAsGpio = 0x0U, /*!< Slave select pin configured as GPIO. */
<> 144:ef7eb2e8f9f7 91 kSPI_SlaveSelectFaultInput = 0x2U, /*!< Slave select pin configured for fault detection. */
<> 144:ef7eb2e8f9f7 92 kSPI_SlaveSelectAutomaticOutput = 0x3U /*!< Slave select pin configured for automatic SPI output. */
<> 144:ef7eb2e8f9f7 93 } spi_ss_output_mode_t;
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 /*! @brief SPI pin mode options.*/
<> 144:ef7eb2e8f9f7 96 typedef enum _spi_pin_mode
<> 144:ef7eb2e8f9f7 97 {
<> 144:ef7eb2e8f9f7 98 kSPI_PinModeNormal = 0x0U, /*!< Pins operate in normal, single-direction mode.*/
<> 144:ef7eb2e8f9f7 99 kSPI_PinModeInput = 0x1U, /*!< Bidirectional mode. Master: MOSI pin is input;
<> 144:ef7eb2e8f9f7 100 * Slave: MISO pin is input. */
<> 144:ef7eb2e8f9f7 101 kSPI_PinModeOutput = 0x3U /*!< Bidirectional mode. Master: MOSI pin is output;
<> 144:ef7eb2e8f9f7 102 * Slave: MISO pin is output. */
<> 144:ef7eb2e8f9f7 103 } spi_pin_mode_t;
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 /*! @brief SPI data length mode options.*/
<> 144:ef7eb2e8f9f7 106 typedef enum _spi_data_bitcount_mode
<> 144:ef7eb2e8f9f7 107 {
<> 144:ef7eb2e8f9f7 108 kSPI_8BitMode = 0x0U, /*!< 8-bit data transmission mode*/
<> 144:ef7eb2e8f9f7 109 kSPI_16BitMode /*!< 16-bit data transmission mode*/
<> 144:ef7eb2e8f9f7 110 } spi_data_bitcount_mode_t;
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 /*! @brief SPI interrupt sources.*/
<> 144:ef7eb2e8f9f7 113 enum _spi_interrupt_enable
<> 144:ef7eb2e8f9f7 114 {
<> 144:ef7eb2e8f9f7 115 kSPI_RxFullAndModfInterruptEnable = 0x1U, /*!< Receive buffer full (SPRF) and mode fault (MODF) interrupt */
<> 144:ef7eb2e8f9f7 116 kSPI_TxEmptyInterruptEnable = 0x2U, /*!< Transmit buffer empty interrupt */
<> 144:ef7eb2e8f9f7 117 kSPI_MatchInterruptEnable = 0x4U, /*!< Match interrupt */
<> 144:ef7eb2e8f9f7 118 #if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
<> 144:ef7eb2e8f9f7 119 kSPI_RxFifoNearFullInterruptEnable = 0x8U, /*!< Receive FIFO nearly full interrupt */
<> 144:ef7eb2e8f9f7 120 kSPI_TxFifoNearEmptyInterruptEnable = 0x10U, /*!< Transmit FIFO nearly empty interrupt */
<> 144:ef7eb2e8f9f7 121 #endif /* FSL_FEATURE_SPI_HAS_FIFO */
<> 144:ef7eb2e8f9f7 122 };
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 /*! @brief SPI status flags.*/
<> 144:ef7eb2e8f9f7 125 enum _spi_flags
<> 144:ef7eb2e8f9f7 126 {
<> 144:ef7eb2e8f9f7 127 kSPI_RxBufferFullFlag = SPI_S_SPRF_MASK, /*!< Read buffer full flag */
<> 144:ef7eb2e8f9f7 128 kSPI_MatchFlag = SPI_S_SPMF_MASK, /*!< Match flag */
<> 144:ef7eb2e8f9f7 129 kSPI_TxBufferEmptyFlag = SPI_S_SPTEF_MASK, /*!< Transmit buffer empty flag */
<> 144:ef7eb2e8f9f7 130 kSPI_ModeFaultFlag = SPI_S_MODF_MASK, /*!< Mode fault flag */
<> 144:ef7eb2e8f9f7 131 #if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
<> 144:ef7eb2e8f9f7 132 kSPI_RxFifoNearFullFlag = SPI_S_RNFULLF_MASK, /*!< Rx FIFO near full */
<> 144:ef7eb2e8f9f7 133 kSPI_TxFifoNearEmptyFlag = SPI_S_TNEAREF_MASK, /*!< Tx FIFO near empty */
<> 144:ef7eb2e8f9f7 134 kSPI_TxFifoFullFlag = SPI_S_TXFULLF_MASK, /*!< Tx FIFO full */
<> 144:ef7eb2e8f9f7 135 kSPI_RxFifoEmptyFlag = SPI_S_RFIFOEF_MASK, /*!< Rx FIFO empty */
<> 144:ef7eb2e8f9f7 136 kSPI_TxFifoError = SPI_CI_TXFERR_MASK << 8U, /*!< Tx FIFO error */
<> 144:ef7eb2e8f9f7 137 kSPI_RxFifoError = SPI_CI_RXFERR_MASK << 8U, /*!< Rx FIFO error */
<> 144:ef7eb2e8f9f7 138 kSPI_TxOverflow = SPI_CI_TXFOF_MASK << 8U, /*!< Tx FIFO Overflow */
<> 144:ef7eb2e8f9f7 139 kSPI_RxOverflow = SPI_CI_RXFOF_MASK << 8U /*!< Rx FIFO Overflow */
<> 144:ef7eb2e8f9f7 140 #endif /* FSL_FEATURE_SPI_HAS_FIFO */
<> 144:ef7eb2e8f9f7 141 };
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 #if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
<> 144:ef7eb2e8f9f7 144 /*! @brief SPI FIFO write-1-to-clear interrupt flags.*/
<> 144:ef7eb2e8f9f7 145 typedef enum _spi_w1c_interrupt
<> 144:ef7eb2e8f9f7 146 {
<> 144:ef7eb2e8f9f7 147 kSPI_RxFifoFullClearInterrupt = SPI_CI_SPRFCI_MASK, /*!< Receive FIFO full interrupt */
<> 144:ef7eb2e8f9f7 148 kSPI_TxFifoEmptyClearInterrupt = SPI_CI_SPTEFCI_MASK, /*!< Transmit FIFO empty interrupt */
<> 144:ef7eb2e8f9f7 149 kSPI_RxNearFullClearInterrupt = SPI_CI_RNFULLFCI_MASK, /*!< Receive FIFO nearly full interrupt */
<> 144:ef7eb2e8f9f7 150 kSPI_TxNearEmptyClearInterrupt = SPI_CI_TNEAREFCI_MASK /*!< Transmit FIFO nearly empty interrupt */
<> 144:ef7eb2e8f9f7 151 } spi_w1c_interrupt_t;
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 /*! @brief SPI TX FIFO watermark settings.*/
<> 144:ef7eb2e8f9f7 154 typedef enum _spi_txfifo_watermark
<> 144:ef7eb2e8f9f7 155 {
<> 144:ef7eb2e8f9f7 156 kSPI_TxFifoOneFourthEmpty = 0, /*!< SPI tx watermark at 1/4 FIFO size */
<> 144:ef7eb2e8f9f7 157 kSPI_TxFifoOneHalfEmpty = 1 /*!< SPI tx watermark at 1/2 FIFO size */
<> 144:ef7eb2e8f9f7 158 } spi_txfifo_watermark_t;
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 /*! @brief SPI RX FIFO watermark settings.*/
<> 144:ef7eb2e8f9f7 161 typedef enum _spi_rxfifo_watermark
<> 144:ef7eb2e8f9f7 162 {
<> 144:ef7eb2e8f9f7 163 kSPI_RxFifoThreeFourthsFull = 0, /*!< SPI rx watermark at 3/4 FIFO size */
<> 144:ef7eb2e8f9f7 164 kSPI_RxFifoOneHalfFull = 1 /*!< SPI rx watermark at 1/2 FIFO size */
<> 144:ef7eb2e8f9f7 165 } spi_rxfifo_watermark_t;
<> 144:ef7eb2e8f9f7 166 #endif /* FSL_FEATURE_SPI_HAS_FIFO */
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 #if defined(FSL_FEATURE_SPI_HAS_DMA_SUPPORT) && FSL_FEATURE_SPI_HAS_DMA_SUPPORT
<> 144:ef7eb2e8f9f7 169 /*! @brief SPI DMA source*/
<> 144:ef7eb2e8f9f7 170 enum _spi_dma_enable_t
<> 144:ef7eb2e8f9f7 171 {
<> 144:ef7eb2e8f9f7 172 kSPI_TxDmaEnable = SPI_C2_TXDMAE_MASK, /*!< Tx DMA request source */
<> 144:ef7eb2e8f9f7 173 kSPI_RxDmaEnable = SPI_C2_RXDMAE_MASK, /*!< Rx DMA request source */
<> 144:ef7eb2e8f9f7 174 kSPI_DmaAllEnable = (SPI_C2_TXDMAE_MASK | SPI_C2_RXDMAE_MASK) /*!< All DMA request source*/
<> 144:ef7eb2e8f9f7 175 };
<> 144:ef7eb2e8f9f7 176 #endif /* FSL_FEATURE_SPI_HAS_DMA_SUPPORT */
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 /*! @brief SPI master user configure structure.*/
<> 144:ef7eb2e8f9f7 179 typedef struct _spi_master_config
<> 144:ef7eb2e8f9f7 180 {
<> 144:ef7eb2e8f9f7 181 bool enableMaster; /*!< Enable SPI at initialization time */
<> 144:ef7eb2e8f9f7 182 bool enableStopInWaitMode; /*!< SPI stop in wait mode */
<> 144:ef7eb2e8f9f7 183 spi_clock_polarity_t polarity; /*!< Clock polarity */
<> 144:ef7eb2e8f9f7 184 spi_clock_phase_t phase; /*!< Clock phase */
<> 144:ef7eb2e8f9f7 185 spi_shift_direction_t direction; /*!< MSB or LSB */
<> 144:ef7eb2e8f9f7 186 #if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS
<> 144:ef7eb2e8f9f7 187 spi_data_bitcount_mode_t dataMode; /*!< 8bit or 16bit mode */
<> 144:ef7eb2e8f9f7 188 #endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
<> 144:ef7eb2e8f9f7 189 #if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
<> 144:ef7eb2e8f9f7 190 spi_txfifo_watermark_t txWatermark; /*!< Tx watermark settings */
<> 144:ef7eb2e8f9f7 191 spi_rxfifo_watermark_t rxWatermark; /*!< Rx watermark settings */
<> 144:ef7eb2e8f9f7 192 #endif /* FSL_FEATURE_SPI_HAS_FIFO */
<> 144:ef7eb2e8f9f7 193 spi_ss_output_mode_t outputMode; /*!< SS pin setting */
<> 144:ef7eb2e8f9f7 194 spi_pin_mode_t pinMode; /*!< SPI pin mode select */
<> 144:ef7eb2e8f9f7 195 uint32_t baudRate_Bps; /*!< Baud Rate for SPI in Hz */
<> 144:ef7eb2e8f9f7 196 } spi_master_config_t;
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 /*! @brief SPI slave user configure structure.*/
<> 144:ef7eb2e8f9f7 199 typedef struct _spi_slave_config
<> 144:ef7eb2e8f9f7 200 {
<> 144:ef7eb2e8f9f7 201 bool enableSlave; /*!< Enable SPI at initialization time */
<> 144:ef7eb2e8f9f7 202 bool enableStopInWaitMode; /*!< SPI stop in wait mode */
<> 144:ef7eb2e8f9f7 203 spi_clock_polarity_t polarity; /*!< Clock polarity */
<> 144:ef7eb2e8f9f7 204 spi_clock_phase_t phase; /*!< Clock phase */
<> 144:ef7eb2e8f9f7 205 spi_shift_direction_t direction; /*!< MSB or LSB */
<> 144:ef7eb2e8f9f7 206 #if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS
<> 144:ef7eb2e8f9f7 207 spi_data_bitcount_mode_t dataMode; /*!< 8bit or 16bit mode */
<> 144:ef7eb2e8f9f7 208 #endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
<> 144:ef7eb2e8f9f7 209 #if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
<> 144:ef7eb2e8f9f7 210 spi_txfifo_watermark_t txWatermark; /*!< Tx watermark settings */
<> 144:ef7eb2e8f9f7 211 spi_rxfifo_watermark_t rxWatermark; /*!< Rx watermark settings */
<> 144:ef7eb2e8f9f7 212 #endif /* FSL_FEATURE_SPI_HAS_FIFO */
<> 144:ef7eb2e8f9f7 213 } spi_slave_config_t;
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 /*! @brief SPI transfer structure */
<> 144:ef7eb2e8f9f7 216 typedef struct _spi_transfer
<> 144:ef7eb2e8f9f7 217 {
<> 144:ef7eb2e8f9f7 218 uint8_t *txData; /*!< Send buffer */
<> 144:ef7eb2e8f9f7 219 uint8_t *rxData; /*!< Receive buffer */
<> 144:ef7eb2e8f9f7 220 size_t dataSize; /*!< Transfer bytes */
<> 144:ef7eb2e8f9f7 221 uint32_t flags; /*!< SPI control flag, useless to SPI.*/
<> 144:ef7eb2e8f9f7 222 } spi_transfer_t;
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 typedef struct _spi_master_handle spi_master_handle_t;
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 /*! @brief Slave handle is the same with master handle */
<> 144:ef7eb2e8f9f7 227 typedef spi_master_handle_t spi_slave_handle_t;
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 /*! @brief SPI master callback for finished transmit */
<> 144:ef7eb2e8f9f7 230 typedef void (*spi_master_callback_t)(SPI_Type *base, spi_master_handle_t *handle, status_t status, void *userData);
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 /*! @brief SPI master callback for finished transmit */
<> 144:ef7eb2e8f9f7 233 typedef void (*spi_slave_callback_t)(SPI_Type *base, spi_slave_handle_t *handle, status_t status, void *userData);
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 /*! @brief SPI transfer handle structure */
<> 144:ef7eb2e8f9f7 236 struct _spi_master_handle
<> 144:ef7eb2e8f9f7 237 {
<> 144:ef7eb2e8f9f7 238 uint8_t *volatile txData; /*!< Transfer buffer */
<> 144:ef7eb2e8f9f7 239 uint8_t *volatile rxData; /*!< Receive buffer */
<> 144:ef7eb2e8f9f7 240 volatile size_t txRemainingBytes; /*!< Send data remaining in bytes */
<> 144:ef7eb2e8f9f7 241 volatile size_t rxRemainingBytes; /*!< Receive data remaining in bytes */
<> 144:ef7eb2e8f9f7 242 volatile uint32_t state; /*!< SPI internal state */
<> 144:ef7eb2e8f9f7 243 size_t transferSize; /*!< Bytes to be transferred */
<> 144:ef7eb2e8f9f7 244 uint8_t bytePerFrame; /*!< SPI mode, 2bytes or 1byte in a frame */
<> 144:ef7eb2e8f9f7 245 uint8_t watermark; /*!< Watermark value for SPI transfer */
<> 144:ef7eb2e8f9f7 246 spi_master_callback_t callback; /*!< SPI callback */
<> 144:ef7eb2e8f9f7 247 void *userData; /*!< Callback parameter */
<> 144:ef7eb2e8f9f7 248 };
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250 #if defined(__cplusplus)
<> 144:ef7eb2e8f9f7 251 extern "C" {
<> 144:ef7eb2e8f9f7 252 #endif
<> 144:ef7eb2e8f9f7 253 /*******************************************************************************
<> 144:ef7eb2e8f9f7 254 * APIs
<> 144:ef7eb2e8f9f7 255 ******************************************************************************/
<> 144:ef7eb2e8f9f7 256 /*!
<> 144:ef7eb2e8f9f7 257 * @name Initialization and deinitialization
<> 144:ef7eb2e8f9f7 258 * @{
<> 144:ef7eb2e8f9f7 259 */
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 /*!
<> 144:ef7eb2e8f9f7 262 * @brief Sets the SPI master configuration structure to default values.
<> 144:ef7eb2e8f9f7 263 *
<> 144:ef7eb2e8f9f7 264 * The purpose of this API is to get the configuration structure initialized for use in SPI_MasterInit().
<> 144:ef7eb2e8f9f7 265 * User may use the initialized structure unchanged in SPI_MasterInit(), or modify
<> 144:ef7eb2e8f9f7 266 * some fields of the structure before calling SPI_MasterInit(). After calling this API,
<> 144:ef7eb2e8f9f7 267 * the master is ready to transfer.
<> 144:ef7eb2e8f9f7 268 * Example:
<> 144:ef7eb2e8f9f7 269 @code
<> 144:ef7eb2e8f9f7 270 spi_master_config_t config;
<> 144:ef7eb2e8f9f7 271 SPI_MasterGetDefaultConfig(&config);
<> 144:ef7eb2e8f9f7 272 @endcode
<> 144:ef7eb2e8f9f7 273 *
<> 144:ef7eb2e8f9f7 274 * @param config pointer to master config structure
<> 144:ef7eb2e8f9f7 275 */
<> 144:ef7eb2e8f9f7 276 void SPI_MasterGetDefaultConfig(spi_master_config_t *config);
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 /*!
<> 144:ef7eb2e8f9f7 279 * @brief Initializes the SPI with master configuration.
<> 144:ef7eb2e8f9f7 280 *
<> 144:ef7eb2e8f9f7 281 * The configuration structure can be filled by user from scratch, or be set with default
<> 144:ef7eb2e8f9f7 282 * values by SPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer.
<> 144:ef7eb2e8f9f7 283 * Example
<> 144:ef7eb2e8f9f7 284 @code
<> 144:ef7eb2e8f9f7 285 spi_master_config_t config = {
<> 144:ef7eb2e8f9f7 286 .baudRate_Bps = 400000,
<> 144:ef7eb2e8f9f7 287 ...
<> 144:ef7eb2e8f9f7 288 };
<> 144:ef7eb2e8f9f7 289 SPI_MasterInit(SPI0, &config);
<> 144:ef7eb2e8f9f7 290 @endcode
<> 144:ef7eb2e8f9f7 291 *
<> 144:ef7eb2e8f9f7 292 * @param base SPI base pointer
<> 144:ef7eb2e8f9f7 293 * @param config pointer to master configuration structure
<> 144:ef7eb2e8f9f7 294 * @param srcClock_Hz Source clock frequency.
<> 144:ef7eb2e8f9f7 295 */
<> 144:ef7eb2e8f9f7 296 void SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz);
<> 144:ef7eb2e8f9f7 297
<> 144:ef7eb2e8f9f7 298 /*!
<> 144:ef7eb2e8f9f7 299 * @brief Sets the SPI slave configuration structure to default values.
<> 144:ef7eb2e8f9f7 300 *
<> 144:ef7eb2e8f9f7 301 * The purpose of this API is to get the configuration structure initialized for use in SPI_SlaveInit().
<> 144:ef7eb2e8f9f7 302 * Modify some fields of the structure before calling SPI_SlaveInit().
<> 144:ef7eb2e8f9f7 303 * Example:
<> 144:ef7eb2e8f9f7 304 @code
<> 144:ef7eb2e8f9f7 305 spi_slave_config_t config;
<> 144:ef7eb2e8f9f7 306 SPI_SlaveGetDefaultConfig(&config);
<> 144:ef7eb2e8f9f7 307 @endcode
<> 144:ef7eb2e8f9f7 308 *
<> 144:ef7eb2e8f9f7 309 * @param config pointer to slave configuration structure
<> 144:ef7eb2e8f9f7 310 */
<> 144:ef7eb2e8f9f7 311 void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config);
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 /*!
<> 144:ef7eb2e8f9f7 314 * @brief Initializes the SPI with slave configuration.
<> 144:ef7eb2e8f9f7 315 *
<> 144:ef7eb2e8f9f7 316 * The configuration structure can be filled by user from scratch or be set with
<> 144:ef7eb2e8f9f7 317 * default values by SPI_SlaveGetDefaultConfig().
<> 144:ef7eb2e8f9f7 318 * After calling this API, the slave is ready to transfer.
<> 144:ef7eb2e8f9f7 319 * Example
<> 144:ef7eb2e8f9f7 320 @code
<> 144:ef7eb2e8f9f7 321 spi_slave_config_t config = {
<> 144:ef7eb2e8f9f7 322 .polarity = kSPIClockPolarity_ActiveHigh;
<> 144:ef7eb2e8f9f7 323 .phase = kSPIClockPhase_FirstEdge;
<> 144:ef7eb2e8f9f7 324 .direction = kSPIMsbFirst;
<> 144:ef7eb2e8f9f7 325 ...
<> 144:ef7eb2e8f9f7 326 };
<> 144:ef7eb2e8f9f7 327 SPI_MasterInit(SPI0, &config);
<> 144:ef7eb2e8f9f7 328 @endcode
<> 144:ef7eb2e8f9f7 329 *
<> 144:ef7eb2e8f9f7 330 * @param base SPI base pointer
<> 144:ef7eb2e8f9f7 331 * @param config pointer to master configuration structure
<> 144:ef7eb2e8f9f7 332 */
<> 144:ef7eb2e8f9f7 333 void SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config);
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 /*!
<> 144:ef7eb2e8f9f7 336 * @brief De-initializes the SPI.
<> 144:ef7eb2e8f9f7 337 *
<> 144:ef7eb2e8f9f7 338 * Calling this API resets the SPI module, gates the SPI clock.
<> 144:ef7eb2e8f9f7 339 * The SPI module can't work unless calling the SPI_MasterInit/SPI_SlaveInit to initialize module.
<> 144:ef7eb2e8f9f7 340 *
<> 144:ef7eb2e8f9f7 341 * @param base SPI base pointer
<> 144:ef7eb2e8f9f7 342 */
<> 144:ef7eb2e8f9f7 343 void SPI_Deinit(SPI_Type *base);
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 /*!
<> 144:ef7eb2e8f9f7 346 * @brief Enables or disables the SPI.
<> 144:ef7eb2e8f9f7 347 *
<> 144:ef7eb2e8f9f7 348 * @param base SPI base pointer
<> 144:ef7eb2e8f9f7 349 * @param enable pass true to enable module, false to disable module
<> 144:ef7eb2e8f9f7 350 */
<> 144:ef7eb2e8f9f7 351 static inline void SPI_Enable(SPI_Type *base, bool enable)
<> 144:ef7eb2e8f9f7 352 {
<> 144:ef7eb2e8f9f7 353 if (enable)
<> 144:ef7eb2e8f9f7 354 {
<> 144:ef7eb2e8f9f7 355 base->C1 |= SPI_C1_SPE_MASK;
<> 144:ef7eb2e8f9f7 356 }
<> 144:ef7eb2e8f9f7 357 else
<> 144:ef7eb2e8f9f7 358 {
<> 144:ef7eb2e8f9f7 359 base->C1 &= ~SPI_C1_SPE_MASK;
<> 144:ef7eb2e8f9f7 360 }
<> 144:ef7eb2e8f9f7 361 }
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 /*! @} */
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 /*!
<> 144:ef7eb2e8f9f7 366 * @name Status
<> 144:ef7eb2e8f9f7 367 * @{
<> 144:ef7eb2e8f9f7 368 */
<> 144:ef7eb2e8f9f7 369
<> 144:ef7eb2e8f9f7 370 /*!
<> 144:ef7eb2e8f9f7 371 * @brief Gets the status flag.
<> 144:ef7eb2e8f9f7 372 *
<> 144:ef7eb2e8f9f7 373 * @param base SPI base pointer
<> 144:ef7eb2e8f9f7 374 * @return SPI Status, use status flag to AND #_spi_flags could get the related status.
<> 144:ef7eb2e8f9f7 375 */
<> 144:ef7eb2e8f9f7 376 uint32_t SPI_GetStatusFlags(SPI_Type *base);
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 #if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
<> 144:ef7eb2e8f9f7 379 /*!
<> 144:ef7eb2e8f9f7 380 * @brief Clear the interrupt if enable INCTLR.
<> 144:ef7eb2e8f9f7 381 *
<> 144:ef7eb2e8f9f7 382 * @param base SPI base pointer
<> 144:ef7eb2e8f9f7 383 * @param interrupt Interrupt need to be cleared
<> 144:ef7eb2e8f9f7 384 * The parameter could be any combination of the following values:
<> 144:ef7eb2e8f9f7 385 * @arg kSPIRxFifoFullClearInt
<> 144:ef7eb2e8f9f7 386 * @arg kSPITxFifoEmptyClearInt
<> 144:ef7eb2e8f9f7 387 * @arg kSPIRxNearFullClearInt
<> 144:ef7eb2e8f9f7 388 * @arg kSPITxNearEmptyClearInt
<> 144:ef7eb2e8f9f7 389 */
<> 144:ef7eb2e8f9f7 390 static inline void SPI_ClearInterrupt(SPI_Type *base, uint32_t mask)
<> 144:ef7eb2e8f9f7 391 {
<> 144:ef7eb2e8f9f7 392 base->CI |= mask;
<> 144:ef7eb2e8f9f7 393 }
<> 144:ef7eb2e8f9f7 394 #endif /* FSL_FEATURE_SPI_HAS_FIFO */
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 /*! @} */
<> 144:ef7eb2e8f9f7 397
<> 144:ef7eb2e8f9f7 398 /*!
<> 144:ef7eb2e8f9f7 399 * @name Interrupts
<> 144:ef7eb2e8f9f7 400 * @{
<> 144:ef7eb2e8f9f7 401 */
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 /*!
<> 144:ef7eb2e8f9f7 404 * @brief Enables the interrupt for the SPI.
<> 144:ef7eb2e8f9f7 405 *
<> 144:ef7eb2e8f9f7 406 * @param base SPI base pointer
<> 144:ef7eb2e8f9f7 407 * @param mask SPI interrupt source. The parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 408 * @arg kSPI_RxFullAndModfInterruptEnable
<> 144:ef7eb2e8f9f7 409 * @arg kSPI_TxEmptyInterruptEnable
<> 144:ef7eb2e8f9f7 410 * @arg kSPI_MatchInterruptEnable
<> 144:ef7eb2e8f9f7 411 * @arg kSPI_RxFifoNearFullInterruptEnable
<> 144:ef7eb2e8f9f7 412 * @arg kSPI_TxFifoNearEmptyInterruptEnable
<> 144:ef7eb2e8f9f7 413 */
<> 144:ef7eb2e8f9f7 414 void SPI_EnableInterrupts(SPI_Type *base, uint32_t mask);
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 /*!
<> 144:ef7eb2e8f9f7 417 * @brief Disables the interrupt for the SPI.
<> 144:ef7eb2e8f9f7 418 *
<> 144:ef7eb2e8f9f7 419 * @param base SPI base pointer
<> 144:ef7eb2e8f9f7 420 * @param mask SPI interrupt source. The parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 421 * @arg kSPI_RxFullAndModfInterruptEnable
<> 144:ef7eb2e8f9f7 422 * @arg kSPI_TxEmptyInterruptEnable
<> 144:ef7eb2e8f9f7 423 * @arg kSPI_MatchInterruptEnable
<> 144:ef7eb2e8f9f7 424 * @arg kSPI_RxFifoNearFullInterruptEnable
<> 144:ef7eb2e8f9f7 425 * @arg kSPI_TxFifoNearEmptyInterruptEnable
<> 144:ef7eb2e8f9f7 426 */
<> 144:ef7eb2e8f9f7 427 void SPI_DisableInterrupts(SPI_Type *base, uint32_t mask);
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 /*! @} */
<> 144:ef7eb2e8f9f7 430
<> 144:ef7eb2e8f9f7 431 /*!
<> 144:ef7eb2e8f9f7 432 * @name DMA Control
<> 144:ef7eb2e8f9f7 433 * @{
<> 144:ef7eb2e8f9f7 434 */
<> 144:ef7eb2e8f9f7 435
<> 144:ef7eb2e8f9f7 436 #if defined(FSL_FEATURE_SPI_HAS_DMA_SUPPORT) && FSL_FEATURE_SPI_HAS_DMA_SUPPORT
<> 144:ef7eb2e8f9f7 437 /*!
<> 144:ef7eb2e8f9f7 438 * @brief Enables the DMA source for SPI.
<> 144:ef7eb2e8f9f7 439 *
<> 144:ef7eb2e8f9f7 440 * @param base SPI base pointer
<> 144:ef7eb2e8f9f7 441 * @param source SPI DMA source.
<> 144:ef7eb2e8f9f7 442 * @param enable True means enable DMA, false means disable DMA
<> 144:ef7eb2e8f9f7 443 */
<> 144:ef7eb2e8f9f7 444 static inline void SPI_EnableDMA(SPI_Type *base, uint32_t mask, bool enable)
<> 144:ef7eb2e8f9f7 445 {
<> 144:ef7eb2e8f9f7 446 if (enable)
<> 144:ef7eb2e8f9f7 447 {
<> 144:ef7eb2e8f9f7 448 base->C2 |= mask;
<> 144:ef7eb2e8f9f7 449 }
<> 144:ef7eb2e8f9f7 450 else
<> 144:ef7eb2e8f9f7 451 {
<> 144:ef7eb2e8f9f7 452 base->C2 &= ~mask;
<> 144:ef7eb2e8f9f7 453 }
<> 144:ef7eb2e8f9f7 454 }
<> 144:ef7eb2e8f9f7 455 #endif /* FSL_FEATURE_SPI_HAS_DMA_SUPPORT */
<> 144:ef7eb2e8f9f7 456
<> 144:ef7eb2e8f9f7 457 /*!
<> 144:ef7eb2e8f9f7 458 * @brief Gets the SPI tx/rx data register address.
<> 144:ef7eb2e8f9f7 459 *
<> 144:ef7eb2e8f9f7 460 * This API is used to provide a transfer address for the SPI DMA transfer configuration.
<> 144:ef7eb2e8f9f7 461 *
<> 144:ef7eb2e8f9f7 462 * @param base SPI base pointer
<> 144:ef7eb2e8f9f7 463 * @return data register address
<> 144:ef7eb2e8f9f7 464 */
<> 144:ef7eb2e8f9f7 465 static inline uint32_t SPI_GetDataRegisterAddress(SPI_Type *base)
<> 144:ef7eb2e8f9f7 466 {
<> 144:ef7eb2e8f9f7 467 #if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS
<> 144:ef7eb2e8f9f7 468 return (uint32_t)(&(base->DL));
<> 144:ef7eb2e8f9f7 469 #else
<> 144:ef7eb2e8f9f7 470 return (uint32_t)(&(base->D));
<> 144:ef7eb2e8f9f7 471 #endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
<> 144:ef7eb2e8f9f7 472 }
<> 144:ef7eb2e8f9f7 473
<> 144:ef7eb2e8f9f7 474 /*! @} */
<> 144:ef7eb2e8f9f7 475
<> 144:ef7eb2e8f9f7 476 /*!
<> 144:ef7eb2e8f9f7 477 * @name Bus Operations
<> 144:ef7eb2e8f9f7 478 * @{
<> 144:ef7eb2e8f9f7 479 */
<> 144:ef7eb2e8f9f7 480
<> 144:ef7eb2e8f9f7 481 /*!
<> 144:ef7eb2e8f9f7 482 * @brief Sets the baud rate for SPI transfer. This is only used in master.
<> 144:ef7eb2e8f9f7 483 *
<> 144:ef7eb2e8f9f7 484 * @param base SPI base pointer
<> 144:ef7eb2e8f9f7 485 * @param baudRate_Bps baud rate needed in Hz.
<> 144:ef7eb2e8f9f7 486 * @param srcClock_Hz SPI source clock frequency in Hz.
<> 144:ef7eb2e8f9f7 487 */
<> 144:ef7eb2e8f9f7 488 void SPI_MasterSetBaudRate(SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz);
<> 144:ef7eb2e8f9f7 489
<> 144:ef7eb2e8f9f7 490 /*!
<> 144:ef7eb2e8f9f7 491 * @brief Sets the match data for SPI.
<> 144:ef7eb2e8f9f7 492 *
<> 144:ef7eb2e8f9f7 493 * The match data is a hardware comparison value. When the value received in the SPI receive data
<> 144:ef7eb2e8f9f7 494 * buffer equals the hardware comparison value, the SPI Match Flag in the S register (S[SPMF]) sets.
<> 144:ef7eb2e8f9f7 495 * This can also generate an interrupt if the enable bit sets.
<> 144:ef7eb2e8f9f7 496 *
<> 144:ef7eb2e8f9f7 497 * @param base SPI base pointer
<> 144:ef7eb2e8f9f7 498 * @param matchData Match data.
<> 144:ef7eb2e8f9f7 499 */
<> 144:ef7eb2e8f9f7 500 static inline void SPI_SetMatchData(SPI_Type *base, uint32_t matchData)
<> 144:ef7eb2e8f9f7 501 {
<> 144:ef7eb2e8f9f7 502 #if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS
<> 144:ef7eb2e8f9f7 503 base->ML = matchData & 0xFFU;
<> 144:ef7eb2e8f9f7 504 base->MH = (matchData >> 8U) & 0xFFU;
<> 144:ef7eb2e8f9f7 505 #else
<> 144:ef7eb2e8f9f7 506 base->M = matchData;
<> 144:ef7eb2e8f9f7 507 #endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
<> 144:ef7eb2e8f9f7 508 }
<> 144:ef7eb2e8f9f7 509
<> 144:ef7eb2e8f9f7 510 #if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
<> 144:ef7eb2e8f9f7 511 /*!
<> 144:ef7eb2e8f9f7 512 * @brief Enables or disables the FIFO if there is a FIFO.
<> 144:ef7eb2e8f9f7 513 *
<> 144:ef7eb2e8f9f7 514 * @param base SPI base pointer
<> 144:ef7eb2e8f9f7 515 * @param enable True means enable FIFO, false means disable FIFO.
<> 144:ef7eb2e8f9f7 516 */
<> 144:ef7eb2e8f9f7 517 void SPI_EnableFIFO(SPI_Type *base, bool enable);
<> 144:ef7eb2e8f9f7 518 #endif
<> 144:ef7eb2e8f9f7 519
<> 144:ef7eb2e8f9f7 520 /*!
<> 144:ef7eb2e8f9f7 521 * @brief Sends a buffer of data bytes using a blocking method.
<> 144:ef7eb2e8f9f7 522 *
<> 144:ef7eb2e8f9f7 523 * @note This function blocks via polling until all bytes have been sent.
<> 144:ef7eb2e8f9f7 524 *
<> 144:ef7eb2e8f9f7 525 * @param base SPI base pointer
<> 144:ef7eb2e8f9f7 526 * @param buffer The data bytes to send
<> 144:ef7eb2e8f9f7 527 * @param size The number of data bytes to send
<> 144:ef7eb2e8f9f7 528 */
<> 144:ef7eb2e8f9f7 529 void SPI_WriteBlocking(SPI_Type *base, uint8_t *buffer, size_t size);
<> 144:ef7eb2e8f9f7 530
<> 144:ef7eb2e8f9f7 531 /*!
<> 144:ef7eb2e8f9f7 532 * @brief Writes a data into the SPI data register.
<> 144:ef7eb2e8f9f7 533 *
<> 144:ef7eb2e8f9f7 534 * @param base SPI base pointer
<> 144:ef7eb2e8f9f7 535 * @param data needs to be write.
<> 144:ef7eb2e8f9f7 536 */
<> 144:ef7eb2e8f9f7 537 void SPI_WriteData(SPI_Type *base, uint16_t data);
<> 144:ef7eb2e8f9f7 538
<> 144:ef7eb2e8f9f7 539 /*!
<> 144:ef7eb2e8f9f7 540 * @brief Gets a data from the SPI data register.
<> 144:ef7eb2e8f9f7 541 *
<> 144:ef7eb2e8f9f7 542 * @param base SPI base pointer
<> 144:ef7eb2e8f9f7 543 * @return Data in the register.
<> 144:ef7eb2e8f9f7 544 */
<> 144:ef7eb2e8f9f7 545 uint16_t SPI_ReadData(SPI_Type *base);
<> 144:ef7eb2e8f9f7 546
<> 144:ef7eb2e8f9f7 547 /*! @} */
<> 144:ef7eb2e8f9f7 548
<> 144:ef7eb2e8f9f7 549 /*!
<> 144:ef7eb2e8f9f7 550 * @name Transactional
<> 144:ef7eb2e8f9f7 551 * @{
<> 144:ef7eb2e8f9f7 552 */
<> 144:ef7eb2e8f9f7 553
<> 144:ef7eb2e8f9f7 554 /*!
<> 144:ef7eb2e8f9f7 555 * @brief Initializes the SPI master handle.
<> 144:ef7eb2e8f9f7 556 *
<> 144:ef7eb2e8f9f7 557 * This function initializes the SPI master handle which can be used for other SPI master transactional APIs. Usually,
<> 144:ef7eb2e8f9f7 558 * for a specified SPI instance, call this API once to get the initialized handle.
<> 144:ef7eb2e8f9f7 559 *
<> 144:ef7eb2e8f9f7 560 * @param base SPI peripheral base address.
<> 144:ef7eb2e8f9f7 561 * @param handle SPI handle pointer.
<> 144:ef7eb2e8f9f7 562 * @param callback Callback function.
<> 144:ef7eb2e8f9f7 563 * @param userData User data.
<> 144:ef7eb2e8f9f7 564 */
<> 144:ef7eb2e8f9f7 565 void SPI_MasterTransferCreateHandle(SPI_Type *base,
<> 144:ef7eb2e8f9f7 566 spi_master_handle_t *handle,
<> 144:ef7eb2e8f9f7 567 spi_master_callback_t callback,
<> 144:ef7eb2e8f9f7 568 void *userData);
<> 144:ef7eb2e8f9f7 569
<> 144:ef7eb2e8f9f7 570 /*!
<> 144:ef7eb2e8f9f7 571 * @brief Transfers a block of data using a polling method.
<> 144:ef7eb2e8f9f7 572 *
<> 144:ef7eb2e8f9f7 573 * @param base SPI base pointer
<> 144:ef7eb2e8f9f7 574 * @param xfer pointer to spi_xfer_config_t structure
<> 144:ef7eb2e8f9f7 575 * @retval kStatus_Success Successfully start a transfer.
<> 144:ef7eb2e8f9f7 576 * @retval kStatus_InvalidArgument Input argument is invalid.
<> 144:ef7eb2e8f9f7 577 */
<> 144:ef7eb2e8f9f7 578 status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer);
<> 144:ef7eb2e8f9f7 579
<> 144:ef7eb2e8f9f7 580 /*!
<> 144:ef7eb2e8f9f7 581 * @brief Performs a non-blocking SPI interrupt transfer.
<> 144:ef7eb2e8f9f7 582 *
<> 144:ef7eb2e8f9f7 583 * @note The API immediately returns after transfer initialization is finished.
<> 144:ef7eb2e8f9f7 584 * Call SPI_GetStatusIRQ() to get the transfer status.
<> 144:ef7eb2e8f9f7 585 * @note If using the SPI with FIFO for the interrupt transfer, the transfer size is the integer times of the watermark.
<> 144:ef7eb2e8f9f7 586 * Otherwise,
<> 144:ef7eb2e8f9f7 587 * the last data may be lost because it cannot generate an interrupt request. Users can also call the functional API to
<> 144:ef7eb2e8f9f7 588 * get the last
<> 144:ef7eb2e8f9f7 589 * received data.
<> 144:ef7eb2e8f9f7 590 *
<> 144:ef7eb2e8f9f7 591 * @param base SPI peripheral base address.
<> 144:ef7eb2e8f9f7 592 * @param handle pointer to spi_master_handle_t structure which stores the transfer state
<> 144:ef7eb2e8f9f7 593 * @param xfer pointer to spi_xfer_config_t structure
<> 144:ef7eb2e8f9f7 594 * @retval kStatus_Success Successfully start a transfer.
<> 144:ef7eb2e8f9f7 595 * @retval kStatus_InvalidArgument Input argument is invalid.
<> 144:ef7eb2e8f9f7 596 * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer.
<> 144:ef7eb2e8f9f7 597 */
<> 144:ef7eb2e8f9f7 598 status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer);
<> 144:ef7eb2e8f9f7 599
<> 144:ef7eb2e8f9f7 600 /*!
<> 144:ef7eb2e8f9f7 601 * @brief Gets the bytes of the SPI interrupt transferred.
<> 144:ef7eb2e8f9f7 602 *
<> 144:ef7eb2e8f9f7 603 * @param base SPI peripheral base address.
<> 144:ef7eb2e8f9f7 604 * @param handle Pointer to SPI transfer handle, this should be a static variable.
<> 144:ef7eb2e8f9f7 605 * @param count Transferred bytes of SPI master.
<> 144:ef7eb2e8f9f7 606 * @retval kStatus_SPI_Success Succeed get the transfer count.
<> 144:ef7eb2e8f9f7 607 * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
<> 144:ef7eb2e8f9f7 608 */
<> 144:ef7eb2e8f9f7 609 status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count);
<> 144:ef7eb2e8f9f7 610
<> 144:ef7eb2e8f9f7 611 /*!
<> 144:ef7eb2e8f9f7 612 * @brief Aborts an SPI transfer using interrupt.
<> 144:ef7eb2e8f9f7 613 *
<> 144:ef7eb2e8f9f7 614 * @param base SPI peripheral base address.
<> 144:ef7eb2e8f9f7 615 * @param handle Pointer to SPI transfer handle, this should be a static variable.
<> 144:ef7eb2e8f9f7 616 */
<> 144:ef7eb2e8f9f7 617 void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle);
<> 144:ef7eb2e8f9f7 618
<> 144:ef7eb2e8f9f7 619 /*!
<> 144:ef7eb2e8f9f7 620 * @brief Interrupts the handler for the SPI.
<> 144:ef7eb2e8f9f7 621 *
<> 144:ef7eb2e8f9f7 622 * @param base SPI peripheral base address.
<> 144:ef7eb2e8f9f7 623 * @param handle pointer to spi_master_handle_t structure which stores the transfer state.
<> 144:ef7eb2e8f9f7 624 */
<> 144:ef7eb2e8f9f7 625 void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle);
<> 144:ef7eb2e8f9f7 626
<> 144:ef7eb2e8f9f7 627 /*!
<> 144:ef7eb2e8f9f7 628 * @brief Initializes the SPI slave handle.
<> 144:ef7eb2e8f9f7 629 *
<> 144:ef7eb2e8f9f7 630 * This function initializes the SPI slave handle which can be used for other SPI slave transactional APIs. Usually,
<> 144:ef7eb2e8f9f7 631 * for a specified SPI instance, call this API once to get the initialized handle.
<> 144:ef7eb2e8f9f7 632 *
<> 144:ef7eb2e8f9f7 633 * @param base SPI peripheral base address.
<> 144:ef7eb2e8f9f7 634 * @param handle SPI handle pointer.
<> 144:ef7eb2e8f9f7 635 * @param callback Callback function.
<> 144:ef7eb2e8f9f7 636 * @param userData User data.
<> 144:ef7eb2e8f9f7 637 */
<> 144:ef7eb2e8f9f7 638 void SPI_SlaveTransferCreateHandle(SPI_Type *base,
<> 144:ef7eb2e8f9f7 639 spi_slave_handle_t *handle,
<> 144:ef7eb2e8f9f7 640 spi_slave_callback_t callback,
<> 144:ef7eb2e8f9f7 641 void *userData);
<> 144:ef7eb2e8f9f7 642
<> 144:ef7eb2e8f9f7 643 /*!
<> 144:ef7eb2e8f9f7 644 * @brief Performs a non-blocking SPI slave interrupt transfer.
<> 144:ef7eb2e8f9f7 645 *
<> 144:ef7eb2e8f9f7 646 * @note The API returns immediately after the transfer initialization is finished.
<> 144:ef7eb2e8f9f7 647 * Call SPI_GetStatusIRQ() to get the transfer status.
<> 144:ef7eb2e8f9f7 648 * @note If using the SPI with FIFO for the interrupt transfer, the transfer size is the integer times the watermark.
<> 144:ef7eb2e8f9f7 649 * Otherwise,
<> 144:ef7eb2e8f9f7 650 * the last data may be lost because it cannot generate an interrupt request. Call the functional API to get the last
<> 144:ef7eb2e8f9f7 651 * several
<> 144:ef7eb2e8f9f7 652 * receive data.
<> 144:ef7eb2e8f9f7 653 *
<> 144:ef7eb2e8f9f7 654 * @param base SPI peripheral base address.
<> 144:ef7eb2e8f9f7 655 * @param handle pointer to spi_master_handle_t structure which stores the transfer state
<> 144:ef7eb2e8f9f7 656 * @param xfer pointer to spi_xfer_config_t structure
<> 144:ef7eb2e8f9f7 657 * @retval kStatus_Success Successfully start a transfer.
<> 144:ef7eb2e8f9f7 658 * @retval kStatus_InvalidArgument Input argument is invalid.
<> 144:ef7eb2e8f9f7 659 * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer.
<> 144:ef7eb2e8f9f7 660 */
<> 144:ef7eb2e8f9f7 661 static inline status_t SPI_SlaveTransferNonBlocking(SPI_Type *base, spi_slave_handle_t *handle, spi_transfer_t *xfer)
<> 144:ef7eb2e8f9f7 662 {
<> 144:ef7eb2e8f9f7 663 return SPI_MasterTransferNonBlocking(base, handle, xfer);
<> 144:ef7eb2e8f9f7 664 }
<> 144:ef7eb2e8f9f7 665
<> 144:ef7eb2e8f9f7 666 /*!
<> 144:ef7eb2e8f9f7 667 * @brief Gets the bytes of the SPI interrupt transferred.
<> 144:ef7eb2e8f9f7 668 *
<> 144:ef7eb2e8f9f7 669 * @param base SPI peripheral base address.
<> 144:ef7eb2e8f9f7 670 * @param handle Pointer to SPI transfer handle, this should be a static variable.
<> 144:ef7eb2e8f9f7 671 * @param count Transferred bytes of SPI slave.
<> 144:ef7eb2e8f9f7 672 * @retval kStatus_SPI_Success Succeed get the transfer count.
<> 144:ef7eb2e8f9f7 673 * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
<> 144:ef7eb2e8f9f7 674 */
<> 144:ef7eb2e8f9f7 675 static inline status_t SPI_SlaveTransferGetCount(SPI_Type *base, spi_slave_handle_t *handle, size_t *count)
<> 144:ef7eb2e8f9f7 676 {
<> 144:ef7eb2e8f9f7 677 return SPI_MasterTransferGetCount(base, handle, count);
<> 144:ef7eb2e8f9f7 678 }
<> 144:ef7eb2e8f9f7 679
<> 144:ef7eb2e8f9f7 680 /*!
<> 144:ef7eb2e8f9f7 681 * @brief Aborts an SPI slave transfer using interrupt.
<> 144:ef7eb2e8f9f7 682 *
<> 144:ef7eb2e8f9f7 683 * @param base SPI peripheral base address.
<> 144:ef7eb2e8f9f7 684 * @param handle Pointer to SPI transfer handle, this should be a static variable.
<> 144:ef7eb2e8f9f7 685 */
<> 144:ef7eb2e8f9f7 686 static inline void SPI_SlaveTransferAbort(SPI_Type *base, spi_slave_handle_t *handle)
<> 144:ef7eb2e8f9f7 687 {
<> 144:ef7eb2e8f9f7 688 SPI_MasterTransferAbort(base, handle);
<> 144:ef7eb2e8f9f7 689 }
<> 144:ef7eb2e8f9f7 690
<> 144:ef7eb2e8f9f7 691 /*!
<> 144:ef7eb2e8f9f7 692 * @brief Interrupts a handler for the SPI slave.
<> 144:ef7eb2e8f9f7 693 *
<> 144:ef7eb2e8f9f7 694 * @param base SPI peripheral base address.
<> 144:ef7eb2e8f9f7 695 * @param handle pointer to spi_slave_handle_t structure which stores the transfer state
<> 144:ef7eb2e8f9f7 696 */
<> 144:ef7eb2e8f9f7 697 void SPI_SlaveTransferHandleIRQ(SPI_Type *base, spi_slave_handle_t *handle);
<> 144:ef7eb2e8f9f7 698
<> 144:ef7eb2e8f9f7 699 /*! @} */
<> 144:ef7eb2e8f9f7 700
<> 144:ef7eb2e8f9f7 701 #if defined(__cplusplus)
<> 144:ef7eb2e8f9f7 702 }
<> 144:ef7eb2e8f9f7 703 #endif
<> 144:ef7eb2e8f9f7 704
<> 144:ef7eb2e8f9f7 705 /*! @} */
<> 144:ef7eb2e8f9f7 706
<> 144:ef7eb2e8f9f7 707 #endif /* _FSL_SPI_H_*/