Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/drivers/fsl_slcd.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 144:ef7eb2e8f9f7 3 * All rights reserved.
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 6 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 9 * of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 12 * list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 13 * other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 144:ef7eb2e8f9f7 16 * contributors may be used to endorse or promote products derived from this
<> 144:ef7eb2e8f9f7 17 * software without specific prior written permission.
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 29 */
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 #include "fsl_slcd.h"
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 /*******************************************************************************
<> 144:ef7eb2e8f9f7 34 * Definitions
<> 144:ef7eb2e8f9f7 35 ******************************************************************************/
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 #define SLCD_WAVEFORM_CONFIG_NUM 16
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 /*******************************************************************************
<> 144:ef7eb2e8f9f7 40 * Prototypes
<> 144:ef7eb2e8f9f7 41 ******************************************************************************/
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /*!
<> 144:ef7eb2e8f9f7 44 * @brief Get the SLCD instance from peripheral base address.
<> 144:ef7eb2e8f9f7 45 *
<> 144:ef7eb2e8f9f7 46 * @param base SLCD peripheral base address.
<> 144:ef7eb2e8f9f7 47 * @return SLCD instance.
<> 144:ef7eb2e8f9f7 48 */
<> 144:ef7eb2e8f9f7 49 static uint32_t SLCD_GetInstance(LCD_Type *base);
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 /*******************************************************************************
<> 144:ef7eb2e8f9f7 52 * Variables
<> 144:ef7eb2e8f9f7 53 ******************************************************************************/
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /*! @brief Pointers to slcd clocks for each instance. */
<> 144:ef7eb2e8f9f7 56 const clock_ip_name_t s_slcdClock[FSL_FEATURE_SOC_SLCD_COUNT] = SLCD_CLOCKS;
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 /*! @brief Pointers to slcd bases for each instance. */
<> 144:ef7eb2e8f9f7 59 static LCD_Type *const s_slcdBases[] = LCD_BASE_PTRS;
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 /*******************************************************************************
<> 144:ef7eb2e8f9f7 62 * Code
<> 144:ef7eb2e8f9f7 63 ******************************************************************************/
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 static uint32_t SLCD_GetInstance(LCD_Type *base)
<> 144:ef7eb2e8f9f7 66 {
<> 144:ef7eb2e8f9f7 67 uint32_t instance;
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 /* Find the instance index from base address mappings. */
<> 144:ef7eb2e8f9f7 70 for (instance = 0; instance < FSL_FEATURE_SOC_SLCD_COUNT; instance++)
<> 144:ef7eb2e8f9f7 71 {
<> 144:ef7eb2e8f9f7 72 if (s_slcdBases[instance] == base)
<> 144:ef7eb2e8f9f7 73 {
<> 144:ef7eb2e8f9f7 74 break;
<> 144:ef7eb2e8f9f7 75 }
<> 144:ef7eb2e8f9f7 76 }
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 assert(instance < FSL_FEATURE_SOC_SLCD_COUNT);
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 return instance;
<> 144:ef7eb2e8f9f7 81 }
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 void SLCD_Init(LCD_Type *base, slcd_config_t *configure)
<> 144:ef7eb2e8f9f7 84 {
<> 144:ef7eb2e8f9f7 85 assert(configure);
<> 144:ef7eb2e8f9f7 86 assert(configure->clkConfig);
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 uint32_t gcrReg = 0;
<> 144:ef7eb2e8f9f7 89 bool intEnabled = false;
<> 144:ef7eb2e8f9f7 90 uint32_t regNum = 0;
<> 144:ef7eb2e8f9f7 91 uint32_t instance = SLCD_GetInstance(base);
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 /* Un-gate the SLCD clock. */
<> 144:ef7eb2e8f9f7 94 CLOCK_EnableClock(s_slcdClock[instance]);
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 /* Configure general setting: power supply. */
<> 144:ef7eb2e8f9f7 97 gcrReg = LCD_GCR_RVEN(configure->powerSupply & 0x1U) | LCD_GCR_CPSEL((configure->powerSupply >> 1U) & 0x1U) |
<> 144:ef7eb2e8f9f7 98 LCD_GCR_VSUPPLY((configure->powerSupply >> 2U) & 0x1U) | LCD_GCR_LADJ(configure->loadAdjust);
<> 144:ef7eb2e8f9f7 99 /* Configure general setting: clock source. */
<> 144:ef7eb2e8f9f7 100 gcrReg |= LCD_GCR_SOURCE((configure->clkConfig->clkSource) & 0x1U) |
<> 144:ef7eb2e8f9f7 101 LCD_GCR_LCLK(configure->clkConfig->clkPrescaler) | LCD_GCR_ALTDIV(configure->clkConfig->altClkDivider);
<> 144:ef7eb2e8f9f7 102 /* Configure the duty and set the work for low power wait and stop mode. */
<> 144:ef7eb2e8f9f7 103 gcrReg |= LCD_GCR_DUTY(configure->dutyCycle) | LCD_GCR_LCDSTP(configure->lowPowerBehavior & 0x1U);
<> 144:ef7eb2e8f9f7 104 #if FSL_FEATURE_SLCD_HAS_LCD_WAIT
<> 144:ef7eb2e8f9f7 105 gcrReg |= LCD_GCR_LCDWAIT((configure->lowPowerBehavior >> 1U) & 0x1U);
<> 144:ef7eb2e8f9f7 106 #endif
<> 144:ef7eb2e8f9f7 107 #if FSL_FEATURE_SLCD_HAS_LCD_DOZE_ENABLE
<> 144:ef7eb2e8f9f7 108 gcrReg |= LCD_GCR_LCDDOZE((configure->lowPowerBehavior >> 1U) & 0x1U);
<> 144:ef7eb2e8f9f7 109 #endif
<> 144:ef7eb2e8f9f7 110 #if FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT
<> 144:ef7eb2e8f9f7 111 /* Configure for frame frequency interrupt. */
<> 144:ef7eb2e8f9f7 112 gcrReg |= LCD_GCR_LCDIEN(configure->frameFreqIntEnable);
<> 144:ef7eb2e8f9f7 113 #endif /* FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT */
<> 144:ef7eb2e8f9f7 114 #if FSL_FEATURE_SLCD_HAS_MULTI_ALTERNATE_CLOCK_SOURCE
<> 144:ef7eb2e8f9f7 115 /* Select the alternate clock for alternate clock source. */
<> 144:ef7eb2e8f9f7 116 gcrReg |= LCD_GCR_ALTSOURCE(((configure->clkConfig->clkSource) >> 1U) & 0x1U);
<> 144:ef7eb2e8f9f7 117 #endif /* FSL_FEATURE_SLCD_HAS_MULTI_ALTERNATE_CLOCK_SOURCE */
<> 144:ef7eb2e8f9f7 118 #if FSL_FEATURE_SLCD_HAS_FAST_FRAME_RATE
<> 144:ef7eb2e8f9f7 119 /* Configure the for fast frame rate. */
<> 144:ef7eb2e8f9f7 120 gcrReg |= LCD_GCR_FFR(configure->clkConfig->fastFrameRateEnable ? 1U : 0U);
<> 144:ef7eb2e8f9f7 121 #endif /* FSL_FEATURE_SLCD_HAS_FAST_FRAME_RATE */
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 if (configure->powerSupply & 0x1U)
<> 144:ef7eb2e8f9f7 124 {
<> 144:ef7eb2e8f9f7 125 gcrReg |= LCD_GCR_RVTRIM(configure->voltageTrim);
<> 144:ef7eb2e8f9f7 126 }
<> 144:ef7eb2e8f9f7 127 base->GCR = gcrReg;
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 /* Set display mode. */
<> 144:ef7eb2e8f9f7 130 base->AR = LCD_AR_ALT(configure->displayMode & 0x1U) | LCD_AR_BLANK((configure->displayMode >> 1U) & 0x1U);
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 /* Configure the front plane and back plane pin setting. */
<> 144:ef7eb2e8f9f7 133 base->BPEN[0] = configure->backPlaneLowPin;
<> 144:ef7eb2e8f9f7 134 base->BPEN[1] = configure->backPlaneHighPin;
<> 144:ef7eb2e8f9f7 135 base->PEN[0] = configure->slcdLowPinEnabled;
<> 144:ef7eb2e8f9f7 136 base->PEN[1] = configure->slcdHighPinEnabled;
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 /* Set the fault frame detection. */
<> 144:ef7eb2e8f9f7 139 base->FDCR = 0;
<> 144:ef7eb2e8f9f7 140 if (configure->faultConfig)
<> 144:ef7eb2e8f9f7 141 {
<> 144:ef7eb2e8f9f7 142 /* If fault configure structure is not NULL, the fault detection is enabled. */
<> 144:ef7eb2e8f9f7 143 base->FDCR = LCD_FDCR_FDPRS(configure->faultConfig->faultPrescaler) |
<> 144:ef7eb2e8f9f7 144 LCD_FDCR_FDSWW(configure->faultConfig->width) |
<> 144:ef7eb2e8f9f7 145 LCD_FDCR_FDBPEN(configure->faultConfig->faultDetectBackPlaneEnable ? 1U : 0U) |
<> 144:ef7eb2e8f9f7 146 LCD_FDCR_FDPINID(configure->faultConfig->faultDetectPinIndex) | LCD_FDCR_FDEN_MASK;
<> 144:ef7eb2e8f9f7 147 if (configure->faultConfig->faultDetectIntEnable)
<> 144:ef7eb2e8f9f7 148 {
<> 144:ef7eb2e8f9f7 149 base->GCR |= LCD_GCR_FDCIEN_MASK;
<> 144:ef7eb2e8f9f7 150 intEnabled = true;
<> 144:ef7eb2e8f9f7 151 }
<> 144:ef7eb2e8f9f7 152 }
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 /* Initialize the Waveform. */
<> 144:ef7eb2e8f9f7 155 for (regNum = 0; regNum < SLCD_WAVEFORM_CONFIG_NUM; regNum++)
<> 144:ef7eb2e8f9f7 156 {
<> 144:ef7eb2e8f9f7 157 base->WF[regNum] = 0;
<> 144:ef7eb2e8f9f7 158 }
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 /* Enable the NVIC. */
<> 144:ef7eb2e8f9f7 161 #if FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT
<> 144:ef7eb2e8f9f7 162 if (configure->frameFreqIntEnable)
<> 144:ef7eb2e8f9f7 163 {
<> 144:ef7eb2e8f9f7 164 intEnabled = true;
<> 144:ef7eb2e8f9f7 165 }
<> 144:ef7eb2e8f9f7 166 #endif /* FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT */
<> 144:ef7eb2e8f9f7 167 if (intEnabled)
<> 144:ef7eb2e8f9f7 168 {
<> 144:ef7eb2e8f9f7 169 EnableIRQ(LCD_IRQn);
<> 144:ef7eb2e8f9f7 170 }
<> 144:ef7eb2e8f9f7 171 }
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 void SLCD_Deinit(LCD_Type *base)
<> 144:ef7eb2e8f9f7 174 {
<> 144:ef7eb2e8f9f7 175 uint32_t instance = SLCD_GetInstance(base);
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 /* Stop SLCD display. */
<> 144:ef7eb2e8f9f7 178 SLCD_StopDisplay(base);
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 /* Gate the SLCD clock. */
<> 144:ef7eb2e8f9f7 181 CLOCK_DisableClock(s_slcdClock[instance]);
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 /* Disable NVIC. */
<> 144:ef7eb2e8f9f7 184 DisableIRQ(LCD_IRQn);
<> 144:ef7eb2e8f9f7 185 }
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 void SLCD_GetDefaultConfig(slcd_config_t *configure)
<> 144:ef7eb2e8f9f7 188 {
<> 144:ef7eb2e8f9f7 189 assert(configure);
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 /* Get Default parameters for the configuration structure. */
<> 144:ef7eb2e8f9f7 192 /* SLCD in normal mode. */
<> 144:ef7eb2e8f9f7 193 configure->displayMode = kSLCD_NormalMode;
<> 144:ef7eb2e8f9f7 194 /* Power supply default: use charge pump to generate VLL1 and VLL2, VLL3 connected to VDD internally. */
<> 144:ef7eb2e8f9f7 195 configure->powerSupply = kSLCD_InternalVll3UseChargePump;
<> 144:ef7eb2e8f9f7 196 configure->voltageTrim = kSLCD_RegulatedVolatgeTrim00;
<> 144:ef7eb2e8f9f7 197 /* Work in low power mode. */
<> 144:ef7eb2e8f9f7 198 configure->lowPowerBehavior = kSLCD_EnabledInWaitStop;
<> 144:ef7eb2e8f9f7 199 #if FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT
<> 144:ef7eb2e8f9f7 200 /* No interrupt source is enabled. */
<> 144:ef7eb2e8f9f7 201 configure->frameFreqIntEnable = false;
<> 144:ef7eb2e8f9f7 202 #endif /* FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT */
<> 144:ef7eb2e8f9f7 203 /* Fault detection is disabled. */
<> 144:ef7eb2e8f9f7 204 configure->faultConfig = NULL;
<> 144:ef7eb2e8f9f7 205 }
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 void SLCD_StartBlinkMode(LCD_Type *base, slcd_blink_mode_t mode, slcd_blink_rate_t rate)
<> 144:ef7eb2e8f9f7 208 {
<> 144:ef7eb2e8f9f7 209 base->AR &= ~(LCD_AR_BMODE_MASK | LCD_AR_BRATE_MASK);
<> 144:ef7eb2e8f9f7 210 /* Set blink mode and blink rate. */
<> 144:ef7eb2e8f9f7 211 base->AR |= LCD_AR_BMODE(mode) | LCD_AR_BRATE(rate);
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 /* Enable Blink mode. */
<> 144:ef7eb2e8f9f7 214 base->AR |= LCD_AR_BLINK_MASK;
<> 144:ef7eb2e8f9f7 215 }
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 void SLCD_EnableInterrupts(LCD_Type *base, uint32_t mask)
<> 144:ef7eb2e8f9f7 218 {
<> 144:ef7eb2e8f9f7 219 uint32_t gcReg = base->GCR;
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 gcReg |= LCD_GCR_FDCIEN(mask & 0x1U);
<> 144:ef7eb2e8f9f7 222 #if FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT
<> 144:ef7eb2e8f9f7 223 gcReg |= LCD_GCR_LCDEN((mask >> 1U) & 0x1U);
<> 144:ef7eb2e8f9f7 224 #endif /* FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT */
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 base->GCR = gcReg;
<> 144:ef7eb2e8f9f7 227 }
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 void SLCD_DisableInterrupts(LCD_Type *base, uint32_t mask)
<> 144:ef7eb2e8f9f7 230 {
<> 144:ef7eb2e8f9f7 231 uint32_t gcrReg = base->GCR;
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 /*!< SLCD fault detection complete interrupt source. */
<> 144:ef7eb2e8f9f7 234 if (mask & kSLCD_FaultDetectCompleteInterrupt)
<> 144:ef7eb2e8f9f7 235 {
<> 144:ef7eb2e8f9f7 236 gcrReg &= ~LCD_GCR_FDCIEN_MASK;
<> 144:ef7eb2e8f9f7 237 }
<> 144:ef7eb2e8f9f7 238 /*!< SLCD frame frequency interrupt source. */
<> 144:ef7eb2e8f9f7 239 #if FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT
<> 144:ef7eb2e8f9f7 240 if (mask & kSLCD_FrameFreqInterrupt)
<> 144:ef7eb2e8f9f7 241 {
<> 144:ef7eb2e8f9f7 242 gcrReg &= ~LCD_GCR_LCDIEN_MASK;
<> 144:ef7eb2e8f9f7 243 }
<> 144:ef7eb2e8f9f7 244 #endif /* FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT */
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 base->GCR = gcrReg;
<> 144:ef7eb2e8f9f7 247 }
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 void SLCD_ClearInterruptStatus(LCD_Type *base, uint32_t mask)
<> 144:ef7eb2e8f9f7 250 {
<> 144:ef7eb2e8f9f7 251 /*!< SLCD fault detection complete interrupt source. */
<> 144:ef7eb2e8f9f7 252 if (mask & kSLCD_FaultDetectCompleteInterrupt)
<> 144:ef7eb2e8f9f7 253 {
<> 144:ef7eb2e8f9f7 254 base->FDSR |= LCD_FDSR_FDCF_MASK;
<> 144:ef7eb2e8f9f7 255 }
<> 144:ef7eb2e8f9f7 256 /*!< SLCD frame frequency interrupt source. */
<> 144:ef7eb2e8f9f7 257 #if FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT
<> 144:ef7eb2e8f9f7 258 if (mask & kSLCD_FrameFreqInterrupt)
<> 144:ef7eb2e8f9f7 259 {
<> 144:ef7eb2e8f9f7 260 base->AR |= LCD_AR_LCDIF_MASK;
<> 144:ef7eb2e8f9f7 261 }
<> 144:ef7eb2e8f9f7 262 #endif /* FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT */
<> 144:ef7eb2e8f9f7 263 }
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 uint32_t SLCD_GetInterruptStatus(LCD_Type *base)
<> 144:ef7eb2e8f9f7 266 {
<> 144:ef7eb2e8f9f7 267 uint32_t status = 0;
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269 /* Get the frame detect complete interrupt status. */
<> 144:ef7eb2e8f9f7 270 status = ((base->FDSR & LCD_FDSR_FDCF_MASK) >> LCD_FDSR_FDCF_SHIFT);
<> 144:ef7eb2e8f9f7 271
<> 144:ef7eb2e8f9f7 272 #if FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT
<> 144:ef7eb2e8f9f7 273 /* Get the frame frequency interrupt status. */
<> 144:ef7eb2e8f9f7 274 status |= ((base->AR & LCD_AR_LCDIF_MASK) >> (LCD_AR_LCDIF_SHIFT - 1));
<> 144:ef7eb2e8f9f7 275 #endif /* FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT */
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 return status;
<> 144:ef7eb2e8f9f7 278 }