Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/drivers/fsl_lpuart_dma.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 144:ef7eb2e8f9f7 3 * All rights reserved.
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 6 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 9 * of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 12 * list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 13 * other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 144:ef7eb2e8f9f7 16 * contributors may be used to endorse or promote products derived from this
<> 144:ef7eb2e8f9f7 17 * software without specific prior written permission.
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 29 */
<> 144:ef7eb2e8f9f7 30 #include "fsl_lpuart_dma.h"
<> 144:ef7eb2e8f9f7 31 #include "fsl_dmamux.h"
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 /*******************************************************************************
<> 144:ef7eb2e8f9f7 34 * Definitions
<> 144:ef7eb2e8f9f7 35 ******************************************************************************/
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 /*<! Structure definition for lpuart_dma_handle_t. The structure is private. */
<> 144:ef7eb2e8f9f7 38 typedef struct _lpuart_dma_private_handle
<> 144:ef7eb2e8f9f7 39 {
<> 144:ef7eb2e8f9f7 40 LPUART_Type *base;
<> 144:ef7eb2e8f9f7 41 lpuart_dma_handle_t *handle;
<> 144:ef7eb2e8f9f7 42 } lpuart_dma_private_handle_t;
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /* LPUART DMA transfer handle. */
<> 144:ef7eb2e8f9f7 45 enum _uart_dma_tansfer_states
<> 144:ef7eb2e8f9f7 46 {
<> 144:ef7eb2e8f9f7 47 kLPUART_TxIdle, /* TX idle. */
<> 144:ef7eb2e8f9f7 48 kLPUART_TxBusy, /* TX busy. */
<> 144:ef7eb2e8f9f7 49 kLPUART_RxIdle, /* RX idle. */
<> 144:ef7eb2e8f9f7 50 kLPUART_RxBusy /* RX busy. */
<> 144:ef7eb2e8f9f7 51 };
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /*******************************************************************************
<> 144:ef7eb2e8f9f7 54 * Variables
<> 144:ef7eb2e8f9f7 55 ******************************************************************************/
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /*<! Private handle only used for internally. */
<> 144:ef7eb2e8f9f7 58 static lpuart_dma_private_handle_t s_dmaPrivateHandle[FSL_FEATURE_SOC_LPUART_COUNT];
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 /*******************************************************************************
<> 144:ef7eb2e8f9f7 61 * Prototypes
<> 144:ef7eb2e8f9f7 62 ******************************************************************************/
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 /*!
<> 144:ef7eb2e8f9f7 65 * @brief LPUART DMA send finished callback function.
<> 144:ef7eb2e8f9f7 66 *
<> 144:ef7eb2e8f9f7 67 * This function is called when LPUART DMA send finished. It disables the LPUART
<> 144:ef7eb2e8f9f7 68 * TX DMA request and sends @ref kStatus_LPUART_TxIdle to LPUART callback.
<> 144:ef7eb2e8f9f7 69 *
<> 144:ef7eb2e8f9f7 70 * @param handle The DMA handle.
<> 144:ef7eb2e8f9f7 71 * @param param Callback function parameter.
<> 144:ef7eb2e8f9f7 72 */
<> 144:ef7eb2e8f9f7 73 static void LPUART_TransferSendDMACallback(dma_handle_t *handle, void *param);
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 /*!
<> 144:ef7eb2e8f9f7 76 * @brief LPUART DMA receive finished callback function.
<> 144:ef7eb2e8f9f7 77 *
<> 144:ef7eb2e8f9f7 78 * This function is called when LPUART DMA receive finished. It disables the LPUART
<> 144:ef7eb2e8f9f7 79 * RX DMA request and sends @ref kStatus_LPUART_RxIdle to LPUART callback.
<> 144:ef7eb2e8f9f7 80 *
<> 144:ef7eb2e8f9f7 81 * @param handle The DMA handle.
<> 144:ef7eb2e8f9f7 82 * @param param Callback function parameter.
<> 144:ef7eb2e8f9f7 83 */
<> 144:ef7eb2e8f9f7 84 static void LPUART_TransferReceiveDMACallback(dma_handle_t *handle, void *param);
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 /*!
<> 144:ef7eb2e8f9f7 87 * @brief Get the LPUART instance from peripheral base address.
<> 144:ef7eb2e8f9f7 88 *
<> 144:ef7eb2e8f9f7 89 * @param base LPUART peripheral base address.
<> 144:ef7eb2e8f9f7 90 * @return LPUART instance.
<> 144:ef7eb2e8f9f7 91 */
<> 144:ef7eb2e8f9f7 92 extern uint32_t LPUART_GetInstance(LPUART_Type *base);
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 /*******************************************************************************
<> 144:ef7eb2e8f9f7 95 * Code
<> 144:ef7eb2e8f9f7 96 ******************************************************************************/
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 static void LPUART_TransferSendDMACallback(dma_handle_t *handle, void *param)
<> 144:ef7eb2e8f9f7 99 {
<> 144:ef7eb2e8f9f7 100 lpuart_dma_private_handle_t *lpuartPrivateHandle = (lpuart_dma_private_handle_t *)param;
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 /* Disable LPUART TX DMA. */
<> 144:ef7eb2e8f9f7 103 LPUART_EnableTxDMA(lpuartPrivateHandle->base, false);
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 /* Disable interrupt. */
<> 144:ef7eb2e8f9f7 106 DMA_DisableInterrupts(lpuartPrivateHandle->handle->txDmaHandle->base,
<> 144:ef7eb2e8f9f7 107 lpuartPrivateHandle->handle->txDmaHandle->channel);
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 lpuartPrivateHandle->handle->txState = kLPUART_TxIdle;
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 if (lpuartPrivateHandle->handle->callback)
<> 144:ef7eb2e8f9f7 112 {
<> 144:ef7eb2e8f9f7 113 lpuartPrivateHandle->handle->callback(lpuartPrivateHandle->base, lpuartPrivateHandle->handle,
<> 144:ef7eb2e8f9f7 114 kStatus_LPUART_TxIdle, lpuartPrivateHandle->handle->userData);
<> 144:ef7eb2e8f9f7 115 }
<> 144:ef7eb2e8f9f7 116 }
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 static void LPUART_TransferReceiveDMACallback(dma_handle_t *handle, void *param)
<> 144:ef7eb2e8f9f7 119 {
<> 144:ef7eb2e8f9f7 120 lpuart_dma_private_handle_t *lpuartPrivateHandle = (lpuart_dma_private_handle_t *)param;
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 /* Disable LPUART RX DMA. */
<> 144:ef7eb2e8f9f7 123 LPUART_EnableRxDMA(lpuartPrivateHandle->base, false);
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 /* Disable interrupt. */
<> 144:ef7eb2e8f9f7 126 DMA_DisableInterrupts(lpuartPrivateHandle->handle->rxDmaHandle->base,
<> 144:ef7eb2e8f9f7 127 lpuartPrivateHandle->handle->rxDmaHandle->channel);
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 lpuartPrivateHandle->handle->rxState = kLPUART_RxIdle;
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 if (lpuartPrivateHandle->handle->callback)
<> 144:ef7eb2e8f9f7 132 {
<> 144:ef7eb2e8f9f7 133 lpuartPrivateHandle->handle->callback(lpuartPrivateHandle->base, lpuartPrivateHandle->handle,
<> 144:ef7eb2e8f9f7 134 kStatus_LPUART_RxIdle, lpuartPrivateHandle->handle->userData);
<> 144:ef7eb2e8f9f7 135 }
<> 144:ef7eb2e8f9f7 136 }
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 void LPUART_TransferCreateHandleDMA(LPUART_Type *base,
<> 144:ef7eb2e8f9f7 139 lpuart_dma_handle_t *handle,
<> 144:ef7eb2e8f9f7 140 lpuart_dma_transfer_callback_t callback,
<> 144:ef7eb2e8f9f7 141 void *userData,
<> 144:ef7eb2e8f9f7 142 dma_handle_t *txDmaHandle,
<> 144:ef7eb2e8f9f7 143 dma_handle_t *rxDmaHandle)
<> 144:ef7eb2e8f9f7 144 {
<> 144:ef7eb2e8f9f7 145 assert(handle);
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 uint32_t instance = LPUART_GetInstance(base);
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 memset(handle, 0, sizeof(lpuart_dma_handle_t));
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 s_dmaPrivateHandle[instance].base = base;
<> 144:ef7eb2e8f9f7 152 s_dmaPrivateHandle[instance].handle = handle;
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 handle->rxState = kLPUART_RxIdle;
<> 144:ef7eb2e8f9f7 155 handle->txState = kLPUART_TxIdle;
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 handle->callback = callback;
<> 144:ef7eb2e8f9f7 158 handle->userData = userData;
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 144:ef7eb2e8f9f7 161 /* Note:
<> 144:ef7eb2e8f9f7 162 Take care of the RX FIFO, DMA request only assert when received bytes
<> 144:ef7eb2e8f9f7 163 equal or more than RX water mark, there is potential issue if RX water
<> 144:ef7eb2e8f9f7 164 mark larger than 1.
<> 144:ef7eb2e8f9f7 165 For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and
<> 144:ef7eb2e8f9f7 166 5 bytes are received. the last byte will be saved in FIFO but not trigger
<> 144:ef7eb2e8f9f7 167 DMA transfer because the water mark is 2.
<> 144:ef7eb2e8f9f7 168 */
<> 144:ef7eb2e8f9f7 169 if (rxDmaHandle)
<> 144:ef7eb2e8f9f7 170 {
<> 144:ef7eb2e8f9f7 171 base->WATER &= (~LPUART_WATER_RXWATER_MASK);
<> 144:ef7eb2e8f9f7 172 }
<> 144:ef7eb2e8f9f7 173 #endif
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 handle->rxDmaHandle = rxDmaHandle;
<> 144:ef7eb2e8f9f7 176 handle->txDmaHandle = txDmaHandle;
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 /* Configure TX. */
<> 144:ef7eb2e8f9f7 179 if (txDmaHandle)
<> 144:ef7eb2e8f9f7 180 {
<> 144:ef7eb2e8f9f7 181 DMA_SetCallback(txDmaHandle, LPUART_TransferSendDMACallback, &s_dmaPrivateHandle[instance]);
<> 144:ef7eb2e8f9f7 182 }
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 /* Configure RX. */
<> 144:ef7eb2e8f9f7 185 if (rxDmaHandle)
<> 144:ef7eb2e8f9f7 186 {
<> 144:ef7eb2e8f9f7 187 DMA_SetCallback(rxDmaHandle, LPUART_TransferReceiveDMACallback, &s_dmaPrivateHandle[instance]);
<> 144:ef7eb2e8f9f7 188 }
<> 144:ef7eb2e8f9f7 189 }
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 status_t LPUART_TransferSendDMA(LPUART_Type *base, lpuart_dma_handle_t *handle, lpuart_transfer_t *xfer)
<> 144:ef7eb2e8f9f7 192 {
<> 144:ef7eb2e8f9f7 193 assert(handle->txDmaHandle);
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 status_t status;
<> 144:ef7eb2e8f9f7 196 dma_transfer_config_t xferConfig;
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 /* Return error if xfer invalid. */
<> 144:ef7eb2e8f9f7 199 if ((0U == xfer->dataSize) || (NULL == xfer->data))
<> 144:ef7eb2e8f9f7 200 {
<> 144:ef7eb2e8f9f7 201 return kStatus_InvalidArgument;
<> 144:ef7eb2e8f9f7 202 }
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 /* If previous TX not finished. */
<> 144:ef7eb2e8f9f7 205 if (kLPUART_TxBusy == handle->txState)
<> 144:ef7eb2e8f9f7 206 {
<> 144:ef7eb2e8f9f7 207 status = kStatus_LPUART_TxBusy;
<> 144:ef7eb2e8f9f7 208 }
<> 144:ef7eb2e8f9f7 209 else
<> 144:ef7eb2e8f9f7 210 {
<> 144:ef7eb2e8f9f7 211 handle->txState = kLPUART_TxBusy;
<> 144:ef7eb2e8f9f7 212 handle->txDataSizeAll = xfer->dataSize;
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 /* Prepare transfer. */
<> 144:ef7eb2e8f9f7 215 DMA_PrepareTransfer(&xferConfig, xfer->data, sizeof(uint8_t), (void *)LPUART_GetDataRegisterAddress(base),
<> 144:ef7eb2e8f9f7 216 sizeof(uint8_t), xfer->dataSize, kDMA_MemoryToPeripheral);
<> 144:ef7eb2e8f9f7 217
<> 144:ef7eb2e8f9f7 218 /* Submit transfer. */
<> 144:ef7eb2e8f9f7 219 DMA_SubmitTransfer(handle->txDmaHandle, &xferConfig, kDMA_EnableInterrupt);
<> 144:ef7eb2e8f9f7 220 DMA_StartTransfer(handle->txDmaHandle);
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 /* Enable LPUART TX DMA. */
<> 144:ef7eb2e8f9f7 223 LPUART_EnableTxDMA(base, true);
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 status = kStatus_Success;
<> 144:ef7eb2e8f9f7 226 }
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 return status;
<> 144:ef7eb2e8f9f7 229 }
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 status_t LPUART_TransferReceiveDMA(LPUART_Type *base, lpuart_dma_handle_t *handle, lpuart_transfer_t *xfer)
<> 144:ef7eb2e8f9f7 232 {
<> 144:ef7eb2e8f9f7 233 assert(handle->rxDmaHandle);
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 status_t status;
<> 144:ef7eb2e8f9f7 236 dma_transfer_config_t xferConfig;
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 /* Return error if xfer invalid. */
<> 144:ef7eb2e8f9f7 239 if ((0U == xfer->dataSize) || (NULL == xfer->data))
<> 144:ef7eb2e8f9f7 240 {
<> 144:ef7eb2e8f9f7 241 return kStatus_InvalidArgument;
<> 144:ef7eb2e8f9f7 242 }
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 /* If previous RX not finished. */
<> 144:ef7eb2e8f9f7 245 if (kLPUART_RxBusy == handle->rxState)
<> 144:ef7eb2e8f9f7 246 {
<> 144:ef7eb2e8f9f7 247 status = kStatus_LPUART_RxBusy;
<> 144:ef7eb2e8f9f7 248 }
<> 144:ef7eb2e8f9f7 249 else
<> 144:ef7eb2e8f9f7 250 {
<> 144:ef7eb2e8f9f7 251 handle->rxState = kLPUART_RxBusy;
<> 144:ef7eb2e8f9f7 252 handle->rxDataSizeAll = xfer->dataSize;
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 /* Prepare transfer. */
<> 144:ef7eb2e8f9f7 255 DMA_PrepareTransfer(&xferConfig, (void *)LPUART_GetDataRegisterAddress(base), sizeof(uint8_t), xfer->data,
<> 144:ef7eb2e8f9f7 256 sizeof(uint8_t), xfer->dataSize, kDMA_PeripheralToMemory);
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 /* Submit transfer. */
<> 144:ef7eb2e8f9f7 259 DMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig, kDMA_EnableInterrupt);
<> 144:ef7eb2e8f9f7 260 DMA_StartTransfer(handle->rxDmaHandle);
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 /* Enable LPUART RX DMA. */
<> 144:ef7eb2e8f9f7 263 LPUART_EnableRxDMA(base, true);
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 status = kStatus_Success;
<> 144:ef7eb2e8f9f7 266 }
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 return status;
<> 144:ef7eb2e8f9f7 269 }
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 void LPUART_TransferAbortSendDMA(LPUART_Type *base, lpuart_dma_handle_t *handle)
<> 144:ef7eb2e8f9f7 272 {
<> 144:ef7eb2e8f9f7 273 assert(handle->txDmaHandle);
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275 /* Disable LPUART TX DMA. */
<> 144:ef7eb2e8f9f7 276 LPUART_EnableTxDMA(base, false);
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 /* Stop transfer. */
<> 144:ef7eb2e8f9f7 279 DMA_AbortTransfer(handle->txDmaHandle);
<> 144:ef7eb2e8f9f7 280
<> 144:ef7eb2e8f9f7 281 /* Write DMA->DSR[DONE] to abort transfer and clear status. */
<> 144:ef7eb2e8f9f7 282 DMA_ClearChannelStatusFlags(handle->txDmaHandle->base, handle->txDmaHandle->channel, kDMA_TransactionsDoneFlag);
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 handle->txState = kLPUART_TxIdle;
<> 144:ef7eb2e8f9f7 285 }
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 void LPUART_TransferAbortReceiveDMA(LPUART_Type *base, lpuart_dma_handle_t *handle)
<> 144:ef7eb2e8f9f7 288 {
<> 144:ef7eb2e8f9f7 289 assert(handle->rxDmaHandle);
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 /* Disable LPUART RX DMA. */
<> 144:ef7eb2e8f9f7 292 LPUART_EnableRxDMA(base, false);
<> 144:ef7eb2e8f9f7 293
<> 144:ef7eb2e8f9f7 294 /* Stop transfer. */
<> 144:ef7eb2e8f9f7 295 DMA_AbortTransfer(handle->rxDmaHandle);
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 /* Write DMA->DSR[DONE] to abort transfer and clear status. */
<> 144:ef7eb2e8f9f7 298 DMA_ClearChannelStatusFlags(handle->rxDmaHandle->base, handle->rxDmaHandle->channel, kDMA_TransactionsDoneFlag);
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 handle->rxState = kLPUART_RxIdle;
<> 144:ef7eb2e8f9f7 301 }
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 status_t LPUART_TransferGetSendCountDMA(LPUART_Type *base, lpuart_dma_handle_t *handle, uint32_t *count)
<> 144:ef7eb2e8f9f7 304 {
<> 144:ef7eb2e8f9f7 305 assert(handle->txDmaHandle);
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 if (kLPUART_TxIdle == handle->txState)
<> 144:ef7eb2e8f9f7 308 {
<> 144:ef7eb2e8f9f7 309 return kStatus_NoTransferInProgress;
<> 144:ef7eb2e8f9f7 310 }
<> 144:ef7eb2e8f9f7 311
<> 144:ef7eb2e8f9f7 312 if (!count)
<> 144:ef7eb2e8f9f7 313 {
<> 144:ef7eb2e8f9f7 314 return kStatus_InvalidArgument;
<> 144:ef7eb2e8f9f7 315 }
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 *count = handle->txDataSizeAll - DMA_GetRemainingBytes(handle->txDmaHandle->base, handle->txDmaHandle->channel);
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 return kStatus_Success;
<> 144:ef7eb2e8f9f7 320 }
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 status_t LPUART_TransferGetReceiveCountDMA(LPUART_Type *base, lpuart_dma_handle_t *handle, uint32_t *count)
<> 144:ef7eb2e8f9f7 323 {
<> 144:ef7eb2e8f9f7 324 assert(handle->rxDmaHandle);
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 if (kLPUART_RxIdle == handle->rxState)
<> 144:ef7eb2e8f9f7 327 {
<> 144:ef7eb2e8f9f7 328 return kStatus_NoTransferInProgress;
<> 144:ef7eb2e8f9f7 329 }
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 if (!count)
<> 144:ef7eb2e8f9f7 332 {
<> 144:ef7eb2e8f9f7 333 return kStatus_InvalidArgument;
<> 144:ef7eb2e8f9f7 334 }
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 *count = handle->rxDataSizeAll - DMA_GetRemainingBytes(handle->rxDmaHandle->base, handle->rxDmaHandle->channel);
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338 return kStatus_Success;
<> 144:ef7eb2e8f9f7 339 }