added prescaler for 16 bit pwm in LPC1347 target
Fork of mbed-dev by
targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_uart.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)
- Committer:
- <>
- Date:
- Fri Sep 02 15:07:44 2016 +0100
- Revision:
- 144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /* |
<> | 144:ef7eb2e8f9f7 | 2 | * Copyright (c) 2015, Freescale Semiconductor, Inc. |
<> | 144:ef7eb2e8f9f7 | 3 | * All rights reserved. |
<> | 144:ef7eb2e8f9f7 | 4 | * |
<> | 144:ef7eb2e8f9f7 | 5 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 144:ef7eb2e8f9f7 | 6 | * are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 7 | * |
<> | 144:ef7eb2e8f9f7 | 8 | * o Redistributions of source code must retain the above copyright notice, this list |
<> | 144:ef7eb2e8f9f7 | 9 | * of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 10 | * |
<> | 144:ef7eb2e8f9f7 | 11 | * o Redistributions in binary form must reproduce the above copyright notice, this |
<> | 144:ef7eb2e8f9f7 | 12 | * list of conditions and the following disclaimer in the documentation and/or |
<> | 144:ef7eb2e8f9f7 | 13 | * other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 14 | * |
<> | 144:ef7eb2e8f9f7 | 15 | * o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
<> | 144:ef7eb2e8f9f7 | 16 | * contributors may be used to endorse or promote products derived from this |
<> | 144:ef7eb2e8f9f7 | 17 | * software without specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 18 | * |
<> | 144:ef7eb2e8f9f7 | 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
<> | 144:ef7eb2e8f9f7 | 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
<> | 144:ef7eb2e8f9f7 | 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 144:ef7eb2e8f9f7 | 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
<> | 144:ef7eb2e8f9f7 | 23 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
<> | 144:ef7eb2e8f9f7 | 24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
<> | 144:ef7eb2e8f9f7 | 25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
<> | 144:ef7eb2e8f9f7 | 26 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
<> | 144:ef7eb2e8f9f7 | 27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
<> | 144:ef7eb2e8f9f7 | 28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 29 | */ |
<> | 144:ef7eb2e8f9f7 | 30 | |
<> | 144:ef7eb2e8f9f7 | 31 | #include "fsl_uart.h" |
<> | 144:ef7eb2e8f9f7 | 32 | |
<> | 144:ef7eb2e8f9f7 | 33 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 34 | * Definitions |
<> | 144:ef7eb2e8f9f7 | 35 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 36 | |
<> | 144:ef7eb2e8f9f7 | 37 | /* UART transfer state. */ |
<> | 144:ef7eb2e8f9f7 | 38 | enum _uart_tansfer_states |
<> | 144:ef7eb2e8f9f7 | 39 | { |
<> | 144:ef7eb2e8f9f7 | 40 | kUART_TxIdle, /* TX idle. */ |
<> | 144:ef7eb2e8f9f7 | 41 | kUART_TxBusy, /* TX busy. */ |
<> | 144:ef7eb2e8f9f7 | 42 | kUART_RxIdle, /* RX idle. */ |
<> | 144:ef7eb2e8f9f7 | 43 | kUART_RxBusy /* RX busy. */ |
<> | 144:ef7eb2e8f9f7 | 44 | }; |
<> | 144:ef7eb2e8f9f7 | 45 | |
<> | 144:ef7eb2e8f9f7 | 46 | /* Typedef for interrupt handler. */ |
<> | 144:ef7eb2e8f9f7 | 47 | typedef void (*uart_isr_t)(UART_Type *base, uart_handle_t *handle); |
<> | 144:ef7eb2e8f9f7 | 48 | |
<> | 144:ef7eb2e8f9f7 | 49 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 50 | * Prototypes |
<> | 144:ef7eb2e8f9f7 | 51 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 52 | |
<> | 144:ef7eb2e8f9f7 | 53 | /*! |
<> | 144:ef7eb2e8f9f7 | 54 | * @brief Get the UART instance from peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 55 | * |
<> | 144:ef7eb2e8f9f7 | 56 | * @param base UART peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 57 | * @return UART instance. |
<> | 144:ef7eb2e8f9f7 | 58 | */ |
<> | 144:ef7eb2e8f9f7 | 59 | uint32_t UART_GetInstance(UART_Type *base); |
<> | 144:ef7eb2e8f9f7 | 60 | |
<> | 144:ef7eb2e8f9f7 | 61 | /*! |
<> | 144:ef7eb2e8f9f7 | 62 | * @brief Get the length of received data in RX ring buffer. |
<> | 144:ef7eb2e8f9f7 | 63 | * |
<> | 144:ef7eb2e8f9f7 | 64 | * @param handle UART handle pointer. |
<> | 144:ef7eb2e8f9f7 | 65 | * @return Length of received data in RX ring buffer. |
<> | 144:ef7eb2e8f9f7 | 66 | */ |
<> | 144:ef7eb2e8f9f7 | 67 | static size_t UART_TransferGetRxRingBufferLength(uart_handle_t *handle); |
<> | 144:ef7eb2e8f9f7 | 68 | |
<> | 144:ef7eb2e8f9f7 | 69 | /*! |
<> | 144:ef7eb2e8f9f7 | 70 | * @brief Check whether the RX ring buffer is full. |
<> | 144:ef7eb2e8f9f7 | 71 | * |
<> | 144:ef7eb2e8f9f7 | 72 | * @param handle UART handle pointer. |
<> | 144:ef7eb2e8f9f7 | 73 | * @retval true RX ring buffer is full. |
<> | 144:ef7eb2e8f9f7 | 74 | * @retval false RX ring buffer is not full. |
<> | 144:ef7eb2e8f9f7 | 75 | */ |
<> | 144:ef7eb2e8f9f7 | 76 | static bool UART_TransferIsRxRingBufferFull(uart_handle_t *handle); |
<> | 144:ef7eb2e8f9f7 | 77 | |
<> | 144:ef7eb2e8f9f7 | 78 | /*! |
<> | 144:ef7eb2e8f9f7 | 79 | * @brief Read RX register using non-blocking method. |
<> | 144:ef7eb2e8f9f7 | 80 | * |
<> | 144:ef7eb2e8f9f7 | 81 | * This function reads data from the TX register directly, upper layer must make |
<> | 144:ef7eb2e8f9f7 | 82 | * sure the RX register is full or TX FIFO has data before calling this function. |
<> | 144:ef7eb2e8f9f7 | 83 | * |
<> | 144:ef7eb2e8f9f7 | 84 | * @param base UART peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 85 | * @param data Start addresss of the buffer to store the received data. |
<> | 144:ef7eb2e8f9f7 | 86 | * @param length Size of the buffer. |
<> | 144:ef7eb2e8f9f7 | 87 | */ |
<> | 144:ef7eb2e8f9f7 | 88 | static void UART_ReadNonBlocking(UART_Type *base, uint8_t *data, size_t length); |
<> | 144:ef7eb2e8f9f7 | 89 | |
<> | 144:ef7eb2e8f9f7 | 90 | /*! |
<> | 144:ef7eb2e8f9f7 | 91 | * @brief Write to TX register using non-blocking method. |
<> | 144:ef7eb2e8f9f7 | 92 | * |
<> | 144:ef7eb2e8f9f7 | 93 | * This function writes data to the TX register directly, upper layer must make |
<> | 144:ef7eb2e8f9f7 | 94 | * sure the TX register is empty or TX FIFO has empty room before calling this function. |
<> | 144:ef7eb2e8f9f7 | 95 | * |
<> | 144:ef7eb2e8f9f7 | 96 | * @note This function does not check whether all the data has been sent out to bus, |
<> | 144:ef7eb2e8f9f7 | 97 | * so before disable TX, check kUART_TransmissionCompleteFlag to ensure the TX is |
<> | 144:ef7eb2e8f9f7 | 98 | * finished. |
<> | 144:ef7eb2e8f9f7 | 99 | * |
<> | 144:ef7eb2e8f9f7 | 100 | * @param base UART peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 101 | * @param data Start addresss of the data to write. |
<> | 144:ef7eb2e8f9f7 | 102 | * @param length Size of the buffer to be sent. |
<> | 144:ef7eb2e8f9f7 | 103 | */ |
<> | 144:ef7eb2e8f9f7 | 104 | static void UART_WriteNonBlocking(UART_Type *base, const uint8_t *data, size_t length); |
<> | 144:ef7eb2e8f9f7 | 105 | |
<> | 144:ef7eb2e8f9f7 | 106 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 107 | * Variables |
<> | 144:ef7eb2e8f9f7 | 108 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 109 | /* Array of UART handle. */ |
<> | 144:ef7eb2e8f9f7 | 110 | #if (defined(UART5)) |
<> | 144:ef7eb2e8f9f7 | 111 | #define UART_HANDLE_ARRAY_SIZE 6 |
<> | 144:ef7eb2e8f9f7 | 112 | #else /* UART5 */ |
<> | 144:ef7eb2e8f9f7 | 113 | #if (defined(UART4)) |
<> | 144:ef7eb2e8f9f7 | 114 | #define UART_HANDLE_ARRAY_SIZE 5 |
<> | 144:ef7eb2e8f9f7 | 115 | #else /* UART4 */ |
<> | 144:ef7eb2e8f9f7 | 116 | #if (defined(UART3)) |
<> | 144:ef7eb2e8f9f7 | 117 | #define UART_HANDLE_ARRAY_SIZE 4 |
<> | 144:ef7eb2e8f9f7 | 118 | #else /* UART3 */ |
<> | 144:ef7eb2e8f9f7 | 119 | #if (defined(UART2)) |
<> | 144:ef7eb2e8f9f7 | 120 | #define UART_HANDLE_ARRAY_SIZE 3 |
<> | 144:ef7eb2e8f9f7 | 121 | #else /* UART2 */ |
<> | 144:ef7eb2e8f9f7 | 122 | #if (defined(UART1)) |
<> | 144:ef7eb2e8f9f7 | 123 | #define UART_HANDLE_ARRAY_SIZE 2 |
<> | 144:ef7eb2e8f9f7 | 124 | #else /* UART1 */ |
<> | 144:ef7eb2e8f9f7 | 125 | #if (defined(UART0)) |
<> | 144:ef7eb2e8f9f7 | 126 | #define UART_HANDLE_ARRAY_SIZE 1 |
<> | 144:ef7eb2e8f9f7 | 127 | #else /* UART0 */ |
<> | 144:ef7eb2e8f9f7 | 128 | #error No UART instance. |
<> | 144:ef7eb2e8f9f7 | 129 | #endif /* UART 0 */ |
<> | 144:ef7eb2e8f9f7 | 130 | #endif /* UART 1 */ |
<> | 144:ef7eb2e8f9f7 | 131 | #endif /* UART 2 */ |
<> | 144:ef7eb2e8f9f7 | 132 | #endif /* UART 3 */ |
<> | 144:ef7eb2e8f9f7 | 133 | #endif /* UART 4 */ |
<> | 144:ef7eb2e8f9f7 | 134 | #endif /* UART 5 */ |
<> | 144:ef7eb2e8f9f7 | 135 | static uart_handle_t *s_uartHandle[UART_HANDLE_ARRAY_SIZE]; |
<> | 144:ef7eb2e8f9f7 | 136 | /* Array of UART peripheral base address. */ |
<> | 144:ef7eb2e8f9f7 | 137 | static UART_Type *const s_uartBases[] = UART_BASE_PTRS; |
<> | 144:ef7eb2e8f9f7 | 138 | |
<> | 144:ef7eb2e8f9f7 | 139 | /* Array of UART IRQ number. */ |
<> | 144:ef7eb2e8f9f7 | 140 | static const IRQn_Type s_uartIRQ[] = UART_RX_TX_IRQS; |
<> | 144:ef7eb2e8f9f7 | 141 | /* Array of UART clock name. */ |
<> | 144:ef7eb2e8f9f7 | 142 | static const clock_ip_name_t s_uartClock[] = UART_CLOCKS; |
<> | 144:ef7eb2e8f9f7 | 143 | |
<> | 144:ef7eb2e8f9f7 | 144 | /* UART ISR for transactional APIs. */ |
<> | 144:ef7eb2e8f9f7 | 145 | static uart_isr_t s_uartIsr; |
<> | 144:ef7eb2e8f9f7 | 146 | |
<> | 144:ef7eb2e8f9f7 | 147 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 148 | * Code |
<> | 144:ef7eb2e8f9f7 | 149 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 150 | |
<> | 144:ef7eb2e8f9f7 | 151 | uint32_t UART_GetInstance(UART_Type *base) |
<> | 144:ef7eb2e8f9f7 | 152 | { |
<> | 144:ef7eb2e8f9f7 | 153 | uint32_t instance; |
<> | 144:ef7eb2e8f9f7 | 154 | uint32_t uartArrayCount = (sizeof(s_uartBases) / sizeof(s_uartBases[0])); |
<> | 144:ef7eb2e8f9f7 | 155 | |
<> | 144:ef7eb2e8f9f7 | 156 | /* Find the instance index from base address mappings. */ |
<> | 144:ef7eb2e8f9f7 | 157 | for (instance = 0; instance < uartArrayCount; instance++) |
<> | 144:ef7eb2e8f9f7 | 158 | { |
<> | 144:ef7eb2e8f9f7 | 159 | if (s_uartBases[instance] == base) |
<> | 144:ef7eb2e8f9f7 | 160 | { |
<> | 144:ef7eb2e8f9f7 | 161 | break; |
<> | 144:ef7eb2e8f9f7 | 162 | } |
<> | 144:ef7eb2e8f9f7 | 163 | } |
<> | 144:ef7eb2e8f9f7 | 164 | |
<> | 144:ef7eb2e8f9f7 | 165 | assert(instance < uartArrayCount); |
<> | 144:ef7eb2e8f9f7 | 166 | |
<> | 144:ef7eb2e8f9f7 | 167 | return instance; |
<> | 144:ef7eb2e8f9f7 | 168 | } |
<> | 144:ef7eb2e8f9f7 | 169 | |
<> | 144:ef7eb2e8f9f7 | 170 | static size_t UART_TransferGetRxRingBufferLength(uart_handle_t *handle) |
<> | 144:ef7eb2e8f9f7 | 171 | { |
<> | 144:ef7eb2e8f9f7 | 172 | size_t size; |
<> | 144:ef7eb2e8f9f7 | 173 | |
<> | 144:ef7eb2e8f9f7 | 174 | if (handle->rxRingBufferTail > handle->rxRingBufferHead) |
<> | 144:ef7eb2e8f9f7 | 175 | { |
<> | 144:ef7eb2e8f9f7 | 176 | size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail); |
<> | 144:ef7eb2e8f9f7 | 177 | } |
<> | 144:ef7eb2e8f9f7 | 178 | else |
<> | 144:ef7eb2e8f9f7 | 179 | { |
<> | 144:ef7eb2e8f9f7 | 180 | size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail); |
<> | 144:ef7eb2e8f9f7 | 181 | } |
<> | 144:ef7eb2e8f9f7 | 182 | |
<> | 144:ef7eb2e8f9f7 | 183 | return size; |
<> | 144:ef7eb2e8f9f7 | 184 | } |
<> | 144:ef7eb2e8f9f7 | 185 | |
<> | 144:ef7eb2e8f9f7 | 186 | static bool UART_TransferIsRxRingBufferFull(uart_handle_t *handle) |
<> | 144:ef7eb2e8f9f7 | 187 | { |
<> | 144:ef7eb2e8f9f7 | 188 | bool full; |
<> | 144:ef7eb2e8f9f7 | 189 | |
<> | 144:ef7eb2e8f9f7 | 190 | if (UART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U)) |
<> | 144:ef7eb2e8f9f7 | 191 | { |
<> | 144:ef7eb2e8f9f7 | 192 | full = true; |
<> | 144:ef7eb2e8f9f7 | 193 | } |
<> | 144:ef7eb2e8f9f7 | 194 | else |
<> | 144:ef7eb2e8f9f7 | 195 | { |
<> | 144:ef7eb2e8f9f7 | 196 | full = false; |
<> | 144:ef7eb2e8f9f7 | 197 | } |
<> | 144:ef7eb2e8f9f7 | 198 | |
<> | 144:ef7eb2e8f9f7 | 199 | return full; |
<> | 144:ef7eb2e8f9f7 | 200 | } |
<> | 144:ef7eb2e8f9f7 | 201 | |
<> | 144:ef7eb2e8f9f7 | 202 | void UART_Init(UART_Type *base, const uart_config_t *config, uint32_t srcClock_Hz) |
<> | 144:ef7eb2e8f9f7 | 203 | { |
<> | 144:ef7eb2e8f9f7 | 204 | assert(config); |
<> | 144:ef7eb2e8f9f7 | 205 | #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO |
<> | 144:ef7eb2e8f9f7 | 206 | assert(FSL_FEATURE_UART_FIFO_SIZEn(base) >= config->txFifoWatermark); |
<> | 144:ef7eb2e8f9f7 | 207 | assert(FSL_FEATURE_UART_FIFO_SIZEn(base) >= config->rxFifoWatermark); |
<> | 144:ef7eb2e8f9f7 | 208 | #endif |
<> | 144:ef7eb2e8f9f7 | 209 | |
<> | 144:ef7eb2e8f9f7 | 210 | uint16_t sbr; |
<> | 144:ef7eb2e8f9f7 | 211 | uint8_t temp; |
<> | 144:ef7eb2e8f9f7 | 212 | |
<> | 144:ef7eb2e8f9f7 | 213 | /* Enable uart clock */ |
<> | 144:ef7eb2e8f9f7 | 214 | CLOCK_EnableClock(s_uartClock[UART_GetInstance(base)]); |
<> | 144:ef7eb2e8f9f7 | 215 | |
<> | 144:ef7eb2e8f9f7 | 216 | /* Disable UART TX RX before setting. */ |
<> | 144:ef7eb2e8f9f7 | 217 | base->C2 &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK); |
<> | 144:ef7eb2e8f9f7 | 218 | |
<> | 144:ef7eb2e8f9f7 | 219 | /* Calculate the baud rate modulo divisor, sbr*/ |
<> | 144:ef7eb2e8f9f7 | 220 | sbr = srcClock_Hz / (config->baudRate_Bps * 16); |
<> | 144:ef7eb2e8f9f7 | 221 | |
<> | 144:ef7eb2e8f9f7 | 222 | /* Write the sbr value to the BDH and BDL registers*/ |
<> | 144:ef7eb2e8f9f7 | 223 | base->BDH = (base->BDH & ~UART_BDH_SBR_MASK) | (uint8_t)(sbr >> 8); |
<> | 144:ef7eb2e8f9f7 | 224 | base->BDL = (uint8_t)sbr; |
<> | 144:ef7eb2e8f9f7 | 225 | |
<> | 144:ef7eb2e8f9f7 | 226 | #if defined(FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT) && FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT |
<> | 144:ef7eb2e8f9f7 | 227 | /* Determine if a fractional divider is needed to fine tune closer to the |
<> | 144:ef7eb2e8f9f7 | 228 | * desired baud, each value of brfa is in 1/32 increments, |
<> | 144:ef7eb2e8f9f7 | 229 | * hence the multiply-by-32. */ |
<> | 144:ef7eb2e8f9f7 | 230 | uint16_t brfa = (32 * srcClock_Hz / (config->baudRate_Bps * 16)) - 32 * sbr; |
<> | 144:ef7eb2e8f9f7 | 231 | |
<> | 144:ef7eb2e8f9f7 | 232 | /* Write the brfa value to the register*/ |
<> | 144:ef7eb2e8f9f7 | 233 | base->C4 = (base->C4 & ~UART_C4_BRFA_MASK) | (brfa & UART_C4_BRFA_MASK); |
<> | 144:ef7eb2e8f9f7 | 234 | #endif |
<> | 144:ef7eb2e8f9f7 | 235 | |
<> | 144:ef7eb2e8f9f7 | 236 | /* Set bit count and parity mode. */ |
<> | 144:ef7eb2e8f9f7 | 237 | temp = base->C1 & ~(UART_C1_PE_MASK | UART_C1_PT_MASK | UART_C1_M_MASK); |
<> | 144:ef7eb2e8f9f7 | 238 | |
<> | 144:ef7eb2e8f9f7 | 239 | if (kUART_ParityDisabled != config->parityMode) |
<> | 144:ef7eb2e8f9f7 | 240 | { |
<> | 144:ef7eb2e8f9f7 | 241 | temp |= (UART_C1_M_MASK | (uint8_t)config->parityMode); |
<> | 144:ef7eb2e8f9f7 | 242 | } |
<> | 144:ef7eb2e8f9f7 | 243 | |
<> | 144:ef7eb2e8f9f7 | 244 | base->C1 = temp; |
<> | 144:ef7eb2e8f9f7 | 245 | |
<> | 144:ef7eb2e8f9f7 | 246 | #if defined(FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT |
<> | 144:ef7eb2e8f9f7 | 247 | /* Set stop bit per char */ |
<> | 144:ef7eb2e8f9f7 | 248 | base->BDH = (base->BDH & ~UART_BDH_SBNS_MASK) | UART_BDH_SBNS((uint8_t)config->stopBitCount); |
<> | 144:ef7eb2e8f9f7 | 249 | #endif |
<> | 144:ef7eb2e8f9f7 | 250 | |
<> | 144:ef7eb2e8f9f7 | 251 | #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO |
<> | 144:ef7eb2e8f9f7 | 252 | /* Set tx/rx FIFO watermark */ |
<> | 144:ef7eb2e8f9f7 | 253 | base->TWFIFO = config->txFifoWatermark; |
<> | 144:ef7eb2e8f9f7 | 254 | base->RWFIFO = config->rxFifoWatermark; |
<> | 144:ef7eb2e8f9f7 | 255 | |
<> | 144:ef7eb2e8f9f7 | 256 | /* Enable tx/rx FIFO */ |
<> | 144:ef7eb2e8f9f7 | 257 | base->PFIFO |= (UART_PFIFO_TXFE_MASK | UART_PFIFO_RXFE_MASK); |
<> | 144:ef7eb2e8f9f7 | 258 | |
<> | 144:ef7eb2e8f9f7 | 259 | /* Flush FIFO */ |
<> | 144:ef7eb2e8f9f7 | 260 | base->CFIFO |= (UART_CFIFO_TXFLUSH_MASK | UART_CFIFO_RXFLUSH_MASK); |
<> | 144:ef7eb2e8f9f7 | 261 | #endif |
<> | 144:ef7eb2e8f9f7 | 262 | |
<> | 144:ef7eb2e8f9f7 | 263 | /* Enable TX/RX base on configure structure. */ |
<> | 144:ef7eb2e8f9f7 | 264 | temp = base->C2; |
<> | 144:ef7eb2e8f9f7 | 265 | |
<> | 144:ef7eb2e8f9f7 | 266 | if (config->enableTx) |
<> | 144:ef7eb2e8f9f7 | 267 | { |
<> | 144:ef7eb2e8f9f7 | 268 | temp |= UART_C2_TE_MASK; |
<> | 144:ef7eb2e8f9f7 | 269 | } |
<> | 144:ef7eb2e8f9f7 | 270 | |
<> | 144:ef7eb2e8f9f7 | 271 | if (config->enableRx) |
<> | 144:ef7eb2e8f9f7 | 272 | { |
<> | 144:ef7eb2e8f9f7 | 273 | temp |= UART_C2_RE_MASK; |
<> | 144:ef7eb2e8f9f7 | 274 | } |
<> | 144:ef7eb2e8f9f7 | 275 | |
<> | 144:ef7eb2e8f9f7 | 276 | base->C2 = temp; |
<> | 144:ef7eb2e8f9f7 | 277 | } |
<> | 144:ef7eb2e8f9f7 | 278 | |
<> | 144:ef7eb2e8f9f7 | 279 | void UART_Deinit(UART_Type *base) |
<> | 144:ef7eb2e8f9f7 | 280 | { |
<> | 144:ef7eb2e8f9f7 | 281 | #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO |
<> | 144:ef7eb2e8f9f7 | 282 | /* Wait tx FIFO send out*/ |
<> | 144:ef7eb2e8f9f7 | 283 | while (0 != base->TCFIFO) |
<> | 144:ef7eb2e8f9f7 | 284 | { |
<> | 144:ef7eb2e8f9f7 | 285 | } |
<> | 144:ef7eb2e8f9f7 | 286 | #endif |
<> | 144:ef7eb2e8f9f7 | 287 | /* Wait last char shoft out */ |
<> | 144:ef7eb2e8f9f7 | 288 | while (0 == (base->S1 & UART_S1_TC_MASK)) |
<> | 144:ef7eb2e8f9f7 | 289 | { |
<> | 144:ef7eb2e8f9f7 | 290 | } |
<> | 144:ef7eb2e8f9f7 | 291 | |
<> | 144:ef7eb2e8f9f7 | 292 | /* Disable the module. */ |
<> | 144:ef7eb2e8f9f7 | 293 | base->C2 = 0; |
<> | 144:ef7eb2e8f9f7 | 294 | |
<> | 144:ef7eb2e8f9f7 | 295 | /* Disable uart clock */ |
<> | 144:ef7eb2e8f9f7 | 296 | CLOCK_DisableClock(s_uartClock[UART_GetInstance(base)]); |
<> | 144:ef7eb2e8f9f7 | 297 | } |
<> | 144:ef7eb2e8f9f7 | 298 | |
<> | 144:ef7eb2e8f9f7 | 299 | void UART_GetDefaultConfig(uart_config_t *config) |
<> | 144:ef7eb2e8f9f7 | 300 | { |
<> | 144:ef7eb2e8f9f7 | 301 | assert(config); |
<> | 144:ef7eb2e8f9f7 | 302 | |
<> | 144:ef7eb2e8f9f7 | 303 | config->baudRate_Bps = 115200U; |
<> | 144:ef7eb2e8f9f7 | 304 | config->parityMode = kUART_ParityDisabled; |
<> | 144:ef7eb2e8f9f7 | 305 | #if defined(FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT |
<> | 144:ef7eb2e8f9f7 | 306 | config->stopBitCount = kUART_OneStopBit; |
<> | 144:ef7eb2e8f9f7 | 307 | #endif |
<> | 144:ef7eb2e8f9f7 | 308 | #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO |
<> | 144:ef7eb2e8f9f7 | 309 | config->txFifoWatermark = 0; |
<> | 144:ef7eb2e8f9f7 | 310 | config->rxFifoWatermark = 1; |
<> | 144:ef7eb2e8f9f7 | 311 | #endif |
<> | 144:ef7eb2e8f9f7 | 312 | config->enableTx = false; |
<> | 144:ef7eb2e8f9f7 | 313 | config->enableRx = false; |
<> | 144:ef7eb2e8f9f7 | 314 | } |
<> | 144:ef7eb2e8f9f7 | 315 | |
<> | 144:ef7eb2e8f9f7 | 316 | void UART_SetBaudRate(UART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) |
<> | 144:ef7eb2e8f9f7 | 317 | { |
<> | 144:ef7eb2e8f9f7 | 318 | uint16_t sbr; |
<> | 144:ef7eb2e8f9f7 | 319 | uint8_t oldCtrl; |
<> | 144:ef7eb2e8f9f7 | 320 | |
<> | 144:ef7eb2e8f9f7 | 321 | /* Store C2 before disable Tx and Rx */ |
<> | 144:ef7eb2e8f9f7 | 322 | oldCtrl = base->C2; |
<> | 144:ef7eb2e8f9f7 | 323 | |
<> | 144:ef7eb2e8f9f7 | 324 | /* Disable UART TX RX before setting. */ |
<> | 144:ef7eb2e8f9f7 | 325 | base->C2 &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK); |
<> | 144:ef7eb2e8f9f7 | 326 | |
<> | 144:ef7eb2e8f9f7 | 327 | /* Calculate the baud rate modulo divisor, sbr*/ |
<> | 144:ef7eb2e8f9f7 | 328 | sbr = srcClock_Hz / (baudRate_Bps * 16); |
<> | 144:ef7eb2e8f9f7 | 329 | |
<> | 144:ef7eb2e8f9f7 | 330 | /* Write the sbr value to the BDH and BDL registers*/ |
<> | 144:ef7eb2e8f9f7 | 331 | base->BDH = (base->BDH & ~UART_BDH_SBR_MASK) | (uint8_t)(sbr >> 8); |
<> | 144:ef7eb2e8f9f7 | 332 | base->BDL = (uint8_t)sbr; |
<> | 144:ef7eb2e8f9f7 | 333 | |
<> | 144:ef7eb2e8f9f7 | 334 | #if defined(FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT) && FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT |
<> | 144:ef7eb2e8f9f7 | 335 | /* Determine if a fractional divider is needed to fine tune closer to the |
<> | 144:ef7eb2e8f9f7 | 336 | * desired baud, each value of brfa is in 1/32 increments, |
<> | 144:ef7eb2e8f9f7 | 337 | * hence the multiply-by-32. */ |
<> | 144:ef7eb2e8f9f7 | 338 | uint16_t brfa = (32 * srcClock_Hz / (baudRate_Bps * 16)) - 32 * sbr; |
<> | 144:ef7eb2e8f9f7 | 339 | |
<> | 144:ef7eb2e8f9f7 | 340 | /* Write the brfa value to the register*/ |
<> | 144:ef7eb2e8f9f7 | 341 | base->C4 = (base->C4 & ~UART_C4_BRFA_MASK) | (brfa & UART_C4_BRFA_MASK); |
<> | 144:ef7eb2e8f9f7 | 342 | #endif |
<> | 144:ef7eb2e8f9f7 | 343 | |
<> | 144:ef7eb2e8f9f7 | 344 | /* Restore C2. */ |
<> | 144:ef7eb2e8f9f7 | 345 | base->C2 = oldCtrl; |
<> | 144:ef7eb2e8f9f7 | 346 | } |
<> | 144:ef7eb2e8f9f7 | 347 | |
<> | 144:ef7eb2e8f9f7 | 348 | void UART_EnableInterrupts(UART_Type *base, uint32_t mask) |
<> | 144:ef7eb2e8f9f7 | 349 | { |
<> | 144:ef7eb2e8f9f7 | 350 | /* The interrupt mask is combined by control bits from several register: ((CFIFO<<24) | (C3<<16) | (C2<<8) |(BDH)) |
<> | 144:ef7eb2e8f9f7 | 351 | */ |
<> | 144:ef7eb2e8f9f7 | 352 | base->BDH |= (mask & 0xFF); |
<> | 144:ef7eb2e8f9f7 | 353 | base->C2 |= ((mask >> 8) & 0xFF); |
<> | 144:ef7eb2e8f9f7 | 354 | base->C3 |= ((mask >> 16) & 0xFF); |
<> | 144:ef7eb2e8f9f7 | 355 | |
<> | 144:ef7eb2e8f9f7 | 356 | #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO |
<> | 144:ef7eb2e8f9f7 | 357 | base->CFIFO |= ((mask >> 24) & 0xFF); |
<> | 144:ef7eb2e8f9f7 | 358 | #endif |
<> | 144:ef7eb2e8f9f7 | 359 | } |
<> | 144:ef7eb2e8f9f7 | 360 | |
<> | 144:ef7eb2e8f9f7 | 361 | void UART_DisableInterrupts(UART_Type *base, uint32_t mask) |
<> | 144:ef7eb2e8f9f7 | 362 | { |
<> | 144:ef7eb2e8f9f7 | 363 | /* The interrupt mask is combined by control bits from several register: ((CFIFO<<24) | (C3<<16) | (C2<<8) |(BDH)) |
<> | 144:ef7eb2e8f9f7 | 364 | */ |
<> | 144:ef7eb2e8f9f7 | 365 | base->BDH &= ~(mask & 0xFF); |
<> | 144:ef7eb2e8f9f7 | 366 | base->C2 &= ~((mask >> 8) & 0xFF); |
<> | 144:ef7eb2e8f9f7 | 367 | base->C3 &= ~((mask >> 16) & 0xFF); |
<> | 144:ef7eb2e8f9f7 | 368 | |
<> | 144:ef7eb2e8f9f7 | 369 | #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO |
<> | 144:ef7eb2e8f9f7 | 370 | base->CFIFO &= ~((mask >> 24) & 0xFF); |
<> | 144:ef7eb2e8f9f7 | 371 | #endif |
<> | 144:ef7eb2e8f9f7 | 372 | } |
<> | 144:ef7eb2e8f9f7 | 373 | |
<> | 144:ef7eb2e8f9f7 | 374 | uint32_t UART_GetEnabledInterrupts(UART_Type *base) |
<> | 144:ef7eb2e8f9f7 | 375 | { |
<> | 144:ef7eb2e8f9f7 | 376 | uint32_t temp; |
<> | 144:ef7eb2e8f9f7 | 377 | |
<> | 144:ef7eb2e8f9f7 | 378 | temp = base->BDH | ((uint32_t)(base->C2) << 8) | ((uint32_t)(base->C3) << 16); |
<> | 144:ef7eb2e8f9f7 | 379 | |
<> | 144:ef7eb2e8f9f7 | 380 | #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO |
<> | 144:ef7eb2e8f9f7 | 381 | temp |= ((uint32_t)(base->CFIFO) << 24); |
<> | 144:ef7eb2e8f9f7 | 382 | #endif |
<> | 144:ef7eb2e8f9f7 | 383 | |
<> | 144:ef7eb2e8f9f7 | 384 | return temp; |
<> | 144:ef7eb2e8f9f7 | 385 | } |
<> | 144:ef7eb2e8f9f7 | 386 | |
<> | 144:ef7eb2e8f9f7 | 387 | uint32_t UART_GetStatusFlags(UART_Type *base) |
<> | 144:ef7eb2e8f9f7 | 388 | { |
<> | 144:ef7eb2e8f9f7 | 389 | uint32_t status_flag; |
<> | 144:ef7eb2e8f9f7 | 390 | |
<> | 144:ef7eb2e8f9f7 | 391 | status_flag = base->S1 | ((uint32_t)(base->S2) << 8); |
<> | 144:ef7eb2e8f9f7 | 392 | |
<> | 144:ef7eb2e8f9f7 | 393 | #if defined(FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS) && FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS |
<> | 144:ef7eb2e8f9f7 | 394 | status_flag |= ((uint32_t)(base->ED) << 16); |
<> | 144:ef7eb2e8f9f7 | 395 | #endif |
<> | 144:ef7eb2e8f9f7 | 396 | |
<> | 144:ef7eb2e8f9f7 | 397 | #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO |
<> | 144:ef7eb2e8f9f7 | 398 | status_flag |= ((uint32_t)(base->SFIFO) << 24); |
<> | 144:ef7eb2e8f9f7 | 399 | #endif |
<> | 144:ef7eb2e8f9f7 | 400 | |
<> | 144:ef7eb2e8f9f7 | 401 | return status_flag; |
<> | 144:ef7eb2e8f9f7 | 402 | } |
<> | 144:ef7eb2e8f9f7 | 403 | |
<> | 144:ef7eb2e8f9f7 | 404 | status_t UART_ClearStatusFlags(UART_Type *base, uint32_t mask) |
<> | 144:ef7eb2e8f9f7 | 405 | { |
<> | 144:ef7eb2e8f9f7 | 406 | uint8_t reg = base->S2; |
<> | 144:ef7eb2e8f9f7 | 407 | status_t status; |
<> | 144:ef7eb2e8f9f7 | 408 | |
<> | 144:ef7eb2e8f9f7 | 409 | #if defined(FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT |
<> | 144:ef7eb2e8f9f7 | 410 | reg &= ~(UART_S2_RXEDGIF_MASK | UART_S2_LBKDIF_MASK); |
<> | 144:ef7eb2e8f9f7 | 411 | #else |
<> | 144:ef7eb2e8f9f7 | 412 | reg &= ~UART_S2_RXEDGIF_MASK; |
<> | 144:ef7eb2e8f9f7 | 413 | #endif |
<> | 144:ef7eb2e8f9f7 | 414 | |
<> | 144:ef7eb2e8f9f7 | 415 | base->S2 = reg | (uint8_t)(mask >> 8); |
<> | 144:ef7eb2e8f9f7 | 416 | |
<> | 144:ef7eb2e8f9f7 | 417 | #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO |
<> | 144:ef7eb2e8f9f7 | 418 | base->SFIFO = (uint8_t)(mask >> 24); |
<> | 144:ef7eb2e8f9f7 | 419 | #endif |
<> | 144:ef7eb2e8f9f7 | 420 | |
<> | 144:ef7eb2e8f9f7 | 421 | if (mask & (kUART_IdleLineFlag | kUART_RxOverrunFlag | kUART_NoiseErrorFlag | kUART_FramingErrorFlag | |
<> | 144:ef7eb2e8f9f7 | 422 | kUART_ParityErrorFlag)) |
<> | 144:ef7eb2e8f9f7 | 423 | { |
<> | 144:ef7eb2e8f9f7 | 424 | /* Read base->D to clear the flags. */ |
<> | 144:ef7eb2e8f9f7 | 425 | (void)base->S1; |
<> | 144:ef7eb2e8f9f7 | 426 | (void)base->D; |
<> | 144:ef7eb2e8f9f7 | 427 | } |
<> | 144:ef7eb2e8f9f7 | 428 | |
<> | 144:ef7eb2e8f9f7 | 429 | /* If some flags still pending. */ |
<> | 144:ef7eb2e8f9f7 | 430 | if (mask & UART_GetStatusFlags(base)) |
<> | 144:ef7eb2e8f9f7 | 431 | { |
<> | 144:ef7eb2e8f9f7 | 432 | /* Some flags can only clear or set by the hardware itself, these flags are: kUART_TxDataRegEmptyFlag, |
<> | 144:ef7eb2e8f9f7 | 433 | kUART_TransmissionCompleteFlag, kUART_RxDataRegFullFlag, kUART_RxActiveFlag, kUART_NoiseErrorInRxDataRegFlag, |
<> | 144:ef7eb2e8f9f7 | 434 | kUART_ParityErrorInRxDataRegFlag, kUART_TxFifoEmptyFlag, kUART_RxFifoEmptyFlag. */ |
<> | 144:ef7eb2e8f9f7 | 435 | status = kStatus_UART_FlagCannotClearManually; |
<> | 144:ef7eb2e8f9f7 | 436 | } |
<> | 144:ef7eb2e8f9f7 | 437 | else |
<> | 144:ef7eb2e8f9f7 | 438 | { |
<> | 144:ef7eb2e8f9f7 | 439 | status = kStatus_Success; |
<> | 144:ef7eb2e8f9f7 | 440 | } |
<> | 144:ef7eb2e8f9f7 | 441 | |
<> | 144:ef7eb2e8f9f7 | 442 | return status; |
<> | 144:ef7eb2e8f9f7 | 443 | } |
<> | 144:ef7eb2e8f9f7 | 444 | |
<> | 144:ef7eb2e8f9f7 | 445 | void UART_WriteBlocking(UART_Type *base, const uint8_t *data, size_t length) |
<> | 144:ef7eb2e8f9f7 | 446 | { |
<> | 144:ef7eb2e8f9f7 | 447 | /* This API can only ensure that the data is written into the data buffer but can't |
<> | 144:ef7eb2e8f9f7 | 448 | ensure all data in the data buffer are sent into the transmit shift buffer. */ |
<> | 144:ef7eb2e8f9f7 | 449 | while (length--) |
<> | 144:ef7eb2e8f9f7 | 450 | { |
<> | 144:ef7eb2e8f9f7 | 451 | while (!(base->S1 & UART_S1_TDRE_MASK)) |
<> | 144:ef7eb2e8f9f7 | 452 | { |
<> | 144:ef7eb2e8f9f7 | 453 | } |
<> | 144:ef7eb2e8f9f7 | 454 | base->D = *(data++); |
<> | 144:ef7eb2e8f9f7 | 455 | } |
<> | 144:ef7eb2e8f9f7 | 456 | } |
<> | 144:ef7eb2e8f9f7 | 457 | |
<> | 144:ef7eb2e8f9f7 | 458 | static void UART_WriteNonBlocking(UART_Type *base, const uint8_t *data, size_t length) |
<> | 144:ef7eb2e8f9f7 | 459 | { |
<> | 144:ef7eb2e8f9f7 | 460 | size_t i; |
<> | 144:ef7eb2e8f9f7 | 461 | |
<> | 144:ef7eb2e8f9f7 | 462 | /* The Non Blocking write data API assume user have ensured there is enough space in |
<> | 144:ef7eb2e8f9f7 | 463 | peripheral to write. */ |
<> | 144:ef7eb2e8f9f7 | 464 | for (i = 0; i < length; i++) |
<> | 144:ef7eb2e8f9f7 | 465 | { |
<> | 144:ef7eb2e8f9f7 | 466 | base->D = data[i]; |
<> | 144:ef7eb2e8f9f7 | 467 | } |
<> | 144:ef7eb2e8f9f7 | 468 | } |
<> | 144:ef7eb2e8f9f7 | 469 | |
<> | 144:ef7eb2e8f9f7 | 470 | status_t UART_ReadBlocking(UART_Type *base, uint8_t *data, size_t length) |
<> | 144:ef7eb2e8f9f7 | 471 | { |
<> | 144:ef7eb2e8f9f7 | 472 | uint32_t statusFlag; |
<> | 144:ef7eb2e8f9f7 | 473 | |
<> | 144:ef7eb2e8f9f7 | 474 | while (length--) |
<> | 144:ef7eb2e8f9f7 | 475 | { |
<> | 144:ef7eb2e8f9f7 | 476 | #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO |
<> | 144:ef7eb2e8f9f7 | 477 | while (!base->RCFIFO) |
<> | 144:ef7eb2e8f9f7 | 478 | #else |
<> | 144:ef7eb2e8f9f7 | 479 | while (!(base->S1 & UART_S1_RDRF_MASK)) |
<> | 144:ef7eb2e8f9f7 | 480 | #endif |
<> | 144:ef7eb2e8f9f7 | 481 | { |
<> | 144:ef7eb2e8f9f7 | 482 | statusFlag = UART_GetStatusFlags(base); |
<> | 144:ef7eb2e8f9f7 | 483 | |
<> | 144:ef7eb2e8f9f7 | 484 | if (statusFlag & kUART_RxOverrunFlag) |
<> | 144:ef7eb2e8f9f7 | 485 | { |
<> | 144:ef7eb2e8f9f7 | 486 | return kStatus_UART_RxHardwareOverrun; |
<> | 144:ef7eb2e8f9f7 | 487 | } |
<> | 144:ef7eb2e8f9f7 | 488 | |
<> | 144:ef7eb2e8f9f7 | 489 | if (statusFlag & kUART_NoiseErrorFlag) |
<> | 144:ef7eb2e8f9f7 | 490 | { |
<> | 144:ef7eb2e8f9f7 | 491 | return kStatus_UART_NoiseError; |
<> | 144:ef7eb2e8f9f7 | 492 | } |
<> | 144:ef7eb2e8f9f7 | 493 | |
<> | 144:ef7eb2e8f9f7 | 494 | if (statusFlag & kUART_FramingErrorFlag) |
<> | 144:ef7eb2e8f9f7 | 495 | { |
<> | 144:ef7eb2e8f9f7 | 496 | return kStatus_UART_FramingError; |
<> | 144:ef7eb2e8f9f7 | 497 | } |
<> | 144:ef7eb2e8f9f7 | 498 | |
<> | 144:ef7eb2e8f9f7 | 499 | if (statusFlag & kUART_ParityErrorFlag) |
<> | 144:ef7eb2e8f9f7 | 500 | { |
<> | 144:ef7eb2e8f9f7 | 501 | return kStatus_UART_ParityError; |
<> | 144:ef7eb2e8f9f7 | 502 | } |
<> | 144:ef7eb2e8f9f7 | 503 | } |
<> | 144:ef7eb2e8f9f7 | 504 | *(data++) = base->D; |
<> | 144:ef7eb2e8f9f7 | 505 | } |
<> | 144:ef7eb2e8f9f7 | 506 | |
<> | 144:ef7eb2e8f9f7 | 507 | return kStatus_Success; |
<> | 144:ef7eb2e8f9f7 | 508 | } |
<> | 144:ef7eb2e8f9f7 | 509 | |
<> | 144:ef7eb2e8f9f7 | 510 | static void UART_ReadNonBlocking(UART_Type *base, uint8_t *data, size_t length) |
<> | 144:ef7eb2e8f9f7 | 511 | { |
<> | 144:ef7eb2e8f9f7 | 512 | size_t i; |
<> | 144:ef7eb2e8f9f7 | 513 | |
<> | 144:ef7eb2e8f9f7 | 514 | /* The Non Blocking read data API assume user have ensured there is enough space in |
<> | 144:ef7eb2e8f9f7 | 515 | peripheral to write. */ |
<> | 144:ef7eb2e8f9f7 | 516 | for (i = 0; i < length; i++) |
<> | 144:ef7eb2e8f9f7 | 517 | { |
<> | 144:ef7eb2e8f9f7 | 518 | data[i] = base->D; |
<> | 144:ef7eb2e8f9f7 | 519 | } |
<> | 144:ef7eb2e8f9f7 | 520 | } |
<> | 144:ef7eb2e8f9f7 | 521 | |
<> | 144:ef7eb2e8f9f7 | 522 | void UART_TransferCreateHandle(UART_Type *base, |
<> | 144:ef7eb2e8f9f7 | 523 | uart_handle_t *handle, |
<> | 144:ef7eb2e8f9f7 | 524 | uart_transfer_callback_t callback, |
<> | 144:ef7eb2e8f9f7 | 525 | void *userData) |
<> | 144:ef7eb2e8f9f7 | 526 | { |
<> | 144:ef7eb2e8f9f7 | 527 | assert(handle); |
<> | 144:ef7eb2e8f9f7 | 528 | |
<> | 144:ef7eb2e8f9f7 | 529 | uint32_t instance; |
<> | 144:ef7eb2e8f9f7 | 530 | |
<> | 144:ef7eb2e8f9f7 | 531 | /* Zero the handle. */ |
<> | 144:ef7eb2e8f9f7 | 532 | memset(handle, 0, sizeof(*handle)); |
<> | 144:ef7eb2e8f9f7 | 533 | |
<> | 144:ef7eb2e8f9f7 | 534 | /* Set the TX/RX state. */ |
<> | 144:ef7eb2e8f9f7 | 535 | handle->rxState = kUART_RxIdle; |
<> | 144:ef7eb2e8f9f7 | 536 | handle->txState = kUART_TxIdle; |
<> | 144:ef7eb2e8f9f7 | 537 | |
<> | 144:ef7eb2e8f9f7 | 538 | /* Set the callback and user data. */ |
<> | 144:ef7eb2e8f9f7 | 539 | handle->callback = callback; |
<> | 144:ef7eb2e8f9f7 | 540 | handle->userData = userData; |
<> | 144:ef7eb2e8f9f7 | 541 | |
<> | 144:ef7eb2e8f9f7 | 542 | #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO |
<> | 144:ef7eb2e8f9f7 | 543 | /* Note: |
<> | 144:ef7eb2e8f9f7 | 544 | Take care of the RX FIFO, RX interrupt request only assert when received bytes |
<> | 144:ef7eb2e8f9f7 | 545 | equal or more than RX water mark, there is potential issue if RX water |
<> | 144:ef7eb2e8f9f7 | 546 | mark larger than 1. |
<> | 144:ef7eb2e8f9f7 | 547 | For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and |
<> | 144:ef7eb2e8f9f7 | 548 | 5 bytes are received. the last byte will be saved in FIFO but not trigger |
<> | 144:ef7eb2e8f9f7 | 549 | RX interrupt because the water mark is 2. |
<> | 144:ef7eb2e8f9f7 | 550 | */ |
<> | 144:ef7eb2e8f9f7 | 551 | base->RWFIFO = 1U; |
<> | 144:ef7eb2e8f9f7 | 552 | #endif |
<> | 144:ef7eb2e8f9f7 | 553 | |
<> | 144:ef7eb2e8f9f7 | 554 | /* Get instance from peripheral base address. */ |
<> | 144:ef7eb2e8f9f7 | 555 | instance = UART_GetInstance(base); |
<> | 144:ef7eb2e8f9f7 | 556 | |
<> | 144:ef7eb2e8f9f7 | 557 | /* Save the handle in global variables to support the double weak mechanism. */ |
<> | 144:ef7eb2e8f9f7 | 558 | s_uartHandle[instance] = handle; |
<> | 144:ef7eb2e8f9f7 | 559 | |
<> | 144:ef7eb2e8f9f7 | 560 | s_uartIsr = UART_TransferHandleIRQ; |
<> | 144:ef7eb2e8f9f7 | 561 | |
<> | 144:ef7eb2e8f9f7 | 562 | /* Enable interrupt in NVIC. */ |
<> | 144:ef7eb2e8f9f7 | 563 | EnableIRQ(s_uartIRQ[instance]); |
<> | 144:ef7eb2e8f9f7 | 564 | } |
<> | 144:ef7eb2e8f9f7 | 565 | |
<> | 144:ef7eb2e8f9f7 | 566 | void UART_TransferStartRingBuffer(UART_Type *base, uart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize) |
<> | 144:ef7eb2e8f9f7 | 567 | { |
<> | 144:ef7eb2e8f9f7 | 568 | assert(handle); |
<> | 144:ef7eb2e8f9f7 | 569 | |
<> | 144:ef7eb2e8f9f7 | 570 | /* Setup the ringbuffer address */ |
<> | 144:ef7eb2e8f9f7 | 571 | if (ringBuffer) |
<> | 144:ef7eb2e8f9f7 | 572 | { |
<> | 144:ef7eb2e8f9f7 | 573 | handle->rxRingBuffer = ringBuffer; |
<> | 144:ef7eb2e8f9f7 | 574 | handle->rxRingBufferSize = ringBufferSize; |
<> | 144:ef7eb2e8f9f7 | 575 | handle->rxRingBufferHead = 0U; |
<> | 144:ef7eb2e8f9f7 | 576 | handle->rxRingBufferTail = 0U; |
<> | 144:ef7eb2e8f9f7 | 577 | |
<> | 144:ef7eb2e8f9f7 | 578 | /* Enable the interrupt to accept the data when user need the ring buffer. */ |
<> | 144:ef7eb2e8f9f7 | 579 | UART_EnableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable); |
<> | 144:ef7eb2e8f9f7 | 580 | } |
<> | 144:ef7eb2e8f9f7 | 581 | } |
<> | 144:ef7eb2e8f9f7 | 582 | |
<> | 144:ef7eb2e8f9f7 | 583 | void UART_TransferStopRingBuffer(UART_Type *base, uart_handle_t *handle) |
<> | 144:ef7eb2e8f9f7 | 584 | { |
<> | 144:ef7eb2e8f9f7 | 585 | assert(handle); |
<> | 144:ef7eb2e8f9f7 | 586 | |
<> | 144:ef7eb2e8f9f7 | 587 | if (handle->rxState == kUART_RxIdle) |
<> | 144:ef7eb2e8f9f7 | 588 | { |
<> | 144:ef7eb2e8f9f7 | 589 | UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable); |
<> | 144:ef7eb2e8f9f7 | 590 | } |
<> | 144:ef7eb2e8f9f7 | 591 | |
<> | 144:ef7eb2e8f9f7 | 592 | handle->rxRingBuffer = NULL; |
<> | 144:ef7eb2e8f9f7 | 593 | handle->rxRingBufferSize = 0U; |
<> | 144:ef7eb2e8f9f7 | 594 | handle->rxRingBufferHead = 0U; |
<> | 144:ef7eb2e8f9f7 | 595 | handle->rxRingBufferTail = 0U; |
<> | 144:ef7eb2e8f9f7 | 596 | } |
<> | 144:ef7eb2e8f9f7 | 597 | |
<> | 144:ef7eb2e8f9f7 | 598 | status_t UART_TransferSendNonBlocking(UART_Type *base, uart_handle_t *handle, uart_transfer_t *xfer) |
<> | 144:ef7eb2e8f9f7 | 599 | { |
<> | 144:ef7eb2e8f9f7 | 600 | status_t status; |
<> | 144:ef7eb2e8f9f7 | 601 | |
<> | 144:ef7eb2e8f9f7 | 602 | /* Return error if xfer invalid. */ |
<> | 144:ef7eb2e8f9f7 | 603 | if ((0U == xfer->dataSize) || (NULL == xfer->data)) |
<> | 144:ef7eb2e8f9f7 | 604 | { |
<> | 144:ef7eb2e8f9f7 | 605 | return kStatus_InvalidArgument; |
<> | 144:ef7eb2e8f9f7 | 606 | } |
<> | 144:ef7eb2e8f9f7 | 607 | |
<> | 144:ef7eb2e8f9f7 | 608 | /* Return error if current TX busy. */ |
<> | 144:ef7eb2e8f9f7 | 609 | if (kUART_TxBusy == handle->txState) |
<> | 144:ef7eb2e8f9f7 | 610 | { |
<> | 144:ef7eb2e8f9f7 | 611 | status = kStatus_UART_TxBusy; |
<> | 144:ef7eb2e8f9f7 | 612 | } |
<> | 144:ef7eb2e8f9f7 | 613 | else |
<> | 144:ef7eb2e8f9f7 | 614 | { |
<> | 144:ef7eb2e8f9f7 | 615 | handle->txData = xfer->data; |
<> | 144:ef7eb2e8f9f7 | 616 | handle->txDataSize = xfer->dataSize; |
<> | 144:ef7eb2e8f9f7 | 617 | handle->txDataSizeAll = xfer->dataSize; |
<> | 144:ef7eb2e8f9f7 | 618 | handle->txState = kUART_TxBusy; |
<> | 144:ef7eb2e8f9f7 | 619 | |
<> | 144:ef7eb2e8f9f7 | 620 | /* Enable transmiter interrupt. */ |
<> | 144:ef7eb2e8f9f7 | 621 | UART_EnableInterrupts(base, kUART_TxDataRegEmptyInterruptEnable); |
<> | 144:ef7eb2e8f9f7 | 622 | |
<> | 144:ef7eb2e8f9f7 | 623 | status = kStatus_Success; |
<> | 144:ef7eb2e8f9f7 | 624 | } |
<> | 144:ef7eb2e8f9f7 | 625 | |
<> | 144:ef7eb2e8f9f7 | 626 | return status; |
<> | 144:ef7eb2e8f9f7 | 627 | } |
<> | 144:ef7eb2e8f9f7 | 628 | |
<> | 144:ef7eb2e8f9f7 | 629 | void UART_TransferAbortSend(UART_Type *base, uart_handle_t *handle) |
<> | 144:ef7eb2e8f9f7 | 630 | { |
<> | 144:ef7eb2e8f9f7 | 631 | UART_DisableInterrupts(base, kUART_TxDataRegEmptyInterruptEnable | kUART_TransmissionCompleteInterruptEnable); |
<> | 144:ef7eb2e8f9f7 | 632 | |
<> | 144:ef7eb2e8f9f7 | 633 | handle->txDataSize = 0; |
<> | 144:ef7eb2e8f9f7 | 634 | handle->txState = kUART_TxIdle; |
<> | 144:ef7eb2e8f9f7 | 635 | } |
<> | 144:ef7eb2e8f9f7 | 636 | |
<> | 144:ef7eb2e8f9f7 | 637 | status_t UART_TransferGetSendCount(UART_Type *base, uart_handle_t *handle, uint32_t *count) |
<> | 144:ef7eb2e8f9f7 | 638 | { |
<> | 144:ef7eb2e8f9f7 | 639 | if (kUART_TxIdle == handle->txState) |
<> | 144:ef7eb2e8f9f7 | 640 | { |
<> | 144:ef7eb2e8f9f7 | 641 | return kStatus_NoTransferInProgress; |
<> | 144:ef7eb2e8f9f7 | 642 | } |
<> | 144:ef7eb2e8f9f7 | 643 | |
<> | 144:ef7eb2e8f9f7 | 644 | if (!count) |
<> | 144:ef7eb2e8f9f7 | 645 | { |
<> | 144:ef7eb2e8f9f7 | 646 | return kStatus_InvalidArgument; |
<> | 144:ef7eb2e8f9f7 | 647 | } |
<> | 144:ef7eb2e8f9f7 | 648 | |
<> | 144:ef7eb2e8f9f7 | 649 | *count = handle->txDataSizeAll - handle->txDataSize; |
<> | 144:ef7eb2e8f9f7 | 650 | |
<> | 144:ef7eb2e8f9f7 | 651 | return kStatus_Success; |
<> | 144:ef7eb2e8f9f7 | 652 | } |
<> | 144:ef7eb2e8f9f7 | 653 | |
<> | 144:ef7eb2e8f9f7 | 654 | status_t UART_TransferReceiveNonBlocking(UART_Type *base, |
<> | 144:ef7eb2e8f9f7 | 655 | uart_handle_t *handle, |
<> | 144:ef7eb2e8f9f7 | 656 | uart_transfer_t *xfer, |
<> | 144:ef7eb2e8f9f7 | 657 | size_t *receivedBytes) |
<> | 144:ef7eb2e8f9f7 | 658 | { |
<> | 144:ef7eb2e8f9f7 | 659 | uint32_t i; |
<> | 144:ef7eb2e8f9f7 | 660 | status_t status; |
<> | 144:ef7eb2e8f9f7 | 661 | /* How many bytes to copy from ring buffer to user memory. */ |
<> | 144:ef7eb2e8f9f7 | 662 | size_t bytesToCopy = 0U; |
<> | 144:ef7eb2e8f9f7 | 663 | /* How many bytes to receive. */ |
<> | 144:ef7eb2e8f9f7 | 664 | size_t bytesToReceive; |
<> | 144:ef7eb2e8f9f7 | 665 | /* How many bytes currently have received. */ |
<> | 144:ef7eb2e8f9f7 | 666 | size_t bytesCurrentReceived; |
<> | 144:ef7eb2e8f9f7 | 667 | uint32_t regPrimask = 0U; |
<> | 144:ef7eb2e8f9f7 | 668 | |
<> | 144:ef7eb2e8f9f7 | 669 | /* Return error if xfer invalid. */ |
<> | 144:ef7eb2e8f9f7 | 670 | if ((0U == xfer->dataSize) || (NULL == xfer->data)) |
<> | 144:ef7eb2e8f9f7 | 671 | { |
<> | 144:ef7eb2e8f9f7 | 672 | return kStatus_InvalidArgument; |
<> | 144:ef7eb2e8f9f7 | 673 | } |
<> | 144:ef7eb2e8f9f7 | 674 | |
<> | 144:ef7eb2e8f9f7 | 675 | /* How to get data: |
<> | 144:ef7eb2e8f9f7 | 676 | 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize |
<> | 144:ef7eb2e8f9f7 | 677 | to uart handle, enable interrupt to store received data to xfer->data. When |
<> | 144:ef7eb2e8f9f7 | 678 | all data received, trigger callback. |
<> | 144:ef7eb2e8f9f7 | 679 | 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. |
<> | 144:ef7eb2e8f9f7 | 680 | If there are enough data in ring buffer, copy them to xfer->data and return. |
<> | 144:ef7eb2e8f9f7 | 681 | If there are not enough data in ring buffer, copy all of them to xfer->data, |
<> | 144:ef7eb2e8f9f7 | 682 | save the xfer->data remained empty space to uart handle, receive data |
<> | 144:ef7eb2e8f9f7 | 683 | to this empty space and trigger callback when finished. */ |
<> | 144:ef7eb2e8f9f7 | 684 | |
<> | 144:ef7eb2e8f9f7 | 685 | if (kUART_RxBusy == handle->rxState) |
<> | 144:ef7eb2e8f9f7 | 686 | { |
<> | 144:ef7eb2e8f9f7 | 687 | status = kStatus_UART_RxBusy; |
<> | 144:ef7eb2e8f9f7 | 688 | } |
<> | 144:ef7eb2e8f9f7 | 689 | else |
<> | 144:ef7eb2e8f9f7 | 690 | { |
<> | 144:ef7eb2e8f9f7 | 691 | bytesToReceive = xfer->dataSize; |
<> | 144:ef7eb2e8f9f7 | 692 | bytesCurrentReceived = 0U; |
<> | 144:ef7eb2e8f9f7 | 693 | |
<> | 144:ef7eb2e8f9f7 | 694 | /* If RX ring buffer is used. */ |
<> | 144:ef7eb2e8f9f7 | 695 | if (handle->rxRingBuffer) |
<> | 144:ef7eb2e8f9f7 | 696 | { |
<> | 144:ef7eb2e8f9f7 | 697 | /* Disable IRQ, protect ring buffer. */ |
<> | 144:ef7eb2e8f9f7 | 698 | regPrimask = DisableGlobalIRQ(); |
<> | 144:ef7eb2e8f9f7 | 699 | |
<> | 144:ef7eb2e8f9f7 | 700 | /* How many bytes in RX ring buffer currently. */ |
<> | 144:ef7eb2e8f9f7 | 701 | bytesToCopy = UART_TransferGetRxRingBufferLength(handle); |
<> | 144:ef7eb2e8f9f7 | 702 | |
<> | 144:ef7eb2e8f9f7 | 703 | if (bytesToCopy) |
<> | 144:ef7eb2e8f9f7 | 704 | { |
<> | 144:ef7eb2e8f9f7 | 705 | bytesToCopy = MIN(bytesToReceive, bytesToCopy); |
<> | 144:ef7eb2e8f9f7 | 706 | |
<> | 144:ef7eb2e8f9f7 | 707 | bytesToReceive -= bytesToCopy; |
<> | 144:ef7eb2e8f9f7 | 708 | |
<> | 144:ef7eb2e8f9f7 | 709 | /* Copy data from ring buffer to user memory. */ |
<> | 144:ef7eb2e8f9f7 | 710 | for (i = 0U; i < bytesToCopy; i++) |
<> | 144:ef7eb2e8f9f7 | 711 | { |
<> | 144:ef7eb2e8f9f7 | 712 | xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail]; |
<> | 144:ef7eb2e8f9f7 | 713 | |
<> | 144:ef7eb2e8f9f7 | 714 | /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ |
<> | 144:ef7eb2e8f9f7 | 715 | if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) |
<> | 144:ef7eb2e8f9f7 | 716 | { |
<> | 144:ef7eb2e8f9f7 | 717 | handle->rxRingBufferTail = 0U; |
<> | 144:ef7eb2e8f9f7 | 718 | } |
<> | 144:ef7eb2e8f9f7 | 719 | else |
<> | 144:ef7eb2e8f9f7 | 720 | { |
<> | 144:ef7eb2e8f9f7 | 721 | handle->rxRingBufferTail++; |
<> | 144:ef7eb2e8f9f7 | 722 | } |
<> | 144:ef7eb2e8f9f7 | 723 | } |
<> | 144:ef7eb2e8f9f7 | 724 | } |
<> | 144:ef7eb2e8f9f7 | 725 | |
<> | 144:ef7eb2e8f9f7 | 726 | /* If ring buffer does not have enough data, still need to read more data. */ |
<> | 144:ef7eb2e8f9f7 | 727 | if (bytesToReceive) |
<> | 144:ef7eb2e8f9f7 | 728 | { |
<> | 144:ef7eb2e8f9f7 | 729 | /* No data in ring buffer, save the request to UART handle. */ |
<> | 144:ef7eb2e8f9f7 | 730 | handle->rxData = xfer->data + bytesCurrentReceived; |
<> | 144:ef7eb2e8f9f7 | 731 | handle->rxDataSize = bytesToReceive; |
<> | 144:ef7eb2e8f9f7 | 732 | handle->rxDataSizeAll = bytesToReceive; |
<> | 144:ef7eb2e8f9f7 | 733 | handle->rxState = kUART_RxBusy; |
<> | 144:ef7eb2e8f9f7 | 734 | } |
<> | 144:ef7eb2e8f9f7 | 735 | |
<> | 144:ef7eb2e8f9f7 | 736 | /* Enable IRQ if previously enabled. */ |
<> | 144:ef7eb2e8f9f7 | 737 | EnableGlobalIRQ(regPrimask); |
<> | 144:ef7eb2e8f9f7 | 738 | |
<> | 144:ef7eb2e8f9f7 | 739 | /* Call user callback since all data are received. */ |
<> | 144:ef7eb2e8f9f7 | 740 | if (0 == bytesToReceive) |
<> | 144:ef7eb2e8f9f7 | 741 | { |
<> | 144:ef7eb2e8f9f7 | 742 | if (handle->callback) |
<> | 144:ef7eb2e8f9f7 | 743 | { |
<> | 144:ef7eb2e8f9f7 | 744 | handle->callback(base, handle, kStatus_UART_RxIdle, handle->userData); |
<> | 144:ef7eb2e8f9f7 | 745 | } |
<> | 144:ef7eb2e8f9f7 | 746 | } |
<> | 144:ef7eb2e8f9f7 | 747 | } |
<> | 144:ef7eb2e8f9f7 | 748 | /* Ring buffer not used. */ |
<> | 144:ef7eb2e8f9f7 | 749 | else |
<> | 144:ef7eb2e8f9f7 | 750 | { |
<> | 144:ef7eb2e8f9f7 | 751 | handle->rxData = xfer->data + bytesCurrentReceived; |
<> | 144:ef7eb2e8f9f7 | 752 | handle->rxDataSize = bytesToReceive; |
<> | 144:ef7eb2e8f9f7 | 753 | handle->rxDataSizeAll = bytesToReceive; |
<> | 144:ef7eb2e8f9f7 | 754 | handle->rxState = kUART_RxBusy; |
<> | 144:ef7eb2e8f9f7 | 755 | |
<> | 144:ef7eb2e8f9f7 | 756 | /* Enable RX interrupt. */ |
<> | 144:ef7eb2e8f9f7 | 757 | UART_EnableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable); |
<> | 144:ef7eb2e8f9f7 | 758 | } |
<> | 144:ef7eb2e8f9f7 | 759 | |
<> | 144:ef7eb2e8f9f7 | 760 | /* Return the how many bytes have read. */ |
<> | 144:ef7eb2e8f9f7 | 761 | if (receivedBytes) |
<> | 144:ef7eb2e8f9f7 | 762 | { |
<> | 144:ef7eb2e8f9f7 | 763 | *receivedBytes = bytesCurrentReceived; |
<> | 144:ef7eb2e8f9f7 | 764 | } |
<> | 144:ef7eb2e8f9f7 | 765 | |
<> | 144:ef7eb2e8f9f7 | 766 | status = kStatus_Success; |
<> | 144:ef7eb2e8f9f7 | 767 | } |
<> | 144:ef7eb2e8f9f7 | 768 | |
<> | 144:ef7eb2e8f9f7 | 769 | return status; |
<> | 144:ef7eb2e8f9f7 | 770 | } |
<> | 144:ef7eb2e8f9f7 | 771 | |
<> | 144:ef7eb2e8f9f7 | 772 | void UART_TransferAbortReceive(UART_Type *base, uart_handle_t *handle) |
<> | 144:ef7eb2e8f9f7 | 773 | { |
<> | 144:ef7eb2e8f9f7 | 774 | /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ |
<> | 144:ef7eb2e8f9f7 | 775 | if (!handle->rxRingBuffer) |
<> | 144:ef7eb2e8f9f7 | 776 | { |
<> | 144:ef7eb2e8f9f7 | 777 | /* Disable RX interrupt. */ |
<> | 144:ef7eb2e8f9f7 | 778 | UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable); |
<> | 144:ef7eb2e8f9f7 | 779 | } |
<> | 144:ef7eb2e8f9f7 | 780 | |
<> | 144:ef7eb2e8f9f7 | 781 | handle->rxDataSize = 0U; |
<> | 144:ef7eb2e8f9f7 | 782 | handle->rxState = kUART_RxIdle; |
<> | 144:ef7eb2e8f9f7 | 783 | } |
<> | 144:ef7eb2e8f9f7 | 784 | |
<> | 144:ef7eb2e8f9f7 | 785 | status_t UART_TransferGetReceiveCount(UART_Type *base, uart_handle_t *handle, uint32_t *count) |
<> | 144:ef7eb2e8f9f7 | 786 | { |
<> | 144:ef7eb2e8f9f7 | 787 | if (kUART_RxIdle == handle->rxState) |
<> | 144:ef7eb2e8f9f7 | 788 | { |
<> | 144:ef7eb2e8f9f7 | 789 | return kStatus_NoTransferInProgress; |
<> | 144:ef7eb2e8f9f7 | 790 | } |
<> | 144:ef7eb2e8f9f7 | 791 | |
<> | 144:ef7eb2e8f9f7 | 792 | if (!count) |
<> | 144:ef7eb2e8f9f7 | 793 | { |
<> | 144:ef7eb2e8f9f7 | 794 | return kStatus_InvalidArgument; |
<> | 144:ef7eb2e8f9f7 | 795 | } |
<> | 144:ef7eb2e8f9f7 | 796 | |
<> | 144:ef7eb2e8f9f7 | 797 | *count = handle->rxDataSizeAll - handle->rxDataSize; |
<> | 144:ef7eb2e8f9f7 | 798 | |
<> | 144:ef7eb2e8f9f7 | 799 | return kStatus_Success; |
<> | 144:ef7eb2e8f9f7 | 800 | } |
<> | 144:ef7eb2e8f9f7 | 801 | |
<> | 144:ef7eb2e8f9f7 | 802 | void UART_TransferHandleIRQ(UART_Type *base, uart_handle_t *handle) |
<> | 144:ef7eb2e8f9f7 | 803 | { |
<> | 144:ef7eb2e8f9f7 | 804 | uint8_t count; |
<> | 144:ef7eb2e8f9f7 | 805 | uint8_t tempCount; |
<> | 144:ef7eb2e8f9f7 | 806 | |
<> | 144:ef7eb2e8f9f7 | 807 | assert(handle); |
<> | 144:ef7eb2e8f9f7 | 808 | |
<> | 144:ef7eb2e8f9f7 | 809 | /* If RX overrun. */ |
<> | 144:ef7eb2e8f9f7 | 810 | if (UART_S1_OR_MASK & base->S1) |
<> | 144:ef7eb2e8f9f7 | 811 | { |
<> | 144:ef7eb2e8f9f7 | 812 | /* Read base->D, otherwise the RX does not work. */ |
<> | 144:ef7eb2e8f9f7 | 813 | (void)base->D; |
<> | 144:ef7eb2e8f9f7 | 814 | |
<> | 144:ef7eb2e8f9f7 | 815 | /* Trigger callback. */ |
<> | 144:ef7eb2e8f9f7 | 816 | if (handle->callback) |
<> | 144:ef7eb2e8f9f7 | 817 | { |
<> | 144:ef7eb2e8f9f7 | 818 | handle->callback(base, handle, kStatus_UART_RxHardwareOverrun, handle->userData); |
<> | 144:ef7eb2e8f9f7 | 819 | } |
<> | 144:ef7eb2e8f9f7 | 820 | } |
<> | 144:ef7eb2e8f9f7 | 821 | |
<> | 144:ef7eb2e8f9f7 | 822 | /* Receive data register full */ |
<> | 144:ef7eb2e8f9f7 | 823 | if ((UART_S1_RDRF_MASK & base->S1) && (UART_C2_RIE_MASK & base->C2)) |
<> | 144:ef7eb2e8f9f7 | 824 | { |
<> | 144:ef7eb2e8f9f7 | 825 | /* Get the size that can be stored into buffer for this interrupt. */ |
<> | 144:ef7eb2e8f9f7 | 826 | #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO |
<> | 144:ef7eb2e8f9f7 | 827 | count = base->RCFIFO; |
<> | 144:ef7eb2e8f9f7 | 828 | #else |
<> | 144:ef7eb2e8f9f7 | 829 | count = 1; |
<> | 144:ef7eb2e8f9f7 | 830 | #endif |
<> | 144:ef7eb2e8f9f7 | 831 | |
<> | 144:ef7eb2e8f9f7 | 832 | /* If handle->rxDataSize is not 0, first save data to handle->rxData. */ |
<> | 144:ef7eb2e8f9f7 | 833 | while ((count) && (handle->rxDataSize)) |
<> | 144:ef7eb2e8f9f7 | 834 | { |
<> | 144:ef7eb2e8f9f7 | 835 | #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO |
<> | 144:ef7eb2e8f9f7 | 836 | tempCount = MIN(handle->rxDataSize, count); |
<> | 144:ef7eb2e8f9f7 | 837 | #else |
<> | 144:ef7eb2e8f9f7 | 838 | tempCount = 1; |
<> | 144:ef7eb2e8f9f7 | 839 | #endif |
<> | 144:ef7eb2e8f9f7 | 840 | |
<> | 144:ef7eb2e8f9f7 | 841 | /* Using non block API to read the data from the registers. */ |
<> | 144:ef7eb2e8f9f7 | 842 | UART_ReadNonBlocking(base, handle->rxData, tempCount); |
<> | 144:ef7eb2e8f9f7 | 843 | handle->rxData += tempCount; |
<> | 144:ef7eb2e8f9f7 | 844 | handle->rxDataSize -= tempCount; |
<> | 144:ef7eb2e8f9f7 | 845 | count -= tempCount; |
<> | 144:ef7eb2e8f9f7 | 846 | |
<> | 144:ef7eb2e8f9f7 | 847 | /* If all the data required for upper layer is ready, trigger callback. */ |
<> | 144:ef7eb2e8f9f7 | 848 | if (!handle->rxDataSize) |
<> | 144:ef7eb2e8f9f7 | 849 | { |
<> | 144:ef7eb2e8f9f7 | 850 | handle->rxState = kUART_RxIdle; |
<> | 144:ef7eb2e8f9f7 | 851 | |
<> | 144:ef7eb2e8f9f7 | 852 | if (handle->callback) |
<> | 144:ef7eb2e8f9f7 | 853 | { |
<> | 144:ef7eb2e8f9f7 | 854 | handle->callback(base, handle, kStatus_UART_RxIdle, handle->userData); |
<> | 144:ef7eb2e8f9f7 | 855 | } |
<> | 144:ef7eb2e8f9f7 | 856 | } |
<> | 144:ef7eb2e8f9f7 | 857 | } |
<> | 144:ef7eb2e8f9f7 | 858 | |
<> | 144:ef7eb2e8f9f7 | 859 | /* If use RX ring buffer, receive data to ring buffer. */ |
<> | 144:ef7eb2e8f9f7 | 860 | if (handle->rxRingBuffer) |
<> | 144:ef7eb2e8f9f7 | 861 | { |
<> | 144:ef7eb2e8f9f7 | 862 | while (count--) |
<> | 144:ef7eb2e8f9f7 | 863 | { |
<> | 144:ef7eb2e8f9f7 | 864 | /* If RX ring buffer is full, trigger callback to notify over run. */ |
<> | 144:ef7eb2e8f9f7 | 865 | if (UART_TransferIsRxRingBufferFull(handle)) |
<> | 144:ef7eb2e8f9f7 | 866 | { |
<> | 144:ef7eb2e8f9f7 | 867 | if (handle->callback) |
<> | 144:ef7eb2e8f9f7 | 868 | { |
<> | 144:ef7eb2e8f9f7 | 869 | handle->callback(base, handle, kStatus_UART_RxRingBufferOverrun, handle->userData); |
<> | 144:ef7eb2e8f9f7 | 870 | } |
<> | 144:ef7eb2e8f9f7 | 871 | } |
<> | 144:ef7eb2e8f9f7 | 872 | |
<> | 144:ef7eb2e8f9f7 | 873 | /* If ring buffer is still full after callback function, the oldest data is overrided. */ |
<> | 144:ef7eb2e8f9f7 | 874 | if (UART_TransferIsRxRingBufferFull(handle)) |
<> | 144:ef7eb2e8f9f7 | 875 | { |
<> | 144:ef7eb2e8f9f7 | 876 | /* Increase handle->rxRingBufferTail to make room for new data. */ |
<> | 144:ef7eb2e8f9f7 | 877 | if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) |
<> | 144:ef7eb2e8f9f7 | 878 | { |
<> | 144:ef7eb2e8f9f7 | 879 | handle->rxRingBufferTail = 0U; |
<> | 144:ef7eb2e8f9f7 | 880 | } |
<> | 144:ef7eb2e8f9f7 | 881 | else |
<> | 144:ef7eb2e8f9f7 | 882 | { |
<> | 144:ef7eb2e8f9f7 | 883 | handle->rxRingBufferTail++; |
<> | 144:ef7eb2e8f9f7 | 884 | } |
<> | 144:ef7eb2e8f9f7 | 885 | } |
<> | 144:ef7eb2e8f9f7 | 886 | |
<> | 144:ef7eb2e8f9f7 | 887 | /* Read data. */ |
<> | 144:ef7eb2e8f9f7 | 888 | handle->rxRingBuffer[handle->rxRingBufferHead] = base->D; |
<> | 144:ef7eb2e8f9f7 | 889 | |
<> | 144:ef7eb2e8f9f7 | 890 | /* Increase handle->rxRingBufferHead. */ |
<> | 144:ef7eb2e8f9f7 | 891 | if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize) |
<> | 144:ef7eb2e8f9f7 | 892 | { |
<> | 144:ef7eb2e8f9f7 | 893 | handle->rxRingBufferHead = 0U; |
<> | 144:ef7eb2e8f9f7 | 894 | } |
<> | 144:ef7eb2e8f9f7 | 895 | else |
<> | 144:ef7eb2e8f9f7 | 896 | { |
<> | 144:ef7eb2e8f9f7 | 897 | handle->rxRingBufferHead++; |
<> | 144:ef7eb2e8f9f7 | 898 | } |
<> | 144:ef7eb2e8f9f7 | 899 | } |
<> | 144:ef7eb2e8f9f7 | 900 | } |
<> | 144:ef7eb2e8f9f7 | 901 | /* If no receive requst pending, stop RX interrupt. */ |
<> | 144:ef7eb2e8f9f7 | 902 | else if (!handle->rxDataSize) |
<> | 144:ef7eb2e8f9f7 | 903 | { |
<> | 144:ef7eb2e8f9f7 | 904 | UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable); |
<> | 144:ef7eb2e8f9f7 | 905 | } |
<> | 144:ef7eb2e8f9f7 | 906 | else |
<> | 144:ef7eb2e8f9f7 | 907 | { |
<> | 144:ef7eb2e8f9f7 | 908 | } |
<> | 144:ef7eb2e8f9f7 | 909 | } |
<> | 144:ef7eb2e8f9f7 | 910 | |
<> | 144:ef7eb2e8f9f7 | 911 | /* Send data register empty and the interrupt is enabled. */ |
<> | 144:ef7eb2e8f9f7 | 912 | if ((base->S1 & UART_S1_TDRE_MASK) && (base->C2 & UART_C2_TIE_MASK)) |
<> | 144:ef7eb2e8f9f7 | 913 | { |
<> | 144:ef7eb2e8f9f7 | 914 | /* Get the bytes that available at this moment. */ |
<> | 144:ef7eb2e8f9f7 | 915 | #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO |
<> | 144:ef7eb2e8f9f7 | 916 | count = FSL_FEATURE_UART_FIFO_SIZEn(base) - base->TCFIFO; |
<> | 144:ef7eb2e8f9f7 | 917 | #else |
<> | 144:ef7eb2e8f9f7 | 918 | count = 1; |
<> | 144:ef7eb2e8f9f7 | 919 | #endif |
<> | 144:ef7eb2e8f9f7 | 920 | |
<> | 144:ef7eb2e8f9f7 | 921 | while ((count) && (handle->txDataSize)) |
<> | 144:ef7eb2e8f9f7 | 922 | { |
<> | 144:ef7eb2e8f9f7 | 923 | #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO |
<> | 144:ef7eb2e8f9f7 | 924 | tempCount = MIN(handle->txDataSize, count); |
<> | 144:ef7eb2e8f9f7 | 925 | #else |
<> | 144:ef7eb2e8f9f7 | 926 | tempCount = 1; |
<> | 144:ef7eb2e8f9f7 | 927 | #endif |
<> | 144:ef7eb2e8f9f7 | 928 | |
<> | 144:ef7eb2e8f9f7 | 929 | /* Using non block API to write the data to the registers. */ |
<> | 144:ef7eb2e8f9f7 | 930 | UART_WriteNonBlocking(base, handle->txData, tempCount); |
<> | 144:ef7eb2e8f9f7 | 931 | handle->txData += tempCount; |
<> | 144:ef7eb2e8f9f7 | 932 | handle->txDataSize -= tempCount; |
<> | 144:ef7eb2e8f9f7 | 933 | count -= tempCount; |
<> | 144:ef7eb2e8f9f7 | 934 | |
<> | 144:ef7eb2e8f9f7 | 935 | /* If all the data are written to data register, TX finished. */ |
<> | 144:ef7eb2e8f9f7 | 936 | if (!handle->txDataSize) |
<> | 144:ef7eb2e8f9f7 | 937 | { |
<> | 144:ef7eb2e8f9f7 | 938 | handle->txState = kUART_TxIdle; |
<> | 144:ef7eb2e8f9f7 | 939 | |
<> | 144:ef7eb2e8f9f7 | 940 | /* Disable TX register empty interrupt. */ |
<> | 144:ef7eb2e8f9f7 | 941 | base->C2 = (base->C2 & ~UART_C2_TIE_MASK); |
<> | 144:ef7eb2e8f9f7 | 942 | |
<> | 144:ef7eb2e8f9f7 | 943 | /* Trigger callback. */ |
<> | 144:ef7eb2e8f9f7 | 944 | if (handle->callback) |
<> | 144:ef7eb2e8f9f7 | 945 | { |
<> | 144:ef7eb2e8f9f7 | 946 | handle->callback(base, handle, kStatus_UART_TxIdle, handle->userData); |
<> | 144:ef7eb2e8f9f7 | 947 | } |
<> | 144:ef7eb2e8f9f7 | 948 | } |
<> | 144:ef7eb2e8f9f7 | 949 | } |
<> | 144:ef7eb2e8f9f7 | 950 | } |
<> | 144:ef7eb2e8f9f7 | 951 | } |
<> | 144:ef7eb2e8f9f7 | 952 | |
<> | 144:ef7eb2e8f9f7 | 953 | void UART_TransferHandleErrorIRQ(UART_Type *base, uart_handle_t *handle) |
<> | 144:ef7eb2e8f9f7 | 954 | { |
<> | 144:ef7eb2e8f9f7 | 955 | /* TODO: To be implemented. */ |
<> | 144:ef7eb2e8f9f7 | 956 | } |
<> | 144:ef7eb2e8f9f7 | 957 | |
<> | 144:ef7eb2e8f9f7 | 958 | #if defined(UART0) |
<> | 144:ef7eb2e8f9f7 | 959 | #if ((!(defined(FSL_FEATURE_SOC_LPSCI_COUNT))) || \ |
<> | 144:ef7eb2e8f9f7 | 960 | ((defined(FSL_FEATURE_SOC_LPSCI_COUNT)) && (FSL_FEATURE_SOC_LPSCI_COUNT == 0))) |
<> | 144:ef7eb2e8f9f7 | 961 | void UART0_DriverIRQHandler(void) |
<> | 144:ef7eb2e8f9f7 | 962 | { |
<> | 144:ef7eb2e8f9f7 | 963 | s_uartIsr(UART0, s_uartHandle[0]); |
<> | 144:ef7eb2e8f9f7 | 964 | } |
<> | 144:ef7eb2e8f9f7 | 965 | |
<> | 144:ef7eb2e8f9f7 | 966 | void UART0_RX_TX_DriverIRQHandler(void) |
<> | 144:ef7eb2e8f9f7 | 967 | { |
<> | 144:ef7eb2e8f9f7 | 968 | UART0_DriverIRQHandler(); |
<> | 144:ef7eb2e8f9f7 | 969 | } |
<> | 144:ef7eb2e8f9f7 | 970 | #endif |
<> | 144:ef7eb2e8f9f7 | 971 | #endif |
<> | 144:ef7eb2e8f9f7 | 972 | |
<> | 144:ef7eb2e8f9f7 | 973 | #if defined(UART1) |
<> | 144:ef7eb2e8f9f7 | 974 | void UART1_DriverIRQHandler(void) |
<> | 144:ef7eb2e8f9f7 | 975 | { |
<> | 144:ef7eb2e8f9f7 | 976 | s_uartIsr(UART1, s_uartHandle[1]); |
<> | 144:ef7eb2e8f9f7 | 977 | } |
<> | 144:ef7eb2e8f9f7 | 978 | |
<> | 144:ef7eb2e8f9f7 | 979 | void UART1_RX_TX_DriverIRQHandler(void) |
<> | 144:ef7eb2e8f9f7 | 980 | { |
<> | 144:ef7eb2e8f9f7 | 981 | UART1_DriverIRQHandler(); |
<> | 144:ef7eb2e8f9f7 | 982 | } |
<> | 144:ef7eb2e8f9f7 | 983 | #endif |
<> | 144:ef7eb2e8f9f7 | 984 | |
<> | 144:ef7eb2e8f9f7 | 985 | #if defined(UART2) |
<> | 144:ef7eb2e8f9f7 | 986 | void UART2_DriverIRQHandler(void) |
<> | 144:ef7eb2e8f9f7 | 987 | { |
<> | 144:ef7eb2e8f9f7 | 988 | s_uartIsr(UART2, s_uartHandle[2]); |
<> | 144:ef7eb2e8f9f7 | 989 | } |
<> | 144:ef7eb2e8f9f7 | 990 | |
<> | 144:ef7eb2e8f9f7 | 991 | void UART2_RX_TX_DriverIRQHandler(void) |
<> | 144:ef7eb2e8f9f7 | 992 | { |
<> | 144:ef7eb2e8f9f7 | 993 | UART2_DriverIRQHandler(); |
<> | 144:ef7eb2e8f9f7 | 994 | } |
<> | 144:ef7eb2e8f9f7 | 995 | |
<> | 144:ef7eb2e8f9f7 | 996 | #endif |
<> | 144:ef7eb2e8f9f7 | 997 | |
<> | 144:ef7eb2e8f9f7 | 998 | #if defined(UART3) |
<> | 144:ef7eb2e8f9f7 | 999 | void UART3_DriverIRQHandler(void) |
<> | 144:ef7eb2e8f9f7 | 1000 | { |
<> | 144:ef7eb2e8f9f7 | 1001 | s_uartIsr(UART3, s_uartHandle[3]); |
<> | 144:ef7eb2e8f9f7 | 1002 | } |
<> | 144:ef7eb2e8f9f7 | 1003 | |
<> | 144:ef7eb2e8f9f7 | 1004 | void UART3_RX_TX_DriverIRQHandler(void) |
<> | 144:ef7eb2e8f9f7 | 1005 | { |
<> | 144:ef7eb2e8f9f7 | 1006 | UART3_DriverIRQHandler(); |
<> | 144:ef7eb2e8f9f7 | 1007 | } |
<> | 144:ef7eb2e8f9f7 | 1008 | #endif |
<> | 144:ef7eb2e8f9f7 | 1009 | |
<> | 144:ef7eb2e8f9f7 | 1010 | #if defined(UART4) |
<> | 144:ef7eb2e8f9f7 | 1011 | void UART4_DriverIRQHandler(void) |
<> | 144:ef7eb2e8f9f7 | 1012 | { |
<> | 144:ef7eb2e8f9f7 | 1013 | s_uartIsr(UART4, s_uartHandle[4]); |
<> | 144:ef7eb2e8f9f7 | 1014 | } |
<> | 144:ef7eb2e8f9f7 | 1015 | |
<> | 144:ef7eb2e8f9f7 | 1016 | void UART4_RX_TX_DriverIRQHandler(void) |
<> | 144:ef7eb2e8f9f7 | 1017 | { |
<> | 144:ef7eb2e8f9f7 | 1018 | UART4_DriverIRQHandler(); |
<> | 144:ef7eb2e8f9f7 | 1019 | } |
<> | 144:ef7eb2e8f9f7 | 1020 | #endif |
<> | 144:ef7eb2e8f9f7 | 1021 | |
<> | 144:ef7eb2e8f9f7 | 1022 | #if defined(UART5) |
<> | 144:ef7eb2e8f9f7 | 1023 | void UART5_DriverIRQHandler(void) |
<> | 144:ef7eb2e8f9f7 | 1024 | { |
<> | 144:ef7eb2e8f9f7 | 1025 | s_uartIsr(UART5, s_uartHandle[5]); |
<> | 144:ef7eb2e8f9f7 | 1026 | } |
<> | 144:ef7eb2e8f9f7 | 1027 | |
<> | 144:ef7eb2e8f9f7 | 1028 | void UART5_RX_TX_DriverIRQHandler(void) |
<> | 144:ef7eb2e8f9f7 | 1029 | { |
<> | 144:ef7eb2e8f9f7 | 1030 | UART5_DriverIRQHandler(); |
<> | 144:ef7eb2e8f9f7 | 1031 | } |
<> | 144:ef7eb2e8f9f7 | 1032 | #endif |