Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_mpu.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 144:ef7eb2e8f9f7 3 * All rights reserved.
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 6 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 9 * of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 12 * list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 13 * other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 144:ef7eb2e8f9f7 16 * contributors may be used to endorse or promote products derived from this
<> 144:ef7eb2e8f9f7 17 * software without specific prior written permission.
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 29 */
<> 144:ef7eb2e8f9f7 30 #ifndef _FSL_MPU_H_
<> 144:ef7eb2e8f9f7 31 #define _FSL_MPU_H_
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 #include "fsl_common.h"
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 /*!
<> 144:ef7eb2e8f9f7 36 * @addtogroup mpu
<> 144:ef7eb2e8f9f7 37 * @{
<> 144:ef7eb2e8f9f7 38 */
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 /*! @file */
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 /*******************************************************************************
<> 144:ef7eb2e8f9f7 43 * Definitions
<> 144:ef7eb2e8f9f7 44 ******************************************************************************/
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /*! @name Driver version */
<> 144:ef7eb2e8f9f7 47 /*@{*/
<> 144:ef7eb2e8f9f7 48 /*! @brief MPU driver version 2.0.0. */
<> 144:ef7eb2e8f9f7 49 #define FSL_MPU_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
<> 144:ef7eb2e8f9f7 50 /*@}*/
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 /*! @brief MPU low master bit shift. */
<> 144:ef7eb2e8f9f7 53 #define MPU_WORD_LOW_MASTER_SHIFT(n) (n * 6)
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /*! @brief MPU low master bit mask. */
<> 144:ef7eb2e8f9f7 56 #define MPU_WORD_LOW_MASTER_MASK(n) (0x1Fu << MPU_WORD_LOW_MASTER_SHIFT(n))
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 /*! @brief MPU low master bit width. */
<> 144:ef7eb2e8f9f7 59 #define MPU_WORD_LOW_MASTER_WIDTH 5
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 /*! @brief MPU low master priority setting. */
<> 144:ef7eb2e8f9f7 62 #define MPU_WORD_LOW_MASTER(n, x) \
<> 144:ef7eb2e8f9f7 63 (((uint32_t)(((uint32_t)(x)) << MPU_WORD_LOW_MASTER_SHIFT(n))) & MPU_WORD_LOW_MASTER_MASK(n))
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 /*! @brief MPU low master process enable bit shift. */
<> 144:ef7eb2e8f9f7 66 #define MPU_LOW_MASTER_PE_SHIFT(n) (n * 6 + 5)
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 /*! @brief MPU low master process enable bit mask. */
<> 144:ef7eb2e8f9f7 69 #define MPU_LOW_MASTER_PE_MASK(n) (0x1u << MPU_LOW_MASTER_PE_SHIFT(n))
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 /*! @brief MPU low master process enable width. */
<> 144:ef7eb2e8f9f7 72 #define MPU_WORD_MASTER_PE_WIDTH 1
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 /*! @brief MPU low master process enable setting. */
<> 144:ef7eb2e8f9f7 75 #define MPU_WORD_MASTER_PE(n, x) \
<> 144:ef7eb2e8f9f7 76 (((uint32_t)(((uint32_t)(x)) << MPU_LOW_MASTER_PE_SHIFT(n))) & MPU_LOW_MASTER_PE_MASK(n))
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 /*! @brief MPU high master bit shift. */
<> 144:ef7eb2e8f9f7 79 #define MPU_WORD_HIGH_MASTER_SHIFT(n) (n * 2 + 24)
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 /*! @brief MPU high master bit mask. */
<> 144:ef7eb2e8f9f7 82 #define MPU_WORD_HIGH_MASTER_MASK(n) (0x03u << MPU_WORD_HIGH_MASTER_SHIFT(n))
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 /*! @brief MPU high master bit width. */
<> 144:ef7eb2e8f9f7 85 #define MPU_WORD_HIGH_MASTER_WIDTH 2
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 /*! @brief MPU high master priority setting. */
<> 144:ef7eb2e8f9f7 88 #define MPU_WORD_HIGH_MASTER(n, x) \
<> 144:ef7eb2e8f9f7 89 (((uint32_t)(((uint32_t)(x)) << MPU_WORD_HIGH_MASTER_SHIFT(n))) & MPU_WORD_HIGH_MASTER_MASK(n))
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 /*! @brief MPU region number. */
<> 144:ef7eb2e8f9f7 92 typedef enum _mpu_region_num
<> 144:ef7eb2e8f9f7 93 {
<> 144:ef7eb2e8f9f7 94 #if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 0U
<> 144:ef7eb2e8f9f7 95 kMPU_RegionNum00 = 0U, /*!< MPU region number 0. */
<> 144:ef7eb2e8f9f7 96 #endif
<> 144:ef7eb2e8f9f7 97 #if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 1U
<> 144:ef7eb2e8f9f7 98 kMPU_RegionNum01 = 1U, /*!< MPU region number 1. */
<> 144:ef7eb2e8f9f7 99 #endif
<> 144:ef7eb2e8f9f7 100 #if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 2U
<> 144:ef7eb2e8f9f7 101 kMPU_RegionNum02 = 2U, /*!< MPU region number 2. */
<> 144:ef7eb2e8f9f7 102 #endif
<> 144:ef7eb2e8f9f7 103 #if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 3U
<> 144:ef7eb2e8f9f7 104 kMPU_RegionNum03 = 3U, /*!< MPU region number 3. */
<> 144:ef7eb2e8f9f7 105 #endif
<> 144:ef7eb2e8f9f7 106 #if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 4U
<> 144:ef7eb2e8f9f7 107 kMPU_RegionNum04 = 4U, /*!< MPU region number 4. */
<> 144:ef7eb2e8f9f7 108 #endif
<> 144:ef7eb2e8f9f7 109 #if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 5U
<> 144:ef7eb2e8f9f7 110 kMPU_RegionNum05 = 5U, /*!< MPU region number 5. */
<> 144:ef7eb2e8f9f7 111 #endif
<> 144:ef7eb2e8f9f7 112 #if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 6U
<> 144:ef7eb2e8f9f7 113 kMPU_RegionNum06 = 6U, /*!< MPU region number 6. */
<> 144:ef7eb2e8f9f7 114 #endif
<> 144:ef7eb2e8f9f7 115 #if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 7U
<> 144:ef7eb2e8f9f7 116 kMPU_RegionNum07 = 7U, /*!< MPU region number 7. */
<> 144:ef7eb2e8f9f7 117 #endif
<> 144:ef7eb2e8f9f7 118 #if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 8U
<> 144:ef7eb2e8f9f7 119 kMPU_RegionNum08 = 8U, /*!< MPU region number 8. */
<> 144:ef7eb2e8f9f7 120 #endif
<> 144:ef7eb2e8f9f7 121 #if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 9U
<> 144:ef7eb2e8f9f7 122 kMPU_RegionNum09 = 9U, /*!< MPU region number 9. */
<> 144:ef7eb2e8f9f7 123 #endif
<> 144:ef7eb2e8f9f7 124 #if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 10U
<> 144:ef7eb2e8f9f7 125 kMPU_RegionNum10 = 10U, /*!< MPU region number 10. */
<> 144:ef7eb2e8f9f7 126 #endif
<> 144:ef7eb2e8f9f7 127 #if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 11U
<> 144:ef7eb2e8f9f7 128 kMPU_RegionNum11 = 11U, /*!< MPU region number 11. */
<> 144:ef7eb2e8f9f7 129 #endif
<> 144:ef7eb2e8f9f7 130 #if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 12U
<> 144:ef7eb2e8f9f7 131 kMPU_RegionNum12 = 12U, /*!< MPU region number 12. */
<> 144:ef7eb2e8f9f7 132 #endif
<> 144:ef7eb2e8f9f7 133 #if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 13U
<> 144:ef7eb2e8f9f7 134 kMPU_RegionNum13 = 13U, /*!< MPU region number 13. */
<> 144:ef7eb2e8f9f7 135 #endif
<> 144:ef7eb2e8f9f7 136 #if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 14U
<> 144:ef7eb2e8f9f7 137 kMPU_RegionNum14 = 14U, /*!< MPU region number 14. */
<> 144:ef7eb2e8f9f7 138 #endif
<> 144:ef7eb2e8f9f7 139 #if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 15U
<> 144:ef7eb2e8f9f7 140 kMPU_RegionNum15 = 15U, /*!< MPU region number 15. */
<> 144:ef7eb2e8f9f7 141 #endif
<> 144:ef7eb2e8f9f7 142 } mpu_region_num_t;
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 /*! @brief MPU master number. */
<> 144:ef7eb2e8f9f7 145 typedef enum _mpu_master
<> 144:ef7eb2e8f9f7 146 {
<> 144:ef7eb2e8f9f7 147 #if FSL_FEATURE_MPU_HAS_MASTER0
<> 144:ef7eb2e8f9f7 148 kMPU_Master0 = 0U, /*!< MPU master core. */
<> 144:ef7eb2e8f9f7 149 #endif
<> 144:ef7eb2e8f9f7 150 #if FSL_FEATURE_MPU_HAS_MASTER1
<> 144:ef7eb2e8f9f7 151 kMPU_Master1 = 1U, /*!< MPU master defined in SoC. */
<> 144:ef7eb2e8f9f7 152 #endif
<> 144:ef7eb2e8f9f7 153 #if FSL_FEATURE_MPU_HAS_MASTER2
<> 144:ef7eb2e8f9f7 154 kMPU_Master2 = 2U, /*!< MPU master defined in SoC. */
<> 144:ef7eb2e8f9f7 155 #endif
<> 144:ef7eb2e8f9f7 156 #if FSL_FEATURE_MPU_HAS_MASTER3
<> 144:ef7eb2e8f9f7 157 kMPU_Master3 = 3U, /*!< MPU master defined in SoC. */
<> 144:ef7eb2e8f9f7 158 #endif
<> 144:ef7eb2e8f9f7 159 #if FSL_FEATURE_MPU_HAS_MASTER4
<> 144:ef7eb2e8f9f7 160 kMPU_Master4 = 4U, /*!< MPU master defined in SoC. */
<> 144:ef7eb2e8f9f7 161 #endif
<> 144:ef7eb2e8f9f7 162 #if FSL_FEATURE_MPU_HAS_MASTER5
<> 144:ef7eb2e8f9f7 163 kMPU_Master5 = 5U, /*!< MPU master defined in SoC. */
<> 144:ef7eb2e8f9f7 164 #endif
<> 144:ef7eb2e8f9f7 165 #if FSL_FEATURE_MPU_HAS_MASTER6
<> 144:ef7eb2e8f9f7 166 kMPU_Master6 = 6U, /*!< MPU master defined in SoC. */
<> 144:ef7eb2e8f9f7 167 #endif
<> 144:ef7eb2e8f9f7 168 #if FSL_FEATURE_MPU_HAS_MASTER7
<> 144:ef7eb2e8f9f7 169 kMPU_Master7 = 7U /*!< MPU master defined in SoC. */
<> 144:ef7eb2e8f9f7 170 #endif
<> 144:ef7eb2e8f9f7 171 } mpu_master_t;
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 /*! @brief Describes the number of MPU regions. */
<> 144:ef7eb2e8f9f7 174 typedef enum _mpu_region_total_num
<> 144:ef7eb2e8f9f7 175 {
<> 144:ef7eb2e8f9f7 176 kMPU_8Regions = 0x0U, /*!< MPU supports 8 regions. */
<> 144:ef7eb2e8f9f7 177 kMPU_12Regions = 0x1U, /*!< MPU supports 12 regions. */
<> 144:ef7eb2e8f9f7 178 kMPU_16Regions = 0x2U /*!< MPU supports 16 regions. */
<> 144:ef7eb2e8f9f7 179 } mpu_region_total_num_t;
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 /*! @brief MPU slave port number. */
<> 144:ef7eb2e8f9f7 182 typedef enum _mpu_slave
<> 144:ef7eb2e8f9f7 183 {
<> 144:ef7eb2e8f9f7 184 kMPU_Slave0 = 4U, /*!< MPU slave port 0. */
<> 144:ef7eb2e8f9f7 185 kMPU_Slave1 = 3U, /*!< MPU slave port 1. */
<> 144:ef7eb2e8f9f7 186 kMPU_Slave2 = 2U, /*!< MPU slave port 2. */
<> 144:ef7eb2e8f9f7 187 kMPU_Slave3 = 1U, /*!< MPU slave port 3. */
<> 144:ef7eb2e8f9f7 188 kMPU_Slave4 = 0U /*!< MPU slave port 4. */
<> 144:ef7eb2e8f9f7 189 } mpu_slave_t;
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 /*! @brief MPU error access control detail. */
<> 144:ef7eb2e8f9f7 192 typedef enum _mpu_err_access_control
<> 144:ef7eb2e8f9f7 193 {
<> 144:ef7eb2e8f9f7 194 kMPU_NoRegionHit = 0U, /*!< No region hit error. */
<> 144:ef7eb2e8f9f7 195 kMPU_NoneOverlappRegion = 1U, /*!< Access single region error. */
<> 144:ef7eb2e8f9f7 196 kMPU_OverlappRegion = 2U /*!< Access overlapping region error. */
<> 144:ef7eb2e8f9f7 197 } mpu_err_access_control_t;
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 /*! @brief MPU error access type. */
<> 144:ef7eb2e8f9f7 200 typedef enum _mpu_err_access_type
<> 144:ef7eb2e8f9f7 201 {
<> 144:ef7eb2e8f9f7 202 kMPU_ErrTypeRead = 0U, /*!< MPU error access type --- read. */
<> 144:ef7eb2e8f9f7 203 kMPU_ErrTypeWrite = 1U /*!< MPU error access type --- write. */
<> 144:ef7eb2e8f9f7 204 } mpu_err_access_type_t;
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /*! @brief MPU access error attributes.*/
<> 144:ef7eb2e8f9f7 207 typedef enum _mpu_err_attributes
<> 144:ef7eb2e8f9f7 208 {
<> 144:ef7eb2e8f9f7 209 kMPU_InstructionAccessInUserMode = 0U, /*!< Access instruction error in user mode. */
<> 144:ef7eb2e8f9f7 210 kMPU_DataAccessInUserMode = 1U, /*!< Access data error in user mode. */
<> 144:ef7eb2e8f9f7 211 kMPU_InstructionAccessInSupervisorMode = 2U, /*!< Access instruction error in supervisor mode. */
<> 144:ef7eb2e8f9f7 212 kMPU_DataAccessInSupervisorMode = 3U /*!< Access data error in supervisor mode. */
<> 144:ef7eb2e8f9f7 213 } mpu_err_attributes_t;
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 /*! @brief MPU access rights in supervisor mode for master port 0 ~ port 3. */
<> 144:ef7eb2e8f9f7 216 typedef enum _mpu_supervisor_access_rights
<> 144:ef7eb2e8f9f7 217 {
<> 144:ef7eb2e8f9f7 218 kMPU_SupervisorReadWriteExecute = 0U, /*!< Read write and execute operations are allowed in supervisor mode. */
<> 144:ef7eb2e8f9f7 219 kMPU_SupervisorReadExecute = 1U, /*!< Read and execute operations are allowed in supervisor mode. */
<> 144:ef7eb2e8f9f7 220 kMPU_SupervisorReadWrite = 2U, /*!< Read write operations are allowed in supervisor mode. */
<> 144:ef7eb2e8f9f7 221 kMPU_SupervisorEqualToUsermode = 3U /*!< Access permission equal to user mode. */
<> 144:ef7eb2e8f9f7 222 } mpu_supervisor_access_rights_t;
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 /*! @brief MPU access rights in user mode for master port 0 ~ port 3. */
<> 144:ef7eb2e8f9f7 225 typedef enum _mpu_user_access_rights
<> 144:ef7eb2e8f9f7 226 {
<> 144:ef7eb2e8f9f7 227 kMPU_UserNoAccessRights = 0U, /*!< No access allowed in user mode. */
<> 144:ef7eb2e8f9f7 228 kMPU_UserExecute = 1U, /*!< Execute operation is allowed in user mode. */
<> 144:ef7eb2e8f9f7 229 kMPU_UserWrite = 2U, /*!< Write operation is allowed in user mode. */
<> 144:ef7eb2e8f9f7 230 kMPU_UserWriteExecute = 3U, /*!< Write and execute operations are allowed in user mode. */
<> 144:ef7eb2e8f9f7 231 kMPU_UserRead = 4U, /*!< Read is allowed in user mode. */
<> 144:ef7eb2e8f9f7 232 kMPU_UserReadExecute = 5U, /*!< Read and execute operations are allowed in user mode. */
<> 144:ef7eb2e8f9f7 233 kMPU_UserReadWrite = 6U, /*!< Read and write operations are allowed in user mode. */
<> 144:ef7eb2e8f9f7 234 kMPU_UserReadWriteExecute = 7U /*!< Read write and execute operations are allowed in user mode. */
<> 144:ef7eb2e8f9f7 235 } mpu_user_access_rights_t;
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 /*! @brief MPU hardware basic information. */
<> 144:ef7eb2e8f9f7 238 typedef struct _mpu_hardware_info
<> 144:ef7eb2e8f9f7 239 {
<> 144:ef7eb2e8f9f7 240 uint8_t hardwareRevisionLevel; /*!< Specifies the MPU's hardware and definition reversion level. */
<> 144:ef7eb2e8f9f7 241 uint8_t slavePortsNumbers; /*!< Specifies the number of slave ports connected to MPU. */
<> 144:ef7eb2e8f9f7 242 mpu_region_total_num_t regionsNumbers; /*!< Indicates the number of region descriptors implemented. */
<> 144:ef7eb2e8f9f7 243 } mpu_hardware_info_t;
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 /*! @brief MPU detail error access information. */
<> 144:ef7eb2e8f9f7 246 typedef struct _mpu_access_err_info
<> 144:ef7eb2e8f9f7 247 {
<> 144:ef7eb2e8f9f7 248 mpu_master_t master; /*!< Access error master. */
<> 144:ef7eb2e8f9f7 249 mpu_err_attributes_t attributes; /*!< Access error attributes. */
<> 144:ef7eb2e8f9f7 250 mpu_err_access_type_t accessType; /*!< Access error type. */
<> 144:ef7eb2e8f9f7 251 mpu_err_access_control_t accessControl; /*!< Access error control. */
<> 144:ef7eb2e8f9f7 252 uint32_t address; /*!< Access error address. */
<> 144:ef7eb2e8f9f7 253 #if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
<> 144:ef7eb2e8f9f7 254 uint8_t processorIdentification; /*!< Access error processor identification. */
<> 144:ef7eb2e8f9f7 255 #endif /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */
<> 144:ef7eb2e8f9f7 256 } mpu_access_err_info_t;
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 /*! @brief MPU access rights for low master master port 0 ~ port 3. */
<> 144:ef7eb2e8f9f7 259 typedef struct _mpu_low_masters_access_rights
<> 144:ef7eb2e8f9f7 260 {
<> 144:ef7eb2e8f9f7 261 mpu_supervisor_access_rights_t superAccessRights; /*!< Master access rights in supervisor mode. */
<> 144:ef7eb2e8f9f7 262 mpu_user_access_rights_t userAccessRights; /*!< Master access rights in user mode. */
<> 144:ef7eb2e8f9f7 263 #if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
<> 144:ef7eb2e8f9f7 264 bool processIdentifierEnable; /*!< Enables or disables process identifier. */
<> 144:ef7eb2e8f9f7 265 #endif /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */
<> 144:ef7eb2e8f9f7 266 } mpu_low_masters_access_rights_t;
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 /*! @brief MPU access rights mode for high master port 4 ~ port 7. */
<> 144:ef7eb2e8f9f7 269 typedef struct _mpu_high_masters_access_rights
<> 144:ef7eb2e8f9f7 270 {
<> 144:ef7eb2e8f9f7 271 bool writeEnable; /*!< Enables or disables write permission. */
<> 144:ef7eb2e8f9f7 272 bool readEnable; /*!< Enables or disables read permission. */
<> 144:ef7eb2e8f9f7 273 } mpu_high_masters_access_rights_t;
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275 /*!
<> 144:ef7eb2e8f9f7 276 * @brief MPU region configuration structure.
<> 144:ef7eb2e8f9f7 277 *
<> 144:ef7eb2e8f9f7 278 * This structure is used to configure the regionNum region.
<> 144:ef7eb2e8f9f7 279 * The accessRights1[0] ~ accessRights1[3] are used to configure the four low master
<> 144:ef7eb2e8f9f7 280 * numbers: master 0 ~ master 3. The accessRights2[0] ~ accessRights2[3] are
<> 144:ef7eb2e8f9f7 281 * used to configure the four high master numbers: master 4 ~ master 7.
<> 144:ef7eb2e8f9f7 282 * The master port assignment is the chip configuration. Normally, the core is the
<> 144:ef7eb2e8f9f7 283 * master 0, debugger is the master 1.
<> 144:ef7eb2e8f9f7 284 * Note: MPU assigns a priority scheme where the debugger is treated as the highest
<> 144:ef7eb2e8f9f7 285 * priority master followed by the core and then all the remaining masters.
<> 144:ef7eb2e8f9f7 286 * MPU protection does not allow writes from the core to affect the "regionNum 0" start
<> 144:ef7eb2e8f9f7 287 * and end address nor the permissions associated with the debugger. It can only write
<> 144:ef7eb2e8f9f7 288 * the permission fields associated with the other masters. This protection guarantee
<> 144:ef7eb2e8f9f7 289 * the debugger always has access to the entire address space and those rights can't
<> 144:ef7eb2e8f9f7 290 * be changed by the core or any other bus master. Prepare
<> 144:ef7eb2e8f9f7 291 * the region configuration when regionNum is kMPU_RegionNum00.
<> 144:ef7eb2e8f9f7 292 */
<> 144:ef7eb2e8f9f7 293 typedef struct _mpu_region_config
<> 144:ef7eb2e8f9f7 294 {
<> 144:ef7eb2e8f9f7 295 mpu_region_num_t regionNum; /*!< MPU region number. */
<> 144:ef7eb2e8f9f7 296 uint32_t startAddress; /*!< Memory region start address. Note: bit0 ~ bit4 always be marked as 0 by MPU. The actual
<> 144:ef7eb2e8f9f7 297 start address is 0-modulo-32 byte address. */
<> 144:ef7eb2e8f9f7 298 uint32_t endAddress; /*!< Memory region end address. Note: bit0 ~ bit4 always be marked as 1 by MPU. The actual end
<> 144:ef7eb2e8f9f7 299 address is 31-modulo-32 byte address. */
<> 144:ef7eb2e8f9f7 300 mpu_low_masters_access_rights_t accessRights1[4]; /*!< Low masters access permission. */
<> 144:ef7eb2e8f9f7 301 mpu_high_masters_access_rights_t accessRights2[4]; /*!< High masters access permission. */
<> 144:ef7eb2e8f9f7 302 #if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
<> 144:ef7eb2e8f9f7 303 uint8_t processIdentifier; /*!< Process identifier used when "processIdentifierEnable" set with true. */
<> 144:ef7eb2e8f9f7 304 uint8_t
<> 144:ef7eb2e8f9f7 305 processIdMask; /*!< Process identifier mask. The setting bit will ignore the same bit in process identifier. */
<> 144:ef7eb2e8f9f7 306 #endif /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */
<> 144:ef7eb2e8f9f7 307 } mpu_region_config_t;
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 /*!
<> 144:ef7eb2e8f9f7 310 * @brief The configuration structure for the MPU initialization.
<> 144:ef7eb2e8f9f7 311 *
<> 144:ef7eb2e8f9f7 312 * This structure is used when calling the MPU_Init function.
<> 144:ef7eb2e8f9f7 313 */
<> 144:ef7eb2e8f9f7 314 typedef struct _mpu_config
<> 144:ef7eb2e8f9f7 315 {
<> 144:ef7eb2e8f9f7 316 mpu_region_config_t regionConfig; /*!< region access permission. */
<> 144:ef7eb2e8f9f7 317 struct _mpu_config *next; /*!< pointer to the next structure. */
<> 144:ef7eb2e8f9f7 318 } mpu_config_t;
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320 /*******************************************************************************
<> 144:ef7eb2e8f9f7 321 * API
<> 144:ef7eb2e8f9f7 322 ******************************************************************************/
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 #if defined(__cplusplus)
<> 144:ef7eb2e8f9f7 325 extern "C" {
<> 144:ef7eb2e8f9f7 326 #endif /* _cplusplus */
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 /*!
<> 144:ef7eb2e8f9f7 329 * @name Initialization and deinitialization
<> 144:ef7eb2e8f9f7 330 * @{
<> 144:ef7eb2e8f9f7 331 */
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 /*!
<> 144:ef7eb2e8f9f7 334 * @brief Initializes the MPU with the user configuration structure.
<> 144:ef7eb2e8f9f7 335 *
<> 144:ef7eb2e8f9f7 336 * This function configures the MPU module with the user-defined configuration.
<> 144:ef7eb2e8f9f7 337 *
<> 144:ef7eb2e8f9f7 338 * @param base MPU peripheral base address.
<> 144:ef7eb2e8f9f7 339 * @param config The pointer to the configuration structure.
<> 144:ef7eb2e8f9f7 340 */
<> 144:ef7eb2e8f9f7 341 void MPU_Init(MPU_Type *base, const mpu_config_t *config);
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 /*!
<> 144:ef7eb2e8f9f7 344 * @brief Deinitializes the MPU regions.
<> 144:ef7eb2e8f9f7 345 *
<> 144:ef7eb2e8f9f7 346 * @param base MPU peripheral base address.
<> 144:ef7eb2e8f9f7 347 */
<> 144:ef7eb2e8f9f7 348 void MPU_Deinit(MPU_Type *base);
<> 144:ef7eb2e8f9f7 349
<> 144:ef7eb2e8f9f7 350 /* @}*/
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 /*!
<> 144:ef7eb2e8f9f7 353 * @name Basic Control Operations
<> 144:ef7eb2e8f9f7 354 * @{
<> 144:ef7eb2e8f9f7 355 */
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 /*!
<> 144:ef7eb2e8f9f7 358 * @brief Enables/disables the MPU globally.
<> 144:ef7eb2e8f9f7 359 *
<> 144:ef7eb2e8f9f7 360 * Call this API to enable or disable the MPU module.
<> 144:ef7eb2e8f9f7 361 *
<> 144:ef7eb2e8f9f7 362 * @param base MPU peripheral base address.
<> 144:ef7eb2e8f9f7 363 * @param enable True enable MPU, false disable MPU.
<> 144:ef7eb2e8f9f7 364 */
<> 144:ef7eb2e8f9f7 365 static inline void MPU_Enable(MPU_Type *base, bool enable)
<> 144:ef7eb2e8f9f7 366 {
<> 144:ef7eb2e8f9f7 367 if (enable)
<> 144:ef7eb2e8f9f7 368 {
<> 144:ef7eb2e8f9f7 369 /* Enable the MPU globally. */
<> 144:ef7eb2e8f9f7 370 base->CESR |= MPU_CESR_VLD_MASK;
<> 144:ef7eb2e8f9f7 371 }
<> 144:ef7eb2e8f9f7 372 else
<> 144:ef7eb2e8f9f7 373 { /* Disable the MPU globally. */
<> 144:ef7eb2e8f9f7 374 base->CESR &= ~MPU_CESR_VLD_MASK;
<> 144:ef7eb2e8f9f7 375 }
<> 144:ef7eb2e8f9f7 376 }
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 /*!
<> 144:ef7eb2e8f9f7 379 * @brief Enables/disables the MPU for a special region.
<> 144:ef7eb2e8f9f7 380 *
<> 144:ef7eb2e8f9f7 381 * When MPU is enabled, call this API to disable an unused region
<> 144:ef7eb2e8f9f7 382 * of an enabled MPU. Call this API to minimize the power dissipation.
<> 144:ef7eb2e8f9f7 383 *
<> 144:ef7eb2e8f9f7 384 * @param base MPU peripheral base address.
<> 144:ef7eb2e8f9f7 385 * @param number MPU region number.
<> 144:ef7eb2e8f9f7 386 * @param enable True enable the special region MPU, false disable the special region MPU.
<> 144:ef7eb2e8f9f7 387 */
<> 144:ef7eb2e8f9f7 388 static inline void MPU_RegionEnable(MPU_Type *base, mpu_region_num_t number, bool enable)
<> 144:ef7eb2e8f9f7 389 {
<> 144:ef7eb2e8f9f7 390 if (enable)
<> 144:ef7eb2e8f9f7 391 {
<> 144:ef7eb2e8f9f7 392 /* Enable the #number region MPU. */
<> 144:ef7eb2e8f9f7 393 base->WORD[number][3] |= MPU_WORD_VLD_MASK;
<> 144:ef7eb2e8f9f7 394 }
<> 144:ef7eb2e8f9f7 395 else
<> 144:ef7eb2e8f9f7 396 { /* Disable the #number region MPU. */
<> 144:ef7eb2e8f9f7 397 base->WORD[number][3] &= ~MPU_WORD_VLD_MASK;
<> 144:ef7eb2e8f9f7 398 }
<> 144:ef7eb2e8f9f7 399 }
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401 /*!
<> 144:ef7eb2e8f9f7 402 * @brief Gets the MPU basic hardware information.
<> 144:ef7eb2e8f9f7 403 *
<> 144:ef7eb2e8f9f7 404 * @param base MPU peripheral base address.
<> 144:ef7eb2e8f9f7 405 * @param hardwareInform The pointer to the MPU hardware information structure. See "mpu_hardware_info_t".
<> 144:ef7eb2e8f9f7 406 */
<> 144:ef7eb2e8f9f7 407 void MPU_GetHardwareInfo(MPU_Type *base, mpu_hardware_info_t *hardwareInform);
<> 144:ef7eb2e8f9f7 408
<> 144:ef7eb2e8f9f7 409 /*!
<> 144:ef7eb2e8f9f7 410 * @brief Sets the MPU region.
<> 144:ef7eb2e8f9f7 411 *
<> 144:ef7eb2e8f9f7 412 * Note: Due to the MPU protection, the kMPU_RegionNum00 does not allow writes from the
<> 144:ef7eb2e8f9f7 413 * core to affect the start and end address nor the permissions associated with
<> 144:ef7eb2e8f9f7 414 * the debugger. It can only write the permission fields associated
<> 144:ef7eb2e8f9f7 415 * with the other masters.
<> 144:ef7eb2e8f9f7 416 *
<> 144:ef7eb2e8f9f7 417 * @param base MPU peripheral base address.
<> 144:ef7eb2e8f9f7 418 * @param regionConfig The pointer to the MPU user configuration structure. See "mpu_region_config_t".
<> 144:ef7eb2e8f9f7 419 */
<> 144:ef7eb2e8f9f7 420 void MPU_SetRegionConfig(MPU_Type *base, const mpu_region_config_t *regionConfig);
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 /*!
<> 144:ef7eb2e8f9f7 423 * @brief Sets the region start and end address.
<> 144:ef7eb2e8f9f7 424 *
<> 144:ef7eb2e8f9f7 425 * Memory region start address. Note: bit0 ~ bit4 is always marked as 0 by MPU.
<> 144:ef7eb2e8f9f7 426 * The actual start address by MPU is 0-modulo-32 byte address.
<> 144:ef7eb2e8f9f7 427 * Memory region end address. Note: bit0 ~ bit4 always be marked as 1 by MPU.
<> 144:ef7eb2e8f9f7 428 * The actual end address used by MPU is 31-modulo-32 byte address.
<> 144:ef7eb2e8f9f7 429 * Note: Due to the MPU protection, the startAddr and endAddr can't be
<> 144:ef7eb2e8f9f7 430 * changed by the core when regionNum is "kMPU_RegionNum00".
<> 144:ef7eb2e8f9f7 431 *
<> 144:ef7eb2e8f9f7 432 * @param base MPU peripheral base address.
<> 144:ef7eb2e8f9f7 433 * @param regionNum MPU region number.
<> 144:ef7eb2e8f9f7 434 * @param startAddr Region start address.
<> 144:ef7eb2e8f9f7 435 * @param endAddr Region end address.
<> 144:ef7eb2e8f9f7 436 */
<> 144:ef7eb2e8f9f7 437 void MPU_SetRegionAddr(MPU_Type *base, mpu_region_num_t regionNum, uint32_t startAddr, uint32_t endAddr);
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 /*!
<> 144:ef7eb2e8f9f7 440 * @brief Sets the MPU region access rights for low master port 0 ~ port 3.
<> 144:ef7eb2e8f9f7 441 * This can be used to change the region access rights for any master port for any region.
<> 144:ef7eb2e8f9f7 442 *
<> 144:ef7eb2e8f9f7 443 * @param base MPU peripheral base address.
<> 144:ef7eb2e8f9f7 444 * @param regionNum MPU region number.
<> 144:ef7eb2e8f9f7 445 * @param masterNum MPU master number. Should range from kMPU_Master0 ~ kMPU_Master3.
<> 144:ef7eb2e8f9f7 446 * @param accessRights The pointer to the MPU access rights configuration. See "mpu_low_masters_access_rights_t".
<> 144:ef7eb2e8f9f7 447 */
<> 144:ef7eb2e8f9f7 448 void MPU_SetRegionLowMasterAccessRights(MPU_Type *base,
<> 144:ef7eb2e8f9f7 449 mpu_region_num_t regionNum,
<> 144:ef7eb2e8f9f7 450 mpu_master_t masterNum,
<> 144:ef7eb2e8f9f7 451 const mpu_low_masters_access_rights_t *accessRights);
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 /*!
<> 144:ef7eb2e8f9f7 454 * @brief Sets the MPU region access rights for high master port 4 ~ port 7.
<> 144:ef7eb2e8f9f7 455 * This can be used to change the region access rights for any master port for any region.
<> 144:ef7eb2e8f9f7 456 *
<> 144:ef7eb2e8f9f7 457 * @param base MPU peripheral base address.
<> 144:ef7eb2e8f9f7 458 * @param regionNum MPU region number.
<> 144:ef7eb2e8f9f7 459 * @param masterNum MPU master number. Should range from kMPU_Master4 ~ kMPU_Master7.
<> 144:ef7eb2e8f9f7 460 * @param accessRights The pointer to the MPU access rights configuration. See "mpu_high_masters_access_rights_t".
<> 144:ef7eb2e8f9f7 461 */
<> 144:ef7eb2e8f9f7 462 void MPU_SetRegionHighMasterAccessRights(MPU_Type *base,
<> 144:ef7eb2e8f9f7 463 mpu_region_num_t regionNum,
<> 144:ef7eb2e8f9f7 464 mpu_master_t masterNum,
<> 144:ef7eb2e8f9f7 465 const mpu_high_masters_access_rights_t *accessRights);
<> 144:ef7eb2e8f9f7 466
<> 144:ef7eb2e8f9f7 467 /*!
<> 144:ef7eb2e8f9f7 468 * @brief Gets the numbers of slave ports where errors occur.
<> 144:ef7eb2e8f9f7 469 *
<> 144:ef7eb2e8f9f7 470 * @param base MPU peripheral base address.
<> 144:ef7eb2e8f9f7 471 * @param slaveNum MPU slave port number.
<> 144:ef7eb2e8f9f7 472 * @return The slave ports error status.
<> 144:ef7eb2e8f9f7 473 * true - error happens in this slave port.
<> 144:ef7eb2e8f9f7 474 * false - error didn't happen in this slave port.
<> 144:ef7eb2e8f9f7 475 */
<> 144:ef7eb2e8f9f7 476 bool MPU_GetSlavePortErrorStatus(MPU_Type *base, mpu_slave_t slaveNum);
<> 144:ef7eb2e8f9f7 477
<> 144:ef7eb2e8f9f7 478 /*!
<> 144:ef7eb2e8f9f7 479 * @brief Gets the MPU detailed error access information.
<> 144:ef7eb2e8f9f7 480 *
<> 144:ef7eb2e8f9f7 481 * @param base MPU peripheral base address.
<> 144:ef7eb2e8f9f7 482 * @param slaveNum MPU slave port number.
<> 144:ef7eb2e8f9f7 483 * @param errInform The pointer to the MPU access error information. See "mpu_access_err_info_t".
<> 144:ef7eb2e8f9f7 484 */
<> 144:ef7eb2e8f9f7 485 void MPU_GetDetailErrorAccessInfo(MPU_Type *base, mpu_slave_t slaveNum, mpu_access_err_info_t *errInform);
<> 144:ef7eb2e8f9f7 486
<> 144:ef7eb2e8f9f7 487 /* @} */
<> 144:ef7eb2e8f9f7 488
<> 144:ef7eb2e8f9f7 489 #if defined(__cplusplus)
<> 144:ef7eb2e8f9f7 490 }
<> 144:ef7eb2e8f9f7 491 #endif
<> 144:ef7eb2e8f9f7 492
<> 144:ef7eb2e8f9f7 493 /*! @}*/
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495 #endif /* _FSL_MPU_H_ */