Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_lmem_cache.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 144:ef7eb2e8f9f7 3 * All rights reserved.
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 6 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 9 * of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 12 * list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 13 * other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 144:ef7eb2e8f9f7 16 * contributors may be used to endorse or promote products derived from this
<> 144:ef7eb2e8f9f7 17 * software without specific prior written permission.
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 29 */
<> 144:ef7eb2e8f9f7 30 #ifndef _FSL_LMEM_CACHE_H_
<> 144:ef7eb2e8f9f7 31 #define _FSL_LMEM_CACHE_H_
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 #include "fsl_common.h"
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 /*!
<> 144:ef7eb2e8f9f7 36 * @addtogroup lmem_cache
<> 144:ef7eb2e8f9f7 37 * @{
<> 144:ef7eb2e8f9f7 38 */
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 /*! @file */
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 /*******************************************************************************
<> 144:ef7eb2e8f9f7 43 * Definitions
<> 144:ef7eb2e8f9f7 44 ******************************************************************************/
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /*! @name Driver version */
<> 144:ef7eb2e8f9f7 47 /*@{*/
<> 144:ef7eb2e8f9f7 48 /*! @brief LMEM controller driver version 2.0.0. */
<> 144:ef7eb2e8f9f7 49 #define FSL_LMEM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
<> 144:ef7eb2e8f9f7 50 /*@}*/
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 #define LMEM_CACHE_LINE_SIZE (0x10U) /*!< Cache line is 16-bytes. */
<> 144:ef7eb2e8f9f7 53 #define LMEM_CACHE_SIZE_ONEWAY (4096U) /*!< Cache size is 4K-bytes one way. */
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /*! @brief LMEM cache mode options. */
<> 144:ef7eb2e8f9f7 56 typedef enum _lmem_cache_mode
<> 144:ef7eb2e8f9f7 57 {
<> 144:ef7eb2e8f9f7 58 kLMEM_NonCacheable = 0x0U, /*!< CACHE mode: non-cacheable. */
<> 144:ef7eb2e8f9f7 59 kLMEM_CacheWriteThrough = 0x2U, /*!< CACHE mode: write-through. */
<> 144:ef7eb2e8f9f7 60 kLMEM_CacheWriteBack = 0x3U /*!< CACHE mode: write-back. */
<> 144:ef7eb2e8f9f7 61 } lmem_cache_mode_t;
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /*! @brief LMEM cache regions. */
<> 144:ef7eb2e8f9f7 64 typedef enum _lmem_cache_region
<> 144:ef7eb2e8f9f7 65 {
<> 144:ef7eb2e8f9f7 66 kLMEM_CacheRegion15 = 0U, /*!< Cache Region 15. */
<> 144:ef7eb2e8f9f7 67 kLMEM_CacheRegion14, /*!< Cache Region 14. */
<> 144:ef7eb2e8f9f7 68 kLMEM_CacheRegion13, /*!< Cache Region 13. */
<> 144:ef7eb2e8f9f7 69 kLMEM_CacheRegion12, /*!< Cache Region 12. */
<> 144:ef7eb2e8f9f7 70 kLMEM_CacheRegion11, /*!< Cache Region 11. */
<> 144:ef7eb2e8f9f7 71 kLMEM_CacheRegion10, /*!< Cache Region 10. */
<> 144:ef7eb2e8f9f7 72 kLMEM_CacheRegion9, /*!< Cache Region 9. */
<> 144:ef7eb2e8f9f7 73 kLMEM_CacheRegion8, /*!< Cache Region 8. */
<> 144:ef7eb2e8f9f7 74 kLMEM_CacheRegion7, /*!< Cache Region 7. */
<> 144:ef7eb2e8f9f7 75 kLMEM_CacheRegion6, /*!< Cache Region 6. */
<> 144:ef7eb2e8f9f7 76 kLMEM_CacheRegion5, /*!< Cache Region 5. */
<> 144:ef7eb2e8f9f7 77 kLMEM_CacheRegion4, /*!< Cache Region 4. */
<> 144:ef7eb2e8f9f7 78 kLMEM_CacheRegion3, /*!< Cache Region 3. */
<> 144:ef7eb2e8f9f7 79 kLMEM_CacheRegion2, /*!< Cache Region 2. */
<> 144:ef7eb2e8f9f7 80 kLMEM_CacheRegion1, /*!< Cache Region 1. */
<> 144:ef7eb2e8f9f7 81 kLMEM_CacheRegion0 /*!< Cache Region 0. */
<> 144:ef7eb2e8f9f7 82 } lmem_cache_region_t;
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 /*! @brief LMEM cache line command. */
<> 144:ef7eb2e8f9f7 85 typedef enum _lmem_cache_line_command
<> 144:ef7eb2e8f9f7 86 {
<> 144:ef7eb2e8f9f7 87 kLMEM_CacheLineSearchReadOrWrite = 0U, /*!< Cache line search and read or write. */
<> 144:ef7eb2e8f9f7 88 kLMEM_CacheLineInvalidate, /*!< Cache line invalidate. */
<> 144:ef7eb2e8f9f7 89 kLMEM_CacheLinePush, /*!< Cache line push. */
<> 144:ef7eb2e8f9f7 90 kLMEM_CacheLineClear, /*!< Cache line clear. */
<> 144:ef7eb2e8f9f7 91 } lmem_cache_line_command_t;
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 /*******************************************************************************
<> 144:ef7eb2e8f9f7 94 * API
<> 144:ef7eb2e8f9f7 95 ******************************************************************************/
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 #if defined(__cplusplus)
<> 144:ef7eb2e8f9f7 98 extern "C" {
<> 144:ef7eb2e8f9f7 99 #endif
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 /*!
<> 144:ef7eb2e8f9f7 102 * @name Local Memory Processor Code Bus Cache Control
<> 144:ef7eb2e8f9f7 103 *@{
<> 144:ef7eb2e8f9f7 104 */
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 /*!
<> 144:ef7eb2e8f9f7 107 * @brief Enables/disables the processor code bus cache.
<> 144:ef7eb2e8f9f7 108 * This function enables/disables the cache. The function first invalidates the entire cache
<> 144:ef7eb2e8f9f7 109 * and then enables/disable both the cache and write buffers.
<> 144:ef7eb2e8f9f7 110 *
<> 144:ef7eb2e8f9f7 111 * @param base LMEM peripheral base address.
<> 144:ef7eb2e8f9f7 112 * @param enable The enable or disable flag.
<> 144:ef7eb2e8f9f7 113 * true - enable the code cache.
<> 144:ef7eb2e8f9f7 114 * false - disable the code cache.
<> 144:ef7eb2e8f9f7 115 */
<> 144:ef7eb2e8f9f7 116 void LMEM_EnableCodeCache(LMEM_Type *base, bool enable);
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 /*!
<> 144:ef7eb2e8f9f7 119 * @brief Invalidates the processor code bus cache.
<> 144:ef7eb2e8f9f7 120 * This function invalidates the cache both ways, which means that
<> 144:ef7eb2e8f9f7 121 * it unconditionally clears valid bits and modifies bits of a cache entry.
<> 144:ef7eb2e8f9f7 122 *
<> 144:ef7eb2e8f9f7 123 * @param base LMEM peripheral base address.
<> 144:ef7eb2e8f9f7 124 */
<> 144:ef7eb2e8f9f7 125 void LMEM_CodeCacheInvalidateAll(LMEM_Type *base);
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 /*!
<> 144:ef7eb2e8f9f7 128 * @brief Pushes all modified lines in the processor code bus cache.
<> 144:ef7eb2e8f9f7 129 * This function pushes all modified lines in both ways in the entire cache.
<> 144:ef7eb2e8f9f7 130 * It pushes a cache entry if it is valid and modified and clears the modified bit. If
<> 144:ef7eb2e8f9f7 131 * the entry is not valid or not modified, leave as is. This action does not clear the valid
<> 144:ef7eb2e8f9f7 132 * bit. A cache push is synonymous with a cache flush.
<> 144:ef7eb2e8f9f7 133 *
<> 144:ef7eb2e8f9f7 134 * @param base LMEM peripheral base address.
<> 144:ef7eb2e8f9f7 135 */
<> 144:ef7eb2e8f9f7 136 void LMEM_CodeCachePushAll(LMEM_Type *base);
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 /*!
<> 144:ef7eb2e8f9f7 139 * @brief Clears the processor code bus cache.
<> 144:ef7eb2e8f9f7 140 * This function clears the entire cache and pushes (flushes) and
<> 144:ef7eb2e8f9f7 141 * invalidates the operation.
<> 144:ef7eb2e8f9f7 142 * Clear - Pushes a cache entry if it is valid and modified, then clears the valid and
<> 144:ef7eb2e8f9f7 143 * modified bits. If the entry is not valid or not modified, clear the valid bit.
<> 144:ef7eb2e8f9f7 144 *
<> 144:ef7eb2e8f9f7 145 * @param base LMEM peripheral base address.
<> 144:ef7eb2e8f9f7 146 */
<> 144:ef7eb2e8f9f7 147 void LMEM_CodeCacheClearAll(LMEM_Type *base);
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 /*!
<> 144:ef7eb2e8f9f7 150 * @brief Invalidates a specific line in the processor code bus cache.
<> 144:ef7eb2e8f9f7 151 * This function invalidates a specific line in the cache
<> 144:ef7eb2e8f9f7 152 * based on the physical address passed in by the user.
<> 144:ef7eb2e8f9f7 153 * Invalidate - Unconditionally clears valid and modified bits of a cache entry.
<> 144:ef7eb2e8f9f7 154 *
<> 144:ef7eb2e8f9f7 155 * @param base LMEM peripheral base address.
<> 144:ef7eb2e8f9f7 156 * @param address The physical address of the cache line. Should be 16-byte aligned address.
<> 144:ef7eb2e8f9f7 157 * If not, it is changed to the 16-byte aligned memory address.
<> 144:ef7eb2e8f9f7 158 */
<> 144:ef7eb2e8f9f7 159 void LMEM_CodeCacheInvalidateLine(LMEM_Type *base, uint32_t address);
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 /*!
<> 144:ef7eb2e8f9f7 162 * @brief Invalidates multiple lines in the processor code bus cache.
<> 144:ef7eb2e8f9f7 163 * This function invalidates multiple lines in the cache
<> 144:ef7eb2e8f9f7 164 * based on the physical address and length in bytes passed in by the
<> 144:ef7eb2e8f9f7 165 * user. If the function detects that the length meets or exceeds half the
<> 144:ef7eb2e8f9f7 166 * cache. Then the function performs an entire cache invalidate function, which is
<> 144:ef7eb2e8f9f7 167 * more efficient than invalidating the cache line-by-line.
<> 144:ef7eb2e8f9f7 168 * The need to check half the total amount of cache is due to the fact that the cache consists of
<> 144:ef7eb2e8f9f7 169 * two ways and that line commands based on the physical address searches both ways.
<> 144:ef7eb2e8f9f7 170 * Invalidate - Unconditionally clear valid and modified bits of a cache entry.
<> 144:ef7eb2e8f9f7 171 *
<> 144:ef7eb2e8f9f7 172 * @param base LMEM peripheral base address.
<> 144:ef7eb2e8f9f7 173 * @param address The physical address of the cache line. Should be 16-byte aligned address.
<> 144:ef7eb2e8f9f7 174 * If not, it is changed to the 16-byte aligned memory address.
<> 144:ef7eb2e8f9f7 175 * @param length The length in bytes of the total amount of cache lines.
<> 144:ef7eb2e8f9f7 176 */
<> 144:ef7eb2e8f9f7 177 void LMEM_CodeCacheInvalidateMultiLines(LMEM_Type *base, uint32_t address, uint32_t length);
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 /*!
<> 144:ef7eb2e8f9f7 180 * @brief Pushes a specific modified line in the processor code bus cache.
<> 144:ef7eb2e8f9f7 181 * This function pushes a specific modified line based on the physical address passed in
<> 144:ef7eb2e8f9f7 182 * by the user.
<> 144:ef7eb2e8f9f7 183 * Push - Push a cache entry if it is valid and modified, then clear the modified bit. If the
<> 144:ef7eb2e8f9f7 184 * entry is not valid or not modified, leave as is. This action does not clear the valid
<> 144:ef7eb2e8f9f7 185 * bit. A cache push is synonymous with a cache flush.
<> 144:ef7eb2e8f9f7 186 *
<> 144:ef7eb2e8f9f7 187 * @param base LMEM peripheral base address.
<> 144:ef7eb2e8f9f7 188 * @param address The physical address of the cache line. Should be 16-byte aligned address.
<> 144:ef7eb2e8f9f7 189 * If not, it is changed to the 16-byte aligned memory address.
<> 144:ef7eb2e8f9f7 190 */
<> 144:ef7eb2e8f9f7 191 void LMEM_CodeCachePushLine(LMEM_Type *base, uint32_t address);
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 /*!
<> 144:ef7eb2e8f9f7 194 * @brief Pushes multiple modified lines in the processor code bus cache.
<> 144:ef7eb2e8f9f7 195 * This function pushes multiple modified lines in the cache
<> 144:ef7eb2e8f9f7 196 * based on the physical address and length in bytes passed in by the
<> 144:ef7eb2e8f9f7 197 * user. If the function detects that the length meets or exceeds half of the
<> 144:ef7eb2e8f9f7 198 * cache, the function performs an cache push function, which is
<> 144:ef7eb2e8f9f7 199 * more efficient than pushing the modified lines in the cache line-by-line.
<> 144:ef7eb2e8f9f7 200 * The need to check half the total amount of cache is due to the fact that the cache consists of
<> 144:ef7eb2e8f9f7 201 * two ways and that line commands based on the physical address searches both ways.
<> 144:ef7eb2e8f9f7 202 * Push - Push a cache entry if it is valid and modified, then clear the modified bit. If
<> 144:ef7eb2e8f9f7 203 * the entry is not valid or not modified, leave as is. This action does not clear the valid
<> 144:ef7eb2e8f9f7 204 * bit. A cache push is synonymous with a cache flush.
<> 144:ef7eb2e8f9f7 205 *
<> 144:ef7eb2e8f9f7 206 * @param base LMEM peripheral base address.
<> 144:ef7eb2e8f9f7 207 * @param address The physical address of the cache line. Should be 16-byte aligned address.
<> 144:ef7eb2e8f9f7 208 * If not, it is changed to the 16-byte aligned memory address.
<> 144:ef7eb2e8f9f7 209 * @param length The length in bytes of the total amount of cache lines.
<> 144:ef7eb2e8f9f7 210 */
<> 144:ef7eb2e8f9f7 211 void LMEM_CodeCachePushMultiLines(LMEM_Type *base, uint32_t address, uint32_t length);
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 /*!
<> 144:ef7eb2e8f9f7 214 * @brief Clears a specific line in the processor code bus cache.
<> 144:ef7eb2e8f9f7 215 * This function clears a specific line based on the physical address passed in
<> 144:ef7eb2e8f9f7 216 * by the user.
<> 144:ef7eb2e8f9f7 217 * Clear - Push a cache entry if it is valid and modified, then clear the valid and
<> 144:ef7eb2e8f9f7 218 * modify bits. If entry not valid or not modified, clear the valid bit.
<> 144:ef7eb2e8f9f7 219 *
<> 144:ef7eb2e8f9f7 220 * @param base LMEM peripheral base address.
<> 144:ef7eb2e8f9f7 221 * @param address The physical address of the cache line. Should be 16-byte aligned address.
<> 144:ef7eb2e8f9f7 222 * If not, it is changed to the 16-byte aligned memory address.
<> 144:ef7eb2e8f9f7 223 */
<> 144:ef7eb2e8f9f7 224 void LMEM_CodeCacheClearLine(LMEM_Type *base, uint32_t address);
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 /*!
<> 144:ef7eb2e8f9f7 227 * @brief Clears multiple lines in the processor code bus cache.
<> 144:ef7eb2e8f9f7 228 * This function clears multiple lines in the cache
<> 144:ef7eb2e8f9f7 229 * based on the physical address and length in bytes passed in by the
<> 144:ef7eb2e8f9f7 230 * user. If the function detects that the length meets or exceeds half the total amount of
<> 144:ef7eb2e8f9f7 231 * cache, the function performs a cache clear function which is
<> 144:ef7eb2e8f9f7 232 * more efficient than clearing the lines in the cache line-by-line.
<> 144:ef7eb2e8f9f7 233 * The need to check half the total amount of cache is due to the fact that the cache consists of
<> 144:ef7eb2e8f9f7 234 * two ways and that line commands based on the physical address searches both ways.
<> 144:ef7eb2e8f9f7 235 * Clear - Push a cache entry if it is valid and modified, then clear the valid and
<> 144:ef7eb2e8f9f7 236 * modify bits. If entry not valid or not modified, clear the valid bit.
<> 144:ef7eb2e8f9f7 237 *
<> 144:ef7eb2e8f9f7 238 * @param base LMEM peripheral base address.
<> 144:ef7eb2e8f9f7 239 * @param address The physical address of the cache line. Should be 16-byte aligned address.
<> 144:ef7eb2e8f9f7 240 * If not, it is changed to the 16-byte aligned memory address.
<> 144:ef7eb2e8f9f7 241 * @param length The length in bytes of the total amount of cache lines.
<> 144:ef7eb2e8f9f7 242 */
<> 144:ef7eb2e8f9f7 243 void LMEM_CodeCacheClearMultiLines(LMEM_Type *base, uint32_t address, uint32_t length);
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 /*!
<> 144:ef7eb2e8f9f7 246 * @brief Demotes the cache mode of a region in processor code bus cache.
<> 144:ef7eb2e8f9f7 247 * This function allows the user to demote the cache mode of a region within the device's
<> 144:ef7eb2e8f9f7 248 * memory map. Demoting the cache mode reduces the cache function applied to a memory
<> 144:ef7eb2e8f9f7 249 * region from write-back to write-through to non-cacheable. The function checks to see
<> 144:ef7eb2e8f9f7 250 * if the requested cache mode is higher than or equal to the current cache mode, and if
<> 144:ef7eb2e8f9f7 251 * so, returns an error. After a region is demoted, its cache mode can only be raised
<> 144:ef7eb2e8f9f7 252 * by a reset, which returns it to its default state which is the highest cache configure for
<> 144:ef7eb2e8f9f7 253 * each region.
<> 144:ef7eb2e8f9f7 254 * To maintain cache coherency, changes to the cache mode should be completed while the
<> 144:ef7eb2e8f9f7 255 * address space being changed is not being accessed or the cache is disabled. Before a
<> 144:ef7eb2e8f9f7 256 * cache mode change, this function completes a cache clear all command to push and invalidate any
<> 144:ef7eb2e8f9f7 257 * cache entries that may have changed.
<> 144:ef7eb2e8f9f7 258 *
<> 144:ef7eb2e8f9f7 259 * @param base LMEM peripheral base address.
<> 144:ef7eb2e8f9f7 260 * @param region The desired region to demote of type lmem_cache_region_t.
<> 144:ef7eb2e8f9f7 261 * @param cacheMode The new, demoted cache mode of type lmem_cache_mode_t.
<> 144:ef7eb2e8f9f7 262 * @return The execution result.
<> 144:ef7eb2e8f9f7 263 * kStatus_Success The cache demote operation is successful.
<> 144:ef7eb2e8f9f7 264 * kStatus_Fail The cache demote operation is failure.
<> 144:ef7eb2e8f9f7 265 */
<> 144:ef7eb2e8f9f7 266 status_t LMEM_CodeCacheDemoteRegion(LMEM_Type *base, lmem_cache_region_t region, lmem_cache_mode_t cacheMode);
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 /*@}*/
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 #if FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE
<> 144:ef7eb2e8f9f7 271 /*!
<> 144:ef7eb2e8f9f7 272 * @name Local Memory Processor System Bus Cache Control
<> 144:ef7eb2e8f9f7 273 *@{
<> 144:ef7eb2e8f9f7 274 */
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 /*!
<> 144:ef7eb2e8f9f7 277 * @brief Enables/disables the processor system bus cache.
<> 144:ef7eb2e8f9f7 278 * This function enables/disables the cache. It first invalidates the entire cache,
<> 144:ef7eb2e8f9f7 279 * then enables /disable both the cache and write buffer.
<> 144:ef7eb2e8f9f7 280 *
<> 144:ef7eb2e8f9f7 281 * @param base LMEM peripheral base address.
<> 144:ef7eb2e8f9f7 282 * @param The enable or disable flag.
<> 144:ef7eb2e8f9f7 283 * true - enable the system cache.
<> 144:ef7eb2e8f9f7 284 * false - disable the system cache.
<> 144:ef7eb2e8f9f7 285 */
<> 144:ef7eb2e8f9f7 286 void LMEM_EnableSystemCache(LMEM_Type *base, bool enable);
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 /*!
<> 144:ef7eb2e8f9f7 289 * @brief Invalidates the processor system bus cache.
<> 144:ef7eb2e8f9f7 290 * This function invalidates the entire cache both ways.
<> 144:ef7eb2e8f9f7 291 * Invalidate - Unconditionally clear valid and modify bits of a cache entry
<> 144:ef7eb2e8f9f7 292 *
<> 144:ef7eb2e8f9f7 293 * @param base LMEM peripheral base address.
<> 144:ef7eb2e8f9f7 294 */
<> 144:ef7eb2e8f9f7 295 void LMEM_SystemCacheInvalidateAll(LMEM_Type *base);
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 /*!
<> 144:ef7eb2e8f9f7 298 * @brief Pushes all modified lines in the processor system bus cache.
<> 144:ef7eb2e8f9f7 299 * This function pushes all modified lines in both ways (the entire cache).
<> 144:ef7eb2e8f9f7 300 * Push - Push a cache entry if it is valid and modified, then clear the modify bit. If
<> 144:ef7eb2e8f9f7 301 * the entry is not valid or not modified, leave as is. This action does not clear the valid
<> 144:ef7eb2e8f9f7 302 * bit. A cache push is synonymous with a cache flush.
<> 144:ef7eb2e8f9f7 303 *
<> 144:ef7eb2e8f9f7 304 * @param base LMEM peripheral base address.
<> 144:ef7eb2e8f9f7 305 */
<> 144:ef7eb2e8f9f7 306 void LMEM_SystemCachePushAll(LMEM_Type *base);
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 /*!
<> 144:ef7eb2e8f9f7 309 * @brief Clears the entire processor system bus cache.
<> 144:ef7eb2e8f9f7 310 * This function clears the entire cache, which is a push (flush) and
<> 144:ef7eb2e8f9f7 311 * invalidate operation.
<> 144:ef7eb2e8f9f7 312 * Clear - Push a cache entry if it is valid and modified, then clear the valid and
<> 144:ef7eb2e8f9f7 313 * modify bits. If the entry is not valid or not modified, clear the valid bit.
<> 144:ef7eb2e8f9f7 314 *
<> 144:ef7eb2e8f9f7 315 * @param base LMEM peripheral base address.
<> 144:ef7eb2e8f9f7 316 */
<> 144:ef7eb2e8f9f7 317 void LMEM_SystemCacheClearAll(LMEM_Type *base);
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 /*!
<> 144:ef7eb2e8f9f7 320 * @brief Invalidates a specific line in the processor system bus cache.
<> 144:ef7eb2e8f9f7 321 * This function invalidates a specific line in the cache
<> 144:ef7eb2e8f9f7 322 * based on the physical address passed in by the user.
<> 144:ef7eb2e8f9f7 323 * Invalidate - Unconditionally clear valid and modify bits of a cache entry
<> 144:ef7eb2e8f9f7 324 *
<> 144:ef7eb2e8f9f7 325 * @param base LMEM peripheral base address. Should be 16-byte aligned address.
<> 144:ef7eb2e8f9f7 326 * If not, it is changed to the 16-byte aligned memory address.
<> 144:ef7eb2e8f9f7 327 * @param address The physical address of the cache line.
<> 144:ef7eb2e8f9f7 328 */
<> 144:ef7eb2e8f9f7 329 void LMEM_SystemCacheInvalidateLine(LMEM_Type *base, uint32_t address);
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 /*!
<> 144:ef7eb2e8f9f7 332 * @brief Invalidates multiple lines in the processor system bus cache.
<> 144:ef7eb2e8f9f7 333 * This function invalidates multiple lines in the cache
<> 144:ef7eb2e8f9f7 334 * based on the physical address and length in bytes passed in by the
<> 144:ef7eb2e8f9f7 335 * user. If the function detects that the length meets or exceeds half of the
<> 144:ef7eb2e8f9f7 336 * cache, the function performs an entire cache invalidate function (which is
<> 144:ef7eb2e8f9f7 337 * more efficient than invalidating the cache line-by-line).
<> 144:ef7eb2e8f9f7 338 * The need to check half the total amount of cache is due to the fact that the cache consists of
<> 144:ef7eb2e8f9f7 339 * two ways and that line commands based on the physical address searches both ways.
<> 144:ef7eb2e8f9f7 340 * Invalidate - Unconditionally clear valid and modify bits of a cache entry
<> 144:ef7eb2e8f9f7 341 *
<> 144:ef7eb2e8f9f7 342 * @param base LMEM peripheral base address.
<> 144:ef7eb2e8f9f7 343 * @param address The physical address of the cache line. Should be 16-byte aligned address.
<> 144:ef7eb2e8f9f7 344 * If not, it is changed to the 16-byte aligned memory address.
<> 144:ef7eb2e8f9f7 345 * @param length The length in bytes of the total amount of cache lines.
<> 144:ef7eb2e8f9f7 346 */
<> 144:ef7eb2e8f9f7 347 void LMEM_SystemCacheInvalidateMultiLines(LMEM_Type *base, uint32_t address, uint32_t length);
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 /*!
<> 144:ef7eb2e8f9f7 350 * @brief Pushes a specific modified line in the processor system bus cache.
<> 144:ef7eb2e8f9f7 351 * This function pushes a specific modified line based on the physical address passed in
<> 144:ef7eb2e8f9f7 352 * by the user.
<> 144:ef7eb2e8f9f7 353 * Push - Push a cache entry if it is valid and modified, then clear the modify bit. If
<> 144:ef7eb2e8f9f7 354 * the entry is not valid or not modified, leave as is. This action does not clear the valid
<> 144:ef7eb2e8f9f7 355 * bit. A cache push is synonymous with a cache flush.
<> 144:ef7eb2e8f9f7 356 *
<> 144:ef7eb2e8f9f7 357 * @param base LMEM peripheral base address.
<> 144:ef7eb2e8f9f7 358 * @param address The physical address of the cache line. Should be 16-byte aligned address.
<> 144:ef7eb2e8f9f7 359 * If not, it is changed to the 16-byte aligned memory address.
<> 144:ef7eb2e8f9f7 360 */
<> 144:ef7eb2e8f9f7 361 void LMEM_SystemCachePushLine(LMEM_Type *base, uint32_t address);
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 /*!
<> 144:ef7eb2e8f9f7 364 * @brief Pushes multiple modified lines in the processor system bus cache.
<> 144:ef7eb2e8f9f7 365 * This function pushes multiple modified lines in the cache
<> 144:ef7eb2e8f9f7 366 * based on the physical address and length in bytes passed in by the
<> 144:ef7eb2e8f9f7 367 * user. If the function detects that the length meets or exceeds half of the
<> 144:ef7eb2e8f9f7 368 * cache, the function performs an entire cache push function (which is
<> 144:ef7eb2e8f9f7 369 * more efficient than pushing the modified lines in the cache line-by-line).
<> 144:ef7eb2e8f9f7 370 * The need to check half the total amount of cache is due to the fact that the cache consists of
<> 144:ef7eb2e8f9f7 371 * two ways and that line commands based on the physical address searches both ways.
<> 144:ef7eb2e8f9f7 372 * Push - Push a cache entry if it is valid and modified, then clear the modify bit. If
<> 144:ef7eb2e8f9f7 373 * the entry is not valid or not modified, leave as is. This action does not clear the valid
<> 144:ef7eb2e8f9f7 374 * bit. A cache push is synonymous with a cache flush.
<> 144:ef7eb2e8f9f7 375 *
<> 144:ef7eb2e8f9f7 376 * @param base LMEM peripheral base address.
<> 144:ef7eb2e8f9f7 377 * @param address The physical address of the cache line. Should be 16-byte aligned address.
<> 144:ef7eb2e8f9f7 378 * If not, it is changed to the 16-byte aligned memory address.
<> 144:ef7eb2e8f9f7 379 * @param length The length in bytes of the total amount of cache lines.
<> 144:ef7eb2e8f9f7 380 */
<> 144:ef7eb2e8f9f7 381 void LMEM_SystemCachePushMultiLines(LMEM_Type *base, uint32_t address, uint32_t length);
<> 144:ef7eb2e8f9f7 382
<> 144:ef7eb2e8f9f7 383 /*!
<> 144:ef7eb2e8f9f7 384 * @brief Clears a specific line in the processor system bus cache.
<> 144:ef7eb2e8f9f7 385 * This function clears a specific line based on the physical address passed in
<> 144:ef7eb2e8f9f7 386 * by the user.
<> 144:ef7eb2e8f9f7 387 * Clear - Push a cache entry if it is valid and modified, then clear the valid and
<> 144:ef7eb2e8f9f7 388 * modify bits. If the entry is not valid or not modified, clear the valid bit.
<> 144:ef7eb2e8f9f7 389 *
<> 144:ef7eb2e8f9f7 390 * @param base LMEM peripheral base address.
<> 144:ef7eb2e8f9f7 391 * @param address The physical address of the cache line. Should be 16-byte aligned address.
<> 144:ef7eb2e8f9f7 392 * If not, it is changed to the 16-byte aligned memory address.
<> 144:ef7eb2e8f9f7 393 */
<> 144:ef7eb2e8f9f7 394 void LMEM_SystemCacheClearLine(LMEM_Type *base, uint32_t address);
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 /*!
<> 144:ef7eb2e8f9f7 397 * @brief Clears multiple lines in the processor system bus cache.
<> 144:ef7eb2e8f9f7 398 * This function clears multiple lines in the cache
<> 144:ef7eb2e8f9f7 399 * based on the physical address and length in bytes passed in by the
<> 144:ef7eb2e8f9f7 400 * user. If the function detects that the length meets or exceeds half of the
<> 144:ef7eb2e8f9f7 401 * cache, the function performs an entire cache clear function (which is
<> 144:ef7eb2e8f9f7 402 * more efficient than clearing the lines in the cache line-by-line).
<> 144:ef7eb2e8f9f7 403 * The need to check half the total amount of cache is due to the fact that the cache consists of
<> 144:ef7eb2e8f9f7 404 * two ways and that line commands based on the physical address searches both ways.
<> 144:ef7eb2e8f9f7 405 * Clear - Push a cache entry if it is valid and modified, then clear the valid and
<> 144:ef7eb2e8f9f7 406 * modify bits. If the entry is not valid or not modified, clear the valid bit.
<> 144:ef7eb2e8f9f7 407 *
<> 144:ef7eb2e8f9f7 408 * @param base LMEM peripheral base address.
<> 144:ef7eb2e8f9f7 409 * @param address The physical address of the cache line. Should be 16-byte aligned address.
<> 144:ef7eb2e8f9f7 410 * If not, it is changed to the 16-byte aligned memory address.
<> 144:ef7eb2e8f9f7 411 * @param length The length in bytes of the total amount of cache lines.
<> 144:ef7eb2e8f9f7 412 */
<> 144:ef7eb2e8f9f7 413 void LMEM_SystemCacheClearMultiLines(LMEM_Type *base, uint32_t address, uint32_t length);
<> 144:ef7eb2e8f9f7 414
<> 144:ef7eb2e8f9f7 415 /*!
<> 144:ef7eb2e8f9f7 416 * @brief Demotes the cache mode of a region in the processor system bus cache.
<> 144:ef7eb2e8f9f7 417 * This function allows the user to demote the cache mode of a region within the device's
<> 144:ef7eb2e8f9f7 418 * memory map. Demoting the cache mode reduces the cache function applied to a memory
<> 144:ef7eb2e8f9f7 419 * region from write-back to write-through to non-cacheable. The function checks to see
<> 144:ef7eb2e8f9f7 420 * if the requested cache mode is higher than or equal to the current cache mode, and if
<> 144:ef7eb2e8f9f7 421 * so, returns an error. After a region is demoted, its cache mode can only be raised
<> 144:ef7eb2e8f9f7 422 * by a reset, which returns it to its default state which is the highest cache configure
<> 144:ef7eb2e8f9f7 423 * for each region.
<> 144:ef7eb2e8f9f7 424 * To maintain cache coherency, changes to the cache mode should be completed while the
<> 144:ef7eb2e8f9f7 425 * address space being changed is not being accessed or the cache is disabled. Before a
<> 144:ef7eb2e8f9f7 426 * cache mode change, this function completes a cache clear all command to push and invalidate any
<> 144:ef7eb2e8f9f7 427 * cache entries that may have changed.
<> 144:ef7eb2e8f9f7 428 *
<> 144:ef7eb2e8f9f7 429 * @param base LMEM peripheral base address.
<> 144:ef7eb2e8f9f7 430 * @param region The desired region to demote of type lmem_cache_region_t.
<> 144:ef7eb2e8f9f7 431 * @param cacheMode The new, demoted cache mode of type lmem_cache_mode_t.
<> 144:ef7eb2e8f9f7 432 * @return The execution result.
<> 144:ef7eb2e8f9f7 433 * kStatus_Success The cache demote operation is successful.
<> 144:ef7eb2e8f9f7 434 * kStatus_Fail The cache demote operation is failure.
<> 144:ef7eb2e8f9f7 435 */
<> 144:ef7eb2e8f9f7 436 status_t LMEM_SystemCacheDemoteRegion(LMEM_Type *base, lmem_cache_region_t region, lmem_cache_mode_t cacheMode);
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438 /*@}*/
<> 144:ef7eb2e8f9f7 439 #endif /* FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE */
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441 #if defined(__cplusplus)
<> 144:ef7eb2e8f9f7 442 }
<> 144:ef7eb2e8f9f7 443 #endif
<> 144:ef7eb2e8f9f7 444
<> 144:ef7eb2e8f9f7 445 /*! @}*/
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 #endif /* _FSL_LMEM_CACHE_H_*/