Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_ftm.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 144:ef7eb2e8f9f7 3 * All rights reserved.
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 6 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 9 * of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 12 * list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 13 * other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 144:ef7eb2e8f9f7 16 * contributors may be used to endorse or promote products derived from this
<> 144:ef7eb2e8f9f7 17 * software without specific prior written permission.
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 29 */
<> 144:ef7eb2e8f9f7 30 #ifndef _FSL_FTM_H_
<> 144:ef7eb2e8f9f7 31 #define _FSL_FTM_H_
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 #include "fsl_common.h"
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 /*!
<> 144:ef7eb2e8f9f7 36 * @addtogroup ftm
<> 144:ef7eb2e8f9f7 37 * @{
<> 144:ef7eb2e8f9f7 38 */
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 /*! @file */
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 /*******************************************************************************
<> 144:ef7eb2e8f9f7 43 * Definitions
<> 144:ef7eb2e8f9f7 44 ******************************************************************************/
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /*! @name Driver version */
<> 144:ef7eb2e8f9f7 47 /*@{*/
<> 144:ef7eb2e8f9f7 48 #define FSL_FTM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
<> 144:ef7eb2e8f9f7 49 /*@}*/
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 /*!
<> 144:ef7eb2e8f9f7 52 * @brief List of FTM channels
<> 144:ef7eb2e8f9f7 53 * @note Actual number of available channels is SoC dependent
<> 144:ef7eb2e8f9f7 54 */
<> 144:ef7eb2e8f9f7 55 typedef enum _ftm_chnl
<> 144:ef7eb2e8f9f7 56 {
<> 144:ef7eb2e8f9f7 57 kFTM_Chnl_0 = 0U, /*!< FTM channel number 0*/
<> 144:ef7eb2e8f9f7 58 kFTM_Chnl_1, /*!< FTM channel number 1 */
<> 144:ef7eb2e8f9f7 59 kFTM_Chnl_2, /*!< FTM channel number 2 */
<> 144:ef7eb2e8f9f7 60 kFTM_Chnl_3, /*!< FTM channel number 3 */
<> 144:ef7eb2e8f9f7 61 kFTM_Chnl_4, /*!< FTM channel number 4 */
<> 144:ef7eb2e8f9f7 62 kFTM_Chnl_5, /*!< FTM channel number 5 */
<> 144:ef7eb2e8f9f7 63 kFTM_Chnl_6, /*!< FTM channel number 6 */
<> 144:ef7eb2e8f9f7 64 kFTM_Chnl_7 /*!< FTM channel number 7 */
<> 144:ef7eb2e8f9f7 65 } ftm_chnl_t;
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 /*! @brief List of FTM faults */
<> 144:ef7eb2e8f9f7 68 typedef enum _ftm_fault_input
<> 144:ef7eb2e8f9f7 69 {
<> 144:ef7eb2e8f9f7 70 kFTM_Fault_0 = 0U, /*!< FTM fault 0 input pin */
<> 144:ef7eb2e8f9f7 71 kFTM_Fault_1, /*!< FTM fault 1 input pin */
<> 144:ef7eb2e8f9f7 72 kFTM_Fault_2, /*!< FTM fault 2 input pin */
<> 144:ef7eb2e8f9f7 73 kFTM_Fault_3 /*!< FTM fault 3 input pin */
<> 144:ef7eb2e8f9f7 74 } ftm_fault_input_t;
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 /*! @brief FTM PWM operation modes */
<> 144:ef7eb2e8f9f7 77 typedef enum _ftm_pwm_mode
<> 144:ef7eb2e8f9f7 78 {
<> 144:ef7eb2e8f9f7 79 kFTM_EdgeAlignedPwm = 0U, /*!< Edge-aligned PWM */
<> 144:ef7eb2e8f9f7 80 kFTM_CenterAlignedPwm, /*!< Center-aligned PWM */
<> 144:ef7eb2e8f9f7 81 kFTM_CombinedPwm /*!< Combined PWM */
<> 144:ef7eb2e8f9f7 82 } ftm_pwm_mode_t;
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 /*! @brief FTM PWM output pulse mode: high-true, low-true or no output */
<> 144:ef7eb2e8f9f7 85 typedef enum _ftm_pwm_level_select
<> 144:ef7eb2e8f9f7 86 {
<> 144:ef7eb2e8f9f7 87 kFTM_NoPwmSignal = 0U, /*!< No PWM output on pin */
<> 144:ef7eb2e8f9f7 88 kFTM_LowTrue, /*!< Low true pulses */
<> 144:ef7eb2e8f9f7 89 kFTM_HighTrue /*!< High true pulses */
<> 144:ef7eb2e8f9f7 90 } ftm_pwm_level_select_t;
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 /*! @brief Options to configure a FTM channel's PWM signal */
<> 144:ef7eb2e8f9f7 93 typedef struct _ftm_chnl_pwm_signal_param
<> 144:ef7eb2e8f9f7 94 {
<> 144:ef7eb2e8f9f7 95 ftm_chnl_t chnlNumber; /*!< The channel/channel pair number.
<> 144:ef7eb2e8f9f7 96 In combined mode, this represents the channel pair number. */
<> 144:ef7eb2e8f9f7 97 ftm_pwm_level_select_t level; /*!< PWM output active level select. */
<> 144:ef7eb2e8f9f7 98 uint8_t dutyCyclePercent; /*!< PWM pulse width, value should be between 0 to 100
<> 144:ef7eb2e8f9f7 99 0 = inactive signal(0% duty cycle)...
<> 144:ef7eb2e8f9f7 100 100 = always active signal (100% duty cycle).*/
<> 144:ef7eb2e8f9f7 101 uint8_t firstEdgeDelayPercent; /*!< Used only in combined PWM mode to generate an asymmetrical PWM.
<> 144:ef7eb2e8f9f7 102 Specifies the delay to the first edge in a PWM period.
<> 144:ef7eb2e8f9f7 103 If unsure leave as 0; Should be specified as a
<> 144:ef7eb2e8f9f7 104 percentage of the PWM period */
<> 144:ef7eb2e8f9f7 105 } ftm_chnl_pwm_signal_param_t;
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 /*! @brief FlexTimer output compare mode */
<> 144:ef7eb2e8f9f7 108 typedef enum _ftm_output_compare_mode
<> 144:ef7eb2e8f9f7 109 {
<> 144:ef7eb2e8f9f7 110 kFTM_NoOutputSignal = (1U << FTM_CnSC_MSA_SHIFT), /*!< No channel output when counter reaches CnV */
<> 144:ef7eb2e8f9f7 111 kFTM_ToggleOnMatch = ((1U << FTM_CnSC_MSA_SHIFT) | (1U << FTM_CnSC_ELSA_SHIFT)), /*!< Toggle output */
<> 144:ef7eb2e8f9f7 112 kFTM_ClearOnMatch = ((1U << FTM_CnSC_MSA_SHIFT) | (2U << FTM_CnSC_ELSA_SHIFT)), /*!< Clear output */
<> 144:ef7eb2e8f9f7 113 kFTM_SetOnMatch = ((1U << FTM_CnSC_MSA_SHIFT) | (3U << FTM_CnSC_ELSA_SHIFT)) /*!< Set output */
<> 144:ef7eb2e8f9f7 114 } ftm_output_compare_mode_t;
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 /*! @brief FlexTimer input capture edge */
<> 144:ef7eb2e8f9f7 117 typedef enum _ftm_input_capture_edge
<> 144:ef7eb2e8f9f7 118 {
<> 144:ef7eb2e8f9f7 119 kFTM_RisingEdge = (1U << FTM_CnSC_ELSA_SHIFT), /*!< Capture on rising edge only*/
<> 144:ef7eb2e8f9f7 120 kFTM_FallingEdge = (2U << FTM_CnSC_ELSA_SHIFT), /*!< Capture on falling edge only*/
<> 144:ef7eb2e8f9f7 121 kFTM_RiseAndFallEdge = (3U << FTM_CnSC_ELSA_SHIFT) /*!< Capture on rising or falling edge */
<> 144:ef7eb2e8f9f7 122 } ftm_input_capture_edge_t;
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 /*! @brief FlexTimer dual edge capture modes */
<> 144:ef7eb2e8f9f7 125 typedef enum _ftm_dual_edge_capture_mode
<> 144:ef7eb2e8f9f7 126 {
<> 144:ef7eb2e8f9f7 127 kFTM_OneShot = 0U, /*!< One-shot capture mode */
<> 144:ef7eb2e8f9f7 128 kFTM_Continuous = (1U << FTM_CnSC_MSA_SHIFT) /*!< Continuous capture mode */
<> 144:ef7eb2e8f9f7 129 } ftm_dual_edge_capture_mode_t;
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /*! @brief FlexTimer dual edge capture parameters */
<> 144:ef7eb2e8f9f7 132 typedef struct _ftm_dual_edge_capture_param
<> 144:ef7eb2e8f9f7 133 {
<> 144:ef7eb2e8f9f7 134 ftm_dual_edge_capture_mode_t mode; /*!< Dual Edge Capture mode */
<> 144:ef7eb2e8f9f7 135 ftm_input_capture_edge_t currChanEdgeMode; /*!< Input capture edge select for channel n */
<> 144:ef7eb2e8f9f7 136 ftm_input_capture_edge_t nextChanEdgeMode; /*!< Input capture edge select for channel n+1 */
<> 144:ef7eb2e8f9f7 137 } ftm_dual_edge_capture_param_t;
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 /*! @brief FlexTimer quadrature decode modes */
<> 144:ef7eb2e8f9f7 140 typedef enum _ftm_quad_decode_mode
<> 144:ef7eb2e8f9f7 141 {
<> 144:ef7eb2e8f9f7 142 kFTM_QuadPhaseEncode = 0U, /*!< Phase A and Phase B encoding mode */
<> 144:ef7eb2e8f9f7 143 kFTM_QuadCountAndDir /*!< Count and direction encoding mode */
<> 144:ef7eb2e8f9f7 144 } ftm_quad_decode_mode_t;
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 /*! @brief FlexTimer quadrature phase polarities */
<> 144:ef7eb2e8f9f7 147 typedef enum _ftm_phase_polarity
<> 144:ef7eb2e8f9f7 148 {
<> 144:ef7eb2e8f9f7 149 kFTM_QuadPhaseNormal = 0U, /*!< Phase input signal is not inverted */
<> 144:ef7eb2e8f9f7 150 kFTM_QuadPhaseInvert /*!< Phase input signal is inverted */
<> 144:ef7eb2e8f9f7 151 } ftm_phase_polarity_t;
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 /*! @brief FlexTimer quadrature decode phase parameters */
<> 144:ef7eb2e8f9f7 154 typedef struct _ftm_phase_param
<> 144:ef7eb2e8f9f7 155 {
<> 144:ef7eb2e8f9f7 156 bool enablePhaseFilter; /*!< True: enable phase filter; false: disable filter */
<> 144:ef7eb2e8f9f7 157 uint32_t phaseFilterVal; /*!< Filter value, used only if phase filter is enabled */
<> 144:ef7eb2e8f9f7 158 ftm_phase_polarity_t phasePolarity; /*!< Phase polarity */
<> 144:ef7eb2e8f9f7 159 } ftm_phase_params_t;
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 /*! @brief Structure is used to hold the parameters to configure a FTM fault */
<> 144:ef7eb2e8f9f7 162 typedef struct _ftm_fault_param
<> 144:ef7eb2e8f9f7 163 {
<> 144:ef7eb2e8f9f7 164 bool enableFaultInput; /*!< True: Fault input is enabled; false: Fault input is disabled */
<> 144:ef7eb2e8f9f7 165 bool faultLevel; /*!< True: Fault polarity is active low i.e., '0' indicates a fault;
<> 144:ef7eb2e8f9f7 166 False: Fault polarity is active high */
<> 144:ef7eb2e8f9f7 167 bool useFaultFilter; /*!< True: Use the filtered fault signal;
<> 144:ef7eb2e8f9f7 168 False: Use the direct path from fault input */
<> 144:ef7eb2e8f9f7 169 } ftm_fault_param_t;
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 /*! @brief FlexTimer pre-scaler factor for the dead time insertion*/
<> 144:ef7eb2e8f9f7 172 typedef enum _ftm_deadtime_prescale
<> 144:ef7eb2e8f9f7 173 {
<> 144:ef7eb2e8f9f7 174 kFTM_Deadtime_Prescale_1 = 1U, /*!< Divide by 1 */
<> 144:ef7eb2e8f9f7 175 kFTM_Deadtime_Prescale_4, /*!< Divide by 4 */
<> 144:ef7eb2e8f9f7 176 kFTM_Deadtime_Prescale_16 /*!< Divide by 16 */
<> 144:ef7eb2e8f9f7 177 } ftm_deadtime_prescale_t;
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 /*! @brief FlexTimer clock source selection*/
<> 144:ef7eb2e8f9f7 180 typedef enum _ftm_clock_source
<> 144:ef7eb2e8f9f7 181 {
<> 144:ef7eb2e8f9f7 182 kFTM_SystemClock = 1U, /*!< System clock selected */
<> 144:ef7eb2e8f9f7 183 kFTM_FixedClock, /*!< Fixed frequency clock */
<> 144:ef7eb2e8f9f7 184 kFTM_ExternalClock /*!< External clock */
<> 144:ef7eb2e8f9f7 185 } ftm_clock_source_t;
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 /*! @brief FlexTimer pre-scaler factor selection for the clock source*/
<> 144:ef7eb2e8f9f7 188 typedef enum _ftm_clock_prescale
<> 144:ef7eb2e8f9f7 189 {
<> 144:ef7eb2e8f9f7 190 kFTM_Prescale_Divide_1 = 0U, /*!< Divide by 1 */
<> 144:ef7eb2e8f9f7 191 kFTM_Prescale_Divide_2, /*!< Divide by 2 */
<> 144:ef7eb2e8f9f7 192 kFTM_Prescale_Divide_4, /*!< Divide by 4 */
<> 144:ef7eb2e8f9f7 193 kFTM_Prescale_Divide_8, /*!< Divide by 8 */
<> 144:ef7eb2e8f9f7 194 kFTM_Prescale_Divide_16, /*!< Divide by 16 */
<> 144:ef7eb2e8f9f7 195 kFTM_Prescale_Divide_32, /*!< Divide by 32 */
<> 144:ef7eb2e8f9f7 196 kFTM_Prescale_Divide_64, /*!< Divide by 64 */
<> 144:ef7eb2e8f9f7 197 kFTM_Prescale_Divide_128 /*!< Divide by 128 */
<> 144:ef7eb2e8f9f7 198 } ftm_clock_prescale_t;
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 /*! @brief Options for the FlexTimer behaviour in BDM Mode */
<> 144:ef7eb2e8f9f7 201 typedef enum _ftm_bdm_mode
<> 144:ef7eb2e8f9f7 202 {
<> 144:ef7eb2e8f9f7 203 kFTM_BdmMode_0 = 0U,
<> 144:ef7eb2e8f9f7 204 /*!< FTM counter stopped, CH(n)F bit can be set, FTM channels in functional mode, writes to MOD,CNTIN and C(n)V
<> 144:ef7eb2e8f9f7 205 registers bypass the register buffers */
<> 144:ef7eb2e8f9f7 206 kFTM_BdmMode_1,
<> 144:ef7eb2e8f9f7 207 /*!< FTM counter stopped, CH(n)F bit is not set, FTM channels outputs are forced to their safe value , writes to
<> 144:ef7eb2e8f9f7 208 MOD,CNTIN and C(n)V registers bypass the register buffers */
<> 144:ef7eb2e8f9f7 209 kFTM_BdmMode_2,
<> 144:ef7eb2e8f9f7 210 /*!< FTM counter stopped, CH(n)F bit is not set, FTM channels outputs are frozen when chip enters in BDM mode,
<> 144:ef7eb2e8f9f7 211 writes to MOD,CNTIN and C(n)V registers bypass the register buffers */
<> 144:ef7eb2e8f9f7 212 kFTM_BdmMode_3
<> 144:ef7eb2e8f9f7 213 /*!< FTM counter in functional mode, CH(n)F bit can be set, FTM channels in functional mode, writes to MOD,CNTIN and
<> 144:ef7eb2e8f9f7 214 C(n)V registers is in fully functional mode */
<> 144:ef7eb2e8f9f7 215 } ftm_bdm_mode_t;
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 /*! @brief Options for the FTM fault control mode */
<> 144:ef7eb2e8f9f7 218 typedef enum _ftm_fault_mode
<> 144:ef7eb2e8f9f7 219 {
<> 144:ef7eb2e8f9f7 220 kFTM_Fault_Disable = 0U, /*!< Fault control is disabled for all channels */
<> 144:ef7eb2e8f9f7 221 kFTM_Fault_EvenChnls, /*!< Enabled for even channels only(0,2,4,6) with manual fault clearing */
<> 144:ef7eb2e8f9f7 222 kFTM_Fault_AllChnlsMan, /*!< Enabled for all channels with manual fault clearing */
<> 144:ef7eb2e8f9f7 223 kFTM_Fault_AllChnlsAuto /*!< Enabled for all channels with automatic fault clearing */
<> 144:ef7eb2e8f9f7 224 } ftm_fault_mode_t;
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 /*!
<> 144:ef7eb2e8f9f7 227 * @brief FTM external trigger options
<> 144:ef7eb2e8f9f7 228 * @note Actual available external trigger sources are SoC-specific
<> 144:ef7eb2e8f9f7 229 */
<> 144:ef7eb2e8f9f7 230 typedef enum _ftm_external_trigger
<> 144:ef7eb2e8f9f7 231 {
<> 144:ef7eb2e8f9f7 232 kFTM_Chnl0Trigger = (1U << 4), /*!< Generate trigger when counter equals chnl 0 CnV reg */
<> 144:ef7eb2e8f9f7 233 kFTM_Chnl1Trigger = (1U << 5), /*!< Generate trigger when counter equals chnl 1 CnV reg */
<> 144:ef7eb2e8f9f7 234 kFTM_Chnl2Trigger = (1U << 0), /*!< Generate trigger when counter equals chnl 2 CnV reg */
<> 144:ef7eb2e8f9f7 235 kFTM_Chnl3Trigger = (1U << 1), /*!< Generate trigger when counter equals chnl 3 CnV reg */
<> 144:ef7eb2e8f9f7 236 kFTM_Chnl4Trigger = (1U << 2), /*!< Generate trigger when counter equals chnl 4 CnV reg */
<> 144:ef7eb2e8f9f7 237 kFTM_Chnl5Trigger = (1U << 3), /*!< Generate trigger when counter equals chnl 5 CnV reg */
<> 144:ef7eb2e8f9f7 238 kFTM_Chnl6Trigger =
<> 144:ef7eb2e8f9f7 239 (1U << 8), /*!< Available on certain SoC's, generate trigger when counter equals chnl 6 CnV reg */
<> 144:ef7eb2e8f9f7 240 kFTM_Chnl7Trigger =
<> 144:ef7eb2e8f9f7 241 (1U << 9), /*!< Available on certain SoC's, generate trigger when counter equals chnl 7 CnV reg */
<> 144:ef7eb2e8f9f7 242 kFTM_InitTrigger = (1U << 6), /*!< Generate Trigger when counter is updated with CNTIN */
<> 144:ef7eb2e8f9f7 243 kFTM_ReloadInitTrigger = (1U << 7) /*!< Available on certain SoC's, trigger on reload point */
<> 144:ef7eb2e8f9f7 244 } ftm_external_trigger_t;
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 /*! @brief FlexTimer PWM sync options to update registers with buffer */
<> 144:ef7eb2e8f9f7 247 typedef enum _ftm_pwm_sync_method
<> 144:ef7eb2e8f9f7 248 {
<> 144:ef7eb2e8f9f7 249 kFTM_SoftwareTrigger = FTM_SYNC_SWSYNC_MASK, /*!< Software triggers PWM sync */
<> 144:ef7eb2e8f9f7 250 kFTM_HardwareTrigger_0 = FTM_SYNC_TRIG0_MASK, /*!< Hardware trigger 0 causes PWM sync */
<> 144:ef7eb2e8f9f7 251 kFTM_HardwareTrigger_1 = FTM_SYNC_TRIG1_MASK, /*!< Hardware trigger 1 causes PWM sync */
<> 144:ef7eb2e8f9f7 252 kFTM_HardwareTrigger_2 = FTM_SYNC_TRIG2_MASK /*!< Hardware trigger 2 causes PWM sync */
<> 144:ef7eb2e8f9f7 253 } ftm_pwm_sync_method_t;
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 /*!
<> 144:ef7eb2e8f9f7 256 * @brief FTM options available as loading point for register reload
<> 144:ef7eb2e8f9f7 257 * @note Actual available reload points are SoC-specific
<> 144:ef7eb2e8f9f7 258 */
<> 144:ef7eb2e8f9f7 259 typedef enum _ftm_reload_point
<> 144:ef7eb2e8f9f7 260 {
<> 144:ef7eb2e8f9f7 261 kFTM_Chnl0Match = (1U << 0), /*!< Channel 0 match included as a reload point */
<> 144:ef7eb2e8f9f7 262 kFTM_Chnl1Match = (1U << 1), /*!< Channel 1 match included as a reload point */
<> 144:ef7eb2e8f9f7 263 kFTM_Chnl2Match = (1U << 2), /*!< Channel 2 match included as a reload point */
<> 144:ef7eb2e8f9f7 264 kFTM_Chnl3Match = (1U << 3), /*!< Channel 3 match included as a reload point */
<> 144:ef7eb2e8f9f7 265 kFTM_Chnl4Match = (1U << 4), /*!< Channel 4 match included as a reload point */
<> 144:ef7eb2e8f9f7 266 kFTM_Chnl5Match = (1U << 5), /*!< Channel 5 match included as a reload point */
<> 144:ef7eb2e8f9f7 267 kFTM_Chnl6Match = (1U << 6), /*!< Channel 6 match included as a reload point */
<> 144:ef7eb2e8f9f7 268 kFTM_Chnl7Match = (1U << 7), /*!< Channel 7 match included as a reload point */
<> 144:ef7eb2e8f9f7 269 kFTM_CntMax = (1U << 8), /*!< Use in up-down count mode only, reload when counter reaches the maximum value */
<> 144:ef7eb2e8f9f7 270 kFTM_CntMin = (1U << 9), /*!< Use in up-down count mode only, reload when counter reaches the minimum value */
<> 144:ef7eb2e8f9f7 271 kFTM_HalfCycMatch = (1U << 10) /*!< Available on certain SoC's, half cycle match reload point */
<> 144:ef7eb2e8f9f7 272 } ftm_reload_point_t;
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 /*!
<> 144:ef7eb2e8f9f7 275 * @brief List of FTM interrupts
<> 144:ef7eb2e8f9f7 276 * @note Actual available interrupts are SoC-specific
<> 144:ef7eb2e8f9f7 277 */
<> 144:ef7eb2e8f9f7 278 typedef enum _ftm_interrupt_enable
<> 144:ef7eb2e8f9f7 279 {
<> 144:ef7eb2e8f9f7 280 kFTM_Chnl0InterruptEnable = (1U << 0), /*!< Channel 0 interrupt */
<> 144:ef7eb2e8f9f7 281 kFTM_Chnl1InterruptEnable = (1U << 1), /*!< Channel 1 interrupt */
<> 144:ef7eb2e8f9f7 282 kFTM_Chnl2InterruptEnable = (1U << 2), /*!< Channel 2 interrupt */
<> 144:ef7eb2e8f9f7 283 kFTM_Chnl3InterruptEnable = (1U << 3), /*!< Channel 3 interrupt */
<> 144:ef7eb2e8f9f7 284 kFTM_Chnl4InterruptEnable = (1U << 4), /*!< Channel 4 interrupt */
<> 144:ef7eb2e8f9f7 285 kFTM_Chnl5InterruptEnable = (1U << 5), /*!< Channel 5 interrupt */
<> 144:ef7eb2e8f9f7 286 kFTM_Chnl6InterruptEnable = (1U << 6), /*!< Channel 6 interrupt */
<> 144:ef7eb2e8f9f7 287 kFTM_Chnl7InterruptEnable = (1U << 7), /*!< Channel 7 interrupt */
<> 144:ef7eb2e8f9f7 288 kFTM_FaultInterruptEnable = (1U << 8), /*!< Fault interrupt */
<> 144:ef7eb2e8f9f7 289 kFTM_TimeOverflowInterruptEnable = (1U << 9), /*!< Time overflow interrupt */
<> 144:ef7eb2e8f9f7 290 kFTM_ReloadInterruptEnable = (1U << 10) /*!< Reload interrupt; Available only on certain SoC's */
<> 144:ef7eb2e8f9f7 291 } ftm_interrupt_enable_t;
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 /*!
<> 144:ef7eb2e8f9f7 294 * @brief List of FTM flags
<> 144:ef7eb2e8f9f7 295 * @note Actual available flags are SoC-specific
<> 144:ef7eb2e8f9f7 296 */
<> 144:ef7eb2e8f9f7 297 typedef enum _ftm_status_flags
<> 144:ef7eb2e8f9f7 298 {
<> 144:ef7eb2e8f9f7 299 kFTM_Chnl0Flag = (1U << 0), /*!< Channel 0 Flag */
<> 144:ef7eb2e8f9f7 300 kFTM_Chnl1Flag = (1U << 1), /*!< Channel 1 Flag */
<> 144:ef7eb2e8f9f7 301 kFTM_Chnl2Flag = (1U << 2), /*!< Channel 2 Flag */
<> 144:ef7eb2e8f9f7 302 kFTM_Chnl3Flag = (1U << 3), /*!< Channel 3 Flag */
<> 144:ef7eb2e8f9f7 303 kFTM_Chnl4Flag = (1U << 4), /*!< Channel 4 Flag */
<> 144:ef7eb2e8f9f7 304 kFTM_Chnl5Flag = (1U << 5), /*!< Channel 5 Flag */
<> 144:ef7eb2e8f9f7 305 kFTM_Chnl6Flag = (1U << 6), /*!< Channel 6 Flag */
<> 144:ef7eb2e8f9f7 306 kFTM_Chnl7Flag = (1U << 7), /*!< Channel 7 Flag */
<> 144:ef7eb2e8f9f7 307 kFTM_FaultFlag = (1U << 8), /*!< Fault Flag */
<> 144:ef7eb2e8f9f7 308 kFTM_TimeOverflowFlag = (1U << 9), /*!< Time overflow Flag */
<> 144:ef7eb2e8f9f7 309 kFTM_ChnlTriggerFlag = (1U << 10), /*!< Channel trigger Flag */
<> 144:ef7eb2e8f9f7 310 kFTM_ReloadFlag = (1U << 11) /*!< Reload Flag; Available only on certain SoC's */
<> 144:ef7eb2e8f9f7 311 } ftm_status_flags_t;
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 /*!
<> 144:ef7eb2e8f9f7 314 * @brief FTM configuration structure
<> 144:ef7eb2e8f9f7 315 *
<> 144:ef7eb2e8f9f7 316 * This structure holds the configuration settings for the FTM peripheral. To initialize this
<> 144:ef7eb2e8f9f7 317 * structure to reasonable defaults, call the FTM_GetDefaultConfig() function and pass a
<> 144:ef7eb2e8f9f7 318 * pointer to the configuration structure instance.
<> 144:ef7eb2e8f9f7 319 *
<> 144:ef7eb2e8f9f7 320 * The configuration structure can be made constant so as to reside in flash.
<> 144:ef7eb2e8f9f7 321 */
<> 144:ef7eb2e8f9f7 322 typedef struct _ftm_config
<> 144:ef7eb2e8f9f7 323 {
<> 144:ef7eb2e8f9f7 324 ftm_clock_prescale_t prescale; /*!< FTM clock prescale value */
<> 144:ef7eb2e8f9f7 325 ftm_bdm_mode_t bdmMode; /*!< FTM behavior in BDM mode */
<> 144:ef7eb2e8f9f7 326 uint32_t pwmSyncMode; /*!< Synchronization methods to use to update buffered registers; Multiple
<> 144:ef7eb2e8f9f7 327 update modes can be used by providing an OR'ed list of options
<> 144:ef7eb2e8f9f7 328 available in enumeration ::ftm_pwm_sync_method_t. */
<> 144:ef7eb2e8f9f7 329 uint32_t reloadPoints; /*!< FTM reload points; When using this, the PWM
<> 144:ef7eb2e8f9f7 330 synchronization is not required. Multiple reload points can be used by providing
<> 144:ef7eb2e8f9f7 331 an OR'ed list of options available in
<> 144:ef7eb2e8f9f7 332 enumeration ::ftm_reload_point_t. */
<> 144:ef7eb2e8f9f7 333 ftm_fault_mode_t faultMode; /*!< FTM fault control mode */
<> 144:ef7eb2e8f9f7 334 uint8_t faultFilterValue; /*!< Fault input filter value */
<> 144:ef7eb2e8f9f7 335 ftm_deadtime_prescale_t deadTimePrescale; /*!< The dead time prescalar value */
<> 144:ef7eb2e8f9f7 336 uint8_t deadTimeValue; /*!< The dead time value */
<> 144:ef7eb2e8f9f7 337 uint32_t extTriggers; /*!< External triggers to enable. Multiple trigger sources can be
<> 144:ef7eb2e8f9f7 338 enabled by providing an OR'ed list of options available in
<> 144:ef7eb2e8f9f7 339 enumeration ::ftm_external_trigger_t. */
<> 144:ef7eb2e8f9f7 340 uint8_t chnlInitState; /*!< Defines the initialization value of the channels in OUTINT register */
<> 144:ef7eb2e8f9f7 341 uint8_t chnlPolarity; /*!< Defines the output polarity of the channels in POL register */
<> 144:ef7eb2e8f9f7 342 bool useGlobalTimeBase; /*!< True: Use of an external global time base is enabled;
<> 144:ef7eb2e8f9f7 343 False: disabled */
<> 144:ef7eb2e8f9f7 344 } ftm_config_t;
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 /*******************************************************************************
<> 144:ef7eb2e8f9f7 347 * API
<> 144:ef7eb2e8f9f7 348 ******************************************************************************/
<> 144:ef7eb2e8f9f7 349
<> 144:ef7eb2e8f9f7 350 #if defined(__cplusplus)
<> 144:ef7eb2e8f9f7 351 extern "C" {
<> 144:ef7eb2e8f9f7 352 #endif
<> 144:ef7eb2e8f9f7 353
<> 144:ef7eb2e8f9f7 354 /*!
<> 144:ef7eb2e8f9f7 355 * @name Initialization and deinitialization
<> 144:ef7eb2e8f9f7 356 * @{
<> 144:ef7eb2e8f9f7 357 */
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 /*!
<> 144:ef7eb2e8f9f7 360 * @brief Ungates the FTM clock and configures the peripheral for basic operation.
<> 144:ef7eb2e8f9f7 361 *
<> 144:ef7eb2e8f9f7 362 * @note This API should be called at the beginning of the application using the FTM driver.
<> 144:ef7eb2e8f9f7 363 *
<> 144:ef7eb2e8f9f7 364 * @param base FTM peripheral base address
<> 144:ef7eb2e8f9f7 365 * @param config Pointer to the user configuration structure.
<> 144:ef7eb2e8f9f7 366 *
<> 144:ef7eb2e8f9f7 367 * @return kStatus_Success indicates success; Else indicates failure.
<> 144:ef7eb2e8f9f7 368 */
<> 144:ef7eb2e8f9f7 369 status_t FTM_Init(FTM_Type *base, const ftm_config_t *config);
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 /*!
<> 144:ef7eb2e8f9f7 372 * @brief Gates the FTM clock.
<> 144:ef7eb2e8f9f7 373 *
<> 144:ef7eb2e8f9f7 374 * @param base FTM peripheral base address
<> 144:ef7eb2e8f9f7 375 */
<> 144:ef7eb2e8f9f7 376 void FTM_Deinit(FTM_Type *base);
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 /*!
<> 144:ef7eb2e8f9f7 379 * @brief Fills in the FTM configuration structure with the default settings.
<> 144:ef7eb2e8f9f7 380 *
<> 144:ef7eb2e8f9f7 381 * The default values are:
<> 144:ef7eb2e8f9f7 382 * @code
<> 144:ef7eb2e8f9f7 383 * config->prescale = kFTM_Prescale_Divide_1;
<> 144:ef7eb2e8f9f7 384 * config->bdmMode = kFTM_BdmMode_0;
<> 144:ef7eb2e8f9f7 385 * config->pwmSyncMode = kFTM_SoftwareTrigger;
<> 144:ef7eb2e8f9f7 386 * config->reloadPoints = 0;
<> 144:ef7eb2e8f9f7 387 * config->faultMode = kFTM_Fault_Disable;
<> 144:ef7eb2e8f9f7 388 * config->faultFilterValue = 0;
<> 144:ef7eb2e8f9f7 389 * config->deadTimePrescale = kFTM_Deadtime_Prescale_1;
<> 144:ef7eb2e8f9f7 390 * config->deadTimeValue = 0;
<> 144:ef7eb2e8f9f7 391 * config->extTriggers = 0;
<> 144:ef7eb2e8f9f7 392 * config->chnlInitState = 0;
<> 144:ef7eb2e8f9f7 393 * config->chnlPolarity = 0;
<> 144:ef7eb2e8f9f7 394 * config->useGlobalTimeBase = false;
<> 144:ef7eb2e8f9f7 395 * @endcode
<> 144:ef7eb2e8f9f7 396 * @param config Pointer to the user configuration structure.
<> 144:ef7eb2e8f9f7 397 */
<> 144:ef7eb2e8f9f7 398 void FTM_GetDefaultConfig(ftm_config_t *config);
<> 144:ef7eb2e8f9f7 399
<> 144:ef7eb2e8f9f7 400 /*! @}*/
<> 144:ef7eb2e8f9f7 401
<> 144:ef7eb2e8f9f7 402 /*!
<> 144:ef7eb2e8f9f7 403 * @name Channel mode operations
<> 144:ef7eb2e8f9f7 404 * @{
<> 144:ef7eb2e8f9f7 405 */
<> 144:ef7eb2e8f9f7 406
<> 144:ef7eb2e8f9f7 407 /*!
<> 144:ef7eb2e8f9f7 408 * @brief Configures the PWM signal parameters.
<> 144:ef7eb2e8f9f7 409 *
<> 144:ef7eb2e8f9f7 410 * Call this function to configure the PWM signal period, mode, duty cycle, and edge. Use this
<> 144:ef7eb2e8f9f7 411 * function to configure all FTM channels that are used to output a PWM signal.
<> 144:ef7eb2e8f9f7 412 *
<> 144:ef7eb2e8f9f7 413 * @param base FTM peripheral base address
<> 144:ef7eb2e8f9f7 414 * @param chnlParams Array of PWM channel parameters to configure the channel(s)
<> 144:ef7eb2e8f9f7 415 * @param numOfChnls Number of channels to configure; This should be the size of the array passed in
<> 144:ef7eb2e8f9f7 416 * @param mode PWM operation mode, options available in enumeration ::ftm_pwm_mode_t
<> 144:ef7eb2e8f9f7 417 * @param pwmFreq_Hz PWM signal frequency in Hz
<> 144:ef7eb2e8f9f7 418 * @param srcClock_Hz FTM counter clock in Hz
<> 144:ef7eb2e8f9f7 419 *
<> 144:ef7eb2e8f9f7 420 * @return kStatus_Success if the PWM setup was successful
<> 144:ef7eb2e8f9f7 421 * kStatus_Error on failure
<> 144:ef7eb2e8f9f7 422 */
<> 144:ef7eb2e8f9f7 423 status_t FTM_SetupPwm(FTM_Type *base,
<> 144:ef7eb2e8f9f7 424 const ftm_chnl_pwm_signal_param_t *chnlParams,
<> 144:ef7eb2e8f9f7 425 uint8_t numOfChnls,
<> 144:ef7eb2e8f9f7 426 ftm_pwm_mode_t mode,
<> 144:ef7eb2e8f9f7 427 uint32_t pwmFreq_Hz,
<> 144:ef7eb2e8f9f7 428 uint32_t srcClock_Hz);
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430 /*!
<> 144:ef7eb2e8f9f7 431 * @brief Updates the duty cycle of an active PWM signal.
<> 144:ef7eb2e8f9f7 432 *
<> 144:ef7eb2e8f9f7 433 * @param base FTM peripheral base address
<> 144:ef7eb2e8f9f7 434 * @param chnlNumber The channel/channel pair number. In combined mode, this represents
<> 144:ef7eb2e8f9f7 435 * the channel pair number
<> 144:ef7eb2e8f9f7 436 * @param currentPwmMode The current PWM mode set during PWM setup
<> 144:ef7eb2e8f9f7 437 * @param dutyCyclePercent New PWM pulse width; The value should be between 0 to 100
<> 144:ef7eb2e8f9f7 438 * 0=inactive signal(0% duty cycle)...
<> 144:ef7eb2e8f9f7 439 * 100=active signal (100% duty cycle)
<> 144:ef7eb2e8f9f7 440 */
<> 144:ef7eb2e8f9f7 441 void FTM_UpdatePwmDutycycle(FTM_Type *base,
<> 144:ef7eb2e8f9f7 442 ftm_chnl_t chnlNumber,
<> 144:ef7eb2e8f9f7 443 ftm_pwm_mode_t currentPwmMode,
<> 144:ef7eb2e8f9f7 444 uint8_t dutyCyclePercent);
<> 144:ef7eb2e8f9f7 445
<> 144:ef7eb2e8f9f7 446 /*!
<> 144:ef7eb2e8f9f7 447 * @brief Updates the edge level selection for a channel.
<> 144:ef7eb2e8f9f7 448 *
<> 144:ef7eb2e8f9f7 449 * @param base FTM peripheral base address
<> 144:ef7eb2e8f9f7 450 * @param chnlNumber The channel number
<> 144:ef7eb2e8f9f7 451 * @param level The level to be set to the ELSnB:ELSnA field; Valid values are 00, 01, 10, 11.
<> 144:ef7eb2e8f9f7 452 * See the Kinetis SoC reference manual for details about this field.
<> 144:ef7eb2e8f9f7 453 */
<> 144:ef7eb2e8f9f7 454 void FTM_UpdateChnlEdgeLevelSelect(FTM_Type *base, ftm_chnl_t chnlNumber, uint8_t level);
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 /*!
<> 144:ef7eb2e8f9f7 457 * @brief Enables capturing an input signal on the channel using the function parameters.
<> 144:ef7eb2e8f9f7 458 *
<> 144:ef7eb2e8f9f7 459 * When the edge specified in the captureMode argument occurs on the channel, the FTM counter is
<> 144:ef7eb2e8f9f7 460 * captured into the CnV register. The user has to read the CnV register separately to get this
<> 144:ef7eb2e8f9f7 461 * value. The filter function is disabled if the filterVal argument passed in is 0. The filter
<> 144:ef7eb2e8f9f7 462 * function is available only for channels 0, 1, 2, 3.
<> 144:ef7eb2e8f9f7 463 *
<> 144:ef7eb2e8f9f7 464 * @param base FTM peripheral base address
<> 144:ef7eb2e8f9f7 465 * @param chnlNumber The channel number
<> 144:ef7eb2e8f9f7 466 * @param captureMode Specifies which edge to capture
<> 144:ef7eb2e8f9f7 467 * @param filterValue Filter value, specify 0 to disable filter. Available only for channels 0-3.
<> 144:ef7eb2e8f9f7 468 */
<> 144:ef7eb2e8f9f7 469 void FTM_SetupInputCapture(FTM_Type *base,
<> 144:ef7eb2e8f9f7 470 ftm_chnl_t chnlNumber,
<> 144:ef7eb2e8f9f7 471 ftm_input_capture_edge_t captureMode,
<> 144:ef7eb2e8f9f7 472 uint32_t filterValue);
<> 144:ef7eb2e8f9f7 473
<> 144:ef7eb2e8f9f7 474 /*!
<> 144:ef7eb2e8f9f7 475 * @brief Configures the FTM to generate timed pulses.
<> 144:ef7eb2e8f9f7 476 *
<> 144:ef7eb2e8f9f7 477 * When the FTM counter matches the value of compareVal argument (this is written into CnV reg),
<> 144:ef7eb2e8f9f7 478 * the channel output is changed based on what is specified in the compareMode argument.
<> 144:ef7eb2e8f9f7 479 *
<> 144:ef7eb2e8f9f7 480 * @param base FTM peripheral base address
<> 144:ef7eb2e8f9f7 481 * @param chnlNumber The channel number
<> 144:ef7eb2e8f9f7 482 * @param compareMode Action to take on the channel output when the compare condition is met
<> 144:ef7eb2e8f9f7 483 * @param compareValue Value to be programmed in the CnV register.
<> 144:ef7eb2e8f9f7 484 */
<> 144:ef7eb2e8f9f7 485 void FTM_SetupOutputCompare(FTM_Type *base,
<> 144:ef7eb2e8f9f7 486 ftm_chnl_t chnlNumber,
<> 144:ef7eb2e8f9f7 487 ftm_output_compare_mode_t compareMode,
<> 144:ef7eb2e8f9f7 488 uint32_t compareValue);
<> 144:ef7eb2e8f9f7 489
<> 144:ef7eb2e8f9f7 490 /*!
<> 144:ef7eb2e8f9f7 491 * @brief Configures the dual edge capture mode of the FTM.
<> 144:ef7eb2e8f9f7 492 *
<> 144:ef7eb2e8f9f7 493 * This function sets up the dual edge capture mode on a channel pair. The capture edge for the
<> 144:ef7eb2e8f9f7 494 * channel pair and the capture mode (one-shot or continuous) is specified in the parameter
<> 144:ef7eb2e8f9f7 495 * argument. The filter function is disabled if the filterVal argument passed is zero. The filter
<> 144:ef7eb2e8f9f7 496 * function is available only on channels 0 and 2. The user has to read the channel CnV registers
<> 144:ef7eb2e8f9f7 497 * separately to get the capture values.
<> 144:ef7eb2e8f9f7 498 *
<> 144:ef7eb2e8f9f7 499 * @param base FTM peripheral base address
<> 144:ef7eb2e8f9f7 500 * @param chnlPairNumber The FTM channel pair number; options are 0, 1, 2, 3
<> 144:ef7eb2e8f9f7 501 * @param edgeParam Sets up the dual edge capture function
<> 144:ef7eb2e8f9f7 502 * @param filterValue Filter value, specify 0 to disable filter. Available only for channel pair 0 and 1.
<> 144:ef7eb2e8f9f7 503 */
<> 144:ef7eb2e8f9f7 504 void FTM_SetupDualEdgeCapture(FTM_Type *base,
<> 144:ef7eb2e8f9f7 505 ftm_chnl_t chnlPairNumber,
<> 144:ef7eb2e8f9f7 506 const ftm_dual_edge_capture_param_t *edgeParam,
<> 144:ef7eb2e8f9f7 507 uint32_t filterValue);
<> 144:ef7eb2e8f9f7 508
<> 144:ef7eb2e8f9f7 509 /*! @}*/
<> 144:ef7eb2e8f9f7 510
<> 144:ef7eb2e8f9f7 511 /*!
<> 144:ef7eb2e8f9f7 512 * @brief Configures the parameters and activates the quadrature decoder mode.
<> 144:ef7eb2e8f9f7 513 *
<> 144:ef7eb2e8f9f7 514 * @param base FTM peripheral base address
<> 144:ef7eb2e8f9f7 515 * @param phaseAParams Phase A configuration parameters
<> 144:ef7eb2e8f9f7 516 * @param phaseBParams Phase B configuration parameters
<> 144:ef7eb2e8f9f7 517 * @param quadMode Selects encoding mode used in quadrature decoder mode
<> 144:ef7eb2e8f9f7 518 */
<> 144:ef7eb2e8f9f7 519 void FTM_SetupQuadDecode(FTM_Type *base,
<> 144:ef7eb2e8f9f7 520 const ftm_phase_params_t *phaseAParams,
<> 144:ef7eb2e8f9f7 521 const ftm_phase_params_t *phaseBParams,
<> 144:ef7eb2e8f9f7 522 ftm_quad_decode_mode_t quadMode);
<> 144:ef7eb2e8f9f7 523
<> 144:ef7eb2e8f9f7 524 /*!
<> 144:ef7eb2e8f9f7 525 * @brief Sets up the working of the FTM fault protection.
<> 144:ef7eb2e8f9f7 526 *
<> 144:ef7eb2e8f9f7 527 * FTM can have up to 4 fault inputs. This function sets up fault parameters, fault level, and a filter.
<> 144:ef7eb2e8f9f7 528 *
<> 144:ef7eb2e8f9f7 529 * @param base FTM peripheral base address
<> 144:ef7eb2e8f9f7 530 * @param faultNumber FTM fault to configure.
<> 144:ef7eb2e8f9f7 531 * @param faultParams Parameters passed in to set up the fault
<> 144:ef7eb2e8f9f7 532 */
<> 144:ef7eb2e8f9f7 533 void FTM_SetupFault(FTM_Type *base, ftm_fault_input_t faultNumber, const ftm_fault_param_t *faultParams);
<> 144:ef7eb2e8f9f7 534
<> 144:ef7eb2e8f9f7 535 /*!
<> 144:ef7eb2e8f9f7 536 * @name Interrupt Interface
<> 144:ef7eb2e8f9f7 537 * @{
<> 144:ef7eb2e8f9f7 538 */
<> 144:ef7eb2e8f9f7 539
<> 144:ef7eb2e8f9f7 540 /*!
<> 144:ef7eb2e8f9f7 541 * @brief Enables the selected FTM interrupts.
<> 144:ef7eb2e8f9f7 542 *
<> 144:ef7eb2e8f9f7 543 * @param base FTM peripheral base address
<> 144:ef7eb2e8f9f7 544 * @param mask The interrupts to enable. This is a logical OR of members of the
<> 144:ef7eb2e8f9f7 545 * enumeration ::ftm_interrupt_enable_t
<> 144:ef7eb2e8f9f7 546 */
<> 144:ef7eb2e8f9f7 547 void FTM_EnableInterrupts(FTM_Type *base, uint32_t mask);
<> 144:ef7eb2e8f9f7 548
<> 144:ef7eb2e8f9f7 549 /*!
<> 144:ef7eb2e8f9f7 550 * @brief Disables the selected FTM interrupts.
<> 144:ef7eb2e8f9f7 551 *
<> 144:ef7eb2e8f9f7 552 * @param base FTM peripheral base address
<> 144:ef7eb2e8f9f7 553 * @param mask The interrupts to enable. This is a logical OR of members of the
<> 144:ef7eb2e8f9f7 554 * enumeration ::ftm_interrupt_enable_t
<> 144:ef7eb2e8f9f7 555 */
<> 144:ef7eb2e8f9f7 556 void FTM_DisableInterrupts(FTM_Type *base, uint32_t mask);
<> 144:ef7eb2e8f9f7 557
<> 144:ef7eb2e8f9f7 558 /*!
<> 144:ef7eb2e8f9f7 559 * @brief Gets the enabled FTM interrupts.
<> 144:ef7eb2e8f9f7 560 *
<> 144:ef7eb2e8f9f7 561 * @param base FTM peripheral base address
<> 144:ef7eb2e8f9f7 562 *
<> 144:ef7eb2e8f9f7 563 * @return The enabled interrupts. This is the logical OR of members of the
<> 144:ef7eb2e8f9f7 564 * enumeration ::ftm_interrupt_enable_t
<> 144:ef7eb2e8f9f7 565 */
<> 144:ef7eb2e8f9f7 566 uint32_t FTM_GetEnabledInterrupts(FTM_Type *base);
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568 /*! @}*/
<> 144:ef7eb2e8f9f7 569
<> 144:ef7eb2e8f9f7 570 /*!
<> 144:ef7eb2e8f9f7 571 * @name Status Interface
<> 144:ef7eb2e8f9f7 572 * @{
<> 144:ef7eb2e8f9f7 573 */
<> 144:ef7eb2e8f9f7 574
<> 144:ef7eb2e8f9f7 575 /*!
<> 144:ef7eb2e8f9f7 576 * @brief Gets the FTM status flags.
<> 144:ef7eb2e8f9f7 577 *
<> 144:ef7eb2e8f9f7 578 * @param base FTM peripheral base address
<> 144:ef7eb2e8f9f7 579 *
<> 144:ef7eb2e8f9f7 580 * @return The status flags. This is the logical OR of members of the
<> 144:ef7eb2e8f9f7 581 * enumeration ::ftm_status_flags_t
<> 144:ef7eb2e8f9f7 582 */
<> 144:ef7eb2e8f9f7 583 uint32_t FTM_GetStatusFlags(FTM_Type *base);
<> 144:ef7eb2e8f9f7 584
<> 144:ef7eb2e8f9f7 585 /*!
<> 144:ef7eb2e8f9f7 586 * @brief Clears the FTM status flags.
<> 144:ef7eb2e8f9f7 587 *
<> 144:ef7eb2e8f9f7 588 * @param base FTM peripheral base address
<> 144:ef7eb2e8f9f7 589 * @param mask The status flags to clear. This is a logical OR of members of the
<> 144:ef7eb2e8f9f7 590 * enumeration ::ftm_status_flags_t
<> 144:ef7eb2e8f9f7 591 */
<> 144:ef7eb2e8f9f7 592 void FTM_ClearStatusFlags(FTM_Type *base, uint32_t mask);
<> 144:ef7eb2e8f9f7 593
<> 144:ef7eb2e8f9f7 594 /*! @}*/
<> 144:ef7eb2e8f9f7 595
<> 144:ef7eb2e8f9f7 596 /*!
<> 144:ef7eb2e8f9f7 597 * @name Timer Start and Stop
<> 144:ef7eb2e8f9f7 598 * @{
<> 144:ef7eb2e8f9f7 599 */
<> 144:ef7eb2e8f9f7 600
<> 144:ef7eb2e8f9f7 601 /*!
<> 144:ef7eb2e8f9f7 602 * @brief Starts the FTM counter.
<> 144:ef7eb2e8f9f7 603 *
<> 144:ef7eb2e8f9f7 604 * @param base FTM peripheral base address
<> 144:ef7eb2e8f9f7 605 * @param clockSource FTM clock source; After the clock source is set, the counter starts running.
<> 144:ef7eb2e8f9f7 606 */
<> 144:ef7eb2e8f9f7 607 static inline void FTM_StartTimer(FTM_Type *base, ftm_clock_source_t clockSource)
<> 144:ef7eb2e8f9f7 608 {
<> 144:ef7eb2e8f9f7 609 uint32_t reg = base->SC;
<> 144:ef7eb2e8f9f7 610
<> 144:ef7eb2e8f9f7 611 reg &= ~(FTM_SC_CLKS_MASK);
<> 144:ef7eb2e8f9f7 612 reg |= FTM_SC_CLKS(clockSource);
<> 144:ef7eb2e8f9f7 613 base->SC = reg;
<> 144:ef7eb2e8f9f7 614 }
<> 144:ef7eb2e8f9f7 615
<> 144:ef7eb2e8f9f7 616 /*!
<> 144:ef7eb2e8f9f7 617 * @brief Stops the FTM counter.
<> 144:ef7eb2e8f9f7 618 *
<> 144:ef7eb2e8f9f7 619 * @param base FTM peripheral base address
<> 144:ef7eb2e8f9f7 620 */
<> 144:ef7eb2e8f9f7 621 static inline void FTM_StopTimer(FTM_Type *base)
<> 144:ef7eb2e8f9f7 622 {
<> 144:ef7eb2e8f9f7 623 /* Set clock source to none to disable counter */
<> 144:ef7eb2e8f9f7 624 base->SC &= ~(FTM_SC_CLKS_MASK);
<> 144:ef7eb2e8f9f7 625 }
<> 144:ef7eb2e8f9f7 626
<> 144:ef7eb2e8f9f7 627 /*! @}*/
<> 144:ef7eb2e8f9f7 628
<> 144:ef7eb2e8f9f7 629 /*!
<> 144:ef7eb2e8f9f7 630 * @name Software output control
<> 144:ef7eb2e8f9f7 631 * @{
<> 144:ef7eb2e8f9f7 632 */
<> 144:ef7eb2e8f9f7 633
<> 144:ef7eb2e8f9f7 634 /*!
<> 144:ef7eb2e8f9f7 635 * @brief Enables or disables the channel software output control.
<> 144:ef7eb2e8f9f7 636 *
<> 144:ef7eb2e8f9f7 637 * @param base FTM peripheral base address
<> 144:ef7eb2e8f9f7 638 * @param chnlNumber Channel to be enabled or disabled
<> 144:ef7eb2e8f9f7 639 * @param value true: channel output is affected by software output control
<> 144:ef7eb2e8f9f7 640 false: channel output is unaffected by software output control
<> 144:ef7eb2e8f9f7 641 */
<> 144:ef7eb2e8f9f7 642 static inline void FTM_SetSoftwareCtrlEnable(FTM_Type *base, ftm_chnl_t chnlNumber, bool value)
<> 144:ef7eb2e8f9f7 643 {
<> 144:ef7eb2e8f9f7 644 if (value)
<> 144:ef7eb2e8f9f7 645 {
<> 144:ef7eb2e8f9f7 646 base->SWOCTRL |= (1U << chnlNumber);
<> 144:ef7eb2e8f9f7 647 }
<> 144:ef7eb2e8f9f7 648 else
<> 144:ef7eb2e8f9f7 649 {
<> 144:ef7eb2e8f9f7 650 base->SWOCTRL &= ~(1U << chnlNumber);
<> 144:ef7eb2e8f9f7 651 }
<> 144:ef7eb2e8f9f7 652 }
<> 144:ef7eb2e8f9f7 653
<> 144:ef7eb2e8f9f7 654 /*!
<> 144:ef7eb2e8f9f7 655 * @brief Sets the channel software output control value.
<> 144:ef7eb2e8f9f7 656 *
<> 144:ef7eb2e8f9f7 657 * @param base FTM peripheral base address.
<> 144:ef7eb2e8f9f7 658 * @param chnlNumber Channel to be configured
<> 144:ef7eb2e8f9f7 659 * @param value true to set 1, false to set 0
<> 144:ef7eb2e8f9f7 660 */
<> 144:ef7eb2e8f9f7 661 static inline void FTM_SetSoftwareCtrlVal(FTM_Type *base, ftm_chnl_t chnlNumber, bool value)
<> 144:ef7eb2e8f9f7 662 {
<> 144:ef7eb2e8f9f7 663 if (value)
<> 144:ef7eb2e8f9f7 664 {
<> 144:ef7eb2e8f9f7 665 base->SWOCTRL |= (1U << (chnlNumber + FTM_SWOCTRL_CH0OCV_SHIFT));
<> 144:ef7eb2e8f9f7 666 }
<> 144:ef7eb2e8f9f7 667 else
<> 144:ef7eb2e8f9f7 668 {
<> 144:ef7eb2e8f9f7 669 base->SWOCTRL &= ~(1U << (chnlNumber + FTM_SWOCTRL_CH0OCV_SHIFT));
<> 144:ef7eb2e8f9f7 670 }
<> 144:ef7eb2e8f9f7 671 }
<> 144:ef7eb2e8f9f7 672
<> 144:ef7eb2e8f9f7 673 /*! @}*/
<> 144:ef7eb2e8f9f7 674
<> 144:ef7eb2e8f9f7 675 /*!
<> 144:ef7eb2e8f9f7 676 * @brief Enables or disables the FTM global time base signal generation to other FTMs.
<> 144:ef7eb2e8f9f7 677 *
<> 144:ef7eb2e8f9f7 678 * @param base FTM peripheral base address
<> 144:ef7eb2e8f9f7 679 * @param enable true to enable, false to disable
<> 144:ef7eb2e8f9f7 680 */
<> 144:ef7eb2e8f9f7 681 static inline void FTM_SetGlobalTimeBaseOutputEnable(FTM_Type *base, bool enable)
<> 144:ef7eb2e8f9f7 682 {
<> 144:ef7eb2e8f9f7 683 if (enable)
<> 144:ef7eb2e8f9f7 684 {
<> 144:ef7eb2e8f9f7 685 base->CONF |= FTM_CONF_GTBEOUT_MASK;
<> 144:ef7eb2e8f9f7 686 }
<> 144:ef7eb2e8f9f7 687 else
<> 144:ef7eb2e8f9f7 688 {
<> 144:ef7eb2e8f9f7 689 base->CONF &= ~FTM_CONF_GTBEOUT_MASK;
<> 144:ef7eb2e8f9f7 690 }
<> 144:ef7eb2e8f9f7 691 }
<> 144:ef7eb2e8f9f7 692
<> 144:ef7eb2e8f9f7 693 /*!
<> 144:ef7eb2e8f9f7 694 * @brief Sets the FTM peripheral timer channel output mask.
<> 144:ef7eb2e8f9f7 695 *
<> 144:ef7eb2e8f9f7 696 * @param base FTM peripheral base address
<> 144:ef7eb2e8f9f7 697 * @param chnlNumber Channel to be configured
<> 144:ef7eb2e8f9f7 698 * @param mask true: masked, channel is forced to its inactive state; false: unmasked
<> 144:ef7eb2e8f9f7 699 */
<> 144:ef7eb2e8f9f7 700 static inline void FTM_SetOutputMask(FTM_Type *base, ftm_chnl_t chnlNumber, bool mask)
<> 144:ef7eb2e8f9f7 701 {
<> 144:ef7eb2e8f9f7 702 if (mask)
<> 144:ef7eb2e8f9f7 703 {
<> 144:ef7eb2e8f9f7 704 base->OUTMASK |= (1U << chnlNumber);
<> 144:ef7eb2e8f9f7 705 }
<> 144:ef7eb2e8f9f7 706 else
<> 144:ef7eb2e8f9f7 707 {
<> 144:ef7eb2e8f9f7 708 base->OUTMASK &= ~(1U << chnlNumber);
<> 144:ef7eb2e8f9f7 709 }
<> 144:ef7eb2e8f9f7 710 }
<> 144:ef7eb2e8f9f7 711
<> 144:ef7eb2e8f9f7 712 #if defined(FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) && (FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT)
<> 144:ef7eb2e8f9f7 713 /*!
<> 144:ef7eb2e8f9f7 714 * @brief Allows user to enable an output on an FTM channel.
<> 144:ef7eb2e8f9f7 715 *
<> 144:ef7eb2e8f9f7 716 * To enable the PWM channel output call this function with val=true. For input mode,
<> 144:ef7eb2e8f9f7 717 * call this function with val=false.
<> 144:ef7eb2e8f9f7 718 *
<> 144:ef7eb2e8f9f7 719 * @param base FTM peripheral base address
<> 144:ef7eb2e8f9f7 720 * @param chnlNumber Channel to be configured
<> 144:ef7eb2e8f9f7 721 * @param value true: enable output; false: output is disabled, used in input mode
<> 144:ef7eb2e8f9f7 722 */
<> 144:ef7eb2e8f9f7 723 static inline void FTM_SetPwmOutputEnable(FTM_Type *base, ftm_chnl_t chnlNumber, bool value)
<> 144:ef7eb2e8f9f7 724 {
<> 144:ef7eb2e8f9f7 725 if (value)
<> 144:ef7eb2e8f9f7 726 {
<> 144:ef7eb2e8f9f7 727 base->SC |= (1U << (chnlNumber + FTM_SC_PWMEN0_SHIFT));
<> 144:ef7eb2e8f9f7 728 }
<> 144:ef7eb2e8f9f7 729 else
<> 144:ef7eb2e8f9f7 730 {
<> 144:ef7eb2e8f9f7 731 base->SC &= ~(1U << (chnlNumber + FTM_SC_PWMEN0_SHIFT));
<> 144:ef7eb2e8f9f7 732 }
<> 144:ef7eb2e8f9f7 733 }
<> 144:ef7eb2e8f9f7 734 #endif
<> 144:ef7eb2e8f9f7 735
<> 144:ef7eb2e8f9f7 736 /*!
<> 144:ef7eb2e8f9f7 737 * @name Channel pair operations
<> 144:ef7eb2e8f9f7 738 * @{
<> 144:ef7eb2e8f9f7 739 */
<> 144:ef7eb2e8f9f7 740
<> 144:ef7eb2e8f9f7 741 /*!
<> 144:ef7eb2e8f9f7 742 * @brief This function enables/disables the fault control in a channel pair.
<> 144:ef7eb2e8f9f7 743 *
<> 144:ef7eb2e8f9f7 744 * @param base FTM peripheral base address
<> 144:ef7eb2e8f9f7 745 * @param chnlPairNumber The FTM channel pair number; options are 0, 1, 2, 3
<> 144:ef7eb2e8f9f7 746 * @param value true: Enable fault control for this channel pair; false: No fault control
<> 144:ef7eb2e8f9f7 747 */
<> 144:ef7eb2e8f9f7 748 static inline void FTM_SetFaultControlEnable(FTM_Type *base, ftm_chnl_t chnlPairNumber, bool value)
<> 144:ef7eb2e8f9f7 749 {
<> 144:ef7eb2e8f9f7 750 if (value)
<> 144:ef7eb2e8f9f7 751 {
<> 144:ef7eb2e8f9f7 752 base->COMBINE |= (1U << (FTM_COMBINE_FAULTEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber)));
<> 144:ef7eb2e8f9f7 753 }
<> 144:ef7eb2e8f9f7 754 else
<> 144:ef7eb2e8f9f7 755 {
<> 144:ef7eb2e8f9f7 756 base->COMBINE &= ~(1U << (FTM_COMBINE_FAULTEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber)));
<> 144:ef7eb2e8f9f7 757 }
<> 144:ef7eb2e8f9f7 758 }
<> 144:ef7eb2e8f9f7 759
<> 144:ef7eb2e8f9f7 760 /*!
<> 144:ef7eb2e8f9f7 761 * @brief This function enables/disables the dead time insertion in a channel pair.
<> 144:ef7eb2e8f9f7 762 *
<> 144:ef7eb2e8f9f7 763 * @param base FTM peripheral base address
<> 144:ef7eb2e8f9f7 764 * @param chnlPairNumber The FTM channel pair number; options are 0, 1, 2, 3
<> 144:ef7eb2e8f9f7 765 * @param value true: Insert dead time in this channel pair; false: No dead time inserted
<> 144:ef7eb2e8f9f7 766 */
<> 144:ef7eb2e8f9f7 767 static inline void FTM_SetDeadTimeEnable(FTM_Type *base, ftm_chnl_t chnlPairNumber, bool value)
<> 144:ef7eb2e8f9f7 768 {
<> 144:ef7eb2e8f9f7 769 if (value)
<> 144:ef7eb2e8f9f7 770 {
<> 144:ef7eb2e8f9f7 771 base->COMBINE |= (1U << (FTM_COMBINE_DTEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber)));
<> 144:ef7eb2e8f9f7 772 }
<> 144:ef7eb2e8f9f7 773 else
<> 144:ef7eb2e8f9f7 774 {
<> 144:ef7eb2e8f9f7 775 base->COMBINE &= ~(1U << (FTM_COMBINE_DTEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber)));
<> 144:ef7eb2e8f9f7 776 }
<> 144:ef7eb2e8f9f7 777 }
<> 144:ef7eb2e8f9f7 778
<> 144:ef7eb2e8f9f7 779 /*!
<> 144:ef7eb2e8f9f7 780 * @brief This function enables/disables complementary mode in a channel pair.
<> 144:ef7eb2e8f9f7 781 *
<> 144:ef7eb2e8f9f7 782 * @param base FTM peripheral base address
<> 144:ef7eb2e8f9f7 783 * @param chnlPairNumber The FTM channel pair number; options are 0, 1, 2, 3
<> 144:ef7eb2e8f9f7 784 * @param value true: enable complementary mode; false: disable complementary mode
<> 144:ef7eb2e8f9f7 785 */
<> 144:ef7eb2e8f9f7 786 static inline void FTM_SetComplementaryEnable(FTM_Type *base, ftm_chnl_t chnlPairNumber, bool value)
<> 144:ef7eb2e8f9f7 787 {
<> 144:ef7eb2e8f9f7 788 if (value)
<> 144:ef7eb2e8f9f7 789 {
<> 144:ef7eb2e8f9f7 790 base->COMBINE |= (1U << (FTM_COMBINE_COMP0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber)));
<> 144:ef7eb2e8f9f7 791 }
<> 144:ef7eb2e8f9f7 792 else
<> 144:ef7eb2e8f9f7 793 {
<> 144:ef7eb2e8f9f7 794 base->COMBINE &= ~(1U << (FTM_COMBINE_COMP0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber)));
<> 144:ef7eb2e8f9f7 795 }
<> 144:ef7eb2e8f9f7 796 }
<> 144:ef7eb2e8f9f7 797
<> 144:ef7eb2e8f9f7 798 /*!
<> 144:ef7eb2e8f9f7 799 * @brief This function enables/disables inverting control in a channel pair.
<> 144:ef7eb2e8f9f7 800 *
<> 144:ef7eb2e8f9f7 801 * @param base FTM peripheral base address
<> 144:ef7eb2e8f9f7 802 * @param chnlPairNumber The FTM channel pair number; options are 0, 1, 2, 3
<> 144:ef7eb2e8f9f7 803 * @param value true: enable inverting; false: disable inverting
<> 144:ef7eb2e8f9f7 804 */
<> 144:ef7eb2e8f9f7 805 static inline void FTM_SetInvertEnable(FTM_Type *base, ftm_chnl_t chnlPairNumber, bool value)
<> 144:ef7eb2e8f9f7 806 {
<> 144:ef7eb2e8f9f7 807 if (value)
<> 144:ef7eb2e8f9f7 808 {
<> 144:ef7eb2e8f9f7 809 base->INVCTRL |= (1U << chnlPairNumber);
<> 144:ef7eb2e8f9f7 810 }
<> 144:ef7eb2e8f9f7 811 else
<> 144:ef7eb2e8f9f7 812 {
<> 144:ef7eb2e8f9f7 813 base->INVCTRL &= ~(1U << chnlPairNumber);
<> 144:ef7eb2e8f9f7 814 }
<> 144:ef7eb2e8f9f7 815 }
<> 144:ef7eb2e8f9f7 816
<> 144:ef7eb2e8f9f7 817 /*! @}*/
<> 144:ef7eb2e8f9f7 818
<> 144:ef7eb2e8f9f7 819 /*!
<> 144:ef7eb2e8f9f7 820 * @brief Enables or disables the FTM software trigger for PWM synchronization.
<> 144:ef7eb2e8f9f7 821 *
<> 144:ef7eb2e8f9f7 822 * @param base FTM peripheral base address
<> 144:ef7eb2e8f9f7 823 * @param enable true: software trigger is selected, false: software trigger is not selected
<> 144:ef7eb2e8f9f7 824 */
<> 144:ef7eb2e8f9f7 825 static inline void FTM_SetSoftwareTrigger(FTM_Type *base, bool enable)
<> 144:ef7eb2e8f9f7 826 {
<> 144:ef7eb2e8f9f7 827 if (enable)
<> 144:ef7eb2e8f9f7 828 {
<> 144:ef7eb2e8f9f7 829 base->SYNC |= FTM_SYNC_SWSYNC_MASK;
<> 144:ef7eb2e8f9f7 830 }
<> 144:ef7eb2e8f9f7 831 else
<> 144:ef7eb2e8f9f7 832 {
<> 144:ef7eb2e8f9f7 833 base->SYNC &= ~FTM_SYNC_SWSYNC_MASK;
<> 144:ef7eb2e8f9f7 834 }
<> 144:ef7eb2e8f9f7 835 }
<> 144:ef7eb2e8f9f7 836
<> 144:ef7eb2e8f9f7 837 /*!
<> 144:ef7eb2e8f9f7 838 * @brief Enables or disables the FTM write protection.
<> 144:ef7eb2e8f9f7 839 *
<> 144:ef7eb2e8f9f7 840 * @param base FTM peripheral base address
<> 144:ef7eb2e8f9f7 841 * @param enable true: Write-protection is enabled, false: Write-protection is disabled
<> 144:ef7eb2e8f9f7 842 */
<> 144:ef7eb2e8f9f7 843 static inline void FTM_SetWriteProtection(FTM_Type *base, bool enable)
<> 144:ef7eb2e8f9f7 844 {
<> 144:ef7eb2e8f9f7 845 /* Configure write protection */
<> 144:ef7eb2e8f9f7 846 if (enable)
<> 144:ef7eb2e8f9f7 847 {
<> 144:ef7eb2e8f9f7 848 base->FMS |= FTM_FMS_WPEN_MASK;
<> 144:ef7eb2e8f9f7 849 }
<> 144:ef7eb2e8f9f7 850 else
<> 144:ef7eb2e8f9f7 851 {
<> 144:ef7eb2e8f9f7 852 base->MODE |= FTM_MODE_WPDIS_MASK;
<> 144:ef7eb2e8f9f7 853 }
<> 144:ef7eb2e8f9f7 854 }
<> 144:ef7eb2e8f9f7 855
<> 144:ef7eb2e8f9f7 856 #if defined(__cplusplus)
<> 144:ef7eb2e8f9f7 857 }
<> 144:ef7eb2e8f9f7 858 #endif
<> 144:ef7eb2e8f9f7 859
<> 144:ef7eb2e8f9f7 860 /*! @}*/
<> 144:ef7eb2e8f9f7 861
<> 144:ef7eb2e8f9f7 862 #endif /* _FSL_FTM_H_*/