Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_flexcan.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 144:ef7eb2e8f9f7 3 * All rights reserved.
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 6 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 9 * of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 12 * list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 13 * other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 144:ef7eb2e8f9f7 16 * contributors may be used to endorse or promote products derived from this
<> 144:ef7eb2e8f9f7 17 * software without specific prior written permission.
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 29 */
<> 144:ef7eb2e8f9f7 30 #ifndef _FSL_FLEXCAN_H_
<> 144:ef7eb2e8f9f7 31 #define _FSL_FLEXCAN_H_
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 #include "fsl_common.h"
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 /*!
<> 144:ef7eb2e8f9f7 36 * @addtogroup flexcan_driver
<> 144:ef7eb2e8f9f7 37 * @{
<> 144:ef7eb2e8f9f7 38 */
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 /*! @file*/
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 /******************************************************************************
<> 144:ef7eb2e8f9f7 43 * Definitions
<> 144:ef7eb2e8f9f7 44 *****************************************************************************/
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /*! @name Driver version */
<> 144:ef7eb2e8f9f7 47 /*@{*/
<> 144:ef7eb2e8f9f7 48 /*! @brief FlexCAN driver version 2.1.0. */
<> 144:ef7eb2e8f9f7 49 #define FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
<> 144:ef7eb2e8f9f7 50 /*@}*/
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 /*! @brief FlexCAN Frame ID helper macro. */
<> 144:ef7eb2e8f9f7 53 #define FLEXCAN_ID_STD(id) \
<> 144:ef7eb2e8f9f7 54 (((uint32_t)(((uint32_t)(id)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) /*!< Standard Frame ID helper macro. */
<> 144:ef7eb2e8f9f7 55 #define FLEXCAN_ID_EXT(id) \
<> 144:ef7eb2e8f9f7 56 (((uint32_t)(((uint32_t)(id)) << CAN_ID_EXT_SHIFT)) & \
<> 144:ef7eb2e8f9f7 57 (CAN_ID_EXT_MASK | CAN_ID_STD_MASK)) /*!< Extend Frame ID helper macro. */
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /*! @brief FlexCAN Rx Message Buffer Mask helper macro. */
<> 144:ef7eb2e8f9f7 60 #define FLEXCAN_RX_MB_STD_MASK(id, rtr, ide) \
<> 144:ef7eb2e8f9f7 61 (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
<> 144:ef7eb2e8f9f7 62 FLEXCAN_ID_STD(id)) /*!< Standard Rx Message Buffer Mask helper macro. */
<> 144:ef7eb2e8f9f7 63 #define FLEXCAN_RX_MB_EXT_MASK(id, rtr, ide) \
<> 144:ef7eb2e8f9f7 64 (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
<> 144:ef7eb2e8f9f7 65 FLEXCAN_ID_EXT(id)) /*!< Extend Rx Message Buffer Mask helper macro. */
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 /*! @brief FlexCAN Rx FIFO Mask helper macro. */
<> 144:ef7eb2e8f9f7 68 #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_A(id, rtr, ide) \
<> 144:ef7eb2e8f9f7 69 (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
<> 144:ef7eb2e8f9f7 70 (FLEXCAN_ID_STD(id) << 1)) /*!< Standard Rx FIFO Mask helper macro Type A helper macro. */
<> 144:ef7eb2e8f9f7 71 #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_HIGH(id, rtr, ide) \
<> 144:ef7eb2e8f9f7 72 (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
<> 144:ef7eb2e8f9f7 73 (FLEXCAN_ID_STD(id) << 16)) /*!< Standard Rx FIFO Mask helper macro Type B upper part helper macro. */
<> 144:ef7eb2e8f9f7 74 #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_LOW(id, rtr, ide) \
<> 144:ef7eb2e8f9f7 75 (((uint32_t)((uint32_t)(rtr) << 15) | (uint32_t)((uint32_t)(ide) << 14)) | \
<> 144:ef7eb2e8f9f7 76 FLEXCAN_ID_STD(id)) /*!< Standard Rx FIFO Mask helper macro Type B lower part helper macro. */
<> 144:ef7eb2e8f9f7 77 #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_HIGH(id) \
<> 144:ef7eb2e8f9f7 78 ((FLEXCAN_ID_STD(id) & 0x7F8) << 21) /*!< Standard Rx FIFO Mask helper macro Type C upper part helper macro. */
<> 144:ef7eb2e8f9f7 79 #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_HIGH(id) \
<> 144:ef7eb2e8f9f7 80 ((FLEXCAN_ID_STD(id) & 0x7F8) << 13) /*!< Standard Rx FIFO Mask helper macro Type C mid-upper part helper macro. \
<> 144:ef7eb2e8f9f7 81 */
<> 144:ef7eb2e8f9f7 82 #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_LOW(id) \
<> 144:ef7eb2e8f9f7 83 ((FLEXCAN_ID_STD(id) & 0x7F8) << 5) /*!< Standard Rx FIFO Mask helper macro Type C mid-lower part helper macro. */
<> 144:ef7eb2e8f9f7 84 #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW(id) \
<> 144:ef7eb2e8f9f7 85 ((FLEXCAN_ID_STD(id) & 0x7F8) >> 3) /*!< Standard Rx FIFO Mask helper macro Type C lower part helper macro. */
<> 144:ef7eb2e8f9f7 86 #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_A(id, rtr, ide) \
<> 144:ef7eb2e8f9f7 87 (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
<> 144:ef7eb2e8f9f7 88 (FLEXCAN_ID_EXT(id) << 1)) /*!< Extend Rx FIFO Mask helper macro Type A helper macro. */
<> 144:ef7eb2e8f9f7 89 #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_HIGH(id, rtr, ide) \
<> 144:ef7eb2e8f9f7 90 ( \
<> 144:ef7eb2e8f9f7 91 ((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
<> 144:ef7eb2e8f9f7 92 ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) \
<> 144:ef7eb2e8f9f7 93 << 1)) /*!< Extend Rx FIFO Mask helper macro Type B upper part helper macro. */
<> 144:ef7eb2e8f9f7 94 #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW(id, rtr, ide) \
<> 144:ef7eb2e8f9f7 95 (((uint32_t)((uint32_t)(rtr) << 15) | (uint32_t)((uint32_t)(ide) << 14)) | \
<> 144:ef7eb2e8f9f7 96 ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) >> \
<> 144:ef7eb2e8f9f7 97 15)) /*!< Extend Rx FIFO Mask helper macro Type B lower part helper macro. */
<> 144:ef7eb2e8f9f7 98 #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH(id) \
<> 144:ef7eb2e8f9f7 99 ((FLEXCAN_ID_EXT(id) & 0x1FE00000) << 3) /*!< Extend Rx FIFO Mask helper macro Type C upper part helper macro. */
<> 144:ef7eb2e8f9f7 100 #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_HIGH(id) \
<> 144:ef7eb2e8f9f7 101 ((FLEXCAN_ID_EXT(id) & 0x1FE00000) >> \
<> 144:ef7eb2e8f9f7 102 5) /*!< Extend Rx FIFO Mask helper macro Type C mid-upper part helper macro. */
<> 144:ef7eb2e8f9f7 103 #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_LOW(id) \
<> 144:ef7eb2e8f9f7 104 ((FLEXCAN_ID_EXT(id) & 0x1FE00000) >> \
<> 144:ef7eb2e8f9f7 105 13) /*!< Extend Rx FIFO Mask helper macro Type C mid-lower part helper macro. */
<> 144:ef7eb2e8f9f7 106 #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_LOW(id) \
<> 144:ef7eb2e8f9f7 107 ((FLEXCAN_ID_EXT(id) & 0x1FE00000) >> 21) /*!< Extend Rx FIFO Mask helper macro Type C lower part helper macro. */
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 /*! @brief FlexCAN Rx FIFO Filter helper macro. */
<> 144:ef7eb2e8f9f7 110 #define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_A(id, rtr, ide) \
<> 144:ef7eb2e8f9f7 111 FLEXCAN_RX_FIFO_STD_MASK_TYPE_A(id, rtr, ide) /*!< Standard Rx FIFO Filter helper macro Type A helper macro. */
<> 144:ef7eb2e8f9f7 112 #define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_B_HIGH(id, rtr, ide) \
<> 144:ef7eb2e8f9f7 113 FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_HIGH( \
<> 144:ef7eb2e8f9f7 114 id, rtr, ide) /*!< Standard Rx FIFO Filter helper macro Type B upper part helper macro. */
<> 144:ef7eb2e8f9f7 115 #define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_B_LOW(id, rtr, ide) \
<> 144:ef7eb2e8f9f7 116 FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_LOW( \
<> 144:ef7eb2e8f9f7 117 id, rtr, ide) /*!< Standard Rx FIFO Filter helper macro Type B lower part helper macro. */
<> 144:ef7eb2e8f9f7 118 #define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_HIGH(id) \
<> 144:ef7eb2e8f9f7 119 FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_HIGH( \
<> 144:ef7eb2e8f9f7 120 id) /*!< Standard Rx FIFO Filter helper macro Type C upper part helper macro. */
<> 144:ef7eb2e8f9f7 121 #define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_MID_HIGH(id) \
<> 144:ef7eb2e8f9f7 122 FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_HIGH( \
<> 144:ef7eb2e8f9f7 123 id) /*!< Standard Rx FIFO Filter helper macro Type C mid-upper part helper macro. */
<> 144:ef7eb2e8f9f7 124 #define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_MID_LOW(id) \
<> 144:ef7eb2e8f9f7 125 FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_LOW( \
<> 144:ef7eb2e8f9f7 126 id) /*!< Standard Rx FIFO Filter helper macro Type C mid-lower part helper macro. */
<> 144:ef7eb2e8f9f7 127 #define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_LOW(id) \
<> 144:ef7eb2e8f9f7 128 FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW(id) /*!< Standard Rx FIFO Filter helper macro Type C lower part helper macro. \
<> 144:ef7eb2e8f9f7 129 */
<> 144:ef7eb2e8f9f7 130 #define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_A(id, rtr, ide) \
<> 144:ef7eb2e8f9f7 131 FLEXCAN_RX_FIFO_EXT_MASK_TYPE_A(id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type A helper macro. */
<> 144:ef7eb2e8f9f7 132 #define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_HIGH(id, rtr, ide) \
<> 144:ef7eb2e8f9f7 133 FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_HIGH( \
<> 144:ef7eb2e8f9f7 134 id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type B upper part helper macro. */
<> 144:ef7eb2e8f9f7 135 #define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_LOW(id, rtr, ide) \
<> 144:ef7eb2e8f9f7 136 FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW( \
<> 144:ef7eb2e8f9f7 137 id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type B lower part helper macro. */
<> 144:ef7eb2e8f9f7 138 #define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_HIGH(id) \
<> 144:ef7eb2e8f9f7 139 FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH(id) /*!< Extend Rx FIFO Filter helper macro Type C upper part helper macro. \
<> 144:ef7eb2e8f9f7 140 */
<> 144:ef7eb2e8f9f7 141 #define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_MID_HIGH(id) \
<> 144:ef7eb2e8f9f7 142 FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_HIGH( \
<> 144:ef7eb2e8f9f7 143 id) /*!< Extend Rx FIFO Filter helper macro Type C mid-upper part helper macro. */
<> 144:ef7eb2e8f9f7 144 #define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_MID_LOW(id) \
<> 144:ef7eb2e8f9f7 145 FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_LOW( \
<> 144:ef7eb2e8f9f7 146 id) /*!< Extend Rx FIFO Filter helper macro Type C mid-lower part helper macro. */
<> 144:ef7eb2e8f9f7 147 #define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_LOW(id) \
<> 144:ef7eb2e8f9f7 148 FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_LOW(id) /*!< Extend Rx FIFO Filter helper macro Type C lower part helper macro. */
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 /*! @brief FlexCAN transfer status. */
<> 144:ef7eb2e8f9f7 151 enum _flexcan_status
<> 144:ef7eb2e8f9f7 152 {
<> 144:ef7eb2e8f9f7 153 kStatus_FLEXCAN_TxBusy = MAKE_STATUS(kStatusGroup_FLEXCAN, 0), /*!< Tx Message Buffer is Busy. */
<> 144:ef7eb2e8f9f7 154 kStatus_FLEXCAN_TxIdle = MAKE_STATUS(kStatusGroup_FLEXCAN, 1), /*!< Tx Message Buffer is Idle. */
<> 144:ef7eb2e8f9f7 155 kStatus_FLEXCAN_TxSwitchToRx = MAKE_STATUS(
<> 144:ef7eb2e8f9f7 156 kStatusGroup_FLEXCAN, 2), /*!< Remote Message is send out and Message buffer changed to Receive one. */
<> 144:ef7eb2e8f9f7 157 kStatus_FLEXCAN_RxBusy = MAKE_STATUS(kStatusGroup_FLEXCAN, 3), /*!< Rx Message Buffer is Busy. */
<> 144:ef7eb2e8f9f7 158 kStatus_FLEXCAN_RxIdle = MAKE_STATUS(kStatusGroup_FLEXCAN, 4), /*!< Rx Message Buffer is Idle. */
<> 144:ef7eb2e8f9f7 159 kStatus_FLEXCAN_RxOverflow = MAKE_STATUS(kStatusGroup_FLEXCAN, 5), /*!< Rx Message Buffer is Overflowed. */
<> 144:ef7eb2e8f9f7 160 kStatus_FLEXCAN_RxFifoBusy = MAKE_STATUS(kStatusGroup_FLEXCAN, 6), /*!< Rx Message FIFO is Busy. */
<> 144:ef7eb2e8f9f7 161 kStatus_FLEXCAN_RxFifoIdle = MAKE_STATUS(kStatusGroup_FLEXCAN, 7), /*!< Rx Message FIFO is Idle. */
<> 144:ef7eb2e8f9f7 162 kStatus_FLEXCAN_RxFifoOverflow = MAKE_STATUS(kStatusGroup_FLEXCAN, 8), /*!< Rx Message FIFO is overflowed. */
<> 144:ef7eb2e8f9f7 163 kStatus_FLEXCAN_RxFifoWarning = MAKE_STATUS(kStatusGroup_FLEXCAN, 0), /*!< Rx Message FIFO is almost overflowed. */
<> 144:ef7eb2e8f9f7 164 kStatus_FLEXCAN_ErrorStatus = MAKE_STATUS(kStatusGroup_FLEXCAN, 10), /*!< FlexCAN Module Error and Status. */
<> 144:ef7eb2e8f9f7 165 kStatus_FLEXCAN_UnHandled = MAKE_STATUS(kStatusGroup_FLEXCAN, 11), /*!< UnHadled Interrupt asserted. */
<> 144:ef7eb2e8f9f7 166 };
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 /*! @brief FlexCAN frame format. */
<> 144:ef7eb2e8f9f7 169 typedef enum _flexcan_frame_format
<> 144:ef7eb2e8f9f7 170 {
<> 144:ef7eb2e8f9f7 171 kFLEXCAN_FrameFormatStandard = 0x0U, /*!< Standard frame format attribute. */
<> 144:ef7eb2e8f9f7 172 kFLEXCAN_FrameFormatExtend = 0x1U, /*!< Extend frame format attribute. */
<> 144:ef7eb2e8f9f7 173 } flexcan_frame_format_t;
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 /*! @brief FlexCAN frame type. */
<> 144:ef7eb2e8f9f7 176 typedef enum _flexcan_frame_type
<> 144:ef7eb2e8f9f7 177 {
<> 144:ef7eb2e8f9f7 178 kFLEXCAN_FrameTypeData = 0x0U, /*!< Data frame type attribute. */
<> 144:ef7eb2e8f9f7 179 kFLEXCAN_FrameTypeRemote = 0x1U, /*!< Remote frame type attribute. */
<> 144:ef7eb2e8f9f7 180 } flexcan_frame_type_t;
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 /*! @brief FlexCAN clock source. */
<> 144:ef7eb2e8f9f7 183 typedef enum _flexcan_clock_source
<> 144:ef7eb2e8f9f7 184 {
<> 144:ef7eb2e8f9f7 185 kFLEXCAN_ClkSrcOsc = 0x0U, /*!< FlexCAN Protocol Engine clock from Oscillator. */
<> 144:ef7eb2e8f9f7 186 kFLEXCAN_ClkSrcPeri = 0x1U, /*!< FlexCAN Protocol Engine clock from Peripheral Clock. */
<> 144:ef7eb2e8f9f7 187 } flexcan_clock_source_t;
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 /*! @brief FlexCAN Rx Fifo Filter type. */
<> 144:ef7eb2e8f9f7 190 typedef enum _flexcan_rx_fifo_filter_type
<> 144:ef7eb2e8f9f7 191 {
<> 144:ef7eb2e8f9f7 192 kFLEXCAN_RxFifoFilterTypeA = 0x0U, /*!< One full ID (standard and extended) per ID Filter element. */
<> 144:ef7eb2e8f9f7 193 kFLEXCAN_RxFifoFilterTypeB =
<> 144:ef7eb2e8f9f7 194 0x1U, /*!< Two full standard IDs or two partial 14-bit ID slices per ID Filter Table element. */
<> 144:ef7eb2e8f9f7 195 kFLEXCAN_RxFifoFilterTypeC =
<> 144:ef7eb2e8f9f7 196 0x2U, /*!< Four partial 8-bit Standard or extended ID slices per ID Filter Table element. */
<> 144:ef7eb2e8f9f7 197 kFLEXCAN_RxFifoFilterTypeD = 0x3U, /*!< All frames rejected. */
<> 144:ef7eb2e8f9f7 198 } flexcan_rx_fifo_filter_type_t;
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 /*!
<> 144:ef7eb2e8f9f7 201 * @brief FlexCAN Rx FIFO priority
<> 144:ef7eb2e8f9f7 202 *
<> 144:ef7eb2e8f9f7 203 * The matching process starts from the Rx MB(or Rx FIFO) with higher priority.
<> 144:ef7eb2e8f9f7 204 * If no MB(or Rx FIFO filter) is satisfied, the matching process goes on with
<> 144:ef7eb2e8f9f7 205 * the Rx FIFO(or Rx MB) with lower priority.
<> 144:ef7eb2e8f9f7 206 */
<> 144:ef7eb2e8f9f7 207 typedef enum _flexcan_rx_fifo_priority
<> 144:ef7eb2e8f9f7 208 {
<> 144:ef7eb2e8f9f7 209 kFLEXCAN_RxFifoPrioLow = 0x0U, /*!< Matching process start from Rx Message Buffer first*/
<> 144:ef7eb2e8f9f7 210 kFLEXCAN_RxFifoPrioHigh = 0x1U, /*!< Matching process start from Rx FIFO first*/
<> 144:ef7eb2e8f9f7 211 } flexcan_rx_fifo_priority_t;
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 /*!
<> 144:ef7eb2e8f9f7 214 * @brief FlexCAN interrupt configuration structure, default settings all disabled.
<> 144:ef7eb2e8f9f7 215 *
<> 144:ef7eb2e8f9f7 216 * This structure contains the settings for all of the FlexCAN Module interrupt configurations.
<> 144:ef7eb2e8f9f7 217 * Note: FlexCAN Message Buffers and Rx FIFO have their own interrupts.
<> 144:ef7eb2e8f9f7 218 */
<> 144:ef7eb2e8f9f7 219 enum _flexcan_interrupt_enable
<> 144:ef7eb2e8f9f7 220 {
<> 144:ef7eb2e8f9f7 221 kFLEXCAN_BusOffInterruptEnable = CAN_CTRL1_BOFFMSK_MASK, /*!< Bus Off interrupt. */
<> 144:ef7eb2e8f9f7 222 kFLEXCAN_ErrorInterruptEnable = CAN_CTRL1_ERRMSK_MASK, /*!< Error interrupt. */
<> 144:ef7eb2e8f9f7 223 kFLEXCAN_RxWarningInterruptEnable = CAN_CTRL1_RWRNMSK_MASK, /*!< Rx Warning interrupt. */
<> 144:ef7eb2e8f9f7 224 kFLEXCAN_TxWarningInterruptEnable = CAN_CTRL1_TWRNMSK_MASK, /*!< Tx Warning interrupt. */
<> 144:ef7eb2e8f9f7 225 kFLEXCAN_WakeUpInterruptEnable = CAN_MCR_WAKMSK_MASK, /*!< Wake Up interrupt. */
<> 144:ef7eb2e8f9f7 226 };
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 /*!
<> 144:ef7eb2e8f9f7 229 * @brief FlexCAN status flags.
<> 144:ef7eb2e8f9f7 230 *
<> 144:ef7eb2e8f9f7 231 * This provides constants for the FlexCAN status flags for use in the FlexCAN functions.
<> 144:ef7eb2e8f9f7 232 * Note: The CPU read action clears FlEXCAN_ErrorFlag, therefore user need to
<> 144:ef7eb2e8f9f7 233 * read FlEXCAN_ErrorFlag and distinguish which error is occur using
<> 144:ef7eb2e8f9f7 234 * @ref _flexcan_error_flags enumerations.
<> 144:ef7eb2e8f9f7 235 */
<> 144:ef7eb2e8f9f7 236 enum _flexcan_flags
<> 144:ef7eb2e8f9f7 237 {
<> 144:ef7eb2e8f9f7 238 kFLEXCAN_SynchFlag = CAN_ESR1_SYNCH_MASK, /*!< CAN Synchronization Status. */
<> 144:ef7eb2e8f9f7 239 kFLEXCAN_TxWarningIntFlag = CAN_ESR1_TWRNINT_MASK, /*!< Tx Warning Interrupt Flag. */
<> 144:ef7eb2e8f9f7 240 kFLEXCAN_RxWarningIntFlag = CAN_ESR1_RWRNINT_MASK, /*!< Rx Warning Interrupt Flag. */
<> 144:ef7eb2e8f9f7 241 kFLEXCAN_TxErrorWarningFlag = CAN_ESR1_TXWRN_MASK, /*!< Tx Error Warning Status. */
<> 144:ef7eb2e8f9f7 242 kFLEXCAN_RxErrorWarningFlag = CAN_ESR1_RXWRN_MASK, /*!< Rx Error Warning Status. */
<> 144:ef7eb2e8f9f7 243 kFLEXCAN_IdleFlag = CAN_ESR1_IDLE_MASK, /*!< CAN IDLE Status Flag. */
<> 144:ef7eb2e8f9f7 244 kFLEXCAN_FaultConfinementFlag = CAN_ESR1_FLTCONF_MASK, /*!< Fault Confinement State Flag. */
<> 144:ef7eb2e8f9f7 245 kFLEXCAN_TransmittingFlag = CAN_ESR1_TX_MASK, /*!< FlexCAN In Transmission Status. */
<> 144:ef7eb2e8f9f7 246 kFLEXCAN_ReceivingFlag = CAN_ESR1_RX_MASK, /*!< FlexCAN In Reception Status. */
<> 144:ef7eb2e8f9f7 247 kFLEXCAN_BusOffIntFlag = CAN_ESR1_BOFFINT_MASK, /*!< Bus Off Interrupt Flag. */
<> 144:ef7eb2e8f9f7 248 kFLEXCAN_ErrorIntFlag = CAN_ESR1_ERRINT_MASK, /*!< Error Interrupt Flag. */
<> 144:ef7eb2e8f9f7 249 kFLEXCAN_WakeUpIntFlag = CAN_ESR1_WAKINT_MASK, /*!< Wake-Up Interrupt Flag. */
<> 144:ef7eb2e8f9f7 250 kFLEXCAN_ErrorFlag = CAN_ESR1_BIT1ERR_MASK | /*!< All FlexCAN Error Status. */
<> 144:ef7eb2e8f9f7 251 CAN_ESR1_BIT0ERR_MASK |
<> 144:ef7eb2e8f9f7 252 CAN_ESR1_ACKERR_MASK | CAN_ESR1_CRCERR_MASK | CAN_ESR1_FRMERR_MASK | CAN_ESR1_STFERR_MASK,
<> 144:ef7eb2e8f9f7 253 };
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 /*!
<> 144:ef7eb2e8f9f7 256 * @brief FlexCAN error status flags.
<> 144:ef7eb2e8f9f7 257 *
<> 144:ef7eb2e8f9f7 258 * The FlexCAN Error Status enumerations is used to report current error of the FlexCAN bus.
<> 144:ef7eb2e8f9f7 259 * This enumerations should be used with KFLEXCAN_ErrorFlag in @ref _flexcan_flags enumerations
<> 144:ef7eb2e8f9f7 260 * to ditermine which error is generated.
<> 144:ef7eb2e8f9f7 261 */
<> 144:ef7eb2e8f9f7 262 enum _flexcan_error_flags
<> 144:ef7eb2e8f9f7 263 {
<> 144:ef7eb2e8f9f7 264 kFLEXCAN_StuffingError = CAN_ESR1_STFERR_MASK, /*!< Stuffing Error. */
<> 144:ef7eb2e8f9f7 265 kFLEXCAN_FormError = CAN_ESR1_FRMERR_MASK, /*!< Form Error. */
<> 144:ef7eb2e8f9f7 266 kFLEXCAN_CrcError = CAN_ESR1_CRCERR_MASK, /*!< Cyclic Redundancy Check Error. */
<> 144:ef7eb2e8f9f7 267 kFLEXCAN_AckError = CAN_ESR1_ACKERR_MASK, /*!< Received no ACK on transmission. */
<> 144:ef7eb2e8f9f7 268 kFLEXCAN_Bit0Error = CAN_ESR1_BIT0ERR_MASK, /*!< Unable to send dominant bit. */
<> 144:ef7eb2e8f9f7 269 kFLEXCAN_Bit1Error = CAN_ESR1_BIT1ERR_MASK, /*!< Unable to send recessive bit. */
<> 144:ef7eb2e8f9f7 270 };
<> 144:ef7eb2e8f9f7 271
<> 144:ef7eb2e8f9f7 272 /*!
<> 144:ef7eb2e8f9f7 273 * @brief FlexCAN Rx FIFO status flags.
<> 144:ef7eb2e8f9f7 274 *
<> 144:ef7eb2e8f9f7 275 * The FlexCAN Rx FIFO Status enumerations are used to determine the status of the
<> 144:ef7eb2e8f9f7 276 * Rx FIFO. Because Rx FIFO occupy the MB0 ~ MB7 (Rx Fifo filter also occupies
<> 144:ef7eb2e8f9f7 277 * more Message Buffer space), Rx FIFO status flags are mapped to the corresponding
<> 144:ef7eb2e8f9f7 278 * Message Buffer status flags.
<> 144:ef7eb2e8f9f7 279 */
<> 144:ef7eb2e8f9f7 280 enum _flexcan_rx_fifo_flags
<> 144:ef7eb2e8f9f7 281 {
<> 144:ef7eb2e8f9f7 282 kFLEXCAN_RxFifoOverflowFlag = CAN_IFLAG1_BUF7I_MASK, /*!< Rx FIFO overflow flag. */
<> 144:ef7eb2e8f9f7 283 kFLEXCAN_RxFifoWarningFlag = CAN_IFLAG1_BUF6I_MASK, /*!< Rx FIFO almost full flag. */
<> 144:ef7eb2e8f9f7 284 kFLEXCAN_RxFifoFrameAvlFlag = CAN_IFLAG1_BUF5I_MASK, /*!< Frames available in Rx FIFO flag. */
<> 144:ef7eb2e8f9f7 285 };
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 #if defined(__CC_ARM)
<> 144:ef7eb2e8f9f7 288 #pragma anon_unions
<> 144:ef7eb2e8f9f7 289 #endif
<> 144:ef7eb2e8f9f7 290 /*! @brief FlexCAN message frame structure. */
<> 144:ef7eb2e8f9f7 291 typedef struct _flexcan_frame
<> 144:ef7eb2e8f9f7 292 {
<> 144:ef7eb2e8f9f7 293 struct
<> 144:ef7eb2e8f9f7 294 {
<> 144:ef7eb2e8f9f7 295 uint32_t timestamp : 16; /*!< FlexCAN internal Free-Running Counter Time Stamp. */
<> 144:ef7eb2e8f9f7 296 uint32_t length : 4; /*!< CAN frame payload length in bytes(Range: 0~8). */
<> 144:ef7eb2e8f9f7 297 uint32_t type : 1; /*!< CAN Frame Type(DATA or REMOTE). */
<> 144:ef7eb2e8f9f7 298 uint32_t format : 1; /*!< CAN Frame Identifier(STD or EXT format). */
<> 144:ef7eb2e8f9f7 299 uint32_t reserve1 : 1; /*!< Reserved for placeholder. */
<> 144:ef7eb2e8f9f7 300 uint32_t idhit : 9; /*!< CAN Rx FIFO filter hit id(This value is only used in Rx FIFO receive mode). */
<> 144:ef7eb2e8f9f7 301 };
<> 144:ef7eb2e8f9f7 302 struct
<> 144:ef7eb2e8f9f7 303 {
<> 144:ef7eb2e8f9f7 304 uint32_t id : 29; /*!< CAN Frame Identifier, should be set using FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro. */
<> 144:ef7eb2e8f9f7 305 uint32_t reserve2 : 3; /*!< Reserved for place holder. */
<> 144:ef7eb2e8f9f7 306 };
<> 144:ef7eb2e8f9f7 307 union
<> 144:ef7eb2e8f9f7 308 {
<> 144:ef7eb2e8f9f7 309 struct
<> 144:ef7eb2e8f9f7 310 {
<> 144:ef7eb2e8f9f7 311 uint32_t dataWord0; /*!< CAN Frame payload word0. */
<> 144:ef7eb2e8f9f7 312 uint32_t dataWord1; /*!< CAN Frame payload word1. */
<> 144:ef7eb2e8f9f7 313 };
<> 144:ef7eb2e8f9f7 314 struct
<> 144:ef7eb2e8f9f7 315 {
<> 144:ef7eb2e8f9f7 316 uint8_t dataByte3; /*!< CAN Frame payload byte3. */
<> 144:ef7eb2e8f9f7 317 uint8_t dataByte2; /*!< CAN Frame payload byte2. */
<> 144:ef7eb2e8f9f7 318 uint8_t dataByte1; /*!< CAN Frame payload byte1. */
<> 144:ef7eb2e8f9f7 319 uint8_t dataByte0; /*!< CAN Frame payload byte0. */
<> 144:ef7eb2e8f9f7 320 uint8_t dataByte7; /*!< CAN Frame payload byte7. */
<> 144:ef7eb2e8f9f7 321 uint8_t dataByte6; /*!< CAN Frame payload byte6. */
<> 144:ef7eb2e8f9f7 322 uint8_t dataByte5; /*!< CAN Frame payload byte5. */
<> 144:ef7eb2e8f9f7 323 uint8_t dataByte4; /*!< CAN Frame payload byte4. */
<> 144:ef7eb2e8f9f7 324 };
<> 144:ef7eb2e8f9f7 325 };
<> 144:ef7eb2e8f9f7 326 } flexcan_frame_t;
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 /*! @brief FlexCAN module configuration structure. */
<> 144:ef7eb2e8f9f7 329 typedef struct _flexcan_config
<> 144:ef7eb2e8f9f7 330 {
<> 144:ef7eb2e8f9f7 331 uint32_t baudRate; /*!< FlexCAN baud rate in bps. */
<> 144:ef7eb2e8f9f7 332 flexcan_clock_source_t clkSrc; /*!< Clock source for FlexCAN Protocol Engine. */
<> 144:ef7eb2e8f9f7 333 uint8_t maxMbNum; /*!< The maximum number of Message Buffers used by user. */
<> 144:ef7eb2e8f9f7 334 bool enableLoopBack; /*!< Enable or Disable Loop Back Self Test Mode. */
<> 144:ef7eb2e8f9f7 335 bool enableSelfWakeup; /*!< Enable or Disable Self Wakeup Mode. */
<> 144:ef7eb2e8f9f7 336 bool enableIndividMask; /*!< Enable or Disable Rx Individual Mask. */
<> 144:ef7eb2e8f9f7 337 #if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT)
<> 144:ef7eb2e8f9f7 338 bool enableDoze; /*!< Enable or Disable Doze Mode. */
<> 144:ef7eb2e8f9f7 339 #endif
<> 144:ef7eb2e8f9f7 340 } flexcan_config_t;
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342 /*! @brief FlexCAN protocol timing characteristic configuration structure. */
<> 144:ef7eb2e8f9f7 343 typedef struct _flexcan_timing_config
<> 144:ef7eb2e8f9f7 344 {
<> 144:ef7eb2e8f9f7 345 uint8_t preDivider; /*!< Clock Pre-scaler Division Factor. */
<> 144:ef7eb2e8f9f7 346 uint8_t rJumpwidth; /*!< Re-sync Jump Width. */
<> 144:ef7eb2e8f9f7 347 uint8_t phaseSeg1; /*!< Phase Segment 1. */
<> 144:ef7eb2e8f9f7 348 uint8_t phaseSeg2; /*!< Phase Segment 2. */
<> 144:ef7eb2e8f9f7 349 uint8_t propSeg; /*!< Propagation Segment. */
<> 144:ef7eb2e8f9f7 350 } flexcan_timing_config_t;
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 /*!
<> 144:ef7eb2e8f9f7 353 * @brief FlexCAN Receive Message Buffer configuration structure
<> 144:ef7eb2e8f9f7 354 *
<> 144:ef7eb2e8f9f7 355 * This structure is used as the parameter of FLEXCAN_SetRxMbConfig() function.
<> 144:ef7eb2e8f9f7 356 * The FLEXCAN_SetRxMbConfig() function is used to configure FlexCAN Receive
<> 144:ef7eb2e8f9f7 357 * Message Buffer. The function abort previous receiving process, clean the
<> 144:ef7eb2e8f9f7 358 * Message Buffer and activate the Rx Message Buffer using given Message Buffer
<> 144:ef7eb2e8f9f7 359 * setting.
<> 144:ef7eb2e8f9f7 360 */
<> 144:ef7eb2e8f9f7 361 typedef struct _flexcan_rx_mb_config
<> 144:ef7eb2e8f9f7 362 {
<> 144:ef7eb2e8f9f7 363 uint32_t id; /*!< CAN Message Buffer Frame Identifier, should be set using
<> 144:ef7eb2e8f9f7 364 FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro. */
<> 144:ef7eb2e8f9f7 365 flexcan_frame_format_t format; /*!< CAN Frame Identifier format(Standard of Extend). */
<> 144:ef7eb2e8f9f7 366 flexcan_frame_type_t type; /*!< CAN Frame Type(Data or Remote). */
<> 144:ef7eb2e8f9f7 367 } flexcan_rx_mb_config_t;
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369 /*! @brief FlexCAN Rx FIFO configure structure. */
<> 144:ef7eb2e8f9f7 370 typedef struct _flexcan_rx_fifo_config
<> 144:ef7eb2e8f9f7 371 {
<> 144:ef7eb2e8f9f7 372 uint32_t *idFilterTable; /*!< Pointer to FlexCAN Rx FIFO identifier filter table. */
<> 144:ef7eb2e8f9f7 373 uint8_t idFilterNum; /*!< The quantity of filter elements. */
<> 144:ef7eb2e8f9f7 374 flexcan_rx_fifo_filter_type_t idFilterType; /*!< The FlexCAN Rx FIFO Filter type. */
<> 144:ef7eb2e8f9f7 375 flexcan_rx_fifo_priority_t priority; /*!< The FlexCAN Rx FIFO receive priority. */
<> 144:ef7eb2e8f9f7 376 } flexcan_rx_fifo_config_t;
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 /*! @brief FlexCAN Message Buffer transfer. */
<> 144:ef7eb2e8f9f7 379 typedef struct _flexcan_mb_transfer
<> 144:ef7eb2e8f9f7 380 {
<> 144:ef7eb2e8f9f7 381 flexcan_frame_t *frame; /*!< The buffer of CAN Message to be transfer. */
<> 144:ef7eb2e8f9f7 382 uint8_t mbIdx; /*!< The index of Message buffer used to transfer Message. */
<> 144:ef7eb2e8f9f7 383 } flexcan_mb_transfer_t;
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385 /*! @brief FlexCAN Rx FIFO transfer. */
<> 144:ef7eb2e8f9f7 386 typedef struct _flexcan_fifo_transfer
<> 144:ef7eb2e8f9f7 387 {
<> 144:ef7eb2e8f9f7 388 flexcan_frame_t *frame; /*!< The buffer of CAN Message to be received from Rx FIFO. */
<> 144:ef7eb2e8f9f7 389 } flexcan_fifo_transfer_t;
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 /*! @brief FlexCAN handle structure definition. */
<> 144:ef7eb2e8f9f7 392 typedef struct _flexcan_handle flexcan_handle_t;
<> 144:ef7eb2e8f9f7 393
<> 144:ef7eb2e8f9f7 394 /*! @brief FlexCAN transfer callback function.
<> 144:ef7eb2e8f9f7 395 *
<> 144:ef7eb2e8f9f7 396 * The FlexCAN transfer callback returns a value from the underlying layer.
<> 144:ef7eb2e8f9f7 397 * If the status equals to kStatus_FLEXCAN_ErrorStatus, the result parameter is the Content of
<> 144:ef7eb2e8f9f7 398 * FlexCAN status register which can be used to get the working status(or error status) of FlexCAN module.
<> 144:ef7eb2e8f9f7 399 * If the status equals to other FlexCAN Message Buffer transfer status, the result is the index of
<> 144:ef7eb2e8f9f7 400 * Message Buffer that generate transfer event.
<> 144:ef7eb2e8f9f7 401 * If the status equals to other FlexCAN Message Buffer transfer status, the result is meaningless and should be
<> 144:ef7eb2e8f9f7 402 * Ignored.
<> 144:ef7eb2e8f9f7 403 */
<> 144:ef7eb2e8f9f7 404 typedef void (*flexcan_transfer_callback_t)(
<> 144:ef7eb2e8f9f7 405 CAN_Type *base, flexcan_handle_t *handle, status_t status, uint32_t result, void *userData);
<> 144:ef7eb2e8f9f7 406
<> 144:ef7eb2e8f9f7 407 /*! @brief FlexCAN handle structure. */
<> 144:ef7eb2e8f9f7 408 struct _flexcan_handle
<> 144:ef7eb2e8f9f7 409 {
<> 144:ef7eb2e8f9f7 410 flexcan_transfer_callback_t callback; /*!< Callback function. */
<> 144:ef7eb2e8f9f7 411 void *userData; /*!< FlexCAN callback function parameter.*/
<> 144:ef7eb2e8f9f7 412 flexcan_frame_t *volatile mbFrameBuf[CAN_WORD1_COUNT];
<> 144:ef7eb2e8f9f7 413 /*!< The buffer for received data from Message Buffers. */
<> 144:ef7eb2e8f9f7 414 flexcan_frame_t *volatile rxFifoFrameBuf; /*!< The buffer for received data from Rx FIFO. */
<> 144:ef7eb2e8f9f7 415 volatile uint8_t mbState[CAN_WORD1_COUNT]; /*!< Message Buffer transfer state. */
<> 144:ef7eb2e8f9f7 416 volatile uint8_t rxFifoState; /*!< Rx FIFO transfer state. */
<> 144:ef7eb2e8f9f7 417 };
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 /******************************************************************************
<> 144:ef7eb2e8f9f7 420 * API
<> 144:ef7eb2e8f9f7 421 *****************************************************************************/
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 #if defined(__cplusplus)
<> 144:ef7eb2e8f9f7 424 extern "C" {
<> 144:ef7eb2e8f9f7 425 #endif
<> 144:ef7eb2e8f9f7 426
<> 144:ef7eb2e8f9f7 427 /*!
<> 144:ef7eb2e8f9f7 428 * @name Initialization and deinitialization
<> 144:ef7eb2e8f9f7 429 * @{
<> 144:ef7eb2e8f9f7 430 */
<> 144:ef7eb2e8f9f7 431
<> 144:ef7eb2e8f9f7 432 /*!
<> 144:ef7eb2e8f9f7 433 * @brief Initializes a FlexCAN instance.
<> 144:ef7eb2e8f9f7 434 *
<> 144:ef7eb2e8f9f7 435 * This function initializes the FlexCAN module with user-defined settings.
<> 144:ef7eb2e8f9f7 436 * This example shows how to set up the flexcan_config_t parameters and how
<> 144:ef7eb2e8f9f7 437 * to call the FLEXCAN_Init function by passing in these parameters:
<> 144:ef7eb2e8f9f7 438 * @code
<> 144:ef7eb2e8f9f7 439 * flexcan_config_t flexcanConfig;
<> 144:ef7eb2e8f9f7 440 * flexcanConfig.clkSrc = KFLEXCAN_ClkSrcOsc;
<> 144:ef7eb2e8f9f7 441 * flexcanConfig.baudRate = 125000U;
<> 144:ef7eb2e8f9f7 442 * flexcanConfig.maxMbNum = 16;
<> 144:ef7eb2e8f9f7 443 * flexcanConfig.enableLoopBack = false;
<> 144:ef7eb2e8f9f7 444 * flexcanConfig.enableSelfWakeup = false;
<> 144:ef7eb2e8f9f7 445 * flexcanConfig.enableIndividMask = false;
<> 144:ef7eb2e8f9f7 446 * flexcanConfig.enableDoze = false;
<> 144:ef7eb2e8f9f7 447 * FLEXCAN_Init(CAN0, &flexcanConfig, 8000000UL);
<> 144:ef7eb2e8f9f7 448 * @endcode
<> 144:ef7eb2e8f9f7 449 *
<> 144:ef7eb2e8f9f7 450 * @param base FlexCAN peripheral base address.
<> 144:ef7eb2e8f9f7 451 * @param config Pointer to user-defined configuration structure.
<> 144:ef7eb2e8f9f7 452 * @param sourceClock_Hz FlexCAN Protocol Engine clock source frequency in Hz.
<> 144:ef7eb2e8f9f7 453 */
<> 144:ef7eb2e8f9f7 454 void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *config, uint32_t sourceClock_Hz);
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 /*!
<> 144:ef7eb2e8f9f7 457 * @brief De-initializes a FlexCAN instance.
<> 144:ef7eb2e8f9f7 458 *
<> 144:ef7eb2e8f9f7 459 * This function disable the FlexCAN module clock and set all register value
<> 144:ef7eb2e8f9f7 460 * to reset value.
<> 144:ef7eb2e8f9f7 461 *
<> 144:ef7eb2e8f9f7 462 * @param base FlexCAN peripheral base address.
<> 144:ef7eb2e8f9f7 463 */
<> 144:ef7eb2e8f9f7 464 void FLEXCAN_Deinit(CAN_Type *base);
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 /*!
<> 144:ef7eb2e8f9f7 467 * @brief Get the default configuration structure.
<> 144:ef7eb2e8f9f7 468 *
<> 144:ef7eb2e8f9f7 469 * This function initializes the FlexCAN configure structure to default value. The default
<> 144:ef7eb2e8f9f7 470 * value are:
<> 144:ef7eb2e8f9f7 471 * flexcanConfig->clkSrc = KFLEXCAN_ClkSrcOsc;
<> 144:ef7eb2e8f9f7 472 * flexcanConfig->baudRate = 125000U;
<> 144:ef7eb2e8f9f7 473 * flexcanConfig->maxMbNum = 16;
<> 144:ef7eb2e8f9f7 474 * flexcanConfig->enableLoopBack = false;
<> 144:ef7eb2e8f9f7 475 * flexcanConfig->enableSelfWakeup = false;
<> 144:ef7eb2e8f9f7 476 * flexcanConfig->enableIndividMask = false;
<> 144:ef7eb2e8f9f7 477 * flexcanConfig->enableDoze = false;
<> 144:ef7eb2e8f9f7 478 *
<> 144:ef7eb2e8f9f7 479 * @param config Pointer to FlexCAN configuration structure.
<> 144:ef7eb2e8f9f7 480 */
<> 144:ef7eb2e8f9f7 481 void FLEXCAN_GetDefaultConfig(flexcan_config_t *config);
<> 144:ef7eb2e8f9f7 482
<> 144:ef7eb2e8f9f7 483 /* @} */
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 /*!
<> 144:ef7eb2e8f9f7 486 * @name Configuration.
<> 144:ef7eb2e8f9f7 487 * @{
<> 144:ef7eb2e8f9f7 488 */
<> 144:ef7eb2e8f9f7 489
<> 144:ef7eb2e8f9f7 490 /*!
<> 144:ef7eb2e8f9f7 491 * @brief Sets the FlexCAN protocol timing characteristic.
<> 144:ef7eb2e8f9f7 492 *
<> 144:ef7eb2e8f9f7 493 * This function gives user settings to CAN bus timing characteristic.
<> 144:ef7eb2e8f9f7 494 * The function is for an experienced user. For less experienced users, call
<> 144:ef7eb2e8f9f7 495 * the FLEXCAN_Init() and fill the baud rate field with a desired value.
<> 144:ef7eb2e8f9f7 496 * This provides the default timing characteristics to the module.
<> 144:ef7eb2e8f9f7 497 *
<> 144:ef7eb2e8f9f7 498 * Note that calling FLEXCAN_SetTimingConfig() overrides the baud rate set
<> 144:ef7eb2e8f9f7 499 * in FLEXCAN_Init().
<> 144:ef7eb2e8f9f7 500 *
<> 144:ef7eb2e8f9f7 501 * @param base FlexCAN peripheral base address.
<> 144:ef7eb2e8f9f7 502 * @param config Pointer to the timing configuration structure.
<> 144:ef7eb2e8f9f7 503 */
<> 144:ef7eb2e8f9f7 504 void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *config);
<> 144:ef7eb2e8f9f7 505
<> 144:ef7eb2e8f9f7 506 /*!
<> 144:ef7eb2e8f9f7 507 * @brief Sets the FlexCAN receive message buffer global mask.
<> 144:ef7eb2e8f9f7 508 *
<> 144:ef7eb2e8f9f7 509 * This function sets the global mask for FlexCAN message buffer in a matching process.
<> 144:ef7eb2e8f9f7 510 * The configuration is only effective when the Rx individual mask is disabled in the FLEXCAN_Init().
<> 144:ef7eb2e8f9f7 511 *
<> 144:ef7eb2e8f9f7 512 * @param base FlexCAN peripheral base address.
<> 144:ef7eb2e8f9f7 513 * @param mask Rx Message Buffer Global Mask value.
<> 144:ef7eb2e8f9f7 514 */
<> 144:ef7eb2e8f9f7 515 void FlEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask);
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517 /*!
<> 144:ef7eb2e8f9f7 518 * @brief Sets the FlexCAN receive FIFO global mask.
<> 144:ef7eb2e8f9f7 519 *
<> 144:ef7eb2e8f9f7 520 * This function sets the global mask for FlexCAN FIFO in a matching process.
<> 144:ef7eb2e8f9f7 521 *
<> 144:ef7eb2e8f9f7 522 * @param base FlexCAN peripheral base address.
<> 144:ef7eb2e8f9f7 523 * @param mask Rx Fifo Global Mask value.
<> 144:ef7eb2e8f9f7 524 */
<> 144:ef7eb2e8f9f7 525 void FlEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask);
<> 144:ef7eb2e8f9f7 526
<> 144:ef7eb2e8f9f7 527 /*!
<> 144:ef7eb2e8f9f7 528 * @brief Sets the FlexCAN receive individual mask.
<> 144:ef7eb2e8f9f7 529 *
<> 144:ef7eb2e8f9f7 530 * This function sets the individual mask for FlexCAN matching process.
<> 144:ef7eb2e8f9f7 531 * The configuration is only effective when the Rx individual mask is enabled in FLEXCAN_Init().
<> 144:ef7eb2e8f9f7 532 * If Rx FIFO is disabled, the individual mask is applied to the corresponding Message Buffer.
<> 144:ef7eb2e8f9f7 533 * If Rx FIFO is enabled, the individual mask for Rx FIFO occupied Message Buffer is applied to
<> 144:ef7eb2e8f9f7 534 * the Rx Filter with same index. What calls for special attention is that only the first 32
<> 144:ef7eb2e8f9f7 535 * individual masks can be used as Rx FIFO filter mask.
<> 144:ef7eb2e8f9f7 536 *
<> 144:ef7eb2e8f9f7 537 * @param base FlexCAN peripheral base address.
<> 144:ef7eb2e8f9f7 538 * @param maskIdx The Index of individual Mask.
<> 144:ef7eb2e8f9f7 539 * @param mask Rx Individual Mask value.
<> 144:ef7eb2e8f9f7 540 */
<> 144:ef7eb2e8f9f7 541 void FlEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask);
<> 144:ef7eb2e8f9f7 542
<> 144:ef7eb2e8f9f7 543 /*!
<> 144:ef7eb2e8f9f7 544 * @brief Configures a FlexCAN transmit message buffer.
<> 144:ef7eb2e8f9f7 545 *
<> 144:ef7eb2e8f9f7 546 * This function aborts the previous transmission, cleans the Message Buffer, and
<> 144:ef7eb2e8f9f7 547 * configures it as a Transmit Message Buffer.
<> 144:ef7eb2e8f9f7 548 *
<> 144:ef7eb2e8f9f7 549 * @param base FlexCAN peripheral base address.
<> 144:ef7eb2e8f9f7 550 * @param mbIdx The Message Buffer index.
<> 144:ef7eb2e8f9f7 551 * @param enable Enable/Disable Tx Message Buffer.
<> 144:ef7eb2e8f9f7 552 * - true: Enable Tx Message Buffer.
<> 144:ef7eb2e8f9f7 553 * - false: Disable Tx Message Buffer.
<> 144:ef7eb2e8f9f7 554 */
<> 144:ef7eb2e8f9f7 555 void FLEXCAN_SetTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable);
<> 144:ef7eb2e8f9f7 556
<> 144:ef7eb2e8f9f7 557 /*!
<> 144:ef7eb2e8f9f7 558 * @brief Configures a FlexCAN Receive Message Buffer.
<> 144:ef7eb2e8f9f7 559 *
<> 144:ef7eb2e8f9f7 560 * This function cleans a FlexCAN build-in Message Buffer and configures it
<> 144:ef7eb2e8f9f7 561 * as a Receive Message Buffer.
<> 144:ef7eb2e8f9f7 562 *
<> 144:ef7eb2e8f9f7 563 * @param base FlexCAN peripheral base address.
<> 144:ef7eb2e8f9f7 564 * @param mbIdx The Message Buffer index.
<> 144:ef7eb2e8f9f7 565 * @param config Pointer to FlexCAN Message Buffer configuration structure.
<> 144:ef7eb2e8f9f7 566 * @param enable Enable/Disable Rx Message Buffer.
<> 144:ef7eb2e8f9f7 567 * - true: Enable Rx Message Buffer.
<> 144:ef7eb2e8f9f7 568 * - false: Disable Rx Message Buffer.
<> 144:ef7eb2e8f9f7 569 */
<> 144:ef7eb2e8f9f7 570 void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *config, bool enable);
<> 144:ef7eb2e8f9f7 571
<> 144:ef7eb2e8f9f7 572 /*!
<> 144:ef7eb2e8f9f7 573 * @brief Configures the FlexCAN Rx FIFO.
<> 144:ef7eb2e8f9f7 574 *
<> 144:ef7eb2e8f9f7 575 * This function configures the Rx FIFO with given Rx FIFO configuration.
<> 144:ef7eb2e8f9f7 576 *
<> 144:ef7eb2e8f9f7 577 * @param base FlexCAN peripheral base address.
<> 144:ef7eb2e8f9f7 578 * @param config Pointer to FlexCAN Rx FIFO configuration structure.
<> 144:ef7eb2e8f9f7 579 * @param enable Enable/Disable Rx FIFO.
<> 144:ef7eb2e8f9f7 580 * - true: Enable Rx FIFO.
<> 144:ef7eb2e8f9f7 581 * - false: Disable Rx FIFO.
<> 144:ef7eb2e8f9f7 582 */
<> 144:ef7eb2e8f9f7 583 void FlEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable);
<> 144:ef7eb2e8f9f7 584
<> 144:ef7eb2e8f9f7 585 /* @} */
<> 144:ef7eb2e8f9f7 586
<> 144:ef7eb2e8f9f7 587 /*!
<> 144:ef7eb2e8f9f7 588 * @name Status
<> 144:ef7eb2e8f9f7 589 * @{
<> 144:ef7eb2e8f9f7 590 */
<> 144:ef7eb2e8f9f7 591
<> 144:ef7eb2e8f9f7 592 /*!
<> 144:ef7eb2e8f9f7 593 * @brief Gets the FlexCAN module interrupt flags.
<> 144:ef7eb2e8f9f7 594 *
<> 144:ef7eb2e8f9f7 595 * This function gets all FlexCAN status flags. The flags are returned as the logical
<> 144:ef7eb2e8f9f7 596 * OR value of the enumerators @ref _flexcan_flags. To check the specific status,
<> 144:ef7eb2e8f9f7 597 * compare the return value with enumerators in @ref _flexcan_flags.
<> 144:ef7eb2e8f9f7 598 *
<> 144:ef7eb2e8f9f7 599 * @param base FlexCAN peripheral base address.
<> 144:ef7eb2e8f9f7 600 * @return FlexCAN status flags which are ORed by the enumerators in the _flexcan_flags.
<> 144:ef7eb2e8f9f7 601 */
<> 144:ef7eb2e8f9f7 602 static inline uint32_t FLEXCAN_GetStatusFlags(CAN_Type *base)
<> 144:ef7eb2e8f9f7 603 {
<> 144:ef7eb2e8f9f7 604 return base->ESR1;
<> 144:ef7eb2e8f9f7 605 }
<> 144:ef7eb2e8f9f7 606
<> 144:ef7eb2e8f9f7 607 /*!
<> 144:ef7eb2e8f9f7 608 * @brief Clears status flags with the provided mask.
<> 144:ef7eb2e8f9f7 609 *
<> 144:ef7eb2e8f9f7 610 * This function clears the FlexCAN status flags with a provided mask. An automatically cleared flag
<> 144:ef7eb2e8f9f7 611 * can't be cleared by this function.
<> 144:ef7eb2e8f9f7 612 *
<> 144:ef7eb2e8f9f7 613 * @param base FlexCAN peripheral base address.
<> 144:ef7eb2e8f9f7 614 * @param mask The status flags to be cleared, it is logical OR value of @ref _flexcan_flags.
<> 144:ef7eb2e8f9f7 615 */
<> 144:ef7eb2e8f9f7 616 static inline void FLEXCAN_ClearStatusFlags(CAN_Type *base, uint32_t mask)
<> 144:ef7eb2e8f9f7 617 {
<> 144:ef7eb2e8f9f7 618 /* Write 1 to clear status flag. */
<> 144:ef7eb2e8f9f7 619 base->ESR1 = mask;
<> 144:ef7eb2e8f9f7 620 }
<> 144:ef7eb2e8f9f7 621
<> 144:ef7eb2e8f9f7 622 /*!
<> 144:ef7eb2e8f9f7 623 * @brief Gets the FlexCAN Bus Error Counter value.
<> 144:ef7eb2e8f9f7 624 *
<> 144:ef7eb2e8f9f7 625 * This function gets the FlexCAN Bus Error Counter value for both Tx and
<> 144:ef7eb2e8f9f7 626 * Rx direction. These values may be needed in the upper layer error handling.
<> 144:ef7eb2e8f9f7 627 *
<> 144:ef7eb2e8f9f7 628 * @param base FlexCAN peripheral base address.
<> 144:ef7eb2e8f9f7 629 * @param txErrBuf Buffer to store Tx Error Counter value.
<> 144:ef7eb2e8f9f7 630 * @param rxErrBuf Buffer to store Rx Error Counter value.
<> 144:ef7eb2e8f9f7 631 */
<> 144:ef7eb2e8f9f7 632 static inline void FlEXCAN_GetBusErrCount(CAN_Type *base, uint8_t *txErrBuf, uint8_t *rxErrBuf)
<> 144:ef7eb2e8f9f7 633 {
<> 144:ef7eb2e8f9f7 634 if (txErrBuf)
<> 144:ef7eb2e8f9f7 635 {
<> 144:ef7eb2e8f9f7 636 *txErrBuf = (uint8_t)((base->ECR & CAN_ECR_TXERRCNT_MASK) >> CAN_ECR_TXERRCNT_SHIFT);
<> 144:ef7eb2e8f9f7 637 }
<> 144:ef7eb2e8f9f7 638
<> 144:ef7eb2e8f9f7 639 if (rxErrBuf)
<> 144:ef7eb2e8f9f7 640 {
<> 144:ef7eb2e8f9f7 641 *rxErrBuf = (uint8_t)((base->ECR & CAN_ECR_RXERRCNT_MASK) >> CAN_ECR_RXERRCNT_SHIFT);
<> 144:ef7eb2e8f9f7 642 }
<> 144:ef7eb2e8f9f7 643 }
<> 144:ef7eb2e8f9f7 644
<> 144:ef7eb2e8f9f7 645 /*!
<> 144:ef7eb2e8f9f7 646 * @brief Gets the FlexCAN Message Buffer interrupt flags.
<> 144:ef7eb2e8f9f7 647 *
<> 144:ef7eb2e8f9f7 648 * This function gets the interrupt flags of a given Message Buffers.
<> 144:ef7eb2e8f9f7 649 *
<> 144:ef7eb2e8f9f7 650 * @param base FlexCAN peripheral base address.
<> 144:ef7eb2e8f9f7 651 * @param mask The ORed FlexCAN Message Buffer mask.
<> 144:ef7eb2e8f9f7 652 * @return The status of given Message Buffers.
<> 144:ef7eb2e8f9f7 653 */
<> 144:ef7eb2e8f9f7 654 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
<> 144:ef7eb2e8f9f7 655 static inline uint64_t FLEXCAN_GetMbStatusFlags(CAN_Type *base, uint64_t mask)
<> 144:ef7eb2e8f9f7 656 #else
<> 144:ef7eb2e8f9f7 657 static inline uint32_t FLEXCAN_GetMbStatusFlags(CAN_Type *base, uint32_t mask)
<> 144:ef7eb2e8f9f7 658 #endif
<> 144:ef7eb2e8f9f7 659 {
<> 144:ef7eb2e8f9f7 660 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
<> 144:ef7eb2e8f9f7 661 return ((((uint64_t)base->IFLAG1) & mask) | ((((uint64_t)base->IFLAG2) << 32) & mask));
<> 144:ef7eb2e8f9f7 662 #else
<> 144:ef7eb2e8f9f7 663 return (base->IFLAG1 & mask);
<> 144:ef7eb2e8f9f7 664 #endif
<> 144:ef7eb2e8f9f7 665 }
<> 144:ef7eb2e8f9f7 666
<> 144:ef7eb2e8f9f7 667 /*!
<> 144:ef7eb2e8f9f7 668 * @brief Clears the FlexCAN Message Buffer interrupt flags.
<> 144:ef7eb2e8f9f7 669 *
<> 144:ef7eb2e8f9f7 670 * This function clears the interrupt flags of a given Message Buffers.
<> 144:ef7eb2e8f9f7 671 *
<> 144:ef7eb2e8f9f7 672 * @param base FlexCAN peripheral base address.
<> 144:ef7eb2e8f9f7 673 * @param mask The ORed FlexCAN Message Buffer mask.
<> 144:ef7eb2e8f9f7 674 */
<> 144:ef7eb2e8f9f7 675 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
<> 144:ef7eb2e8f9f7 676 static inline void FLEXCAN_ClearMbStatusFlags(CAN_Type *base, uint64_t mask)
<> 144:ef7eb2e8f9f7 677 #else
<> 144:ef7eb2e8f9f7 678 static inline void FLEXCAN_ClearMbStatusFlags(CAN_Type *base, uint32_t mask)
<> 144:ef7eb2e8f9f7 679 #endif
<> 144:ef7eb2e8f9f7 680 {
<> 144:ef7eb2e8f9f7 681 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
<> 144:ef7eb2e8f9f7 682 base->IFLAG1 = (uint32_t)(mask & 0xFFFFFFFF);
<> 144:ef7eb2e8f9f7 683 base->IFLAG2 = (uint32_t)(mask >> 32);
<> 144:ef7eb2e8f9f7 684 #else
<> 144:ef7eb2e8f9f7 685 base->IFLAG1 = mask;
<> 144:ef7eb2e8f9f7 686 #endif
<> 144:ef7eb2e8f9f7 687 }
<> 144:ef7eb2e8f9f7 688
<> 144:ef7eb2e8f9f7 689 /* @} */
<> 144:ef7eb2e8f9f7 690
<> 144:ef7eb2e8f9f7 691 /*!
<> 144:ef7eb2e8f9f7 692 * @name Interrupts
<> 144:ef7eb2e8f9f7 693 * @{
<> 144:ef7eb2e8f9f7 694 */
<> 144:ef7eb2e8f9f7 695
<> 144:ef7eb2e8f9f7 696 /*!
<> 144:ef7eb2e8f9f7 697 * @brief Enables FlexCAN interrupts according to provided mask.
<> 144:ef7eb2e8f9f7 698 *
<> 144:ef7eb2e8f9f7 699 * This function enables the FlexCAN interrupts according to provided mask. The mask
<> 144:ef7eb2e8f9f7 700 * is a logical OR of enumeration members, see @ref _flexcan_interrupt_enable.
<> 144:ef7eb2e8f9f7 701 *
<> 144:ef7eb2e8f9f7 702 * @param base FlexCAN peripheral base address.
<> 144:ef7eb2e8f9f7 703 * @param mask The interrupts to enable. Logical OR of @ref _flexcan_interrupt_enable.
<> 144:ef7eb2e8f9f7 704 */
<> 144:ef7eb2e8f9f7 705 static inline void FLEXCAN_EnableInterrupts(CAN_Type *base, uint32_t mask)
<> 144:ef7eb2e8f9f7 706 {
<> 144:ef7eb2e8f9f7 707 /* Solve Wake Up Interrupt. */
<> 144:ef7eb2e8f9f7 708 if (mask & kFLEXCAN_WakeUpInterruptEnable)
<> 144:ef7eb2e8f9f7 709 {
<> 144:ef7eb2e8f9f7 710 base->MCR |= CAN_MCR_WAKMSK_MASK;
<> 144:ef7eb2e8f9f7 711 }
<> 144:ef7eb2e8f9f7 712
<> 144:ef7eb2e8f9f7 713 /* Solve others. */
<> 144:ef7eb2e8f9f7 714 base->CTRL1 |= (mask & (~((uint32_t)kFLEXCAN_WakeUpInterruptEnable)));
<> 144:ef7eb2e8f9f7 715 }
<> 144:ef7eb2e8f9f7 716
<> 144:ef7eb2e8f9f7 717 /*!
<> 144:ef7eb2e8f9f7 718 * @brief Disables FlexCAN interrupts according to provided mask.
<> 144:ef7eb2e8f9f7 719 *
<> 144:ef7eb2e8f9f7 720 * This function disables the FlexCAN interrupts according to provided mask. The mask
<> 144:ef7eb2e8f9f7 721 * is a logical OR of enumeration members, see @ref _flexcan_interrupt_enable.
<> 144:ef7eb2e8f9f7 722 *
<> 144:ef7eb2e8f9f7 723 * @param base FlexCAN peripheral base address.
<> 144:ef7eb2e8f9f7 724 * @param mask The interrupts to disable. Logical OR of @ref _flexcan_interrupt_enable.
<> 144:ef7eb2e8f9f7 725 */
<> 144:ef7eb2e8f9f7 726 static inline void FLEXCAN_DisableInterrupts(CAN_Type *base, uint32_t mask)
<> 144:ef7eb2e8f9f7 727 {
<> 144:ef7eb2e8f9f7 728 /* Solve Wake Up Interrupt. */
<> 144:ef7eb2e8f9f7 729 if (mask & kFLEXCAN_WakeUpInterruptEnable)
<> 144:ef7eb2e8f9f7 730 {
<> 144:ef7eb2e8f9f7 731 base->MCR &= ~CAN_MCR_WAKMSK_MASK;
<> 144:ef7eb2e8f9f7 732 }
<> 144:ef7eb2e8f9f7 733
<> 144:ef7eb2e8f9f7 734 /* Solve others. */
<> 144:ef7eb2e8f9f7 735 base->CTRL1 &= ~(mask & (~((uint32_t)kFLEXCAN_WakeUpInterruptEnable)));
<> 144:ef7eb2e8f9f7 736 }
<> 144:ef7eb2e8f9f7 737
<> 144:ef7eb2e8f9f7 738 /*!
<> 144:ef7eb2e8f9f7 739 * @brief Enables FlexCAN Message Buffer interrupts.
<> 144:ef7eb2e8f9f7 740 *
<> 144:ef7eb2e8f9f7 741 * This function enables the interrupts of given Message Buffers
<> 144:ef7eb2e8f9f7 742 *
<> 144:ef7eb2e8f9f7 743 * @param base FlexCAN peripheral base address.
<> 144:ef7eb2e8f9f7 744 * @param mask The ORed FlexCAN Message Buffer mask.
<> 144:ef7eb2e8f9f7 745 */
<> 144:ef7eb2e8f9f7 746 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
<> 144:ef7eb2e8f9f7 747 static inline void FLEXCAN_EnableMbInterrupts(CAN_Type *base, uint64_t mask)
<> 144:ef7eb2e8f9f7 748 #else
<> 144:ef7eb2e8f9f7 749 static inline void FLEXCAN_EnableMbInterrupts(CAN_Type *base, uint32_t mask)
<> 144:ef7eb2e8f9f7 750 #endif
<> 144:ef7eb2e8f9f7 751 {
<> 144:ef7eb2e8f9f7 752 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
<> 144:ef7eb2e8f9f7 753 base->IMASK1 |= (uint32_t)(mask & 0xFFFFFFFF);
<> 144:ef7eb2e8f9f7 754 base->IMASK2 |= (uint32_t)(mask >> 32);
<> 144:ef7eb2e8f9f7 755 #else
<> 144:ef7eb2e8f9f7 756 base->IMASK1 |= mask;
<> 144:ef7eb2e8f9f7 757 #endif
<> 144:ef7eb2e8f9f7 758 }
<> 144:ef7eb2e8f9f7 759
<> 144:ef7eb2e8f9f7 760 /*!
<> 144:ef7eb2e8f9f7 761 * @brief Disables FlexCAN Message Buffer interrupts.
<> 144:ef7eb2e8f9f7 762 *
<> 144:ef7eb2e8f9f7 763 * This function disables the interrupts of given Message Buffers
<> 144:ef7eb2e8f9f7 764 *
<> 144:ef7eb2e8f9f7 765 * @param base FlexCAN peripheral base address.
<> 144:ef7eb2e8f9f7 766 * @param mask The ORed FlexCAN Message Buffer mask.
<> 144:ef7eb2e8f9f7 767 */
<> 144:ef7eb2e8f9f7 768 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
<> 144:ef7eb2e8f9f7 769 static inline void FLEXCAN_DisableMbInterrupts(CAN_Type *base, uint64_t mask)
<> 144:ef7eb2e8f9f7 770 #else
<> 144:ef7eb2e8f9f7 771 static inline void FLEXCAN_DisableMbInterrupts(CAN_Type *base, uint32_t mask)
<> 144:ef7eb2e8f9f7 772 #endif
<> 144:ef7eb2e8f9f7 773 {
<> 144:ef7eb2e8f9f7 774 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
<> 144:ef7eb2e8f9f7 775 base->IMASK1 &= ~((uint32_t)(mask & 0xFFFFFFFF));
<> 144:ef7eb2e8f9f7 776 base->IMASK2 &= ~((uint32_t)(mask >> 32));
<> 144:ef7eb2e8f9f7 777 #else
<> 144:ef7eb2e8f9f7 778 base->IMASK1 &= ~mask;
<> 144:ef7eb2e8f9f7 779 #endif
<> 144:ef7eb2e8f9f7 780 }
<> 144:ef7eb2e8f9f7 781
<> 144:ef7eb2e8f9f7 782 /* @} */
<> 144:ef7eb2e8f9f7 783
<> 144:ef7eb2e8f9f7 784 #if (defined(FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) && FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA)
<> 144:ef7eb2e8f9f7 785 /*!
<> 144:ef7eb2e8f9f7 786 * @name DMA Control
<> 144:ef7eb2e8f9f7 787 * @{
<> 144:ef7eb2e8f9f7 788 */
<> 144:ef7eb2e8f9f7 789
<> 144:ef7eb2e8f9f7 790 /*!
<> 144:ef7eb2e8f9f7 791 * @brief Enables or disables the FlexCAN Rx FIFO DMA request.
<> 144:ef7eb2e8f9f7 792 *
<> 144:ef7eb2e8f9f7 793 * This function enables or disables the DMA feature of FlexCAN build-in Rx FIFO.
<> 144:ef7eb2e8f9f7 794 *
<> 144:ef7eb2e8f9f7 795 * @param base FlexCAN peripheral base address.
<> 144:ef7eb2e8f9f7 796 * @param enable true to enable, false to disable.
<> 144:ef7eb2e8f9f7 797 */
<> 144:ef7eb2e8f9f7 798 void FLEXCAN_EnableRxFifoDMA(CAN_Type *base, bool enable);
<> 144:ef7eb2e8f9f7 799
<> 144:ef7eb2e8f9f7 800 /*!
<> 144:ef7eb2e8f9f7 801 * @brief Gets the Rx FIFO Head address.
<> 144:ef7eb2e8f9f7 802 *
<> 144:ef7eb2e8f9f7 803 * This function returns the FlexCAN Rx FIFO Head address, which is mainly used for the DMA/eDMA use case.
<> 144:ef7eb2e8f9f7 804 *
<> 144:ef7eb2e8f9f7 805 * @param base FlexCAN peripheral base address.
<> 144:ef7eb2e8f9f7 806 * @return FlexCAN Rx FIFO Head address.
<> 144:ef7eb2e8f9f7 807 */
<> 144:ef7eb2e8f9f7 808 static inline uint32_t FLEXCAN_GetRxFifoHeadAddr(CAN_Type *base)
<> 144:ef7eb2e8f9f7 809 {
<> 144:ef7eb2e8f9f7 810 return (uint32_t) & (base->MB[0].CS);
<> 144:ef7eb2e8f9f7 811 }
<> 144:ef7eb2e8f9f7 812
<> 144:ef7eb2e8f9f7 813 /* @} */
<> 144:ef7eb2e8f9f7 814 #endif /* FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA */
<> 144:ef7eb2e8f9f7 815
<> 144:ef7eb2e8f9f7 816 /*!
<> 144:ef7eb2e8f9f7 817 * @name Bus Operations
<> 144:ef7eb2e8f9f7 818 * @{
<> 144:ef7eb2e8f9f7 819 */
<> 144:ef7eb2e8f9f7 820
<> 144:ef7eb2e8f9f7 821 /*!
<> 144:ef7eb2e8f9f7 822 * @brief Enables or disables the FlexCAN module operation.
<> 144:ef7eb2e8f9f7 823 *
<> 144:ef7eb2e8f9f7 824 * This function enables or disables the FlexCAN module.
<> 144:ef7eb2e8f9f7 825 *
<> 144:ef7eb2e8f9f7 826 * @param base FlexCAN base pointer.
<> 144:ef7eb2e8f9f7 827 * @param enable true to enable, false to disable.
<> 144:ef7eb2e8f9f7 828 */
<> 144:ef7eb2e8f9f7 829 static inline void FLEXCAN_Enable(CAN_Type *base, bool enable)
<> 144:ef7eb2e8f9f7 830 {
<> 144:ef7eb2e8f9f7 831 if (enable)
<> 144:ef7eb2e8f9f7 832 {
<> 144:ef7eb2e8f9f7 833 base->MCR &= ~CAN_MCR_MDIS_MASK;
<> 144:ef7eb2e8f9f7 834
<> 144:ef7eb2e8f9f7 835 /* Wait FlexCAN exit from low-power mode. */
<> 144:ef7eb2e8f9f7 836 while (base->MCR & CAN_MCR_LPMACK_MASK)
<> 144:ef7eb2e8f9f7 837 {
<> 144:ef7eb2e8f9f7 838 }
<> 144:ef7eb2e8f9f7 839 }
<> 144:ef7eb2e8f9f7 840 else
<> 144:ef7eb2e8f9f7 841 {
<> 144:ef7eb2e8f9f7 842 base->MCR |= CAN_MCR_MDIS_MASK;
<> 144:ef7eb2e8f9f7 843
<> 144:ef7eb2e8f9f7 844 /* Wait FlexCAN enter low-power mode. */
<> 144:ef7eb2e8f9f7 845 while (!(base->MCR & CAN_MCR_LPMACK_MASK))
<> 144:ef7eb2e8f9f7 846 {
<> 144:ef7eb2e8f9f7 847 }
<> 144:ef7eb2e8f9f7 848 }
<> 144:ef7eb2e8f9f7 849 }
<> 144:ef7eb2e8f9f7 850
<> 144:ef7eb2e8f9f7 851 /*!
<> 144:ef7eb2e8f9f7 852 * @brief Writes a FlexCAN Message to Transmit Message Buffer.
<> 144:ef7eb2e8f9f7 853 *
<> 144:ef7eb2e8f9f7 854 * This function writes a CAN Message to the specified Transmit Message Buffer
<> 144:ef7eb2e8f9f7 855 * and changes the Message Buffer state to start CAN Message transmit. After
<> 144:ef7eb2e8f9f7 856 * that the function returns immediately.
<> 144:ef7eb2e8f9f7 857 *
<> 144:ef7eb2e8f9f7 858 * @param base FlexCAN peripheral base address.
<> 144:ef7eb2e8f9f7 859 * @param mbIdx The FlexCAN Message Buffer index.
<> 144:ef7eb2e8f9f7 860 * @param txFrame Pointer to CAN message frame to be sent.
<> 144:ef7eb2e8f9f7 861 * @retval kStatus_Success - Write Tx Message Buffer Successfully.
<> 144:ef7eb2e8f9f7 862 * @retval kStatus_Fail - Tx Message Buffer is currently in use.
<> 144:ef7eb2e8f9f7 863 */
<> 144:ef7eb2e8f9f7 864 status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t *txFrame);
<> 144:ef7eb2e8f9f7 865
<> 144:ef7eb2e8f9f7 866 /*!
<> 144:ef7eb2e8f9f7 867 * @brief Reads a FlexCAN Message from Receive Message Buffer.
<> 144:ef7eb2e8f9f7 868 *
<> 144:ef7eb2e8f9f7 869 * This function reads a CAN message from a specified Receive Message Buffer.
<> 144:ef7eb2e8f9f7 870 * The function fills a receive CAN message frame structure with
<> 144:ef7eb2e8f9f7 871 * just received data and activates the Message Buffer again.
<> 144:ef7eb2e8f9f7 872 * The function returns immediately.
<> 144:ef7eb2e8f9f7 873 *
<> 144:ef7eb2e8f9f7 874 * @param base FlexCAN peripheral base address.
<> 144:ef7eb2e8f9f7 875 * @param mbIdx The FlexCAN Message Buffer index.
<> 144:ef7eb2e8f9f7 876 * @param rxFrame Pointer to CAN message frame structure for reception.
<> 144:ef7eb2e8f9f7 877 * @retval kStatus_Success - Rx Message Buffer is full and has been read successfully.
<> 144:ef7eb2e8f9f7 878 * @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully.
<> 144:ef7eb2e8f9f7 879 * @retval kStatus_Fail - Rx Message Buffer is empty.
<> 144:ef7eb2e8f9f7 880 */
<> 144:ef7eb2e8f9f7 881 status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame);
<> 144:ef7eb2e8f9f7 882
<> 144:ef7eb2e8f9f7 883 /*!
<> 144:ef7eb2e8f9f7 884 * @brief Reads a FlexCAN Message from Rx FIFO.
<> 144:ef7eb2e8f9f7 885 *
<> 144:ef7eb2e8f9f7 886 * This function reads a CAN message from the FlexCAN build-in Rx FIFO.
<> 144:ef7eb2e8f9f7 887 *
<> 144:ef7eb2e8f9f7 888 * @param base FlexCAN peripheral base address.
<> 144:ef7eb2e8f9f7 889 * @param rxFrame Pointer to CAN message frame structure for reception.
<> 144:ef7eb2e8f9f7 890 * @retval kStatus_Success - Read Message from Rx FIFO successfully.
<> 144:ef7eb2e8f9f7 891 * @retval kStatus_Fail - Rx FIFO is not enabled.
<> 144:ef7eb2e8f9f7 892 */
<> 144:ef7eb2e8f9f7 893 status_t FlEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame);
<> 144:ef7eb2e8f9f7 894
<> 144:ef7eb2e8f9f7 895 /* @} */
<> 144:ef7eb2e8f9f7 896
<> 144:ef7eb2e8f9f7 897 /*!
<> 144:ef7eb2e8f9f7 898 * @name Transactional
<> 144:ef7eb2e8f9f7 899 * @{
<> 144:ef7eb2e8f9f7 900 */
<> 144:ef7eb2e8f9f7 901
<> 144:ef7eb2e8f9f7 902 /*!
<> 144:ef7eb2e8f9f7 903 * @brief Performs a polling send transaction on the CAN bus.
<> 144:ef7eb2e8f9f7 904 *
<> 144:ef7eb2e8f9f7 905 * Note that a transfer handle does not need to be created before calling this API.
<> 144:ef7eb2e8f9f7 906 *
<> 144:ef7eb2e8f9f7 907 * @param base FlexCAN peripheral base pointer.
<> 144:ef7eb2e8f9f7 908 * @param mbIdx The FlexCAN Message Buffer index.
<> 144:ef7eb2e8f9f7 909 * @param txFrame Pointer to CAN message frame to be sent.
<> 144:ef7eb2e8f9f7 910 * @retval kStatus_Success - Write Tx Message Buffer Successfully.
<> 144:ef7eb2e8f9f7 911 * @retval kStatus_Fail - Tx Message Buffer is currently in use.
<> 144:ef7eb2e8f9f7 912 */
<> 144:ef7eb2e8f9f7 913 status_t FlEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame);
<> 144:ef7eb2e8f9f7 914
<> 144:ef7eb2e8f9f7 915 /*!
<> 144:ef7eb2e8f9f7 916 * @brief Performs a polling receive transaction on the CAN bus.
<> 144:ef7eb2e8f9f7 917 *
<> 144:ef7eb2e8f9f7 918 * Note that a transfer handle does not need to be created before calling this API.
<> 144:ef7eb2e8f9f7 919 *
<> 144:ef7eb2e8f9f7 920 * @param base FlexCAN peripheral base pointer.
<> 144:ef7eb2e8f9f7 921 * @param mbIdx The FlexCAN Message Buffer index.
<> 144:ef7eb2e8f9f7 922 * @param rxFrame Pointer to CAN message frame structure for reception.
<> 144:ef7eb2e8f9f7 923 * @retval kStatus_Success - Rx Message Buffer is full and has been read successfully.
<> 144:ef7eb2e8f9f7 924 * @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully.
<> 144:ef7eb2e8f9f7 925 * @retval kStatus_Fail - Rx Message Buffer is empty.
<> 144:ef7eb2e8f9f7 926 */
<> 144:ef7eb2e8f9f7 927 status_t FlEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame);
<> 144:ef7eb2e8f9f7 928
<> 144:ef7eb2e8f9f7 929 /*!
<> 144:ef7eb2e8f9f7 930 * @brief Performs a polling receive transaction from Rx FIFO on the CAN bus.
<> 144:ef7eb2e8f9f7 931 *
<> 144:ef7eb2e8f9f7 932 * Note that a transfer handle does not need to be created before calling this API.
<> 144:ef7eb2e8f9f7 933 *
<> 144:ef7eb2e8f9f7 934 * @param base FlexCAN peripheral base pointer.
<> 144:ef7eb2e8f9f7 935 * @param rxFrame Pointer to CAN message frame structure for reception.
<> 144:ef7eb2e8f9f7 936 * @retval kStatus_Success - Read Message from Rx FIFO successfully.
<> 144:ef7eb2e8f9f7 937 * @retval kStatus_Fail - Rx FIFO is not enabled.
<> 144:ef7eb2e8f9f7 938 */
<> 144:ef7eb2e8f9f7 939 status_t FlEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame);
<> 144:ef7eb2e8f9f7 940
<> 144:ef7eb2e8f9f7 941 /*!
<> 144:ef7eb2e8f9f7 942 * @brief Initializes the FlexCAN handle.
<> 144:ef7eb2e8f9f7 943 *
<> 144:ef7eb2e8f9f7 944 * This function initializes the FlexCAN handle which can be used for other FlexCAN
<> 144:ef7eb2e8f9f7 945 * transactional APIs. Usually, for a specified FlexCAN instance,
<> 144:ef7eb2e8f9f7 946 * call this API once to get the initialized handle.
<> 144:ef7eb2e8f9f7 947 *
<> 144:ef7eb2e8f9f7 948 * @param base FlexCAN peripheral base address.
<> 144:ef7eb2e8f9f7 949 * @param handle FlexCAN handle pointer.
<> 144:ef7eb2e8f9f7 950 * @param callback The callback function.
<> 144:ef7eb2e8f9f7 951 * @param userData The parameter of the callback function.
<> 144:ef7eb2e8f9f7 952 */
<> 144:ef7eb2e8f9f7 953 void FLEXCAN_TransferCreateHandle(CAN_Type *base,
<> 144:ef7eb2e8f9f7 954 flexcan_handle_t *handle,
<> 144:ef7eb2e8f9f7 955 flexcan_transfer_callback_t callback,
<> 144:ef7eb2e8f9f7 956 void *userData);
<> 144:ef7eb2e8f9f7 957
<> 144:ef7eb2e8f9f7 958 /*!
<> 144:ef7eb2e8f9f7 959 * @brief Sends a message using IRQ.
<> 144:ef7eb2e8f9f7 960 *
<> 144:ef7eb2e8f9f7 961 * This function sends a message using IRQ. This is a non-blocking function, which returns
<> 144:ef7eb2e8f9f7 962 * right away. When messages have been sent out, the send callback function is called.
<> 144:ef7eb2e8f9f7 963 *
<> 144:ef7eb2e8f9f7 964 * @param base FlexCAN peripheral base address.
<> 144:ef7eb2e8f9f7 965 * @param handle FlexCAN handle pointer.
<> 144:ef7eb2e8f9f7 966 * @param xfer FlexCAN Message Buffer transfer structure. See the #flexcan_mb_transfer_t.
<> 144:ef7eb2e8f9f7 967 * @retval kStatus_Success Start Tx Message Buffer sending process successfully.
<> 144:ef7eb2e8f9f7 968 * @retval kStatus_Fail Write Tx Message Buffer failed.
<> 144:ef7eb2e8f9f7 969 * @retval kStatus_FLEXCAN_TxBusy Tx Message Buffer is in use.
<> 144:ef7eb2e8f9f7 970 */
<> 144:ef7eb2e8f9f7 971 status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer);
<> 144:ef7eb2e8f9f7 972
<> 144:ef7eb2e8f9f7 973 /*!
<> 144:ef7eb2e8f9f7 974 * @brief Receives a message using IRQ.
<> 144:ef7eb2e8f9f7 975 *
<> 144:ef7eb2e8f9f7 976 * This function receives a message using IRQ. This is non-blocking function, which returns
<> 144:ef7eb2e8f9f7 977 * right away. When the message has been received, the receive callback function is called.
<> 144:ef7eb2e8f9f7 978 *
<> 144:ef7eb2e8f9f7 979 * @param base FlexCAN peripheral base address.
<> 144:ef7eb2e8f9f7 980 * @param handle FlexCAN handle pointer.
<> 144:ef7eb2e8f9f7 981 * @param xfer FlexCAN Message Buffer transfer structure. See the #flexcan_mb_transfer_t.
<> 144:ef7eb2e8f9f7 982 * @retval kStatus_Success - Start Rx Message Buffer receiving process successfully.
<> 144:ef7eb2e8f9f7 983 * @retval kStatus_FLEXCAN_RxBusy - Rx Message Buffer is in use.
<> 144:ef7eb2e8f9f7 984 */
<> 144:ef7eb2e8f9f7 985 status_t FLEXCAN_TransferReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer);
<> 144:ef7eb2e8f9f7 986
<> 144:ef7eb2e8f9f7 987 /*!
<> 144:ef7eb2e8f9f7 988 * @brief Receives a message from Rx FIFO using IRQ.
<> 144:ef7eb2e8f9f7 989 *
<> 144:ef7eb2e8f9f7 990 * This function receives a message using IRQ. This is a non-blocking function, which returns
<> 144:ef7eb2e8f9f7 991 * right away. When all messages have been received, the receive callback function is called.
<> 144:ef7eb2e8f9f7 992 *
<> 144:ef7eb2e8f9f7 993 * @param base FlexCAN peripheral base address.
<> 144:ef7eb2e8f9f7 994 * @param handle FlexCAN handle pointer.
<> 144:ef7eb2e8f9f7 995 * @param xfer FlexCAN Rx FIFO transfer structure. See the @ref flexcan_fifo_transfer_t.
<> 144:ef7eb2e8f9f7 996 * @retval kStatus_Success - Start Rx FIFO receiving process successfully.
<> 144:ef7eb2e8f9f7 997 * @retval kStatus_FLEXCAN_RxFifoBusy - Rx FIFO is currently in use.
<> 144:ef7eb2e8f9f7 998 */
<> 144:ef7eb2e8f9f7 999 status_t FLEXCAN_TransferReceiveFifoNonBlocking(CAN_Type *base,
<> 144:ef7eb2e8f9f7 1000 flexcan_handle_t *handle,
<> 144:ef7eb2e8f9f7 1001 flexcan_fifo_transfer_t *xfer);
<> 144:ef7eb2e8f9f7 1002
<> 144:ef7eb2e8f9f7 1003 /*!
<> 144:ef7eb2e8f9f7 1004 * @brief Aborts the interrupt driven message send process.
<> 144:ef7eb2e8f9f7 1005 *
<> 144:ef7eb2e8f9f7 1006 * This function aborts the interrupt driven message send process.
<> 144:ef7eb2e8f9f7 1007 *
<> 144:ef7eb2e8f9f7 1008 * @param base FlexCAN peripheral base address.
<> 144:ef7eb2e8f9f7 1009 * @param handle FlexCAN handle pointer.
<> 144:ef7eb2e8f9f7 1010 * @param mbIdx The FlexCAN Message Buffer index.
<> 144:ef7eb2e8f9f7 1011 */
<> 144:ef7eb2e8f9f7 1012 void FLEXCAN_TransferAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx);
<> 144:ef7eb2e8f9f7 1013
<> 144:ef7eb2e8f9f7 1014 /*!
<> 144:ef7eb2e8f9f7 1015 * @brief Aborts the interrupt driven message receive process.
<> 144:ef7eb2e8f9f7 1016 *
<> 144:ef7eb2e8f9f7 1017 * This function aborts the interrupt driven message receive process.
<> 144:ef7eb2e8f9f7 1018 *
<> 144:ef7eb2e8f9f7 1019 * @param base FlexCAN peripheral base address.
<> 144:ef7eb2e8f9f7 1020 * @param handle FlexCAN handle pointer.
<> 144:ef7eb2e8f9f7 1021 * @param mbIdx The FlexCAN Message Buffer index.
<> 144:ef7eb2e8f9f7 1022 */
<> 144:ef7eb2e8f9f7 1023 void FLEXCAN_TransferAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx);
<> 144:ef7eb2e8f9f7 1024
<> 144:ef7eb2e8f9f7 1025 /*!
<> 144:ef7eb2e8f9f7 1026 * @brief Aborts the interrupt driven message receive from Rx FIFO process.
<> 144:ef7eb2e8f9f7 1027 *
<> 144:ef7eb2e8f9f7 1028 * This function aborts the interrupt driven message receive from Rx FIFO process.
<> 144:ef7eb2e8f9f7 1029 *
<> 144:ef7eb2e8f9f7 1030 * @param base FlexCAN peripheral base address.
<> 144:ef7eb2e8f9f7 1031 * @param handle FlexCAN handle pointer.
<> 144:ef7eb2e8f9f7 1032 */
<> 144:ef7eb2e8f9f7 1033 void FLEXCAN_TransferAbortReceiveFifo(CAN_Type *base, flexcan_handle_t *handle);
<> 144:ef7eb2e8f9f7 1034
<> 144:ef7eb2e8f9f7 1035 /*!
<> 144:ef7eb2e8f9f7 1036 * @brief FlexCAN IRQ handle function.
<> 144:ef7eb2e8f9f7 1037 *
<> 144:ef7eb2e8f9f7 1038 * This function handles the FlexCAN Error, the Message Buffer, and the Rx FIFO IRQ request.
<> 144:ef7eb2e8f9f7 1039 *
<> 144:ef7eb2e8f9f7 1040 * @param base FlexCAN peripheral base address.
<> 144:ef7eb2e8f9f7 1041 * @param handle FlexCAN handle pointer.
<> 144:ef7eb2e8f9f7 1042 */
<> 144:ef7eb2e8f9f7 1043 void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle);
<> 144:ef7eb2e8f9f7 1044
<> 144:ef7eb2e8f9f7 1045 /* @} */
<> 144:ef7eb2e8f9f7 1046
<> 144:ef7eb2e8f9f7 1047 #if defined(__cplusplus)
<> 144:ef7eb2e8f9f7 1048 }
<> 144:ef7eb2e8f9f7 1049 #endif
<> 144:ef7eb2e8f9f7 1050
<> 144:ef7eb2e8f9f7 1051 /*! @}*/
<> 144:ef7eb2e8f9f7 1052
<> 144:ef7eb2e8f9f7 1053 #endif /* _FSL_FLEXCAN_H_ */