added prescaler for 16 bit pwm in LPC1347 target
Fork of mbed-dev by
targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_enet.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)
- Committer:
- <>
- Date:
- Fri Sep 02 15:07:44 2016 +0100
- Revision:
- 144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /* |
<> | 144:ef7eb2e8f9f7 | 2 | * Copyright (c) 2015, Freescale Semiconductor, Inc. |
<> | 144:ef7eb2e8f9f7 | 3 | * All rights reserved. |
<> | 144:ef7eb2e8f9f7 | 4 | * |
<> | 144:ef7eb2e8f9f7 | 5 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 144:ef7eb2e8f9f7 | 6 | * are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 7 | * |
<> | 144:ef7eb2e8f9f7 | 8 | * o Redistributions of source code must retain the above copyright notice, this list |
<> | 144:ef7eb2e8f9f7 | 9 | * of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 10 | * |
<> | 144:ef7eb2e8f9f7 | 11 | * o Redistributions in binary form must reproduce the above copyright notice, this |
<> | 144:ef7eb2e8f9f7 | 12 | * list of conditions and the following disclaimer in the documentation and/or |
<> | 144:ef7eb2e8f9f7 | 13 | * other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 14 | * |
<> | 144:ef7eb2e8f9f7 | 15 | * o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
<> | 144:ef7eb2e8f9f7 | 16 | * contributors may be used to endorse or promote products derived from this |
<> | 144:ef7eb2e8f9f7 | 17 | * software without specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 18 | * |
<> | 144:ef7eb2e8f9f7 | 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
<> | 144:ef7eb2e8f9f7 | 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
<> | 144:ef7eb2e8f9f7 | 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 144:ef7eb2e8f9f7 | 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
<> | 144:ef7eb2e8f9f7 | 23 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
<> | 144:ef7eb2e8f9f7 | 24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
<> | 144:ef7eb2e8f9f7 | 25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
<> | 144:ef7eb2e8f9f7 | 26 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
<> | 144:ef7eb2e8f9f7 | 27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
<> | 144:ef7eb2e8f9f7 | 28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 29 | */ |
<> | 144:ef7eb2e8f9f7 | 30 | #ifndef _FSL_ENET_H_ |
<> | 144:ef7eb2e8f9f7 | 31 | #define _FSL_ENET_H_ |
<> | 144:ef7eb2e8f9f7 | 32 | |
<> | 144:ef7eb2e8f9f7 | 33 | #include "fsl_common.h" |
<> | 144:ef7eb2e8f9f7 | 34 | |
<> | 144:ef7eb2e8f9f7 | 35 | /*! |
<> | 144:ef7eb2e8f9f7 | 36 | * @addtogroup enet |
<> | 144:ef7eb2e8f9f7 | 37 | * @{ |
<> | 144:ef7eb2e8f9f7 | 38 | */ |
<> | 144:ef7eb2e8f9f7 | 39 | |
<> | 144:ef7eb2e8f9f7 | 40 | /*! @file */ |
<> | 144:ef7eb2e8f9f7 | 41 | |
<> | 144:ef7eb2e8f9f7 | 42 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 43 | * Definitions |
<> | 144:ef7eb2e8f9f7 | 44 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 45 | |
<> | 144:ef7eb2e8f9f7 | 46 | /*! @name Driver version */ |
<> | 144:ef7eb2e8f9f7 | 47 | /*@{*/ |
<> | 144:ef7eb2e8f9f7 | 48 | /*! @brief Defines the driver version. */ |
<> | 144:ef7eb2e8f9f7 | 49 | #define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ |
<> | 144:ef7eb2e8f9f7 | 50 | /*@}*/ |
<> | 144:ef7eb2e8f9f7 | 51 | |
<> | 144:ef7eb2e8f9f7 | 52 | /*! @name Control and status region bit masks of the receive buffer descriptor. */ |
<> | 144:ef7eb2e8f9f7 | 53 | /*@{*/ |
<> | 144:ef7eb2e8f9f7 | 54 | #define ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK 0x8000U /*!< Empty bit mask. */ |
<> | 144:ef7eb2e8f9f7 | 55 | #define ENET_BUFFDESCRIPTOR_RX_SOFTOWNER1_MASK 0x4000U /*!< Software owner one mask. */ |
<> | 144:ef7eb2e8f9f7 | 56 | #define ENET_BUFFDESCRIPTOR_RX_WRAP_MASK 0x2000U /*!< Next buffer descriptor is the start address. */ |
<> | 144:ef7eb2e8f9f7 | 57 | #define ENET_BUFFDESCRIPTOR_RX_SOFTOWNER2_Mask 0x1000U /*!< Software owner two mask. */ |
<> | 144:ef7eb2e8f9f7 | 58 | #define ENET_BUFFDESCRIPTOR_RX_LAST_MASK 0x0800U /*!< Last BD of the frame mask. */ |
<> | 144:ef7eb2e8f9f7 | 59 | #define ENET_BUFFDESCRIPTOR_RX_MISS_MASK 0x0100U /*!< Received because of the promiscuous mode. */ |
<> | 144:ef7eb2e8f9f7 | 60 | #define ENET_BUFFDESCRIPTOR_RX_BROADCAST_MASK 0x0080U /*!< Broadcast packet mask. */ |
<> | 144:ef7eb2e8f9f7 | 61 | #define ENET_BUFFDESCRIPTOR_RX_MULTICAST_MASK 0x0040U /*!< Multicast packet mask. */ |
<> | 144:ef7eb2e8f9f7 | 62 | #define ENET_BUFFDESCRIPTOR_RX_LENVLIOLATE_MASK 0x0020U /*!< Length violation mask. */ |
<> | 144:ef7eb2e8f9f7 | 63 | #define ENET_BUFFDESCRIPTOR_RX_NOOCTET_MASK 0x0010U /*!< Non-octet aligned frame mask. */ |
<> | 144:ef7eb2e8f9f7 | 64 | #define ENET_BUFFDESCRIPTOR_RX_CRC_MASK 0x0004U /*!< CRC error mask. */ |
<> | 144:ef7eb2e8f9f7 | 65 | #define ENET_BUFFDESCRIPTOR_RX_OVERRUN_MASK 0x0002U /*!< FIFO overrun mask. */ |
<> | 144:ef7eb2e8f9f7 | 66 | #define ENET_BUFFDESCRIPTOR_RX_TRUNC_MASK 0x0001U /*!< Frame is truncated mask. */ |
<> | 144:ef7eb2e8f9f7 | 67 | /*@}*/ |
<> | 144:ef7eb2e8f9f7 | 68 | |
<> | 144:ef7eb2e8f9f7 | 69 | /*! @name Control and status bit masks of the transmit buffer descriptor. */ |
<> | 144:ef7eb2e8f9f7 | 70 | /*@{*/ |
<> | 144:ef7eb2e8f9f7 | 71 | #define ENET_BUFFDESCRIPTOR_TX_READY_MASK 0x8000U /*!< Ready bit mask. */ |
<> | 144:ef7eb2e8f9f7 | 72 | #define ENET_BUFFDESCRIPTOR_TX_SOFTOWENER1_MASK 0x4000U /*!< Software owner one mask. */ |
<> | 144:ef7eb2e8f9f7 | 73 | #define ENET_BUFFDESCRIPTOR_TX_WRAP_MASK 0x2000U /*!< Wrap buffer descriptor mask. */ |
<> | 144:ef7eb2e8f9f7 | 74 | #define ENET_BUFFDESCRIPTOR_TX_SOFTOWENER2_MASK 0x1000U /*!< Software owner two mask. */ |
<> | 144:ef7eb2e8f9f7 | 75 | #define ENET_BUFFDESCRIPTOR_TX_LAST_MASK 0x0800U /*!< Last BD of the frame mask. */ |
<> | 144:ef7eb2e8f9f7 | 76 | #define ENET_BUFFDESCRIPTOR_TX_TRANMITCRC_MASK 0x0400U /*!< Transmit CRC mask. */ |
<> | 144:ef7eb2e8f9f7 | 77 | /*@}*/ |
<> | 144:ef7eb2e8f9f7 | 78 | |
<> | 144:ef7eb2e8f9f7 | 79 | /* Extended control regions for enhanced buffer descriptors. */ |
<> | 144:ef7eb2e8f9f7 | 80 | #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE |
<> | 144:ef7eb2e8f9f7 | 81 | /*! @name First extended control region bit masks of the receive buffer descriptor. */ |
<> | 144:ef7eb2e8f9f7 | 82 | /*@{*/ |
<> | 144:ef7eb2e8f9f7 | 83 | #define ENET_BUFFDESCRIPTOR_RX_IPV4_MASK 0x0001U /*!< Ipv4 frame mask. */ |
<> | 144:ef7eb2e8f9f7 | 84 | #define ENET_BUFFDESCRIPTOR_RX_IPV6_MASK 0x0002U /*!< Ipv6 frame mask. */ |
<> | 144:ef7eb2e8f9f7 | 85 | #define ENET_BUFFDESCRIPTOR_RX_VLAN_MASK 0x0004U /*!< VLAN frame mask. */ |
<> | 144:ef7eb2e8f9f7 | 86 | #define ENET_BUFFDESCRIPTOR_RX_PROTOCOLCHECKSUM_MASK 0x0010U /*!< Protocol checksum error mask. */ |
<> | 144:ef7eb2e8f9f7 | 87 | #define ENET_BUFFDESCRIPTOR_RX_IPHEADCHECKSUM_MASK 0x0020U /*!< IP header checksum error mask. */ |
<> | 144:ef7eb2e8f9f7 | 88 | /*@}*/ |
<> | 144:ef7eb2e8f9f7 | 89 | |
<> | 144:ef7eb2e8f9f7 | 90 | /*! @name Second extended control region bit masks of the receive buffer descriptor. */ |
<> | 144:ef7eb2e8f9f7 | 91 | /*@{*/ |
<> | 144:ef7eb2e8f9f7 | 92 | #define ENET_BUFFDESCRIPTOR_RX_INTERRUPT_MASK 0x0080U /*!< BD interrupt mask. */ |
<> | 144:ef7eb2e8f9f7 | 93 | #define ENET_BUFFDESCRIPTOR_RX_UNICAST_MASK 0x0100U /*!< Unicast frame mask. */ |
<> | 144:ef7eb2e8f9f7 | 94 | #define ENET_BUFFDESCRIPTOR_RX_COLLISION_MASK 0x0200U /*!< BD collision mask. */ |
<> | 144:ef7eb2e8f9f7 | 95 | #define ENET_BUFFDESCRIPTOR_RX_PHYERR_MASK 0x0400U /*!< PHY error mask. */ |
<> | 144:ef7eb2e8f9f7 | 96 | #define ENET_BUFFDESCRIPTOR_RX_MACERR_MASK 0x8000U /*!< Mac error mask. */ |
<> | 144:ef7eb2e8f9f7 | 97 | /*@}*/ |
<> | 144:ef7eb2e8f9f7 | 98 | |
<> | 144:ef7eb2e8f9f7 | 99 | /*! @name First extended control region bit masks of the transmit buffer descriptor. */ |
<> | 144:ef7eb2e8f9f7 | 100 | /*@{*/ |
<> | 144:ef7eb2e8f9f7 | 101 | #define ENET_BUFFDESCRIPTOR_TX_ERR_MASK 0x8000U /*!< Transmit error mask. */ |
<> | 144:ef7eb2e8f9f7 | 102 | #define ENET_BUFFDESCRIPTOR_TX_UNDERFLOWERR_MASK 0x2000U /*!< Underflow error mask. */ |
<> | 144:ef7eb2e8f9f7 | 103 | #define ENET_BUFFDESCRIPTOR_TX_EXCCOLLISIONERR_MASK 0x1000U /*!< Excess collision error mask. */ |
<> | 144:ef7eb2e8f9f7 | 104 | #define ENET_BUFFDESCRIPTOR_TX_FRAMEERR_MASK 0x0800U /*!< Frame error mask. */ |
<> | 144:ef7eb2e8f9f7 | 105 | #define ENET_BUFFDESCRIPTOR_TX_LATECOLLISIONERR_MASK 0x0400U /*!< Late collision error mask. */ |
<> | 144:ef7eb2e8f9f7 | 106 | #define ENET_BUFFDESCRIPTOR_TX_OVERFLOWERR_MASK 0x0200U /*!< Overflow error mask. */ |
<> | 144:ef7eb2e8f9f7 | 107 | #define ENET_BUFFDESCRIPTOR_TX_TIMESTAMPERR_MASK 0x0100U /*!< Timestamp error mask. */ |
<> | 144:ef7eb2e8f9f7 | 108 | /*@}*/ |
<> | 144:ef7eb2e8f9f7 | 109 | |
<> | 144:ef7eb2e8f9f7 | 110 | /*! @name Second extended control region bit masks of the transmit buffer descriptor. */ |
<> | 144:ef7eb2e8f9f7 | 111 | /*@{*/ |
<> | 144:ef7eb2e8f9f7 | 112 | #define ENET_BUFFDESCRIPTOR_TX_INTERRUPT_MASK 0x4000U /*!< Interrupt mask. */ |
<> | 144:ef7eb2e8f9f7 | 113 | #define ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK 0x2000U /*!< Timestamp flag mask. */ |
<> | 144:ef7eb2e8f9f7 | 114 | /*@}*/ |
<> | 144:ef7eb2e8f9f7 | 115 | #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ |
<> | 144:ef7eb2e8f9f7 | 116 | |
<> | 144:ef7eb2e8f9f7 | 117 | /*! @brief Defines the receive error status flag mask. */ |
<> | 144:ef7eb2e8f9f7 | 118 | #define ENET_BUFFDESCRIPTOR_RX_ERR_MASK \ |
<> | 144:ef7eb2e8f9f7 | 119 | (ENET_BUFFDESCRIPTOR_RX_TRUNC_MASK | ENET_BUFFDESCRIPTOR_RX_OVERRUN_MASK | \ |
<> | 144:ef7eb2e8f9f7 | 120 | ENET_BUFFDESCRIPTOR_RX_LENVLIOLATE_MASK | ENET_BUFFDESCRIPTOR_RX_NOOCTET_MASK | ENET_BUFFDESCRIPTOR_RX_CRC_MASK) |
<> | 144:ef7eb2e8f9f7 | 121 | #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE |
<> | 144:ef7eb2e8f9f7 | 122 | #define ENET_BUFFDESCRIPTOR_RX_EXT_ERR_MASK \ |
<> | 144:ef7eb2e8f9f7 | 123 | (ENET_BUFFDESCRIPTOR_RX_MACERR_MASK | ENET_BUFFDESCRIPTOR_RX_PHYERR_MASK | ENET_BUFFDESCRIPTOR_RX_COLLISION_MASK) |
<> | 144:ef7eb2e8f9f7 | 124 | #endif |
<> | 144:ef7eb2e8f9f7 | 125 | |
<> | 144:ef7eb2e8f9f7 | 126 | /*! @name Defines the maximum Ethernet frame size. */ |
<> | 144:ef7eb2e8f9f7 | 127 | /*@{*/ |
<> | 144:ef7eb2e8f9f7 | 128 | #define ENET_FRAME_MAX_FRAMELEN 1518U /*!< Maximum Ethernet frame size. */ |
<> | 144:ef7eb2e8f9f7 | 129 | #define ENET_FRAME_MAX_VALNFRAMELEN 1522U /*!< Maximum VLAN frame size. */ |
<> | 144:ef7eb2e8f9f7 | 130 | /*@}*/ |
<> | 144:ef7eb2e8f9f7 | 131 | |
<> | 144:ef7eb2e8f9f7 | 132 | #define ENET_FIFO_MIN_RX_FULL 5U /*!< ENET minimum receive FIFO full. */ |
<> | 144:ef7eb2e8f9f7 | 133 | #define ENET_RX_MIN_BUFFERSIZE 256U /*!< ENET minimum buffer size. */ |
<> | 144:ef7eb2e8f9f7 | 134 | #define ENET_BUFF_ALIGNMENT 16U /*!< Ethernet buffer alignment. */ |
<> | 144:ef7eb2e8f9f7 | 135 | |
<> | 144:ef7eb2e8f9f7 | 136 | /*! @brief Defines the PHY address scope for the ENET. */ |
<> | 144:ef7eb2e8f9f7 | 137 | #define ENET_PHY_MAXADDRESS (ENET_MMFR_PA_MASK >> ENET_MMFR_PA_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 138 | |
<> | 144:ef7eb2e8f9f7 | 139 | /*! @brief Defines the status return codes for transaction. */ |
<> | 144:ef7eb2e8f9f7 | 140 | enum _enet_status |
<> | 144:ef7eb2e8f9f7 | 141 | { |
<> | 144:ef7eb2e8f9f7 | 142 | kStatus_ENET_RxFrameError = MAKE_STATUS(kStatusGroup_ENET, 0U), /*!< A frame received but data error happen. */ |
<> | 144:ef7eb2e8f9f7 | 143 | kStatus_ENET_RxFrameFail = MAKE_STATUS(kStatusGroup_ENET, 1U), /*!< Failed to receive a frame. */ |
<> | 144:ef7eb2e8f9f7 | 144 | kStatus_ENET_RxFrameEmpty = MAKE_STATUS(kStatusGroup_ENET, 2U), /*!< No frame arrive. */ |
<> | 144:ef7eb2e8f9f7 | 145 | kStatus_ENET_TxFrameBusy = |
<> | 144:ef7eb2e8f9f7 | 146 | MAKE_STATUS(kStatusGroup_ENET, 3U), /*!< Transmit buffer descriptors are under process. */ |
<> | 144:ef7eb2e8f9f7 | 147 | kStatus_ENET_TxFrameFail = MAKE_STATUS(kStatusGroup_ENET, 4U) /*!< Transmit frame fail. */ |
<> | 144:ef7eb2e8f9f7 | 148 | #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE |
<> | 144:ef7eb2e8f9f7 | 149 | , |
<> | 144:ef7eb2e8f9f7 | 150 | kStatus_ENET_PtpTsRingFull = MAKE_STATUS(kStatusGroup_ENET, 5U), /*!< Timestamp ring full. */ |
<> | 144:ef7eb2e8f9f7 | 151 | kStatus_ENET_PtpTsRingEmpty = MAKE_STATUS(kStatusGroup_ENET, 6U) /*!< Timestamp ring empty. */ |
<> | 144:ef7eb2e8f9f7 | 152 | #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ |
<> | 144:ef7eb2e8f9f7 | 153 | }; |
<> | 144:ef7eb2e8f9f7 | 154 | |
<> | 144:ef7eb2e8f9f7 | 155 | /*! @brief Defines the RMII or MII mode for data interface between the MAC and the PHY. */ |
<> | 144:ef7eb2e8f9f7 | 156 | typedef enum _enet_mii_mode |
<> | 144:ef7eb2e8f9f7 | 157 | { |
<> | 144:ef7eb2e8f9f7 | 158 | kENET_MiiMode = 0U, /*!< MII mode for data interface. */ |
<> | 144:ef7eb2e8f9f7 | 159 | kENET_RmiiMode /*!< RMII mode for data interface. */ |
<> | 144:ef7eb2e8f9f7 | 160 | } enet_mii_mode_t; |
<> | 144:ef7eb2e8f9f7 | 161 | |
<> | 144:ef7eb2e8f9f7 | 162 | /*! @brief Defines the 10 Mbps or 100 Mbps speed for the MII data interface. */ |
<> | 144:ef7eb2e8f9f7 | 163 | typedef enum _enet_mii_speed |
<> | 144:ef7eb2e8f9f7 | 164 | { |
<> | 144:ef7eb2e8f9f7 | 165 | kENET_MiiSpeed10M = 0U, /*!< Speed 10 Mbps. */ |
<> | 144:ef7eb2e8f9f7 | 166 | kENET_MiiSpeed100M /*!< Speed 100 Mbps. */ |
<> | 144:ef7eb2e8f9f7 | 167 | } enet_mii_speed_t; |
<> | 144:ef7eb2e8f9f7 | 168 | |
<> | 144:ef7eb2e8f9f7 | 169 | /*! @brief Defines the half or full duplex for the MII data interface. */ |
<> | 144:ef7eb2e8f9f7 | 170 | typedef enum _enet_mii_duplex |
<> | 144:ef7eb2e8f9f7 | 171 | { |
<> | 144:ef7eb2e8f9f7 | 172 | kENET_MiiHalfDuplex = 0U, /*!< Half duplex mode. */ |
<> | 144:ef7eb2e8f9f7 | 173 | kENET_MiiFullDuplex /*!< Full duplex mode. */ |
<> | 144:ef7eb2e8f9f7 | 174 | } enet_mii_duplex_t; |
<> | 144:ef7eb2e8f9f7 | 175 | |
<> | 144:ef7eb2e8f9f7 | 176 | /*! @brief Defines the write operation for the MII management frame. */ |
<> | 144:ef7eb2e8f9f7 | 177 | typedef enum _enet_mii_write |
<> | 144:ef7eb2e8f9f7 | 178 | { |
<> | 144:ef7eb2e8f9f7 | 179 | kENET_MiiWriteNoCompliant = 0U, /*!< Write frame operation, but not MII-compliant. */ |
<> | 144:ef7eb2e8f9f7 | 180 | kENET_MiiWriteValidFrame /*!< Write frame operation for a valid MII management frame. */ |
<> | 144:ef7eb2e8f9f7 | 181 | } enet_mii_write_t; |
<> | 144:ef7eb2e8f9f7 | 182 | |
<> | 144:ef7eb2e8f9f7 | 183 | /*! @brief Defines the read operation for the MII management frame. */ |
<> | 144:ef7eb2e8f9f7 | 184 | typedef enum _enet_mii_read |
<> | 144:ef7eb2e8f9f7 | 185 | { |
<> | 144:ef7eb2e8f9f7 | 186 | kENET_MiiReadValidFrame = 2U, /*!< Read frame operation for a valid MII management frame. */ |
<> | 144:ef7eb2e8f9f7 | 187 | kENET_MiiReadNoCompliant = 3U /*!< Read frame operation, but not MII-compliant. */ |
<> | 144:ef7eb2e8f9f7 | 188 | } enet_mii_read_t; |
<> | 144:ef7eb2e8f9f7 | 189 | |
<> | 144:ef7eb2e8f9f7 | 190 | /*! @brief Defines a special configuration for ENET MAC controller. |
<> | 144:ef7eb2e8f9f7 | 191 | * |
<> | 144:ef7eb2e8f9f7 | 192 | * These control flags are provided for special user requirements. |
<> | 144:ef7eb2e8f9f7 | 193 | * Normally, these control flags are unused for ENET initialization. |
<> | 144:ef7eb2e8f9f7 | 194 | * For special requirements, set the flags to |
<> | 144:ef7eb2e8f9f7 | 195 | * macSpecialConfig in the enet_config_t. |
<> | 144:ef7eb2e8f9f7 | 196 | * The kENET_ControlStoreAndFwdDisable is used to disable the FIFO store |
<> | 144:ef7eb2e8f9f7 | 197 | * and forward. FIFO store and forward means that the FIFO read/send is started |
<> | 144:ef7eb2e8f9f7 | 198 | * when a complete frame is stored in TX/RX FIFO. If this flag is set, |
<> | 144:ef7eb2e8f9f7 | 199 | * configure rxFifoFullThreshold and txFifoWatermark |
<> | 144:ef7eb2e8f9f7 | 200 | * in the enet_config_t. |
<> | 144:ef7eb2e8f9f7 | 201 | */ |
<> | 144:ef7eb2e8f9f7 | 202 | typedef enum _enet_special_control_flag |
<> | 144:ef7eb2e8f9f7 | 203 | { |
<> | 144:ef7eb2e8f9f7 | 204 | kENET_ControlFlowControlEnable = 0x0001U, /*!< Enable ENET flow control: pause frame. */ |
<> | 144:ef7eb2e8f9f7 | 205 | kENET_ControlRxPayloadCheckEnable = 0x0002U, /*!< Enable ENET receive payload length check. */ |
<> | 144:ef7eb2e8f9f7 | 206 | kENET_ControlRxPadRemoveEnable = 0x0004U, /*!< Padding is removed from received frames. */ |
<> | 144:ef7eb2e8f9f7 | 207 | kENET_ControlRxBroadCastRejectEnable = 0x0008U, /*!< Enable broadcast frame reject. */ |
<> | 144:ef7eb2e8f9f7 | 208 | kENET_ControlMacAddrInsert = 0x0010U, /*!< Enable MAC address insert. */ |
<> | 144:ef7eb2e8f9f7 | 209 | kENET_ControlStoreAndFwdDisable = 0x0020U, /*!< Enable FIFO store and forward. */ |
<> | 144:ef7eb2e8f9f7 | 210 | kENET_ControlSMIPreambleDisable = 0x0040U, /*!< Enable SMI preamble. */ |
<> | 144:ef7eb2e8f9f7 | 211 | kENET_ControlPromiscuousEnable = 0x0080U, /*!< Enable promiscuous mode. */ |
<> | 144:ef7eb2e8f9f7 | 212 | kENET_ControlMIILoopEnable = 0x0100U, /*!< Enable ENET MII loop back. */ |
<> | 144:ef7eb2e8f9f7 | 213 | kENET_ControlVLANTagEnable = 0x0200U /*!< Enable VLAN tag frame. */ |
<> | 144:ef7eb2e8f9f7 | 214 | } enet_special_control_flag_t; |
<> | 144:ef7eb2e8f9f7 | 215 | |
<> | 144:ef7eb2e8f9f7 | 216 | /*! @brief List of interrupts supported by the peripheral. This |
<> | 144:ef7eb2e8f9f7 | 217 | * enumeration uses one-bot encoding to allow a logical OR of multiple |
<> | 144:ef7eb2e8f9f7 | 218 | * members. Members usually map to interrupt enable bits in one or more |
<> | 144:ef7eb2e8f9f7 | 219 | * peripheral registers. |
<> | 144:ef7eb2e8f9f7 | 220 | */ |
<> | 144:ef7eb2e8f9f7 | 221 | typedef enum _enet_interrupt_enable |
<> | 144:ef7eb2e8f9f7 | 222 | { |
<> | 144:ef7eb2e8f9f7 | 223 | kENET_BabrInterrupt = ENET_EIR_BABR_MASK, /*!< Babbling receive error interrupt source */ |
<> | 144:ef7eb2e8f9f7 | 224 | kENET_BabtInterrupt = ENET_EIR_BABT_MASK, /*!< Babbling transmit error interrupt source */ |
<> | 144:ef7eb2e8f9f7 | 225 | kENET_GraceStopInterrupt = ENET_EIR_GRA_MASK, /*!< Graceful stop complete interrupt source */ |
<> | 144:ef7eb2e8f9f7 | 226 | kENET_TxFrameInterrupt = ENET_EIR_TXF_MASK, /*!< TX FRAME interrupt source */ |
<> | 144:ef7eb2e8f9f7 | 227 | kENET_TxByteInterrupt = ENET_EIR_TXB_MASK, /*!< TX BYTE interrupt source */ |
<> | 144:ef7eb2e8f9f7 | 228 | kENET_RxFrameInterrupt = ENET_EIR_RXF_MASK, /*!< RX FRAME interrupt source */ |
<> | 144:ef7eb2e8f9f7 | 229 | kENET_RxByteInterrupt = ENET_EIR_RXB_MASK, /*!< RX BYTE interrupt source */ |
<> | 144:ef7eb2e8f9f7 | 230 | kENET_MiiInterrupt = ENET_EIR_MII_MASK, /*!< MII interrupt source */ |
<> | 144:ef7eb2e8f9f7 | 231 | kENET_EBusERInterrupt = ENET_EIR_EBERR_MASK, /*!< Ethernet bus error interrupt source */ |
<> | 144:ef7eb2e8f9f7 | 232 | kENET_LateCollisionInterrupt = ENET_EIR_LC_MASK, /*!< Late collision interrupt source */ |
<> | 144:ef7eb2e8f9f7 | 233 | kENET_RetryLimitInterrupt = ENET_EIR_RL_MASK, /*!< Collision Retry Limit interrupt source */ |
<> | 144:ef7eb2e8f9f7 | 234 | kENET_UnderrunInterrupt = ENET_EIR_UN_MASK, /*!< Transmit FIFO underrun interrupt source */ |
<> | 144:ef7eb2e8f9f7 | 235 | kENET_PayloadRxInterrupt = ENET_EIR_PLR_MASK, /*!< Payload Receive interrupt source */ |
<> | 144:ef7eb2e8f9f7 | 236 | kENET_WakeupInterrupt = ENET_EIR_WAKEUP_MASK /*!< WAKEUP interrupt source */ |
<> | 144:ef7eb2e8f9f7 | 237 | #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE |
<> | 144:ef7eb2e8f9f7 | 238 | , |
<> | 144:ef7eb2e8f9f7 | 239 | kENET_TsAvailInterrupt = ENET_EIR_TS_AVAIL_MASK, /*!< TS AVAIL interrupt source for PTP */ |
<> | 144:ef7eb2e8f9f7 | 240 | kENET_TsTimerInterrupt = ENET_EIR_TS_TIMER_MASK /*!< TS WRAP interrupt source for PTP */ |
<> | 144:ef7eb2e8f9f7 | 241 | #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ |
<> | 144:ef7eb2e8f9f7 | 242 | } enet_interrupt_enable_t; |
<> | 144:ef7eb2e8f9f7 | 243 | |
<> | 144:ef7eb2e8f9f7 | 244 | /*! @brief Defines the common interrupt event for callback use. */ |
<> | 144:ef7eb2e8f9f7 | 245 | typedef enum _enet_event |
<> | 144:ef7eb2e8f9f7 | 246 | { |
<> | 144:ef7eb2e8f9f7 | 247 | kENET_RxEvent, /*!< Receive event. */ |
<> | 144:ef7eb2e8f9f7 | 248 | kENET_TxEvent, /*!< Transmit event. */ |
<> | 144:ef7eb2e8f9f7 | 249 | kENET_ErrEvent, /*!< Error event: BABR/BABT/EBERR/LC/RL/UN/PLR . */ |
<> | 144:ef7eb2e8f9f7 | 250 | kENET_WakeUpEvent, /*!< Wake up from sleep mode event. */ |
<> | 144:ef7eb2e8f9f7 | 251 | #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE |
<> | 144:ef7eb2e8f9f7 | 252 | kENET_TimeStampEvent, /*!< Time stamp event. */ |
<> | 144:ef7eb2e8f9f7 | 253 | kENET_TimeStampAvailEvent /*!< Time stamp available event.*/ |
<> | 144:ef7eb2e8f9f7 | 254 | #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ |
<> | 144:ef7eb2e8f9f7 | 255 | } enet_event_t; |
<> | 144:ef7eb2e8f9f7 | 256 | |
<> | 144:ef7eb2e8f9f7 | 257 | /*! @brief Defines the transmit accelerator configuration. */ |
<> | 144:ef7eb2e8f9f7 | 258 | typedef enum _enet_tx_accelerator |
<> | 144:ef7eb2e8f9f7 | 259 | { |
<> | 144:ef7eb2e8f9f7 | 260 | kENET_TxAccelIsShift16Enabled = ENET_TACC_SHIFT16_MASK, /*!< Transmit FIFO shift-16. */ |
<> | 144:ef7eb2e8f9f7 | 261 | kENET_TxAccelIpCheckEnabled = ENET_TACC_IPCHK_MASK, /*!< Insert IP header checksum. */ |
<> | 144:ef7eb2e8f9f7 | 262 | kENET_TxAccelProtoCheckEnabled = ENET_TACC_PROCHK_MASK /*!< Insert protocol checksum. */ |
<> | 144:ef7eb2e8f9f7 | 263 | } enet_tx_accelerator_t; |
<> | 144:ef7eb2e8f9f7 | 264 | |
<> | 144:ef7eb2e8f9f7 | 265 | /*! @brief Defines the receive accelerator configuration. */ |
<> | 144:ef7eb2e8f9f7 | 266 | typedef enum _enet_rx_accelerator |
<> | 144:ef7eb2e8f9f7 | 267 | { |
<> | 144:ef7eb2e8f9f7 | 268 | kENET_RxAccelPadRemoveEnabled = ENET_RACC_PADREM_MASK, /*!< Padding removal for short IP frames. */ |
<> | 144:ef7eb2e8f9f7 | 269 | kENET_RxAccelIpCheckEnabled = ENET_RACC_IPDIS_MASK, /*!< Discard with wrong IP header checksum. */ |
<> | 144:ef7eb2e8f9f7 | 270 | kENET_RxAccelProtoCheckEnabled = ENET_RACC_PRODIS_MASK, /*!< Discard with wrong protocol checksum. */ |
<> | 144:ef7eb2e8f9f7 | 271 | kENET_RxAccelMacCheckEnabled = ENET_RACC_LINEDIS_MASK, /*!< Discard with Mac layer errors. */ |
<> | 144:ef7eb2e8f9f7 | 272 | kENET_RxAccelisShift16Enabled = ENET_RACC_SHIFT16_MASK /*!< Receive FIFO shift-16. */ |
<> | 144:ef7eb2e8f9f7 | 273 | } enet_rx_accelerator_t; |
<> | 144:ef7eb2e8f9f7 | 274 | |
<> | 144:ef7eb2e8f9f7 | 275 | #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE |
<> | 144:ef7eb2e8f9f7 | 276 | /*! @brief Defines the ENET PTP message related constant. */ |
<> | 144:ef7eb2e8f9f7 | 277 | typedef enum _enet_ptp_event_type |
<> | 144:ef7eb2e8f9f7 | 278 | { |
<> | 144:ef7eb2e8f9f7 | 279 | kENET_PtpEventMsgType = 3U, /*!< PTP event message type. */ |
<> | 144:ef7eb2e8f9f7 | 280 | kENET_PtpSrcPortIdLen = 10U, /*!< PTP message sequence id length. */ |
<> | 144:ef7eb2e8f9f7 | 281 | kENET_PtpEventPort = 319U, /*!< PTP event port number. */ |
<> | 144:ef7eb2e8f9f7 | 282 | kENET_PtpGnrlPort = 320U /*!< PTP general port number. */ |
<> | 144:ef7eb2e8f9f7 | 283 | } enet_ptp_event_type_t; |
<> | 144:ef7eb2e8f9f7 | 284 | |
<> | 144:ef7eb2e8f9f7 | 285 | /*! @brief Defines the IEEE 1588 PTP timer channel numbers. */ |
<> | 144:ef7eb2e8f9f7 | 286 | typedef enum _enet_ptp_timer_channel |
<> | 144:ef7eb2e8f9f7 | 287 | { |
<> | 144:ef7eb2e8f9f7 | 288 | kENET_PtpTimerChannel1 = 0U, /*!< IEEE 1588 PTP timer Channel 1. */ |
<> | 144:ef7eb2e8f9f7 | 289 | kENET_PtpTimerChannel2, /*!< IEEE 1588 PTP timer Channel 2. */ |
<> | 144:ef7eb2e8f9f7 | 290 | kENET_PtpTimerChannel3, /*!< IEEE 1588 PTP timer Channel 3. */ |
<> | 144:ef7eb2e8f9f7 | 291 | kENET_PtpTimerChannel4 /*!< IEEE 1588 PTP timer Channel 4. */ |
<> | 144:ef7eb2e8f9f7 | 292 | } enet_ptp_timer_channel_t; |
<> | 144:ef7eb2e8f9f7 | 293 | |
<> | 144:ef7eb2e8f9f7 | 294 | /*! @brief Defines the capture or compare mode for IEEE 1588 PTP timer channels. */ |
<> | 144:ef7eb2e8f9f7 | 295 | typedef enum _enet_ptp_timer_channel_mode |
<> | 144:ef7eb2e8f9f7 | 296 | { |
<> | 144:ef7eb2e8f9f7 | 297 | kENET_PtpChannelDisable = 0U, /*!< Disable timer channel. */ |
<> | 144:ef7eb2e8f9f7 | 298 | kENET_PtpChannelRisingCapture = 1U, /*!< Input capture on rising edge. */ |
<> | 144:ef7eb2e8f9f7 | 299 | kENET_PtpChannelFallingCapture = 2U, /*!< Input capture on falling edge. */ |
<> | 144:ef7eb2e8f9f7 | 300 | kENET_PtpChannelBothCapture = 3U, /*!< Input capture on both edges. */ |
<> | 144:ef7eb2e8f9f7 | 301 | kENET_PtpChannelSoftCompare = 4U, /*!< Output compare software only. */ |
<> | 144:ef7eb2e8f9f7 | 302 | kENET_PtpChannelToggleCompare = 5U, /*!< Toggle output on compare. */ |
<> | 144:ef7eb2e8f9f7 | 303 | kENET_PtpChannelClearCompare = 6U, /*!< Clear output on compare. */ |
<> | 144:ef7eb2e8f9f7 | 304 | kENET_PtpChannelSetCompare = 7U, /*!< Set output on compare. */ |
<> | 144:ef7eb2e8f9f7 | 305 | kENET_PtpChannelClearCompareSetOverflow = 10U, /*!< Clear output on compare, set output on overflow. */ |
<> | 144:ef7eb2e8f9f7 | 306 | kENET_PtpChannelSetCompareClearOverflow = 11U, /*!< Set output on compare, clear output on overflow. */ |
<> | 144:ef7eb2e8f9f7 | 307 | kENET_PtpChannelPulseLowonCompare = 14U, /*!< Pulse output low on compare for one IEEE 1588 clock cycle. */ |
<> | 144:ef7eb2e8f9f7 | 308 | kENET_PtpChannelPulseHighonCompare = 15U /*!< Pulse output high on compare for one IEEE 1588 clock cycle. */ |
<> | 144:ef7eb2e8f9f7 | 309 | } enet_ptp_timer_channel_mode_t; |
<> | 144:ef7eb2e8f9f7 | 310 | #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ |
<> | 144:ef7eb2e8f9f7 | 311 | |
<> | 144:ef7eb2e8f9f7 | 312 | /*! @brief Defines the receive buffer descriptor structure for the little endian system.*/ |
<> | 144:ef7eb2e8f9f7 | 313 | typedef struct _enet_rx_bd_struct |
<> | 144:ef7eb2e8f9f7 | 314 | { |
<> | 144:ef7eb2e8f9f7 | 315 | uint16_t length; /*!< Buffer descriptor data length. */ |
<> | 144:ef7eb2e8f9f7 | 316 | uint16_t control; /*!< Buffer descriptor control and status. */ |
<> | 144:ef7eb2e8f9f7 | 317 | uint8_t *buffer; /*!< Data buffer pointer. */ |
<> | 144:ef7eb2e8f9f7 | 318 | #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE |
<> | 144:ef7eb2e8f9f7 | 319 | uint16_t controlExtend0; /*!< Extend buffer descriptor control0. */ |
<> | 144:ef7eb2e8f9f7 | 320 | uint16_t controlExtend1; /*!< Extend buffer descriptor control1. */ |
<> | 144:ef7eb2e8f9f7 | 321 | uint16_t payloadCheckSum; /*!< Internal payload checksum. */ |
<> | 144:ef7eb2e8f9f7 | 322 | uint8_t headerLength; /*!< Header length. */ |
<> | 144:ef7eb2e8f9f7 | 323 | uint8_t protocolTyte; /*!< Protocol type. */ |
<> | 144:ef7eb2e8f9f7 | 324 | uint16_t reserved0; |
<> | 144:ef7eb2e8f9f7 | 325 | uint16_t controlExtend2; /*!< Extend buffer descriptor control2. */ |
<> | 144:ef7eb2e8f9f7 | 326 | uint32_t timestamp; /*!< Timestamp. */ |
<> | 144:ef7eb2e8f9f7 | 327 | uint16_t reserved1; |
<> | 144:ef7eb2e8f9f7 | 328 | uint16_t reserved2; |
<> | 144:ef7eb2e8f9f7 | 329 | uint16_t reserved3; |
<> | 144:ef7eb2e8f9f7 | 330 | uint16_t reserved4; |
<> | 144:ef7eb2e8f9f7 | 331 | #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ |
<> | 144:ef7eb2e8f9f7 | 332 | } enet_rx_bd_struct_t; |
<> | 144:ef7eb2e8f9f7 | 333 | |
<> | 144:ef7eb2e8f9f7 | 334 | /*! @brief Defines the enhanced transmit buffer descriptor structure for the little endian system. */ |
<> | 144:ef7eb2e8f9f7 | 335 | typedef struct _enet_tx_bd_struct |
<> | 144:ef7eb2e8f9f7 | 336 | { |
<> | 144:ef7eb2e8f9f7 | 337 | uint16_t length; /*!< Buffer descriptor data length. */ |
<> | 144:ef7eb2e8f9f7 | 338 | uint16_t control; /*!< Buffer descriptor control and status. */ |
<> | 144:ef7eb2e8f9f7 | 339 | uint8_t *buffer; /*!< Data buffer pointer. */ |
<> | 144:ef7eb2e8f9f7 | 340 | #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE |
<> | 144:ef7eb2e8f9f7 | 341 | uint16_t controlExtend0; /*!< Extend buffer descriptor control0. */ |
<> | 144:ef7eb2e8f9f7 | 342 | uint16_t controlExtend1; /*!< Extend buffer descriptor control1. */ |
<> | 144:ef7eb2e8f9f7 | 343 | uint16_t reserved0; |
<> | 144:ef7eb2e8f9f7 | 344 | uint16_t reserved1; |
<> | 144:ef7eb2e8f9f7 | 345 | uint16_t reserved2; |
<> | 144:ef7eb2e8f9f7 | 346 | uint16_t controlExtend2; /*!< Extend buffer descriptor control2. */ |
<> | 144:ef7eb2e8f9f7 | 347 | uint32_t timestamp; /*!< Timestamp. */ |
<> | 144:ef7eb2e8f9f7 | 348 | uint16_t reserved3; |
<> | 144:ef7eb2e8f9f7 | 349 | uint16_t reserved4; |
<> | 144:ef7eb2e8f9f7 | 350 | uint16_t reserved5; |
<> | 144:ef7eb2e8f9f7 | 351 | uint16_t reserved6; |
<> | 144:ef7eb2e8f9f7 | 352 | #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ |
<> | 144:ef7eb2e8f9f7 | 353 | } enet_tx_bd_struct_t; |
<> | 144:ef7eb2e8f9f7 | 354 | |
<> | 144:ef7eb2e8f9f7 | 355 | /*! @brief Defines the ENET data error statistic structure. */ |
<> | 144:ef7eb2e8f9f7 | 356 | typedef struct _enet_data_error_stats |
<> | 144:ef7eb2e8f9f7 | 357 | { |
<> | 144:ef7eb2e8f9f7 | 358 | uint32_t statsRxLenGreaterErr; /*!< Receive length greater than RCR[MAX_FL]. */ |
<> | 144:ef7eb2e8f9f7 | 359 | uint32_t statsRxAlignErr; /*!< Receive non-octet alignment/ */ |
<> | 144:ef7eb2e8f9f7 | 360 | uint32_t statsRxFcsErr; /*!< Receive CRC error. */ |
<> | 144:ef7eb2e8f9f7 | 361 | uint32_t statsRxOverRunErr; /*!< Receive over run. */ |
<> | 144:ef7eb2e8f9f7 | 362 | uint32_t statsRxTruncateErr; /*!< Receive truncate. */ |
<> | 144:ef7eb2e8f9f7 | 363 | #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE |
<> | 144:ef7eb2e8f9f7 | 364 | uint32_t statsRxProtocolChecksumErr; /*!< Receive protocol checksum error. */ |
<> | 144:ef7eb2e8f9f7 | 365 | uint32_t statsRxIpHeadChecksumErr; /*!< Receive IP header checksum error. */ |
<> | 144:ef7eb2e8f9f7 | 366 | uint32_t statsRxMacErr; /*!< Receive Mac error. */ |
<> | 144:ef7eb2e8f9f7 | 367 | uint32_t statsRxPhyErr; /*!< Receive PHY error. */ |
<> | 144:ef7eb2e8f9f7 | 368 | uint32_t statsRxCollisionErr; /*!< Receive collision. */ |
<> | 144:ef7eb2e8f9f7 | 369 | uint32_t statsTxErr; /*!< The error happen when transmit the frame. */ |
<> | 144:ef7eb2e8f9f7 | 370 | uint32_t statsTxFrameErr; /*!< The transmit frame is error. */ |
<> | 144:ef7eb2e8f9f7 | 371 | uint32_t statsTxOverFlowErr; /*!< Transmit overflow. */ |
<> | 144:ef7eb2e8f9f7 | 372 | uint32_t statsTxLateCollisionErr; /*!< Transmit late collision. */ |
<> | 144:ef7eb2e8f9f7 | 373 | uint32_t statsTxExcessCollisionErr; /*!< Transmit excess collision.*/ |
<> | 144:ef7eb2e8f9f7 | 374 | uint32_t statsTxUnderFlowErr; /*!< Transmit under flow error. */ |
<> | 144:ef7eb2e8f9f7 | 375 | uint32_t statsTxTsErr; /*!< Transmit time stamp error. */ |
<> | 144:ef7eb2e8f9f7 | 376 | #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ |
<> | 144:ef7eb2e8f9f7 | 377 | } enet_data_error_stats_t; |
<> | 144:ef7eb2e8f9f7 | 378 | |
<> | 144:ef7eb2e8f9f7 | 379 | /*! @brief Defines the receive buffer descriptor configure structure. |
<> | 144:ef7eb2e8f9f7 | 380 | * |
<> | 144:ef7eb2e8f9f7 | 381 | * Note: For the internal DMA requirements, the buffers have a corresponding alignment requirement: |
<> | 144:ef7eb2e8f9f7 | 382 | * 1. The aligned receive and transmit buffer size must be evenly divisible by 16. |
<> | 144:ef7eb2e8f9f7 | 383 | * 2. The aligned transmit and receive buffer descriptor start address must be at |
<> | 144:ef7eb2e8f9f7 | 384 | * least 64 bit aligned. However, it's recommended to be evenly divisible by 16. |
<> | 144:ef7eb2e8f9f7 | 385 | * 3. The aligned transmit and receive buffer start address must be evenly divisible by 16. |
<> | 144:ef7eb2e8f9f7 | 386 | * Receive buffers should be continuous with the total size equal to "rxBdNumber * rxBuffSizeAlign". |
<> | 144:ef7eb2e8f9f7 | 387 | * Transmit buffers should be continuous with the total size equal to "txBdNumber * txBuffSizeAlign". |
<> | 144:ef7eb2e8f9f7 | 388 | */ |
<> | 144:ef7eb2e8f9f7 | 389 | typedef struct _enet_buffer_config |
<> | 144:ef7eb2e8f9f7 | 390 | { |
<> | 144:ef7eb2e8f9f7 | 391 | uint16_t rxBdNumber; /*!< Receive buffer descriptor number. */ |
<> | 144:ef7eb2e8f9f7 | 392 | uint16_t txBdNumber; /*!< Transmit buffer descriptor number. */ |
<> | 144:ef7eb2e8f9f7 | 393 | uint32_t rxBuffSizeAlign; /*!< Aligned receive data buffer size. */ |
<> | 144:ef7eb2e8f9f7 | 394 | uint32_t txBuffSizeAlign; /*!< Aligned transmit data buffer size. */ |
<> | 144:ef7eb2e8f9f7 | 395 | volatile enet_rx_bd_struct_t *rxBdStartAddrAlign; /*!< Aligned receive buffer descriptor start address. */ |
<> | 144:ef7eb2e8f9f7 | 396 | volatile enet_tx_bd_struct_t *txBdStartAddrAlign; /*!< Aligned transmit buffer descriptor start address. */ |
<> | 144:ef7eb2e8f9f7 | 397 | uint8_t *rxBufferAlign; /*!< Receive data buffer start address. */ |
<> | 144:ef7eb2e8f9f7 | 398 | uint8_t *txBufferAlign; /*!< Transmit data buffer start address. */ |
<> | 144:ef7eb2e8f9f7 | 399 | } enet_buffer_config_t; |
<> | 144:ef7eb2e8f9f7 | 400 | |
<> | 144:ef7eb2e8f9f7 | 401 | #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE |
<> | 144:ef7eb2e8f9f7 | 402 | /*! @brief Defines the ENET PTP time stamp structure. */ |
<> | 144:ef7eb2e8f9f7 | 403 | typedef struct _enet_ptp_time |
<> | 144:ef7eb2e8f9f7 | 404 | { |
<> | 144:ef7eb2e8f9f7 | 405 | uint64_t second; /*!< Second. */ |
<> | 144:ef7eb2e8f9f7 | 406 | uint32_t nanosecond; /*!< Nanosecond. */ |
<> | 144:ef7eb2e8f9f7 | 407 | } enet_ptp_time_t; |
<> | 144:ef7eb2e8f9f7 | 408 | |
<> | 144:ef7eb2e8f9f7 | 409 | /*! @brief Defines the structure for the ENET PTP message data and timestamp data.*/ |
<> | 144:ef7eb2e8f9f7 | 410 | typedef struct _enet_ptp_time_data |
<> | 144:ef7eb2e8f9f7 | 411 | { |
<> | 144:ef7eb2e8f9f7 | 412 | uint8_t version; /*!< PTP version. */ |
<> | 144:ef7eb2e8f9f7 | 413 | uint8_t sourcePortId[kENET_PtpSrcPortIdLen]; /*!< PTP source port ID. */ |
<> | 144:ef7eb2e8f9f7 | 414 | uint16_t sequenceId; /*!< PTP sequence ID. */ |
<> | 144:ef7eb2e8f9f7 | 415 | uint8_t messageType; /*!< PTP message type. */ |
<> | 144:ef7eb2e8f9f7 | 416 | enet_ptp_time_t timeStamp; /*!< PTP timestamp. */ |
<> | 144:ef7eb2e8f9f7 | 417 | } enet_ptp_time_data_t; |
<> | 144:ef7eb2e8f9f7 | 418 | |
<> | 144:ef7eb2e8f9f7 | 419 | /*! @brief Defines the ENET PTP ring buffer structure for the PTP message timestamp store.*/ |
<> | 144:ef7eb2e8f9f7 | 420 | typedef struct _enet_ptp_time_data_ring |
<> | 144:ef7eb2e8f9f7 | 421 | { |
<> | 144:ef7eb2e8f9f7 | 422 | uint32_t front; /*!< The first index of the ring. */ |
<> | 144:ef7eb2e8f9f7 | 423 | uint32_t end; /*!< The end index of the ring. */ |
<> | 144:ef7eb2e8f9f7 | 424 | uint32_t size; /*!< The size of the ring. */ |
<> | 144:ef7eb2e8f9f7 | 425 | enet_ptp_time_data_t *ptpTsData; /*!< PTP message data structure. */ |
<> | 144:ef7eb2e8f9f7 | 426 | } enet_ptp_time_data_ring_t; |
<> | 144:ef7eb2e8f9f7 | 427 | |
<> | 144:ef7eb2e8f9f7 | 428 | /*! @brief Defines the ENET PTP configure structure. */ |
<> | 144:ef7eb2e8f9f7 | 429 | typedef struct _enet_ptp_config |
<> | 144:ef7eb2e8f9f7 | 430 | { |
<> | 144:ef7eb2e8f9f7 | 431 | uint8_t ptpTsRxBuffNum; /*!< Receive 1588 timestamp buffer number*/ |
<> | 144:ef7eb2e8f9f7 | 432 | uint8_t ptpTsTxBuffNum; /*!< Transmit 1588 timestamp buffer number*/ |
<> | 144:ef7eb2e8f9f7 | 433 | enet_ptp_time_data_t *rxPtpTsData; /*!< The start address of 1588 receive timestamp buffers */ |
<> | 144:ef7eb2e8f9f7 | 434 | enet_ptp_time_data_t *txPtpTsData; /*!< The start address of 1588 transmit timestamp buffers */ |
<> | 144:ef7eb2e8f9f7 | 435 | enet_ptp_timer_channel_t channel; /*!< Used for ERRATA_2579: the PTP 1588 timer channel for time interrupt. */ |
<> | 144:ef7eb2e8f9f7 | 436 | uint32_t ptp1588ClockSrc_Hz; /*!< The clock source of the PTP 1588 timer. */ |
<> | 144:ef7eb2e8f9f7 | 437 | } enet_ptp_config_t; |
<> | 144:ef7eb2e8f9f7 | 438 | #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ |
<> | 144:ef7eb2e8f9f7 | 439 | |
<> | 144:ef7eb2e8f9f7 | 440 | |
<> | 144:ef7eb2e8f9f7 | 441 | |
<> | 144:ef7eb2e8f9f7 | 442 | /*! @brief Defines the basic configuration structure for the ENET device. |
<> | 144:ef7eb2e8f9f7 | 443 | * |
<> | 144:ef7eb2e8f9f7 | 444 | * Note: |
<> | 144:ef7eb2e8f9f7 | 445 | * 1. macSpecialConfig is used for a special control configuration, A logical OR of |
<> | 144:ef7eb2e8f9f7 | 446 | * "enet_special_control_flag_t". For a special configuration for MAC, |
<> | 144:ef7eb2e8f9f7 | 447 | * set this parameter to 0. |
<> | 144:ef7eb2e8f9f7 | 448 | * 2. txWatermark is used for a cut-through operation. It is in steps of 64 bytes: |
<> | 144:ef7eb2e8f9f7 | 449 | * 0/1 - 64 bytes written to TX FIFO before transmission of a frame begins. |
<> | 144:ef7eb2e8f9f7 | 450 | * 2 - 128 bytes written to TX FIFO .... |
<> | 144:ef7eb2e8f9f7 | 451 | * 3 - 192 bytes written to TX FIFO .... |
<> | 144:ef7eb2e8f9f7 | 452 | * The maximum of txWatermark is 0x2F - 4032 bytes written to TX FIFO .... |
<> | 144:ef7eb2e8f9f7 | 453 | * txWatermark allows minimizing the transmit latency to set the txWatermark to 0 or 1 |
<> | 144:ef7eb2e8f9f7 | 454 | * or for larger bus access latency 3 or larger due to contention for the system bus. |
<> | 144:ef7eb2e8f9f7 | 455 | * 3. rxFifoFullThreshold is similar to the txWatermark for cut-through operation in RX. |
<> | 144:ef7eb2e8f9f7 | 456 | * It is in 64-bit words. The minimum is ENET_FIFO_MIN_RX_FULL and the maximum is 0xFF. |
<> | 144:ef7eb2e8f9f7 | 457 | * If the end of the frame is stored in FIFO and the frame size if smaller than the |
<> | 144:ef7eb2e8f9f7 | 458 | * txWatermark, the frame is still transmitted. The rule is the |
<> | 144:ef7eb2e8f9f7 | 459 | * same for rxFifoFullThreshold in the receive direction. |
<> | 144:ef7eb2e8f9f7 | 460 | * 4. When "kENET_ControlFlowControlEnable" is set in the macSpecialConfig, ensure |
<> | 144:ef7eb2e8f9f7 | 461 | * that the pauseDuration, rxFifoEmptyThreshold, and rxFifoStatEmptyThreshold |
<> | 144:ef7eb2e8f9f7 | 462 | * are set for flow control enabled case. |
<> | 144:ef7eb2e8f9f7 | 463 | * 5. When "kENET_ControlStoreAndFwdDisabled" is set in the macSpecialConfig, ensure |
<> | 144:ef7eb2e8f9f7 | 464 | * that the rxFifoFullThreshold and txFifoWatermark are set for store and forward disable. |
<> | 144:ef7eb2e8f9f7 | 465 | * 6. The rxAccelerConfig and txAccelerConfig default setting with 0 - accelerator |
<> | 144:ef7eb2e8f9f7 | 466 | * are disabled. The "enet_tx_accelerator_t" and "enet_rx_accelerator_t" are |
<> | 144:ef7eb2e8f9f7 | 467 | * recommended to be used to enable the transmit and receive accelerator. |
<> | 144:ef7eb2e8f9f7 | 468 | * After the accelerators are enabled, the store and forward feature should be enabled. |
<> | 144:ef7eb2e8f9f7 | 469 | * As a result, kENET_ControlStoreAndFwdDisabled should not be set. |
<> | 144:ef7eb2e8f9f7 | 470 | */ |
<> | 144:ef7eb2e8f9f7 | 471 | typedef struct _enet_config |
<> | 144:ef7eb2e8f9f7 | 472 | { |
<> | 144:ef7eb2e8f9f7 | 473 | uint32_t macSpecialConfig; /*!< Mac special configuration. A logical OR of "enet_special_control_flag_t". */ |
<> | 144:ef7eb2e8f9f7 | 474 | uint32_t interrupt; /*!< Mac interrupt source. A logical OR of "enet_interrupt_enable_t". */ |
<> | 144:ef7eb2e8f9f7 | 475 | uint16_t rxMaxFrameLen; /*!< Receive maximum frame length. */ |
<> | 144:ef7eb2e8f9f7 | 476 | enet_mii_mode_t miiMode; /*!< MII mode. */ |
<> | 144:ef7eb2e8f9f7 | 477 | enet_mii_speed_t miiSpeed; /*!< MII Speed. */ |
<> | 144:ef7eb2e8f9f7 | 478 | enet_mii_duplex_t miiDuplex; /*!< MII duplex. */ |
<> | 144:ef7eb2e8f9f7 | 479 | uint8_t rxAccelerConfig; /*!< Receive accelerator, A logical OR of "enet_rx_accelerator_t". */ |
<> | 144:ef7eb2e8f9f7 | 480 | uint8_t txAccelerConfig; /*!< Transmit accelerator, A logical OR of "enet_rx_accelerator_t". */ |
<> | 144:ef7eb2e8f9f7 | 481 | uint16_t pauseDuration; /*!< For flow control enabled case: Pause duration. */ |
<> | 144:ef7eb2e8f9f7 | 482 | uint8_t rxFifoEmptyThreshold; /*!< For flow control enabled case: when RX FIFO level reaches this value, |
<> | 144:ef7eb2e8f9f7 | 483 | it makes MAC generate XOFF pause frame. */ |
<> | 144:ef7eb2e8f9f7 | 484 | #if FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD |
<> | 144:ef7eb2e8f9f7 | 485 | uint8_t rxFifoStatEmptyThreshold; /*!< For flow control enabled case: number of frames in the receive FIFO, |
<> | 144:ef7eb2e8f9f7 | 486 | independent of size, that can be accept. If the limit is reached, reception |
<> | 144:ef7eb2e8f9f7 | 487 | continues and a pause frame is triggered. */ |
<> | 144:ef7eb2e8f9f7 | 488 | #endif /* FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD */ |
<> | 144:ef7eb2e8f9f7 | 489 | uint8_t rxFifoFullThreshold; /*!< For store and forward disable case, the data required in RX FIFO to notify |
<> | 144:ef7eb2e8f9f7 | 490 | the MAC receive ready status. */ |
<> | 144:ef7eb2e8f9f7 | 491 | uint8_t txFifoWatermark; /*!< For store and forward disable case, the data required in TX FIFO |
<> | 144:ef7eb2e8f9f7 | 492 | before a frame transmit start. */ |
<> | 144:ef7eb2e8f9f7 | 493 | } enet_config_t; |
<> | 144:ef7eb2e8f9f7 | 494 | |
<> | 144:ef7eb2e8f9f7 | 495 | /* Forward declaration of the handle typedef. */ |
<> | 144:ef7eb2e8f9f7 | 496 | typedef struct _enet_handle enet_handle_t; |
<> | 144:ef7eb2e8f9f7 | 497 | |
<> | 144:ef7eb2e8f9f7 | 498 | /*! @brief ENET callback function. */ |
<> | 144:ef7eb2e8f9f7 | 499 | typedef void (*enet_callback_t)(ENET_Type *base, enet_handle_t *handle, enet_event_t event, void *userData); |
<> | 144:ef7eb2e8f9f7 | 500 | |
<> | 144:ef7eb2e8f9f7 | 501 | /*! @brief Defines the ENET handler structure. */ |
<> | 144:ef7eb2e8f9f7 | 502 | struct _enet_handle |
<> | 144:ef7eb2e8f9f7 | 503 | { |
<> | 144:ef7eb2e8f9f7 | 504 | volatile enet_rx_bd_struct_t *rxBdBase; /*!< Receive buffer descriptor base address pointer. */ |
<> | 144:ef7eb2e8f9f7 | 505 | volatile enet_rx_bd_struct_t *rxBdCurrent; /*!< The current available receive buffer descriptor pointer. */ |
<> | 144:ef7eb2e8f9f7 | 506 | volatile enet_rx_bd_struct_t *rxBdDirty; /*!< The dirty receive buffer descriptor needed to be updated from. */ |
<> | 144:ef7eb2e8f9f7 | 507 | volatile enet_tx_bd_struct_t *txBdBase; /*!< Transmit buffer descriptor base address pointer. */ |
<> | 144:ef7eb2e8f9f7 | 508 | volatile enet_tx_bd_struct_t *txBdCurrent; /*!< The current available transmit buffer descriptor pointer. */ |
<> | 144:ef7eb2e8f9f7 | 509 | volatile enet_tx_bd_struct_t *txBdDirty; /*!< The dirty transmit buffer descriptor needed to be updated from. */ |
<> | 144:ef7eb2e8f9f7 | 510 | uint32_t rxBuffSizeAlign; /*!< Receive buffer size alignment. */ |
<> | 144:ef7eb2e8f9f7 | 511 | uint32_t txBuffSizeAlign; /*!< Transmit buffer size alignment. */ |
<> | 144:ef7eb2e8f9f7 | 512 | enet_callback_t callback; /*!< Callback function. */ |
<> | 144:ef7eb2e8f9f7 | 513 | void *userData; /*!< Callback function parameter.*/ |
<> | 144:ef7eb2e8f9f7 | 514 | #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE |
<> | 144:ef7eb2e8f9f7 | 515 | volatile enet_tx_bd_struct_t *txBdDirtyStatic; /*!< The dirty transmit buffer descriptor for error static update. */ |
<> | 144:ef7eb2e8f9f7 | 516 | volatile enet_tx_bd_struct_t *txBdDirtyTime; /*!< The dirty transmit buffer descriptor for time stamp update. */ |
<> | 144:ef7eb2e8f9f7 | 517 | uint64_t msTimerSecond; /*!< The second for Master PTP timer .*/ |
<> | 144:ef7eb2e8f9f7 | 518 | enet_ptp_time_data_ring_t rxPtpTsDataRing; /*!< Receive PTP 1588 time stamp data ring buffer. */ |
<> | 144:ef7eb2e8f9f7 | 519 | enet_ptp_time_data_ring_t txPtpTsDataRing; /*!< Transmit PTP 1588 time stamp data ring buffer. */ |
<> | 144:ef7eb2e8f9f7 | 520 | #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ |
<> | 144:ef7eb2e8f9f7 | 521 | }; |
<> | 144:ef7eb2e8f9f7 | 522 | |
<> | 144:ef7eb2e8f9f7 | 523 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 524 | * API |
<> | 144:ef7eb2e8f9f7 | 525 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 526 | |
<> | 144:ef7eb2e8f9f7 | 527 | #if defined(__cplusplus) |
<> | 144:ef7eb2e8f9f7 | 528 | extern "C" { |
<> | 144:ef7eb2e8f9f7 | 529 | #endif |
<> | 144:ef7eb2e8f9f7 | 530 | |
<> | 144:ef7eb2e8f9f7 | 531 | /*! |
<> | 144:ef7eb2e8f9f7 | 532 | * @name Initialization and De-initialization |
<> | 144:ef7eb2e8f9f7 | 533 | * @{ |
<> | 144:ef7eb2e8f9f7 | 534 | */ |
<> | 144:ef7eb2e8f9f7 | 535 | |
<> | 144:ef7eb2e8f9f7 | 536 | /*! |
<> | 144:ef7eb2e8f9f7 | 537 | * @brief Gets the ENET default configuration structure. |
<> | 144:ef7eb2e8f9f7 | 538 | * |
<> | 144:ef7eb2e8f9f7 | 539 | * The purpose of this API is to get the default ENET MAC controller |
<> | 144:ef7eb2e8f9f7 | 540 | * configure structure for ENET_Init(). User may use the initialized |
<> | 144:ef7eb2e8f9f7 | 541 | * structure unchanged in ENET_Init(), or modify some fields of the |
<> | 144:ef7eb2e8f9f7 | 542 | * structure before calling ENET_Init(). |
<> | 144:ef7eb2e8f9f7 | 543 | * Example: |
<> | 144:ef7eb2e8f9f7 | 544 | @code |
<> | 144:ef7eb2e8f9f7 | 545 | enet_config_t config; |
<> | 144:ef7eb2e8f9f7 | 546 | ENET_GetDefaultConfig(&config); |
<> | 144:ef7eb2e8f9f7 | 547 | @endcode |
<> | 144:ef7eb2e8f9f7 | 548 | * @param config The ENET mac controller configuration structure pointer. |
<> | 144:ef7eb2e8f9f7 | 549 | */ |
<> | 144:ef7eb2e8f9f7 | 550 | void ENET_GetDefaultConfig(enet_config_t *config); |
<> | 144:ef7eb2e8f9f7 | 551 | |
<> | 144:ef7eb2e8f9f7 | 552 | /*! |
<> | 144:ef7eb2e8f9f7 | 553 | * @brief Initializes the ENET module. |
<> | 144:ef7eb2e8f9f7 | 554 | * |
<> | 144:ef7eb2e8f9f7 | 555 | * This function ungates the module clock and initializes it with the ENET configuration. |
<> | 144:ef7eb2e8f9f7 | 556 | * |
<> | 144:ef7eb2e8f9f7 | 557 | * @param base ENET peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 558 | * @param handle ENET handler pointer. |
<> | 144:ef7eb2e8f9f7 | 559 | * @param config ENET mac configuration structure pointer. |
<> | 144:ef7eb2e8f9f7 | 560 | * The "enet_config_t" type mac configuration return from ENET_GetDefaultConfig |
<> | 144:ef7eb2e8f9f7 | 561 | * can be used directly. It is also possible to verify the Mac configuration using other methods. |
<> | 144:ef7eb2e8f9f7 | 562 | * @param bufferConfig ENET buffer configuration structure pointer. |
<> | 144:ef7eb2e8f9f7 | 563 | * The buffer configuration should be prepared for ENET Initialization. |
<> | 144:ef7eb2e8f9f7 | 564 | * @param macAddr ENET mac address of Ethernet device. This MAC address should be |
<> | 144:ef7eb2e8f9f7 | 565 | * provided. |
<> | 144:ef7eb2e8f9f7 | 566 | * @param srcClock_Hz The internal module clock source for MII clock. |
<> | 144:ef7eb2e8f9f7 | 567 | * |
<> | 144:ef7eb2e8f9f7 | 568 | * @note ENET has two buffer descriptors: legacy buffer descriptors and |
<> | 144:ef7eb2e8f9f7 | 569 | * enhanced 1588 buffer descriptors. The legacy descriptor is used by default. To |
<> | 144:ef7eb2e8f9f7 | 570 | * use 1588 feature, use the enhanced 1588 buffer descriptor |
<> | 144:ef7eb2e8f9f7 | 571 | * by defining "ENET_ENHANCEDBUFFERDESCRIPTOR_MODE" and calling ENET_Ptp1588Configure() |
<> | 144:ef7eb2e8f9f7 | 572 | * to configure the 1588 feature and related buffers after calling ENET_Init(). |
<> | 144:ef7eb2e8f9f7 | 573 | */ |
<> | 144:ef7eb2e8f9f7 | 574 | void ENET_Init(ENET_Type *base, |
<> | 144:ef7eb2e8f9f7 | 575 | enet_handle_t *handle, |
<> | 144:ef7eb2e8f9f7 | 576 | const enet_config_t *config, |
<> | 144:ef7eb2e8f9f7 | 577 | const enet_buffer_config_t *bufferConfig, |
<> | 144:ef7eb2e8f9f7 | 578 | uint8_t *macAddr, |
<> | 144:ef7eb2e8f9f7 | 579 | uint32_t srcClock_Hz); |
<> | 144:ef7eb2e8f9f7 | 580 | /*! |
<> | 144:ef7eb2e8f9f7 | 581 | * @brief Deinitializes the ENET module. |
<> | 144:ef7eb2e8f9f7 | 582 | |
<> | 144:ef7eb2e8f9f7 | 583 | * This function gates the module clock, clears ENET interrupts, and disables the ENET module. |
<> | 144:ef7eb2e8f9f7 | 584 | * |
<> | 144:ef7eb2e8f9f7 | 585 | * @param base ENET peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 586 | */ |
<> | 144:ef7eb2e8f9f7 | 587 | void ENET_Deinit(ENET_Type *base); |
<> | 144:ef7eb2e8f9f7 | 588 | |
<> | 144:ef7eb2e8f9f7 | 589 | /*! |
<> | 144:ef7eb2e8f9f7 | 590 | * @brief Resets the ENET module. |
<> | 144:ef7eb2e8f9f7 | 591 | * |
<> | 144:ef7eb2e8f9f7 | 592 | * This function restores the ENET module to reset state. |
<> | 144:ef7eb2e8f9f7 | 593 | * Note that this function sets all registers to |
<> | 144:ef7eb2e8f9f7 | 594 | * reset state. As a result, the ENET module can't work after calling this function. |
<> | 144:ef7eb2e8f9f7 | 595 | * |
<> | 144:ef7eb2e8f9f7 | 596 | * @param base ENET peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 597 | */ |
<> | 144:ef7eb2e8f9f7 | 598 | static inline void ENET_Reset(ENET_Type *base) |
<> | 144:ef7eb2e8f9f7 | 599 | { |
<> | 144:ef7eb2e8f9f7 | 600 | base->ECR |= ENET_ECR_RESET_MASK; |
<> | 144:ef7eb2e8f9f7 | 601 | } |
<> | 144:ef7eb2e8f9f7 | 602 | |
<> | 144:ef7eb2e8f9f7 | 603 | /* @} */ |
<> | 144:ef7eb2e8f9f7 | 604 | |
<> | 144:ef7eb2e8f9f7 | 605 | /*! |
<> | 144:ef7eb2e8f9f7 | 606 | * @name MII interface operation |
<> | 144:ef7eb2e8f9f7 | 607 | * @{ |
<> | 144:ef7eb2e8f9f7 | 608 | */ |
<> | 144:ef7eb2e8f9f7 | 609 | |
<> | 144:ef7eb2e8f9f7 | 610 | /*! |
<> | 144:ef7eb2e8f9f7 | 611 | * @brief Sets the ENET MII speed and duplex. |
<> | 144:ef7eb2e8f9f7 | 612 | * |
<> | 144:ef7eb2e8f9f7 | 613 | * @param base ENET peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 614 | * @param speed The speed of the RMII mode. |
<> | 144:ef7eb2e8f9f7 | 615 | * @param duplex The duplex of the RMII mode. |
<> | 144:ef7eb2e8f9f7 | 616 | */ |
<> | 144:ef7eb2e8f9f7 | 617 | void ENET_SetMII(ENET_Type *base, enet_mii_speed_t speed, enet_mii_duplex_t duplex); |
<> | 144:ef7eb2e8f9f7 | 618 | |
<> | 144:ef7eb2e8f9f7 | 619 | /*! |
<> | 144:ef7eb2e8f9f7 | 620 | * @brief Sets the ENET SMI(serial management interface)- MII management interface. |
<> | 144:ef7eb2e8f9f7 | 621 | * |
<> | 144:ef7eb2e8f9f7 | 622 | * @param base ENET peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 623 | * @param srcClock_Hz This is the ENET module clock frequency. Normally it's the system clock. See clock distribution. |
<> | 144:ef7eb2e8f9f7 | 624 | * @param isPreambleDisabled The preamble disable flag. |
<> | 144:ef7eb2e8f9f7 | 625 | * - true Enables the preamble. |
<> | 144:ef7eb2e8f9f7 | 626 | * - false Disables the preamble. |
<> | 144:ef7eb2e8f9f7 | 627 | */ |
<> | 144:ef7eb2e8f9f7 | 628 | void ENET_SetSMI(ENET_Type *base, uint32_t srcClock_Hz, bool isPreambleDisabled); |
<> | 144:ef7eb2e8f9f7 | 629 | |
<> | 144:ef7eb2e8f9f7 | 630 | /*! |
<> | 144:ef7eb2e8f9f7 | 631 | * @brief Gets the ENET SMI- MII management interface configuration. |
<> | 144:ef7eb2e8f9f7 | 632 | * |
<> | 144:ef7eb2e8f9f7 | 633 | * This API is used to get the SMI configuration to check if the MII management |
<> | 144:ef7eb2e8f9f7 | 634 | * interface has been set. |
<> | 144:ef7eb2e8f9f7 | 635 | * |
<> | 144:ef7eb2e8f9f7 | 636 | * @param base ENET peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 637 | * @return The SMI setup status true or false. |
<> | 144:ef7eb2e8f9f7 | 638 | */ |
<> | 144:ef7eb2e8f9f7 | 639 | static inline bool ENET_GetSMI(ENET_Type *base) |
<> | 144:ef7eb2e8f9f7 | 640 | { |
<> | 144:ef7eb2e8f9f7 | 641 | return (0 != (base->MSCR & 0x7E)); |
<> | 144:ef7eb2e8f9f7 | 642 | } |
<> | 144:ef7eb2e8f9f7 | 643 | |
<> | 144:ef7eb2e8f9f7 | 644 | /*! |
<> | 144:ef7eb2e8f9f7 | 645 | * @brief Reads data from the PHY register through SMI interface. |
<> | 144:ef7eb2e8f9f7 | 646 | * |
<> | 144:ef7eb2e8f9f7 | 647 | * @param base ENET peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 648 | * @return The data read from PHY |
<> | 144:ef7eb2e8f9f7 | 649 | */ |
<> | 144:ef7eb2e8f9f7 | 650 | static inline uint32_t ENET_ReadSMIData(ENET_Type *base) |
<> | 144:ef7eb2e8f9f7 | 651 | { |
<> | 144:ef7eb2e8f9f7 | 652 | return (uint32_t)((base->MMFR & ENET_MMFR_DATA_MASK) >> ENET_MMFR_DATA_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 653 | } |
<> | 144:ef7eb2e8f9f7 | 654 | |
<> | 144:ef7eb2e8f9f7 | 655 | /*! |
<> | 144:ef7eb2e8f9f7 | 656 | * @brief Starts an SMI (Serial Management Interface) read command. |
<> | 144:ef7eb2e8f9f7 | 657 | * |
<> | 144:ef7eb2e8f9f7 | 658 | * @param base ENET peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 659 | * @param phyAddr The PHY address. |
<> | 144:ef7eb2e8f9f7 | 660 | * @param phyReg The PHY register. |
<> | 144:ef7eb2e8f9f7 | 661 | * @param operation The read operation. |
<> | 144:ef7eb2e8f9f7 | 662 | */ |
<> | 144:ef7eb2e8f9f7 | 663 | void ENET_StartSMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet_mii_read_t operation); |
<> | 144:ef7eb2e8f9f7 | 664 | |
<> | 144:ef7eb2e8f9f7 | 665 | /*! |
<> | 144:ef7eb2e8f9f7 | 666 | * @brief Starts a SMI write command. |
<> | 144:ef7eb2e8f9f7 | 667 | * |
<> | 144:ef7eb2e8f9f7 | 668 | * @param base ENET peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 669 | * @param phyAddr The PHY address. |
<> | 144:ef7eb2e8f9f7 | 670 | * @param phyReg The PHY register. |
<> | 144:ef7eb2e8f9f7 | 671 | * @param operation The write operation. |
<> | 144:ef7eb2e8f9f7 | 672 | * @param data The data written to PHY. |
<> | 144:ef7eb2e8f9f7 | 673 | */ |
<> | 144:ef7eb2e8f9f7 | 674 | void ENET_StartSMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet_mii_write_t operation, uint32_t data); |
<> | 144:ef7eb2e8f9f7 | 675 | |
<> | 144:ef7eb2e8f9f7 | 676 | /* @} */ |
<> | 144:ef7eb2e8f9f7 | 677 | |
<> | 144:ef7eb2e8f9f7 | 678 | /*! |
<> | 144:ef7eb2e8f9f7 | 679 | * @name MAC Address Filter |
<> | 144:ef7eb2e8f9f7 | 680 | * @{ |
<> | 144:ef7eb2e8f9f7 | 681 | */ |
<> | 144:ef7eb2e8f9f7 | 682 | |
<> | 144:ef7eb2e8f9f7 | 683 | /*! |
<> | 144:ef7eb2e8f9f7 | 684 | * @brief Sets the ENET module Mac address. |
<> | 144:ef7eb2e8f9f7 | 685 | * |
<> | 144:ef7eb2e8f9f7 | 686 | * @param base ENET peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 687 | * @param macAddr The six-byte Mac address pointer. |
<> | 144:ef7eb2e8f9f7 | 688 | * The pointer is allocated by application and input into the API. |
<> | 144:ef7eb2e8f9f7 | 689 | */ |
<> | 144:ef7eb2e8f9f7 | 690 | void ENET_SetMacAddr(ENET_Type *base, uint8_t *macAddr); |
<> | 144:ef7eb2e8f9f7 | 691 | |
<> | 144:ef7eb2e8f9f7 | 692 | /*! |
<> | 144:ef7eb2e8f9f7 | 693 | * @brief Gets the ENET module Mac address. |
<> | 144:ef7eb2e8f9f7 | 694 | * |
<> | 144:ef7eb2e8f9f7 | 695 | * @param base ENET peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 696 | * @param macAddr The six-byte Mac address pointer. |
<> | 144:ef7eb2e8f9f7 | 697 | * The pointer is allocated by application and input into the API. |
<> | 144:ef7eb2e8f9f7 | 698 | */ |
<> | 144:ef7eb2e8f9f7 | 699 | void ENET_GetMacAddr(ENET_Type *base, uint8_t *macAddr); |
<> | 144:ef7eb2e8f9f7 | 700 | |
<> | 144:ef7eb2e8f9f7 | 701 | /*! |
<> | 144:ef7eb2e8f9f7 | 702 | * @brief Adds the ENET device to a multicast group. |
<> | 144:ef7eb2e8f9f7 | 703 | * |
<> | 144:ef7eb2e8f9f7 | 704 | * @param base ENET peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 705 | * @param address The six-byte multicast group address which is provided by application. |
<> | 144:ef7eb2e8f9f7 | 706 | */ |
<> | 144:ef7eb2e8f9f7 | 707 | void ENET_AddMulticastGroup(ENET_Type *base, uint8_t *address); |
<> | 144:ef7eb2e8f9f7 | 708 | |
<> | 144:ef7eb2e8f9f7 | 709 | /*! |
<> | 144:ef7eb2e8f9f7 | 710 | * @brief Moves the ENET device from a multicast group. |
<> | 144:ef7eb2e8f9f7 | 711 | * |
<> | 144:ef7eb2e8f9f7 | 712 | * @param base ENET peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 713 | * @param address The six-byte multicast group address which is provided by application. |
<> | 144:ef7eb2e8f9f7 | 714 | */ |
<> | 144:ef7eb2e8f9f7 | 715 | void ENET_LeaveMulticastGroup(ENET_Type *base, uint8_t *address); |
<> | 144:ef7eb2e8f9f7 | 716 | |
<> | 144:ef7eb2e8f9f7 | 717 | /* @} */ |
<> | 144:ef7eb2e8f9f7 | 718 | |
<> | 144:ef7eb2e8f9f7 | 719 | /*! |
<> | 144:ef7eb2e8f9f7 | 720 | * @name Other basic operation |
<> | 144:ef7eb2e8f9f7 | 721 | * @{ |
<> | 144:ef7eb2e8f9f7 | 722 | */ |
<> | 144:ef7eb2e8f9f7 | 723 | |
<> | 144:ef7eb2e8f9f7 | 724 | /*! |
<> | 144:ef7eb2e8f9f7 | 725 | * @brief Activates ENET read or receive. |
<> | 144:ef7eb2e8f9f7 | 726 | * |
<> | 144:ef7eb2e8f9f7 | 727 | * @param base ENET peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 728 | * |
<> | 144:ef7eb2e8f9f7 | 729 | * @note This must be called after the MAC configuration and |
<> | 144:ef7eb2e8f9f7 | 730 | * state are ready. It must be called after the ENET_Init() and |
<> | 144:ef7eb2e8f9f7 | 731 | * ENET_Ptp1588Configure(). This should be called when the ENET receive required. |
<> | 144:ef7eb2e8f9f7 | 732 | */ |
<> | 144:ef7eb2e8f9f7 | 733 | static inline void ENET_ActiveRead(ENET_Type *base) |
<> | 144:ef7eb2e8f9f7 | 734 | { |
<> | 144:ef7eb2e8f9f7 | 735 | base->RDAR = ENET_RDAR_RDAR_MASK; |
<> | 144:ef7eb2e8f9f7 | 736 | } |
<> | 144:ef7eb2e8f9f7 | 737 | |
<> | 144:ef7eb2e8f9f7 | 738 | /*! |
<> | 144:ef7eb2e8f9f7 | 739 | * @brief Enables/disables the MAC to enter sleep mode. |
<> | 144:ef7eb2e8f9f7 | 740 | * This function is used to set the MAC enter sleep mode. |
<> | 144:ef7eb2e8f9f7 | 741 | * When entering sleep mode, the magic frame wakeup interrupt should be enabled |
<> | 144:ef7eb2e8f9f7 | 742 | * to wake up MAC from the sleep mode and reset it to normal mode. |
<> | 144:ef7eb2e8f9f7 | 743 | * |
<> | 144:ef7eb2e8f9f7 | 744 | * @param base ENET peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 745 | * @param enable True enable sleep mode, false disable sleep mode. |
<> | 144:ef7eb2e8f9f7 | 746 | */ |
<> | 144:ef7eb2e8f9f7 | 747 | static inline void ENET_EnableSleepMode(ENET_Type *base, bool enable) |
<> | 144:ef7eb2e8f9f7 | 748 | { |
<> | 144:ef7eb2e8f9f7 | 749 | if (enable) |
<> | 144:ef7eb2e8f9f7 | 750 | { |
<> | 144:ef7eb2e8f9f7 | 751 | /* When this field is set, MAC enters sleep mode. */ |
<> | 144:ef7eb2e8f9f7 | 752 | base->ECR |= ENET_ECR_SLEEP_MASK | ENET_ECR_MAGICEN_MASK; |
<> | 144:ef7eb2e8f9f7 | 753 | } |
<> | 144:ef7eb2e8f9f7 | 754 | else |
<> | 144:ef7eb2e8f9f7 | 755 | { /* MAC exits sleep mode. */ |
<> | 144:ef7eb2e8f9f7 | 756 | base->ECR &= ~(ENET_ECR_SLEEP_MASK | ENET_ECR_MAGICEN_MASK); |
<> | 144:ef7eb2e8f9f7 | 757 | } |
<> | 144:ef7eb2e8f9f7 | 758 | } |
<> | 144:ef7eb2e8f9f7 | 759 | |
<> | 144:ef7eb2e8f9f7 | 760 | /*! |
<> | 144:ef7eb2e8f9f7 | 761 | * @brief Gets ENET transmit and receive accelerator functions from MAC controller. |
<> | 144:ef7eb2e8f9f7 | 762 | * |
<> | 144:ef7eb2e8f9f7 | 763 | * @param base ENET peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 764 | * @param txAccelOption The transmit accelerator option. The "enet_tx_accelerator_t" is |
<> | 144:ef7eb2e8f9f7 | 765 | * recommended to be used to as the mask to get the exact the accelerator option. |
<> | 144:ef7eb2e8f9f7 | 766 | * @param rxAccelOption The receive accelerator option. The "enet_rx_accelerator_t" is |
<> | 144:ef7eb2e8f9f7 | 767 | * recommended to be used to as the mask to get the exact the accelerator option. |
<> | 144:ef7eb2e8f9f7 | 768 | */ |
<> | 144:ef7eb2e8f9f7 | 769 | static inline void ENET_GetAccelFunction(ENET_Type *base, uint32_t *txAccelOption, uint32_t *rxAccelOption) |
<> | 144:ef7eb2e8f9f7 | 770 | { |
<> | 144:ef7eb2e8f9f7 | 771 | assert(txAccelOption); |
<> | 144:ef7eb2e8f9f7 | 772 | assert(txAccelOption); |
<> | 144:ef7eb2e8f9f7 | 773 | |
<> | 144:ef7eb2e8f9f7 | 774 | *txAccelOption = base->TACC; |
<> | 144:ef7eb2e8f9f7 | 775 | *rxAccelOption = base->RACC; |
<> | 144:ef7eb2e8f9f7 | 776 | } |
<> | 144:ef7eb2e8f9f7 | 777 | |
<> | 144:ef7eb2e8f9f7 | 778 | /* @} */ |
<> | 144:ef7eb2e8f9f7 | 779 | |
<> | 144:ef7eb2e8f9f7 | 780 | /*! |
<> | 144:ef7eb2e8f9f7 | 781 | * @name Interrupts. |
<> | 144:ef7eb2e8f9f7 | 782 | * @{ |
<> | 144:ef7eb2e8f9f7 | 783 | */ |
<> | 144:ef7eb2e8f9f7 | 784 | |
<> | 144:ef7eb2e8f9f7 | 785 | /*! |
<> | 144:ef7eb2e8f9f7 | 786 | * @brief Enables the ENET interrupt. |
<> | 144:ef7eb2e8f9f7 | 787 | * |
<> | 144:ef7eb2e8f9f7 | 788 | * This function enables the ENET interrupt according to the provided mask. The mask |
<> | 144:ef7eb2e8f9f7 | 789 | * is a logical OR of enumeration members. See @ref enet_interrupt_enable_t. |
<> | 144:ef7eb2e8f9f7 | 790 | * For example, to enable the TX frame interrupt and RX frame interrupt, do this: |
<> | 144:ef7eb2e8f9f7 | 791 | * @code |
<> | 144:ef7eb2e8f9f7 | 792 | * ENET_EnableInterrupts(ENET, kENET_TxFrameInterrupt | kENET_RxFrameInterrupt); |
<> | 144:ef7eb2e8f9f7 | 793 | * @endcode |
<> | 144:ef7eb2e8f9f7 | 794 | * |
<> | 144:ef7eb2e8f9f7 | 795 | * @param base ENET peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 796 | * @param mask ENET interrupts to enable. This is a logical OR of the |
<> | 144:ef7eb2e8f9f7 | 797 | * enumeration :: enet_interrupt_enable_t. |
<> | 144:ef7eb2e8f9f7 | 798 | */ |
<> | 144:ef7eb2e8f9f7 | 799 | static inline void ENET_EnableInterrupts(ENET_Type *base, uint32_t mask) |
<> | 144:ef7eb2e8f9f7 | 800 | { |
<> | 144:ef7eb2e8f9f7 | 801 | base->EIMR |= mask; |
<> | 144:ef7eb2e8f9f7 | 802 | } |
<> | 144:ef7eb2e8f9f7 | 803 | |
<> | 144:ef7eb2e8f9f7 | 804 | /*! |
<> | 144:ef7eb2e8f9f7 | 805 | * @brief Disables the ENET interrupt. |
<> | 144:ef7eb2e8f9f7 | 806 | * |
<> | 144:ef7eb2e8f9f7 | 807 | * This function disables the ENET interrupts according to the provided mask. The mask |
<> | 144:ef7eb2e8f9f7 | 808 | * is a logical OR of enumeration members. See @ref enet_interrupt_enable_t. |
<> | 144:ef7eb2e8f9f7 | 809 | * For example, to disable the TX frame interrupt and RX frame interrupt, do this: |
<> | 144:ef7eb2e8f9f7 | 810 | * @code |
<> | 144:ef7eb2e8f9f7 | 811 | * ENET_DisableInterrupts(ENET, kENET_TxFrameInterrupt | kENET_RxFrameInterrupt); |
<> | 144:ef7eb2e8f9f7 | 812 | * @endcode |
<> | 144:ef7eb2e8f9f7 | 813 | * |
<> | 144:ef7eb2e8f9f7 | 814 | * @param base ENET peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 815 | * @param mask ENET interrupts to disable. This is a logical OR of the |
<> | 144:ef7eb2e8f9f7 | 816 | * enumeration :: enet_interrupt_enable_t. |
<> | 144:ef7eb2e8f9f7 | 817 | */ |
<> | 144:ef7eb2e8f9f7 | 818 | static inline void ENET_DisableInterrupts(ENET_Type *base, uint32_t mask) |
<> | 144:ef7eb2e8f9f7 | 819 | { |
<> | 144:ef7eb2e8f9f7 | 820 | base->EIMR &= ~mask; |
<> | 144:ef7eb2e8f9f7 | 821 | } |
<> | 144:ef7eb2e8f9f7 | 822 | |
<> | 144:ef7eb2e8f9f7 | 823 | /*! |
<> | 144:ef7eb2e8f9f7 | 824 | * @brief Gets the ENET interrupt status flag. |
<> | 144:ef7eb2e8f9f7 | 825 | * |
<> | 144:ef7eb2e8f9f7 | 826 | * @param base ENET peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 827 | * @return The event status of the interrupt source. This is the logical OR of members |
<> | 144:ef7eb2e8f9f7 | 828 | * of the enumeration :: enet_interrupt_enable_t. |
<> | 144:ef7eb2e8f9f7 | 829 | */ |
<> | 144:ef7eb2e8f9f7 | 830 | static inline uint32_t ENET_GetInterruptStatus(ENET_Type *base) |
<> | 144:ef7eb2e8f9f7 | 831 | { |
<> | 144:ef7eb2e8f9f7 | 832 | return base->EIR; |
<> | 144:ef7eb2e8f9f7 | 833 | } |
<> | 144:ef7eb2e8f9f7 | 834 | |
<> | 144:ef7eb2e8f9f7 | 835 | /*! |
<> | 144:ef7eb2e8f9f7 | 836 | * @brief Clears the ENET interrupt events status flag. |
<> | 144:ef7eb2e8f9f7 | 837 | * |
<> | 144:ef7eb2e8f9f7 | 838 | * This function clears enabled ENET interrupts according to the provided mask. The mask |
<> | 144:ef7eb2e8f9f7 | 839 | * is a logical OR of enumeration members. See the @ref enet_interrupt_enable_t. |
<> | 144:ef7eb2e8f9f7 | 840 | * For example, to clear the TX frame interrupt and RX frame interrupt, do this: |
<> | 144:ef7eb2e8f9f7 | 841 | * @code |
<> | 144:ef7eb2e8f9f7 | 842 | * ENET_ClearInterruptStatus(ENET, kENET_TxFrameInterrupt | kENET_RxFrameInterrupt); |
<> | 144:ef7eb2e8f9f7 | 843 | * @endcode |
<> | 144:ef7eb2e8f9f7 | 844 | * |
<> | 144:ef7eb2e8f9f7 | 845 | * @param base ENET peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 846 | * @param mask ENET interrupt source to be cleared. |
<> | 144:ef7eb2e8f9f7 | 847 | * This is the logical OR of members of the enumeration :: enet_interrupt_enable_t. |
<> | 144:ef7eb2e8f9f7 | 848 | */ |
<> | 144:ef7eb2e8f9f7 | 849 | static inline void ENET_ClearInterruptStatus(ENET_Type *base, uint32_t mask) |
<> | 144:ef7eb2e8f9f7 | 850 | { |
<> | 144:ef7eb2e8f9f7 | 851 | base->EIR = mask; |
<> | 144:ef7eb2e8f9f7 | 852 | } |
<> | 144:ef7eb2e8f9f7 | 853 | |
<> | 144:ef7eb2e8f9f7 | 854 | /* @} */ |
<> | 144:ef7eb2e8f9f7 | 855 | |
<> | 144:ef7eb2e8f9f7 | 856 | /*! |
<> | 144:ef7eb2e8f9f7 | 857 | * @name Transactional operation |
<> | 144:ef7eb2e8f9f7 | 858 | * @{ |
<> | 144:ef7eb2e8f9f7 | 859 | */ |
<> | 144:ef7eb2e8f9f7 | 860 | |
<> | 144:ef7eb2e8f9f7 | 861 | /*! |
<> | 144:ef7eb2e8f9f7 | 862 | * @brief Set the callback function. |
<> | 144:ef7eb2e8f9f7 | 863 | * This API is provided for application callback required case when ENET |
<> | 144:ef7eb2e8f9f7 | 864 | * interrupt is enabled. This API should be called after calling ENET_Init. |
<> | 144:ef7eb2e8f9f7 | 865 | * |
<> | 144:ef7eb2e8f9f7 | 866 | * @param handle ENET handler pointer. Should be provided by application. |
<> | 144:ef7eb2e8f9f7 | 867 | * @param callback The ENET callback function. |
<> | 144:ef7eb2e8f9f7 | 868 | * @param userData The callback function parameter. |
<> | 144:ef7eb2e8f9f7 | 869 | */ |
<> | 144:ef7eb2e8f9f7 | 870 | void ENET_SetCallback(enet_handle_t *handle, enet_callback_t callback, void *userData); |
<> | 144:ef7eb2e8f9f7 | 871 | |
<> | 144:ef7eb2e8f9f7 | 872 | /*! |
<> | 144:ef7eb2e8f9f7 | 873 | * @brief Gets the ENET the error statistics of a received frame. |
<> | 144:ef7eb2e8f9f7 | 874 | * |
<> | 144:ef7eb2e8f9f7 | 875 | * This API must be called after the ENET_GetRxFrameSize and before the ENET_ReadFrame(). |
<> | 144:ef7eb2e8f9f7 | 876 | * If the ENET_GetRxFrameSize returns kStatus_ENET_RxFrameError, |
<> | 144:ef7eb2e8f9f7 | 877 | * the ENET_GetRxErrBeforeReadFrame can be used to get the exact error statistics. |
<> | 144:ef7eb2e8f9f7 | 878 | * For example: |
<> | 144:ef7eb2e8f9f7 | 879 | * @code |
<> | 144:ef7eb2e8f9f7 | 880 | * status = ENET_GetRxFrameSize(&g_handle, &length); |
<> | 144:ef7eb2e8f9f7 | 881 | * if (status == kStatus_ENET_RxFrameError) |
<> | 144:ef7eb2e8f9f7 | 882 | * { |
<> | 144:ef7eb2e8f9f7 | 883 | * // Get the error information of the received frame. |
<> | 144:ef7eb2e8f9f7 | 884 | * ENET_GetRxErrBeforeReadFrame(&g_handle, &eErrStatic); |
<> | 144:ef7eb2e8f9f7 | 885 | * // update the receive buffer. |
<> | 144:ef7eb2e8f9f7 | 886 | * ENET_ReadFrame(EXAMPLE_ENET, &g_handle, NULL, 0); |
<> | 144:ef7eb2e8f9f7 | 887 | * } |
<> | 144:ef7eb2e8f9f7 | 888 | * @endcode |
<> | 144:ef7eb2e8f9f7 | 889 | * @param handle The ENET handler structure pointer. This is the same handler pointer used in the ENET_Init. |
<> | 144:ef7eb2e8f9f7 | 890 | * @param eErrorStatic The error statistics structure pointer. |
<> | 144:ef7eb2e8f9f7 | 891 | */ |
<> | 144:ef7eb2e8f9f7 | 892 | void ENET_GetRxErrBeforeReadFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic); |
<> | 144:ef7eb2e8f9f7 | 893 | |
<> | 144:ef7eb2e8f9f7 | 894 | #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE |
<> | 144:ef7eb2e8f9f7 | 895 | /*! |
<> | 144:ef7eb2e8f9f7 | 896 | * @brief Gets the ENET transmit frame statistics after the data send. |
<> | 144:ef7eb2e8f9f7 | 897 | * |
<> | 144:ef7eb2e8f9f7 | 898 | * This interface gets the error statistics of the transmit frame. |
<> | 144:ef7eb2e8f9f7 | 899 | * Because the error information is reported by the uDMA after the data delivery, this interface |
<> | 144:ef7eb2e8f9f7 | 900 | * should be called after the data transmit API. It is recommended to call this function on |
<> | 144:ef7eb2e8f9f7 | 901 | * transmit interrupt handler. After calling the ENET_SendFrame, the |
<> | 144:ef7eb2e8f9f7 | 902 | * transmit interrupt notifies the transmit completion. |
<> | 144:ef7eb2e8f9f7 | 903 | * |
<> | 144:ef7eb2e8f9f7 | 904 | * @param handle The PTP handler pointer. This is the same handler pointer used in the ENET_Init. |
<> | 144:ef7eb2e8f9f7 | 905 | * @param eErrorStatic The error statistics structure pointer. |
<> | 144:ef7eb2e8f9f7 | 906 | * @return The execute status. |
<> | 144:ef7eb2e8f9f7 | 907 | */ |
<> | 144:ef7eb2e8f9f7 | 908 | status_t ENET_GetTxErrAfterSendFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic); |
<> | 144:ef7eb2e8f9f7 | 909 | #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ |
<> | 144:ef7eb2e8f9f7 | 910 | /*! |
<> | 144:ef7eb2e8f9f7 | 911 | * @brief Gets the size of the read frame. |
<> | 144:ef7eb2e8f9f7 | 912 | * This function reads a received frame size from the ENET buffer descriptors. |
<> | 144:ef7eb2e8f9f7 | 913 | * @note The FCS of the frame is removed by MAC controller and the size is the length without the FCS. |
<> | 144:ef7eb2e8f9f7 | 914 | * After calling ENET_GetRxFrameSize, ENET_ReadFrame() should be called to update the |
<> | 144:ef7eb2e8f9f7 | 915 | * receive buffers If the result is not "kStatus_ENET_RxFrameEmpty". |
<> | 144:ef7eb2e8f9f7 | 916 | * |
<> | 144:ef7eb2e8f9f7 | 917 | * @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. |
<> | 144:ef7eb2e8f9f7 | 918 | * @param length The length of the valid frame received. |
<> | 144:ef7eb2e8f9f7 | 919 | * @retval kStatus_ENET_RxFrameEmpty No frame received. Should not call ENET_ReadFrame to read frame. |
<> | 144:ef7eb2e8f9f7 | 920 | * @retval kStatus_ENET_RxFrameError Data error happens. ENET_ReadFrame should be called with NULL data |
<> | 144:ef7eb2e8f9f7 | 921 | * and NULL length to update the receive buffers. |
<> | 144:ef7eb2e8f9f7 | 922 | * @retval kStatus_Success Receive a frame Successfully then the ENET_ReadFrame |
<> | 144:ef7eb2e8f9f7 | 923 | * should be called with the right data buffer and the captured data length input. |
<> | 144:ef7eb2e8f9f7 | 924 | */ |
<> | 144:ef7eb2e8f9f7 | 925 | status_t ENET_GetRxFrameSize(enet_handle_t *handle, uint32_t *length); |
<> | 144:ef7eb2e8f9f7 | 926 | |
<> | 144:ef7eb2e8f9f7 | 927 | /*! |
<> | 144:ef7eb2e8f9f7 | 928 | * @brief Reads a frame from the ENET device. |
<> | 144:ef7eb2e8f9f7 | 929 | * This function reads a frame (both the data and the length) from the ENET buffer descriptors. |
<> | 144:ef7eb2e8f9f7 | 930 | * The ENET_GetRxFrameSize should be used to get the size of the prepared data buffer. |
<> | 144:ef7eb2e8f9f7 | 931 | * @note The FCS of the frame is removed by MAC controller and is not delivered to the application. |
<> | 144:ef7eb2e8f9f7 | 932 | * |
<> | 144:ef7eb2e8f9f7 | 933 | * @param base ENET peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 934 | * @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. |
<> | 144:ef7eb2e8f9f7 | 935 | * @param data The data buffer provided by user to store the frame which memory size should be at least "length". |
<> | 144:ef7eb2e8f9f7 | 936 | * @param length The size of the data buffer which is still the length of the received frame. |
<> | 144:ef7eb2e8f9f7 | 937 | * @return The execute status, successful or failure. |
<> | 144:ef7eb2e8f9f7 | 938 | */ |
<> | 144:ef7eb2e8f9f7 | 939 | status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length); |
<> | 144:ef7eb2e8f9f7 | 940 | |
<> | 144:ef7eb2e8f9f7 | 941 | /*! |
<> | 144:ef7eb2e8f9f7 | 942 | * @brief Transmits an ENET frame. |
<> | 144:ef7eb2e8f9f7 | 943 | * @note The CRC is automatically appended to the data. Input the data |
<> | 144:ef7eb2e8f9f7 | 944 | * to send without the CRC. |
<> | 144:ef7eb2e8f9f7 | 945 | * |
<> | 144:ef7eb2e8f9f7 | 946 | * @param base ENET peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 947 | * @param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init. |
<> | 144:ef7eb2e8f9f7 | 948 | * @param data The data buffer provided by user to be send. |
<> | 144:ef7eb2e8f9f7 | 949 | * @param length The length of the data to be send. |
<> | 144:ef7eb2e8f9f7 | 950 | * @retval kStatus_Success Send frame succeed. |
<> | 144:ef7eb2e8f9f7 | 951 | * @retval kStatus_ENET_TxFrameBusy Transmit buffer descriptor is busy under transmit. |
<> | 144:ef7eb2e8f9f7 | 952 | * @retval kStatus_ENET_TxFrameFail Transmit frame fail. |
<> | 144:ef7eb2e8f9f7 | 953 | */ |
<> | 144:ef7eb2e8f9f7 | 954 | status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length); |
<> | 144:ef7eb2e8f9f7 | 955 | |
<> | 144:ef7eb2e8f9f7 | 956 | /*! |
<> | 144:ef7eb2e8f9f7 | 957 | * @brief The transmit IRQ handler. |
<> | 144:ef7eb2e8f9f7 | 958 | * |
<> | 144:ef7eb2e8f9f7 | 959 | * @param base ENET peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 960 | * @param handle The ENET handler pointer. |
<> | 144:ef7eb2e8f9f7 | 961 | */ |
<> | 144:ef7eb2e8f9f7 | 962 | void ENET_TransmitIRQHandler(ENET_Type *base, enet_handle_t *handle); |
<> | 144:ef7eb2e8f9f7 | 963 | |
<> | 144:ef7eb2e8f9f7 | 964 | /*! |
<> | 144:ef7eb2e8f9f7 | 965 | * @brief The receive IRQ handler. |
<> | 144:ef7eb2e8f9f7 | 966 | * |
<> | 144:ef7eb2e8f9f7 | 967 | * @param base ENET peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 968 | * @param handle The ENET handler pointer. |
<> | 144:ef7eb2e8f9f7 | 969 | */ |
<> | 144:ef7eb2e8f9f7 | 970 | void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle); |
<> | 144:ef7eb2e8f9f7 | 971 | |
<> | 144:ef7eb2e8f9f7 | 972 | /*! |
<> | 144:ef7eb2e8f9f7 | 973 | * @brief The error IRQ handler. |
<> | 144:ef7eb2e8f9f7 | 974 | * |
<> | 144:ef7eb2e8f9f7 | 975 | * @param base ENET peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 976 | * @param handle The ENET handler pointer. |
<> | 144:ef7eb2e8f9f7 | 977 | */ |
<> | 144:ef7eb2e8f9f7 | 978 | void ENET_ErrorIRQHandler(ENET_Type *base, enet_handle_t *handle); |
<> | 144:ef7eb2e8f9f7 | 979 | |
<> | 144:ef7eb2e8f9f7 | 980 | /* @} */ |
<> | 144:ef7eb2e8f9f7 | 981 | |
<> | 144:ef7eb2e8f9f7 | 982 | #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE |
<> | 144:ef7eb2e8f9f7 | 983 | /*! |
<> | 144:ef7eb2e8f9f7 | 984 | * @name ENET PTP 1588 function operation |
<> | 144:ef7eb2e8f9f7 | 985 | * @{ |
<> | 144:ef7eb2e8f9f7 | 986 | */ |
<> | 144:ef7eb2e8f9f7 | 987 | |
<> | 144:ef7eb2e8f9f7 | 988 | /*! |
<> | 144:ef7eb2e8f9f7 | 989 | * @brief Configures the ENET PTP 1588 feature with the basic configuration. |
<> | 144:ef7eb2e8f9f7 | 990 | * The function sets the clock for PTP 1588 timer and enables |
<> | 144:ef7eb2e8f9f7 | 991 | * time stamp interrupts and transmit interrupts for PTP 1588 features. |
<> | 144:ef7eb2e8f9f7 | 992 | * This API should be called when the 1588 feature is enabled |
<> | 144:ef7eb2e8f9f7 | 993 | * or the ENET_ENHANCEDBUFFERDESCRIPTOR_MODE is defined. |
<> | 144:ef7eb2e8f9f7 | 994 | * ENET_Init should be called before calling this API. |
<> | 144:ef7eb2e8f9f7 | 995 | * |
<> | 144:ef7eb2e8f9f7 | 996 | * @note The PTP 1588 time-stamp second increase though time-stamp interrupt handler |
<> | 144:ef7eb2e8f9f7 | 997 | * and the transmit time-stamp store is done through transmit interrupt handler. |
<> | 144:ef7eb2e8f9f7 | 998 | * As a result, the TS interrupt and TX interrupt are enabled when you call this API. |
<> | 144:ef7eb2e8f9f7 | 999 | * |
<> | 144:ef7eb2e8f9f7 | 1000 | * @param base ENET peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 1001 | * @param handle ENET handler pointer. |
<> | 144:ef7eb2e8f9f7 | 1002 | * @param ptpConfig The ENET PTP1588 configuration. |
<> | 144:ef7eb2e8f9f7 | 1003 | */ |
<> | 144:ef7eb2e8f9f7 | 1004 | void ENET_Ptp1588Configure(ENET_Type *base, enet_handle_t *handle, enet_ptp_config_t *ptpConfig); |
<> | 144:ef7eb2e8f9f7 | 1005 | |
<> | 144:ef7eb2e8f9f7 | 1006 | /*! |
<> | 144:ef7eb2e8f9f7 | 1007 | * @brief Starts the ENET PTP 1588 Timer. |
<> | 144:ef7eb2e8f9f7 | 1008 | * This function is used to initialize the PTP timer. After the PTP starts, |
<> | 144:ef7eb2e8f9f7 | 1009 | * the PTP timer starts running. |
<> | 144:ef7eb2e8f9f7 | 1010 | * |
<> | 144:ef7eb2e8f9f7 | 1011 | * @param base ENET peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 1012 | * @param ptpClkSrc The clock source of the PTP timer. |
<> | 144:ef7eb2e8f9f7 | 1013 | */ |
<> | 144:ef7eb2e8f9f7 | 1014 | void ENET_Ptp1588StartTimer(ENET_Type *base, uint32_t ptpClkSrc); |
<> | 144:ef7eb2e8f9f7 | 1015 | |
<> | 144:ef7eb2e8f9f7 | 1016 | /*! |
<> | 144:ef7eb2e8f9f7 | 1017 | * @brief Stops the ENET PTP 1588 Timer. |
<> | 144:ef7eb2e8f9f7 | 1018 | * This function is used to stops the ENET PTP timer. |
<> | 144:ef7eb2e8f9f7 | 1019 | * |
<> | 144:ef7eb2e8f9f7 | 1020 | * @param base ENET peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 1021 | */ |
<> | 144:ef7eb2e8f9f7 | 1022 | static inline void ENET_Ptp1588StopTimer(ENET_Type *base) |
<> | 144:ef7eb2e8f9f7 | 1023 | { |
<> | 144:ef7eb2e8f9f7 | 1024 | /* Disable PTP timer and reset the timer. */ |
<> | 144:ef7eb2e8f9f7 | 1025 | base->ATCR &= ~ENET_ATCR_EN_MASK; |
<> | 144:ef7eb2e8f9f7 | 1026 | base->ATCR |= ENET_ATCR_RESTART_MASK; |
<> | 144:ef7eb2e8f9f7 | 1027 | } |
<> | 144:ef7eb2e8f9f7 | 1028 | |
<> | 144:ef7eb2e8f9f7 | 1029 | /*! |
<> | 144:ef7eb2e8f9f7 | 1030 | * @brief Adjusts the ENET PTP 1588 timer. |
<> | 144:ef7eb2e8f9f7 | 1031 | * |
<> | 144:ef7eb2e8f9f7 | 1032 | * @param base ENET peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 1033 | * @param corrIncrease The correction increment value. This value is added every time the correction |
<> | 144:ef7eb2e8f9f7 | 1034 | * timer expires. A value less than the PTP timer frequency(1/ptpClkSrc) slows down the timer, |
<> | 144:ef7eb2e8f9f7 | 1035 | * a value greater than the 1/ptpClkSrc speeds up the timer. |
<> | 144:ef7eb2e8f9f7 | 1036 | * @param corrPeriod The PTP timer correction counter wrap-around value. This defines after how |
<> | 144:ef7eb2e8f9f7 | 1037 | * many timer clock the correction counter should be reset and trigger a correction |
<> | 144:ef7eb2e8f9f7 | 1038 | * increment on the timer. A value of 0 disables the correction counter and no correction occurs. |
<> | 144:ef7eb2e8f9f7 | 1039 | */ |
<> | 144:ef7eb2e8f9f7 | 1040 | void ENET_Ptp1588AdjustTimer(ENET_Type *base, uint32_t corrIncrease, uint32_t corrPeriod); |
<> | 144:ef7eb2e8f9f7 | 1041 | |
<> | 144:ef7eb2e8f9f7 | 1042 | /*! |
<> | 144:ef7eb2e8f9f7 | 1043 | * @brief Sets ENET PTP 1588 timer channel mode. |
<> | 144:ef7eb2e8f9f7 | 1044 | * |
<> | 144:ef7eb2e8f9f7 | 1045 | * @param base ENET peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 1046 | * @param channel The ENET PTP timer channel number. |
<> | 144:ef7eb2e8f9f7 | 1047 | * @param mode The PTP timer channel mode, see "enet_ptp_timer_channel_mode_t". |
<> | 144:ef7eb2e8f9f7 | 1048 | * @param intEnable Enables or disables the interrupt. |
<> | 144:ef7eb2e8f9f7 | 1049 | */ |
<> | 144:ef7eb2e8f9f7 | 1050 | static inline void ENET_Ptp1588SetChannelMode(ENET_Type *base, |
<> | 144:ef7eb2e8f9f7 | 1051 | enet_ptp_timer_channel_t channel, |
<> | 144:ef7eb2e8f9f7 | 1052 | enet_ptp_timer_channel_mode_t mode, |
<> | 144:ef7eb2e8f9f7 | 1053 | bool intEnable) |
<> | 144:ef7eb2e8f9f7 | 1054 | { |
<> | 144:ef7eb2e8f9f7 | 1055 | uint32_t tcrReg = 0; |
<> | 144:ef7eb2e8f9f7 | 1056 | |
<> | 144:ef7eb2e8f9f7 | 1057 | tcrReg = ENET_TCSR_TMODE(mode) | ENET_TCSR_TIE(intEnable); |
<> | 144:ef7eb2e8f9f7 | 1058 | /* Disable channel mode first. */ |
<> | 144:ef7eb2e8f9f7 | 1059 | base->CHANNEL[channel].TCSR = 0; |
<> | 144:ef7eb2e8f9f7 | 1060 | base->CHANNEL[channel].TCSR = tcrReg; |
<> | 144:ef7eb2e8f9f7 | 1061 | } |
<> | 144:ef7eb2e8f9f7 | 1062 | |
<> | 144:ef7eb2e8f9f7 | 1063 | /*! |
<> | 144:ef7eb2e8f9f7 | 1064 | * @brief Sets ENET PTP 1588 timer channel comparison value. |
<> | 144:ef7eb2e8f9f7 | 1065 | * |
<> | 144:ef7eb2e8f9f7 | 1066 | * @param base ENET peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 1067 | * @param channel The PTP timer channel, see "enet_ptp_timer_channel_t". |
<> | 144:ef7eb2e8f9f7 | 1068 | * @param cmpValue The compare value for the compare setting. |
<> | 144:ef7eb2e8f9f7 | 1069 | */ |
<> | 144:ef7eb2e8f9f7 | 1070 | static inline void ENET_Ptp1588SetChannelCmpValue(ENET_Type *base, enet_ptp_timer_channel_t channel, uint32_t cmpValue) |
<> | 144:ef7eb2e8f9f7 | 1071 | { |
<> | 144:ef7eb2e8f9f7 | 1072 | base->CHANNEL[channel].TCCR = cmpValue; |
<> | 144:ef7eb2e8f9f7 | 1073 | } |
<> | 144:ef7eb2e8f9f7 | 1074 | |
<> | 144:ef7eb2e8f9f7 | 1075 | /*! |
<> | 144:ef7eb2e8f9f7 | 1076 | * @brief Gets the ENET PTP 1588 timer channel status. |
<> | 144:ef7eb2e8f9f7 | 1077 | * |
<> | 144:ef7eb2e8f9f7 | 1078 | * @param base ENET peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 1079 | * @param channel The IEEE 1588 timer channel number. |
<> | 144:ef7eb2e8f9f7 | 1080 | * @return True or false, Compare or capture operation status |
<> | 144:ef7eb2e8f9f7 | 1081 | */ |
<> | 144:ef7eb2e8f9f7 | 1082 | static inline bool ENET_Ptp1588GetChannelStatus(ENET_Type *base, enet_ptp_timer_channel_t channel) |
<> | 144:ef7eb2e8f9f7 | 1083 | { |
<> | 144:ef7eb2e8f9f7 | 1084 | return (0 != (base->CHANNEL[channel].TCSR & ENET_TCSR_TF_MASK)); |
<> | 144:ef7eb2e8f9f7 | 1085 | } |
<> | 144:ef7eb2e8f9f7 | 1086 | |
<> | 144:ef7eb2e8f9f7 | 1087 | /*! |
<> | 144:ef7eb2e8f9f7 | 1088 | * @brief Clears the ENET PTP 1588 timer channel status. |
<> | 144:ef7eb2e8f9f7 | 1089 | * |
<> | 144:ef7eb2e8f9f7 | 1090 | * @param base ENET peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 1091 | * @param channel The IEEE 1588 timer channel number. |
<> | 144:ef7eb2e8f9f7 | 1092 | */ |
<> | 144:ef7eb2e8f9f7 | 1093 | static inline void ENET_Ptp1588ClearChannelStatus(ENET_Type *base, enet_ptp_timer_channel_t channel) |
<> | 144:ef7eb2e8f9f7 | 1094 | { |
<> | 144:ef7eb2e8f9f7 | 1095 | base->CHANNEL[channel].TCSR |= ENET_TCSR_TF_MASK; |
<> | 144:ef7eb2e8f9f7 | 1096 | base->TGSR = (1U << channel); |
<> | 144:ef7eb2e8f9f7 | 1097 | } |
<> | 144:ef7eb2e8f9f7 | 1098 | |
<> | 144:ef7eb2e8f9f7 | 1099 | /*! |
<> | 144:ef7eb2e8f9f7 | 1100 | * @brief Gets the current ENET time from the PTP 1588 timer. |
<> | 144:ef7eb2e8f9f7 | 1101 | * |
<> | 144:ef7eb2e8f9f7 | 1102 | * @param base ENET peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 1103 | * @param handle The ENET state pointer. This is the same state pointer used in the ENET_Init. |
<> | 144:ef7eb2e8f9f7 | 1104 | * @param ptpTime The PTP timer structure. |
<> | 144:ef7eb2e8f9f7 | 1105 | */ |
<> | 144:ef7eb2e8f9f7 | 1106 | void ENET_Ptp1588GetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime); |
<> | 144:ef7eb2e8f9f7 | 1107 | |
<> | 144:ef7eb2e8f9f7 | 1108 | /*! |
<> | 144:ef7eb2e8f9f7 | 1109 | * @brief Sets the ENET PTP 1588 timer to the assigned time. |
<> | 144:ef7eb2e8f9f7 | 1110 | * |
<> | 144:ef7eb2e8f9f7 | 1111 | * @param base ENET peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 1112 | * @param handle The ENET state pointer. This is the same state pointer used in the ENET_Init. |
<> | 144:ef7eb2e8f9f7 | 1113 | * @param ptpTime The timer to be set to the PTP timer. |
<> | 144:ef7eb2e8f9f7 | 1114 | */ |
<> | 144:ef7eb2e8f9f7 | 1115 | void ENET_Ptp1588SetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime); |
<> | 144:ef7eb2e8f9f7 | 1116 | |
<> | 144:ef7eb2e8f9f7 | 1117 | /*! |
<> | 144:ef7eb2e8f9f7 | 1118 | * @brief The IEEE 1588 PTP time stamp interrupt handler. |
<> | 144:ef7eb2e8f9f7 | 1119 | * |
<> | 144:ef7eb2e8f9f7 | 1120 | * @param base ENET peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 1121 | * @param handle The ENET state pointer. This is the same state pointer used in the ENET_Init. |
<> | 144:ef7eb2e8f9f7 | 1122 | */ |
<> | 144:ef7eb2e8f9f7 | 1123 | void ENET_Ptp1588TimerIRQHandler(ENET_Type *base, enet_handle_t *handle); |
<> | 144:ef7eb2e8f9f7 | 1124 | |
<> | 144:ef7eb2e8f9f7 | 1125 | /*! |
<> | 144:ef7eb2e8f9f7 | 1126 | * @brief Gets the time stamp of the received frame. |
<> | 144:ef7eb2e8f9f7 | 1127 | * |
<> | 144:ef7eb2e8f9f7 | 1128 | * This function is used for PTP stack to get the timestamp captured by the ENET driver. |
<> | 144:ef7eb2e8f9f7 | 1129 | * |
<> | 144:ef7eb2e8f9f7 | 1130 | * @param handle The ENET handler pointer.This is the same state pointer used in |
<> | 144:ef7eb2e8f9f7 | 1131 | * ENET_Init. |
<> | 144:ef7eb2e8f9f7 | 1132 | * @param ptpTimeData The special PTP timestamp data for search the receive timestamp. |
<> | 144:ef7eb2e8f9f7 | 1133 | * @retval kStatus_Success Get 1588 timestamp success. |
<> | 144:ef7eb2e8f9f7 | 1134 | * @retval kStatus_ENET_PtpTsRingEmpty 1588 timestamp ring empty. |
<> | 144:ef7eb2e8f9f7 | 1135 | * @retval kStatus_ENET_PtpTsRingFull 1588 timestamp ring full. |
<> | 144:ef7eb2e8f9f7 | 1136 | */ |
<> | 144:ef7eb2e8f9f7 | 1137 | status_t ENET_GetRxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData); |
<> | 144:ef7eb2e8f9f7 | 1138 | |
<> | 144:ef7eb2e8f9f7 | 1139 | /*! |
<> | 144:ef7eb2e8f9f7 | 1140 | * @brief Gets the time stamp of the transmit frame. |
<> | 144:ef7eb2e8f9f7 | 1141 | * |
<> | 144:ef7eb2e8f9f7 | 1142 | * This function is used for PTP stack to get the timestamp captured by the ENET driver. |
<> | 144:ef7eb2e8f9f7 | 1143 | * |
<> | 144:ef7eb2e8f9f7 | 1144 | * @param handle The ENET handler pointer.This is the same state pointer used in |
<> | 144:ef7eb2e8f9f7 | 1145 | * ENET_Init. |
<> | 144:ef7eb2e8f9f7 | 1146 | * @param ptpTimeData The special PTP timestamp data for search the receive timestamp. |
<> | 144:ef7eb2e8f9f7 | 1147 | * @retval kStatus_Success Get 1588 timestamp success. |
<> | 144:ef7eb2e8f9f7 | 1148 | * @retval kStatus_ENET_PtpTsRingEmpty 1588 timestamp ring empty. |
<> | 144:ef7eb2e8f9f7 | 1149 | * @retval kStatus_ENET_PtpTsRingFull 1588 timestamp ring full. |
<> | 144:ef7eb2e8f9f7 | 1150 | */ |
<> | 144:ef7eb2e8f9f7 | 1151 | status_t ENET_GetTxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData); |
<> | 144:ef7eb2e8f9f7 | 1152 | #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ |
<> | 144:ef7eb2e8f9f7 | 1153 | /* @} */ |
<> | 144:ef7eb2e8f9f7 | 1154 | |
<> | 144:ef7eb2e8f9f7 | 1155 | #if defined(__cplusplus) |
<> | 144:ef7eb2e8f9f7 | 1156 | } |
<> | 144:ef7eb2e8f9f7 | 1157 | #endif |
<> | 144:ef7eb2e8f9f7 | 1158 | |
<> | 144:ef7eb2e8f9f7 | 1159 | /*! @}*/ |
<> | 144:ef7eb2e8f9f7 | 1160 | |
<> | 144:ef7eb2e8f9f7 | 1161 | #endif /* _FSL_ENET_H_ */ |