Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_edma.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 144:ef7eb2e8f9f7 3 * All rights reserved.
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 6 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 9 * of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 12 * list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 13 * other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 144:ef7eb2e8f9f7 16 * contributors may be used to endorse or promote products derived from this
<> 144:ef7eb2e8f9f7 17 * software without specific prior written permission.
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 29 */
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 #ifndef _FSL_EDMA_H_
<> 144:ef7eb2e8f9f7 32 #define _FSL_EDMA_H_
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #include "fsl_common.h"
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 /*!
<> 144:ef7eb2e8f9f7 37 * @addtogroup edma_driver
<> 144:ef7eb2e8f9f7 38 * @{
<> 144:ef7eb2e8f9f7 39 */
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 /*! @file */
<> 144:ef7eb2e8f9f7 42 /*******************************************************************************
<> 144:ef7eb2e8f9f7 43 * Definitions
<> 144:ef7eb2e8f9f7 44 ******************************************************************************/
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /*! @name Driver version */
<> 144:ef7eb2e8f9f7 47 /*@{*/
<> 144:ef7eb2e8f9f7 48 /*! @brief eDMA driver version */
<> 144:ef7eb2e8f9f7 49 #define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
<> 144:ef7eb2e8f9f7 50 /*@}*/
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 /*! @brief Compute the offset unit from DCHPRI3 */
<> 144:ef7eb2e8f9f7 53 #define DMA_DCHPRI_INDEX(channel) (((channel) & ~0x03U) | (3 - ((channel)&0x03U)))
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /*! @brief Get the pointer of DCHPRIn */
<> 144:ef7eb2e8f9f7 56 #define DMA_DCHPRIn(base, channel) ((volatile uint8_t *)&(base->DCHPRI3))[DMA_DCHPRI_INDEX(channel)]
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 /*! @brief eDMA transfer configuration */
<> 144:ef7eb2e8f9f7 59 typedef enum _edma_transfer_size
<> 144:ef7eb2e8f9f7 60 {
<> 144:ef7eb2e8f9f7 61 kEDMA_TransferSize1Bytes = 0x0U, /*!< Source/Destination data transfer size is 1 byte every time */
<> 144:ef7eb2e8f9f7 62 kEDMA_TransferSize2Bytes = 0x1U, /*!< Source/Destination data transfer size is 2 bytes every time */
<> 144:ef7eb2e8f9f7 63 kEDMA_TransferSize4Bytes = 0x2U, /*!< Source/Destination data transfer size is 4 bytes every time */
<> 144:ef7eb2e8f9f7 64 kEDMA_TransferSize16Bytes = 0x4U, /*!< Source/Destination data transfer size is 16 bytes every time */
<> 144:ef7eb2e8f9f7 65 kEDMA_TransferSize32Bytes = 0x5U, /*!< Source/Destination data transfer size is 32 bytes every time */
<> 144:ef7eb2e8f9f7 66 } edma_transfer_size_t;
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 /*! @brief eDMA modulo configuration */
<> 144:ef7eb2e8f9f7 69 typedef enum _edma_modulo
<> 144:ef7eb2e8f9f7 70 {
<> 144:ef7eb2e8f9f7 71 kEDMA_ModuloDisable = 0x0U, /*!< Disable modulo */
<> 144:ef7eb2e8f9f7 72 kEDMA_Modulo2bytes, /*!< Circular buffer size is 2 bytes. */
<> 144:ef7eb2e8f9f7 73 kEDMA_Modulo4bytes, /*!< Circular buffer size is 4 bytes. */
<> 144:ef7eb2e8f9f7 74 kEDMA_Modulo8bytes, /*!< Circular buffer size is 8 bytes. */
<> 144:ef7eb2e8f9f7 75 kEDMA_Modulo16bytes, /*!< Circular buffer size is 16 bytes. */
<> 144:ef7eb2e8f9f7 76 kEDMA_Modulo32bytes, /*!< Circular buffer size is 32 bytes. */
<> 144:ef7eb2e8f9f7 77 kEDMA_Modulo64bytes, /*!< Circular buffer size is 64 bytes. */
<> 144:ef7eb2e8f9f7 78 kEDMA_Modulo128bytes, /*!< Circular buffer size is 128 bytes. */
<> 144:ef7eb2e8f9f7 79 kEDMA_Modulo256bytes, /*!< Circular buffer size is 256 bytes. */
<> 144:ef7eb2e8f9f7 80 kEDMA_Modulo512bytes, /*!< Circular buffer size is 512 bytes. */
<> 144:ef7eb2e8f9f7 81 kEDMA_Modulo1Kbytes, /*!< Circular buffer size is 1K bytes. */
<> 144:ef7eb2e8f9f7 82 kEDMA_Modulo2Kbytes, /*!< Circular buffer size is 2K bytes. */
<> 144:ef7eb2e8f9f7 83 kEDMA_Modulo4Kbytes, /*!< Circular buffer size is 4K bytes. */
<> 144:ef7eb2e8f9f7 84 kEDMA_Modulo8Kbytes, /*!< Circular buffer size is 8K bytes. */
<> 144:ef7eb2e8f9f7 85 kEDMA_Modulo16Kbytes, /*!< Circular buffer size is 16K bytes. */
<> 144:ef7eb2e8f9f7 86 kEDMA_Modulo32Kbytes, /*!< Circular buffer size is 32K bytes. */
<> 144:ef7eb2e8f9f7 87 kEDMA_Modulo64Kbytes, /*!< Circular buffer size is 64K bytes. */
<> 144:ef7eb2e8f9f7 88 kEDMA_Modulo128Kbytes, /*!< Circular buffer size is 128K bytes. */
<> 144:ef7eb2e8f9f7 89 kEDMA_Modulo256Kbytes, /*!< Circular buffer size is 256K bytes. */
<> 144:ef7eb2e8f9f7 90 kEDMA_Modulo512Kbytes, /*!< Circular buffer size is 512K bytes. */
<> 144:ef7eb2e8f9f7 91 kEDMA_Modulo1Mbytes, /*!< Circular buffer size is 1M bytes. */
<> 144:ef7eb2e8f9f7 92 kEDMA_Modulo2Mbytes, /*!< Circular buffer size is 2M bytes. */
<> 144:ef7eb2e8f9f7 93 kEDMA_Modulo4Mbytes, /*!< Circular buffer size is 4M bytes. */
<> 144:ef7eb2e8f9f7 94 kEDMA_Modulo8Mbytes, /*!< Circular buffer size is 8M bytes. */
<> 144:ef7eb2e8f9f7 95 kEDMA_Modulo16Mbytes, /*!< Circular buffer size is 16M bytes. */
<> 144:ef7eb2e8f9f7 96 kEDMA_Modulo32Mbytes, /*!< Circular buffer size is 32M bytes. */
<> 144:ef7eb2e8f9f7 97 kEDMA_Modulo64Mbytes, /*!< Circular buffer size is 64M bytes. */
<> 144:ef7eb2e8f9f7 98 kEDMA_Modulo128Mbytes, /*!< Circular buffer size is 128M bytes. */
<> 144:ef7eb2e8f9f7 99 kEDMA_Modulo256Mbytes, /*!< Circular buffer size is 256M bytes. */
<> 144:ef7eb2e8f9f7 100 kEDMA_Modulo512Mbytes, /*!< Circular buffer size is 512M bytes. */
<> 144:ef7eb2e8f9f7 101 kEDMA_Modulo1Gbytes, /*!< Circular buffer size is 1G bytes. */
<> 144:ef7eb2e8f9f7 102 kEDMA_Modulo2Gbytes, /*!< Circular buffer size is 2G bytes. */
<> 144:ef7eb2e8f9f7 103 } edma_modulo_t;
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 /*! @brief Bandwidth control */
<> 144:ef7eb2e8f9f7 106 typedef enum _edma_bandwidth
<> 144:ef7eb2e8f9f7 107 {
<> 144:ef7eb2e8f9f7 108 kEDMA_BandwidthStallNone = 0x0U, /*!< No eDMA engine stalls. */
<> 144:ef7eb2e8f9f7 109 kEDMA_BandwidthStall4Cycle = 0x2U, /*!< eDMA engine stalls for 4 cycles after each read/write. */
<> 144:ef7eb2e8f9f7 110 kEDMA_BandwidthStall8Cycle = 0x3U, /*!< eDMA engine stalls for 8 cycles after each read/write. */
<> 144:ef7eb2e8f9f7 111 } edma_bandwidth_t;
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 /*! @brief Channel link type */
<> 144:ef7eb2e8f9f7 114 typedef enum _edma_channel_link_type
<> 144:ef7eb2e8f9f7 115 {
<> 144:ef7eb2e8f9f7 116 kEDMA_LinkNone = 0x0U, /*!< No channel link */
<> 144:ef7eb2e8f9f7 117 kEDMA_MinorLink, /*!< Channel link after each minor loop */
<> 144:ef7eb2e8f9f7 118 kEDMA_MajorLink, /*!< Channel link while major loop count exhausted */
<> 144:ef7eb2e8f9f7 119 } edma_channel_link_type_t;
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 /*!@brief eDMA channel status flags. */
<> 144:ef7eb2e8f9f7 122 enum _edma_channel_status_flags
<> 144:ef7eb2e8f9f7 123 {
<> 144:ef7eb2e8f9f7 124 kEDMA_DoneFlag = 0x1U, /*!< DONE flag, set while transfer finished, CITER value exhausted*/
<> 144:ef7eb2e8f9f7 125 kEDMA_ErrorFlag = 0x2U, /*!< eDMA error flag, an error occurred in a transfer */
<> 144:ef7eb2e8f9f7 126 kEDMA_InterruptFlag = 0x4U, /*!< eDMA interrupt flag, set while an interrupt occurred of this channel */
<> 144:ef7eb2e8f9f7 127 };
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 /*! @brief eDMA channel error status flags. */
<> 144:ef7eb2e8f9f7 130 enum _edma_error_status_flags
<> 144:ef7eb2e8f9f7 131 {
<> 144:ef7eb2e8f9f7 132 kEDMA_DestinationBusErrorFlag = DMA_ES_DBE_MASK, /*!< Bus error on destination address */
<> 144:ef7eb2e8f9f7 133 kEDMA_SourceBusErrorFlag = DMA_ES_SBE_MASK, /*!< Bus error on the source address */
<> 144:ef7eb2e8f9f7 134 kEDMA_ScatterGatherErrorFlag = DMA_ES_SGE_MASK, /*!< Error on the Scatter/Gather address, not 32byte aligned. */
<> 144:ef7eb2e8f9f7 135 kEDMA_NbytesErrorFlag = DMA_ES_NCE_MASK, /*!< NBYTES/CITER configuration error */
<> 144:ef7eb2e8f9f7 136 kEDMA_DestinationOffsetErrorFlag = DMA_ES_DOE_MASK, /*!< Destination offset not aligned with destination size */
<> 144:ef7eb2e8f9f7 137 kEDMA_DestinationAddressErrorFlag = DMA_ES_DAE_MASK, /*!< Destination address not aligned with destination size */
<> 144:ef7eb2e8f9f7 138 kEDMA_SourceOffsetErrorFlag = DMA_ES_SOE_MASK, /*!< Source offset not aligned with source size */
<> 144:ef7eb2e8f9f7 139 kEDMA_SourceAddressErrorFlag = DMA_ES_SAE_MASK, /*!< Source address not aligned with source size*/
<> 144:ef7eb2e8f9f7 140 kEDMA_ErrorChannelFlag = DMA_ES_ERRCHN_MASK, /*!< Error channel number of the cancelled channel number */
<> 144:ef7eb2e8f9f7 141 kEDMA_ChannelPriorityErrorFlag = DMA_ES_CPE_MASK, /*!< Channel priority is not unique. */
<> 144:ef7eb2e8f9f7 142 kEDMA_TransferCanceledFlag = DMA_ES_ECX_MASK, /*!< Transfer cancelled */
<> 144:ef7eb2e8f9f7 143 #if defined(FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT) && FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 1
<> 144:ef7eb2e8f9f7 144 kEDMA_GroupPriorityErrorFlag = DMA_ES_GPE_MASK, /*!< Group priority is not unique. */
<> 144:ef7eb2e8f9f7 145 #endif
<> 144:ef7eb2e8f9f7 146 kEDMA_ValidFlag = DMA_ES_VLD_MASK, /*!< No error occurred, this bit will be 0, otherwise be 1 */
<> 144:ef7eb2e8f9f7 147 };
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 /*! @brief eDMA interrupt source */
<> 144:ef7eb2e8f9f7 150 typedef enum _edma_interrupt_enable
<> 144:ef7eb2e8f9f7 151 {
<> 144:ef7eb2e8f9f7 152 kEDMA_ErrorInterruptEnable = 0x1U, /*!< Enable interrupt while channel error occurs. */
<> 144:ef7eb2e8f9f7 153 kEDMA_MajorInterruptEnable = DMA_CSR_INTMAJOR_MASK, /*!< Enable interrupt while major count exhausted. */
<> 144:ef7eb2e8f9f7 154 kEDMA_HalfInterruptEnable = DMA_CSR_INTHALF_MASK, /*!< Enable interrupt while major count to half value. */
<> 144:ef7eb2e8f9f7 155 } edma_interrupt_enable_t;
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 /*! @brief eDMA transfer type */
<> 144:ef7eb2e8f9f7 158 typedef enum _edma_transfer_type
<> 144:ef7eb2e8f9f7 159 {
<> 144:ef7eb2e8f9f7 160 kEDMA_MemoryToMemory = 0x0U, /*!< Transfer from memory to memory */
<> 144:ef7eb2e8f9f7 161 kEDMA_PeripheralToMemory, /*!< Transfer from peripheral to memory */
<> 144:ef7eb2e8f9f7 162 kEDMA_MemoryToPeripheral, /*!< Transfer from memory to peripheral */
<> 144:ef7eb2e8f9f7 163 } edma_transfer_type_t;
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 /*! @brief eDMA transfer status */
<> 144:ef7eb2e8f9f7 166 enum _edma_transfer_status
<> 144:ef7eb2e8f9f7 167 {
<> 144:ef7eb2e8f9f7 168 kStatus_EDMA_QueueFull = MAKE_STATUS(kStatusGroup_EDMA, 0), /*!< TCD queue is full. */
<> 144:ef7eb2e8f9f7 169 kStatus_EDMA_Busy = MAKE_STATUS(kStatusGroup_EDMA, 1), /*!< Channel is busy and can't handle the
<> 144:ef7eb2e8f9f7 170 transfer request. */
<> 144:ef7eb2e8f9f7 171 };
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 /*! @brief eDMA global configuration structure.*/
<> 144:ef7eb2e8f9f7 174 typedef struct _edma_config
<> 144:ef7eb2e8f9f7 175 {
<> 144:ef7eb2e8f9f7 176 bool enableContinuousLinkMode; /*!< Enable (true) continuous link mode. Upon minor loop completion, the channel
<> 144:ef7eb2e8f9f7 177 activates again if that channel has a minor loop channel link enabled and
<> 144:ef7eb2e8f9f7 178 the link channel is itself. */
<> 144:ef7eb2e8f9f7 179 bool enableHaltOnError; /*!< Enable (true) transfer halt on error. Any error causes the HALT bit to set.
<> 144:ef7eb2e8f9f7 180 Subsequently, all service requests are ignored until the HALT bit is cleared.*/
<> 144:ef7eb2e8f9f7 181 bool enableRoundRobinArbitration; /*!< Enable (true) round robin channel arbitration method, or fixed priority
<> 144:ef7eb2e8f9f7 182 arbitration is used for channel selection */
<> 144:ef7eb2e8f9f7 183 bool enableDebugMode; /*!< Enable(true) eDMA debug mode. When in debug mode, the eDMA stalls the start of
<> 144:ef7eb2e8f9f7 184 a new channel. Executing channels are allowed to complete. */
<> 144:ef7eb2e8f9f7 185 } edma_config_t;
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 /*!
<> 144:ef7eb2e8f9f7 188 * @brief eDMA transfer configuration
<> 144:ef7eb2e8f9f7 189 *
<> 144:ef7eb2e8f9f7 190 * This structure configures the source/destination transfer attribute.
<> 144:ef7eb2e8f9f7 191 * This figure shows the eDMA's transfer model:
<> 144:ef7eb2e8f9f7 192 * _________________________________________________
<> 144:ef7eb2e8f9f7 193 * | Transfer Size | |
<> 144:ef7eb2e8f9f7 194 * Minor Loop |_______________| Major loop Count 1 |
<> 144:ef7eb2e8f9f7 195 * Bytes | Transfer Size | |
<> 144:ef7eb2e8f9f7 196 * ____________|_______________|____________________|--> Minor loop complete
<> 144:ef7eb2e8f9f7 197 * ____________________________________
<> 144:ef7eb2e8f9f7 198 * | | |
<> 144:ef7eb2e8f9f7 199 * |_______________| Major Loop Count 2 |
<> 144:ef7eb2e8f9f7 200 * | | |
<> 144:ef7eb2e8f9f7 201 * |_______________|____________________|--> Minor loop Complete
<> 144:ef7eb2e8f9f7 202 *
<> 144:ef7eb2e8f9f7 203 * ---------------------------------------------------------> Transfer complete
<> 144:ef7eb2e8f9f7 204 */
<> 144:ef7eb2e8f9f7 205 typedef struct _edma_transfer_config
<> 144:ef7eb2e8f9f7 206 {
<> 144:ef7eb2e8f9f7 207 uint32_t srcAddr; /*!< Source data address. */
<> 144:ef7eb2e8f9f7 208 uint32_t destAddr; /*!< Destination data address. */
<> 144:ef7eb2e8f9f7 209 edma_transfer_size_t srcTransferSize; /*!< Source data transfer size. */
<> 144:ef7eb2e8f9f7 210 edma_transfer_size_t destTransferSize; /*!< Destination data transfer size. */
<> 144:ef7eb2e8f9f7 211 int16_t srcOffset; /*!< Sign-extended offset applied to the current source address to
<> 144:ef7eb2e8f9f7 212 form the next-state value as each source read is completed. */
<> 144:ef7eb2e8f9f7 213 int16_t destOffset; /*!< Sign-extended offset applied to the current destination address to
<> 144:ef7eb2e8f9f7 214 form the next-state value as each destination write is completed. */
<> 144:ef7eb2e8f9f7 215 uint16_t minorLoopBytes; /*!< Bytes to transfer in a minor loop*/
<> 144:ef7eb2e8f9f7 216 uint32_t majorLoopCounts; /*!< Major loop iteration count. */
<> 144:ef7eb2e8f9f7 217 } edma_transfer_config_t;
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 /*! @brief eDMA channel priority configuration */
<> 144:ef7eb2e8f9f7 220 typedef struct _edma_channel_Preemption_config
<> 144:ef7eb2e8f9f7 221 {
<> 144:ef7eb2e8f9f7 222 bool enableChannelPreemption; /*!< If true: channel can be suspended by other channel with higher priority */
<> 144:ef7eb2e8f9f7 223 bool enablePreemptAbility; /*!< If true: channel can suspend other channel with low priority */
<> 144:ef7eb2e8f9f7 224 uint8_t channelPriority; /*!< Channel priority */
<> 144:ef7eb2e8f9f7 225 } edma_channel_Preemption_config_t;
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 /*! @brief eDMA minor offset configuration */
<> 144:ef7eb2e8f9f7 228 typedef struct _edma_minor_offset_config
<> 144:ef7eb2e8f9f7 229 {
<> 144:ef7eb2e8f9f7 230 bool enableSrcMinorOffset; /*!< Enable(true) or Disable(false) source minor loop offset. */
<> 144:ef7eb2e8f9f7 231 bool enableDestMinorOffset; /*!< Enable(true) or Disable(false) destination minor loop offset. */
<> 144:ef7eb2e8f9f7 232 uint32_t minorOffset; /*!< Offset for minor loop mapping. */
<> 144:ef7eb2e8f9f7 233 } edma_minor_offset_config_t;
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 /*!
<> 144:ef7eb2e8f9f7 236 * @brief eDMA TCD.
<> 144:ef7eb2e8f9f7 237 *
<> 144:ef7eb2e8f9f7 238 * This structure is same as TCD register which is described in reference manual,
<> 144:ef7eb2e8f9f7 239 * and is used to configure scatter/gather feature as a next hardware TCD.
<> 144:ef7eb2e8f9f7 240 */
<> 144:ef7eb2e8f9f7 241 typedef struct _edma_tcd
<> 144:ef7eb2e8f9f7 242 {
<> 144:ef7eb2e8f9f7 243 __IO uint32_t SADDR; /*!< SADDR register, used to save source address */
<> 144:ef7eb2e8f9f7 244 __IO uint16_t SOFF; /*!< SOFF register, save offset bytes every transfer */
<> 144:ef7eb2e8f9f7 245 __IO uint16_t ATTR; /*!< ATTR register, source/destination transfer size and modulo */
<> 144:ef7eb2e8f9f7 246 __IO uint32_t NBYTES; /*!< Nbytes register, minor loop length in bytes */
<> 144:ef7eb2e8f9f7 247 __IO uint32_t SLAST; /*!< SLAST register */
<> 144:ef7eb2e8f9f7 248 __IO uint32_t DADDR; /*!< DADDR register, used for destination address */
<> 144:ef7eb2e8f9f7 249 __IO uint16_t DOFF; /*!< DOFF register, used for destination offset */
<> 144:ef7eb2e8f9f7 250 __IO uint16_t CITER; /*!< CITER register, current minor loop numbers, for unfinished minor loop.*/
<> 144:ef7eb2e8f9f7 251 __IO uint32_t DLAST_SGA; /*!< DLASTSGA register, next stcd address used in scatter-gather mode */
<> 144:ef7eb2e8f9f7 252 __IO uint16_t CSR; /*!< CSR register, for TCD control status */
<> 144:ef7eb2e8f9f7 253 __IO uint16_t BITER; /*!< BITER register, begin minor loop count. */
<> 144:ef7eb2e8f9f7 254 } edma_tcd_t;
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 /*! @brief Callback for eDMA */
<> 144:ef7eb2e8f9f7 257 struct _edma_handle;
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 /*! @brief Define Callback function for eDMA. */
<> 144:ef7eb2e8f9f7 260 typedef void (*edma_callback)(struct _edma_handle *handle, void *userData, bool transferDone, uint32_t tcds);
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 /*! @brief eDMA transfer handle structure */
<> 144:ef7eb2e8f9f7 263 typedef struct _edma_handle
<> 144:ef7eb2e8f9f7 264 {
<> 144:ef7eb2e8f9f7 265 edma_callback callback; /*!< Callback function for major count exhausted. */
<> 144:ef7eb2e8f9f7 266 void *userData; /*!< Callback function parameter. */
<> 144:ef7eb2e8f9f7 267 DMA_Type *base; /*!< eDMA peripheral base address. */
<> 144:ef7eb2e8f9f7 268 edma_tcd_t *tcdPool; /*!< Pointer to memory stored TCDs. */
<> 144:ef7eb2e8f9f7 269 uint8_t channel; /*!< eDMA channel number. */
<> 144:ef7eb2e8f9f7 270 volatile int8_t header; /*!< The first TCD index. */
<> 144:ef7eb2e8f9f7 271 volatile int8_t tail; /*!< The last TCD index. */
<> 144:ef7eb2e8f9f7 272 volatile int8_t tcdUsed; /*!< The number of used TCD slots. */
<> 144:ef7eb2e8f9f7 273 volatile int8_t tcdSize; /*!< The total number of TCD slots in the queue. */
<> 144:ef7eb2e8f9f7 274 uint8_t flags; /*!< The status of the current channel. */
<> 144:ef7eb2e8f9f7 275 } edma_handle_t;
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 /*******************************************************************************
<> 144:ef7eb2e8f9f7 278 * APIs
<> 144:ef7eb2e8f9f7 279 ******************************************************************************/
<> 144:ef7eb2e8f9f7 280 #if defined(__cplusplus)
<> 144:ef7eb2e8f9f7 281 extern "C" {
<> 144:ef7eb2e8f9f7 282 #endif /* __cplusplus */
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 /*!
<> 144:ef7eb2e8f9f7 285 * @name eDMA initialization and De-initialization
<> 144:ef7eb2e8f9f7 286 * @{
<> 144:ef7eb2e8f9f7 287 */
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 /*!
<> 144:ef7eb2e8f9f7 290 * @brief Initializes eDMA peripheral.
<> 144:ef7eb2e8f9f7 291 *
<> 144:ef7eb2e8f9f7 292 * This function ungates the eDMA clock and configure eDMA peripheral according
<> 144:ef7eb2e8f9f7 293 * to the configuration structure.
<> 144:ef7eb2e8f9f7 294 *
<> 144:ef7eb2e8f9f7 295 * @param base eDMA peripheral base address.
<> 144:ef7eb2e8f9f7 296 * @param config Pointer to configuration structure, see "edma_config_t".
<> 144:ef7eb2e8f9f7 297 * @note This function enable the minor loop map feature.
<> 144:ef7eb2e8f9f7 298 */
<> 144:ef7eb2e8f9f7 299 void EDMA_Init(DMA_Type *base, const edma_config_t *config);
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 /*!
<> 144:ef7eb2e8f9f7 302 * @brief Deinitializes eDMA peripheral.
<> 144:ef7eb2e8f9f7 303 *
<> 144:ef7eb2e8f9f7 304 * This function gates the eDMA clock.
<> 144:ef7eb2e8f9f7 305 *
<> 144:ef7eb2e8f9f7 306 * @param base eDMA peripheral base address.
<> 144:ef7eb2e8f9f7 307 */
<> 144:ef7eb2e8f9f7 308 void EDMA_Deinit(DMA_Type *base);
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 /*!
<> 144:ef7eb2e8f9f7 311 * @brief Gets the eDMA default configuration structure.
<> 144:ef7eb2e8f9f7 312 *
<> 144:ef7eb2e8f9f7 313 * This function sets the configuration structure to a default value.
<> 144:ef7eb2e8f9f7 314 * The default configuration is set to the following value:
<> 144:ef7eb2e8f9f7 315 * @code
<> 144:ef7eb2e8f9f7 316 * config.enableContinuousLinkMode = false;
<> 144:ef7eb2e8f9f7 317 * config.enableHaltOnError = true;
<> 144:ef7eb2e8f9f7 318 * config.enableRoundRobinArbitration = false;
<> 144:ef7eb2e8f9f7 319 * config.enableDebugMode = false;
<> 144:ef7eb2e8f9f7 320 * @endcode
<> 144:ef7eb2e8f9f7 321 *
<> 144:ef7eb2e8f9f7 322 * @param config Pointer to eDMA configuration structure.
<> 144:ef7eb2e8f9f7 323 */
<> 144:ef7eb2e8f9f7 324 void EDMA_GetDefaultConfig(edma_config_t *config);
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 /* @} */
<> 144:ef7eb2e8f9f7 327 /*!
<> 144:ef7eb2e8f9f7 328 * @name eDMA Channel Operation
<> 144:ef7eb2e8f9f7 329 * @{
<> 144:ef7eb2e8f9f7 330 */
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 /*!
<> 144:ef7eb2e8f9f7 333 * @brief Sets all TCD registers to a default value.
<> 144:ef7eb2e8f9f7 334 *
<> 144:ef7eb2e8f9f7 335 * This function sets TCD registers for this channel to default value.
<> 144:ef7eb2e8f9f7 336 *
<> 144:ef7eb2e8f9f7 337 * @param base eDMA peripheral base address.
<> 144:ef7eb2e8f9f7 338 * @param channel eDMA channel number.
<> 144:ef7eb2e8f9f7 339 * @note This function must not be called while the channel transfer is on-going,
<> 144:ef7eb2e8f9f7 340 * or it will case unpredicated results.
<> 144:ef7eb2e8f9f7 341 * @note This function will enable auto stop request feature.
<> 144:ef7eb2e8f9f7 342 */
<> 144:ef7eb2e8f9f7 343 void EDMA_ResetChannel(DMA_Type *base, uint32_t channel);
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 /*!
<> 144:ef7eb2e8f9f7 346 * @brief Configures the eDMA transfer attribute.
<> 144:ef7eb2e8f9f7 347 *
<> 144:ef7eb2e8f9f7 348 * This function configure the transfer attribute, including source address, destination address,
<> 144:ef7eb2e8f9f7 349 * transfer size, address offset, and so on. It also configures the scatter gather feature if the
<> 144:ef7eb2e8f9f7 350 * user supplies the TCD address.
<> 144:ef7eb2e8f9f7 351 * Example:
<> 144:ef7eb2e8f9f7 352 * @code
<> 144:ef7eb2e8f9f7 353 * edma_transfer_t config;
<> 144:ef7eb2e8f9f7 354 * edma_tcd_t tcd;
<> 144:ef7eb2e8f9f7 355 * config.srcAddr = ..;
<> 144:ef7eb2e8f9f7 356 * config.destAddr = ..;
<> 144:ef7eb2e8f9f7 357 * ...
<> 144:ef7eb2e8f9f7 358 * EDMA_SetTransferConfig(DMA0, channel, &config, &stcd);
<> 144:ef7eb2e8f9f7 359 * @endcode
<> 144:ef7eb2e8f9f7 360 *
<> 144:ef7eb2e8f9f7 361 * @param base eDMA peripheral base address.
<> 144:ef7eb2e8f9f7 362 * @param channel eDMA channel number.
<> 144:ef7eb2e8f9f7 363 * @param config Pointer to eDMA transfer configuration structure.
<> 144:ef7eb2e8f9f7 364 * @param nextTcd Point to TCD structure. It can be NULL if user
<> 144:ef7eb2e8f9f7 365 * do not want to enable scatter/gather feature.
<> 144:ef7eb2e8f9f7 366 * @note If nextTcd is not NULL, it means scatter gather feature will be enabled.
<> 144:ef7eb2e8f9f7 367 * And DREQ bit will be cleared in the previous transfer configuration which
<> 144:ef7eb2e8f9f7 368 * will be set in eDMA_ResetChannel.
<> 144:ef7eb2e8f9f7 369 */
<> 144:ef7eb2e8f9f7 370 void EDMA_SetTransferConfig(DMA_Type *base,
<> 144:ef7eb2e8f9f7 371 uint32_t channel,
<> 144:ef7eb2e8f9f7 372 const edma_transfer_config_t *config,
<> 144:ef7eb2e8f9f7 373 edma_tcd_t *nextTcd);
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 /*!
<> 144:ef7eb2e8f9f7 376 * @brief Configures the eDMA minor offset feature.
<> 144:ef7eb2e8f9f7 377 *
<> 144:ef7eb2e8f9f7 378 * Minor offset means signed-extended value added to source address or destination
<> 144:ef7eb2e8f9f7 379 * address after each minor loop.
<> 144:ef7eb2e8f9f7 380 *
<> 144:ef7eb2e8f9f7 381 * @param base eDMA peripheral base address.
<> 144:ef7eb2e8f9f7 382 * @param channel eDMA channel number.
<> 144:ef7eb2e8f9f7 383 * @param config Pointer to Minor offset configuration structure.
<> 144:ef7eb2e8f9f7 384 */
<> 144:ef7eb2e8f9f7 385 void EDMA_SetMinorOffsetConfig(DMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config);
<> 144:ef7eb2e8f9f7 386
<> 144:ef7eb2e8f9f7 387 /*!
<> 144:ef7eb2e8f9f7 388 * @brief Configures the eDMA channel preemption feature.
<> 144:ef7eb2e8f9f7 389 *
<> 144:ef7eb2e8f9f7 390 * This function configures the channel preemption attribute and the priority of the channel.
<> 144:ef7eb2e8f9f7 391 *
<> 144:ef7eb2e8f9f7 392 * @param base eDMA peripheral base address.
<> 144:ef7eb2e8f9f7 393 * @param channel eDMA channel number
<> 144:ef7eb2e8f9f7 394 * @param config Pointer to channel preemption configuration structure.
<> 144:ef7eb2e8f9f7 395 */
<> 144:ef7eb2e8f9f7 396 static inline void EDMA_SetChannelPreemptionConfig(DMA_Type *base,
<> 144:ef7eb2e8f9f7 397 uint32_t channel,
<> 144:ef7eb2e8f9f7 398 const edma_channel_Preemption_config_t *config)
<> 144:ef7eb2e8f9f7 399 {
<> 144:ef7eb2e8f9f7 400 assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
<> 144:ef7eb2e8f9f7 401 assert(config != NULL);
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 DMA_DCHPRIn(base, channel) =
<> 144:ef7eb2e8f9f7 404 (DMA_DCHPRI0_DPA(!config->enablePreemptAbility) | DMA_DCHPRI0_ECP(config->enableChannelPreemption) |
<> 144:ef7eb2e8f9f7 405 DMA_DCHPRI0_CHPRI(config->channelPriority));
<> 144:ef7eb2e8f9f7 406 }
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 /*!
<> 144:ef7eb2e8f9f7 409 * @brief Sets the channel link for the eDMA transfer.
<> 144:ef7eb2e8f9f7 410 *
<> 144:ef7eb2e8f9f7 411 * This function configures minor link or major link mode. The minor link means that the channel link is
<> 144:ef7eb2e8f9f7 412 * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is exhausted.
<> 144:ef7eb2e8f9f7 413 *
<> 144:ef7eb2e8f9f7 414 * @param base eDMA peripheral base address.
<> 144:ef7eb2e8f9f7 415 * @param channel eDMA channel number.
<> 144:ef7eb2e8f9f7 416 * @param type Channel link type, it can be one of:
<> 144:ef7eb2e8f9f7 417 * @arg kEDMA_LinkNone
<> 144:ef7eb2e8f9f7 418 * @arg kEDMA_MinorLink
<> 144:ef7eb2e8f9f7 419 * @arg kEDMA_MajorLink
<> 144:ef7eb2e8f9f7 420 * @param linkedChannel The linked channel number.
<> 144:ef7eb2e8f9f7 421 * @note User should ensure that DONE flag is cleared before call this interface, or the configuration will be invalid.
<> 144:ef7eb2e8f9f7 422 */
<> 144:ef7eb2e8f9f7 423 void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel);
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 /*!
<> 144:ef7eb2e8f9f7 426 * @brief Sets the bandwidth for the eDMA transfer.
<> 144:ef7eb2e8f9f7 427 *
<> 144:ef7eb2e8f9f7 428 * In general, because the eDMA processes the minor loop, it continuously generates read/write sequences
<> 144:ef7eb2e8f9f7 429 * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of
<> 144:ef7eb2e8f9f7 430 * each read/write access to control the bus request bandwidth seen by the crossbar switch.
<> 144:ef7eb2e8f9f7 431 *
<> 144:ef7eb2e8f9f7 432 * @param base eDMA peripheral base address.
<> 144:ef7eb2e8f9f7 433 * @param channel eDMA channel number.
<> 144:ef7eb2e8f9f7 434 * @param bandWidth Bandwidth setting, it can be one of:
<> 144:ef7eb2e8f9f7 435 * @arg kEDMABandwidthStallNone
<> 144:ef7eb2e8f9f7 436 * @arg kEDMABandwidthStall4Cycle
<> 144:ef7eb2e8f9f7 437 * @arg kEDMABandwidthStall8Cycle
<> 144:ef7eb2e8f9f7 438 */
<> 144:ef7eb2e8f9f7 439 void EDMA_SetBandWidth(DMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth);
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441 /*!
<> 144:ef7eb2e8f9f7 442 * @brief Sets the source modulo and destination modulo for eDMA transfer.
<> 144:ef7eb2e8f9f7 443 *
<> 144:ef7eb2e8f9f7 444 * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF)
<> 144:ef7eb2e8f9f7 445 * calculation is performed or the original register value. It provides the ability to implement a circular data
<> 144:ef7eb2e8f9f7 446 * queue easily.
<> 144:ef7eb2e8f9f7 447 *
<> 144:ef7eb2e8f9f7 448 * @param base eDMA peripheral base address.
<> 144:ef7eb2e8f9f7 449 * @param channel eDMA channel number.
<> 144:ef7eb2e8f9f7 450 * @param srcModulo Source modulo value.
<> 144:ef7eb2e8f9f7 451 * @param destModulo Destination modulo value.
<> 144:ef7eb2e8f9f7 452 */
<> 144:ef7eb2e8f9f7 453 void EDMA_SetModulo(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo);
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455 #if defined(FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT) && FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT
<> 144:ef7eb2e8f9f7 456 /*!
<> 144:ef7eb2e8f9f7 457 * @brief Enables an async request for the eDMA transfer.
<> 144:ef7eb2e8f9f7 458 *
<> 144:ef7eb2e8f9f7 459 * @param base eDMA peripheral base address.
<> 144:ef7eb2e8f9f7 460 * @param channel eDMA channel number.
<> 144:ef7eb2e8f9f7 461 * @param enable The command for enable(ture) or disable(false).
<> 144:ef7eb2e8f9f7 462 */
<> 144:ef7eb2e8f9f7 463 static inline void EDMA_EnableAsyncRequest(DMA_Type *base, uint32_t channel, bool enable)
<> 144:ef7eb2e8f9f7 464 {
<> 144:ef7eb2e8f9f7 465 assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
<> 144:ef7eb2e8f9f7 466
<> 144:ef7eb2e8f9f7 467 base->EARS = (base->EARS & (~(1U << channel))) | ((uint32_t)enable << channel);
<> 144:ef7eb2e8f9f7 468 }
<> 144:ef7eb2e8f9f7 469 #endif /* FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT */
<> 144:ef7eb2e8f9f7 470
<> 144:ef7eb2e8f9f7 471 /*!
<> 144:ef7eb2e8f9f7 472 * @brief Enables an auto stop request for the eDMA transfer.
<> 144:ef7eb2e8f9f7 473 *
<> 144:ef7eb2e8f9f7 474 * If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request.
<> 144:ef7eb2e8f9f7 475 *
<> 144:ef7eb2e8f9f7 476 * @param base eDMA peripheral base address.
<> 144:ef7eb2e8f9f7 477 * @param channel eDMA channel number.
<> 144:ef7eb2e8f9f7 478 * @param enable The command for enable (true) or disable (false).
<> 144:ef7eb2e8f9f7 479 */
<> 144:ef7eb2e8f9f7 480 static inline void EDMA_EnableAutoStopRequest(DMA_Type *base, uint32_t channel, bool enable)
<> 144:ef7eb2e8f9f7 481 {
<> 144:ef7eb2e8f9f7 482 assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
<> 144:ef7eb2e8f9f7 483
<> 144:ef7eb2e8f9f7 484 base->TCD[channel].CSR = (base->TCD[channel].CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ(enable);
<> 144:ef7eb2e8f9f7 485 }
<> 144:ef7eb2e8f9f7 486
<> 144:ef7eb2e8f9f7 487 /*!
<> 144:ef7eb2e8f9f7 488 * @brief Enables the interrupt source for the eDMA transfer.
<> 144:ef7eb2e8f9f7 489 *
<> 144:ef7eb2e8f9f7 490 * @param base eDMA peripheral base address.
<> 144:ef7eb2e8f9f7 491 * @param channel eDMA channel number.
<> 144:ef7eb2e8f9f7 492 * @param mask The mask of interrupt source to be set. User need to use
<> 144:ef7eb2e8f9f7 493 * the defined edma_interrupt_enable_t type.
<> 144:ef7eb2e8f9f7 494 */
<> 144:ef7eb2e8f9f7 495 void EDMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask);
<> 144:ef7eb2e8f9f7 496
<> 144:ef7eb2e8f9f7 497 /*!
<> 144:ef7eb2e8f9f7 498 * @brief Disables the interrupt source for the eDMA transfer.
<> 144:ef7eb2e8f9f7 499 *
<> 144:ef7eb2e8f9f7 500 * @param base eDMA peripheral base address.
<> 144:ef7eb2e8f9f7 501 * @param channel eDMA channel number.
<> 144:ef7eb2e8f9f7 502 * @param mask The mask of interrupt source to be set. Use
<> 144:ef7eb2e8f9f7 503 * the defined edma_interrupt_enable_t type.
<> 144:ef7eb2e8f9f7 504 */
<> 144:ef7eb2e8f9f7 505 void EDMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask);
<> 144:ef7eb2e8f9f7 506
<> 144:ef7eb2e8f9f7 507 /* @} */
<> 144:ef7eb2e8f9f7 508 /*!
<> 144:ef7eb2e8f9f7 509 * @name eDMA TCD Operation
<> 144:ef7eb2e8f9f7 510 * @{
<> 144:ef7eb2e8f9f7 511 */
<> 144:ef7eb2e8f9f7 512
<> 144:ef7eb2e8f9f7 513 /*!
<> 144:ef7eb2e8f9f7 514 * @brief Sets all fields to default values for the TCD structure.
<> 144:ef7eb2e8f9f7 515 *
<> 144:ef7eb2e8f9f7 516 * This function sets all fields for this TCD structure to default value.
<> 144:ef7eb2e8f9f7 517 *
<> 144:ef7eb2e8f9f7 518 * @param tcd Pointer to the TCD structure.
<> 144:ef7eb2e8f9f7 519 * @note This function will enable auto stop request feature.
<> 144:ef7eb2e8f9f7 520 */
<> 144:ef7eb2e8f9f7 521 void EDMA_TcdReset(edma_tcd_t *tcd);
<> 144:ef7eb2e8f9f7 522
<> 144:ef7eb2e8f9f7 523 /*!
<> 144:ef7eb2e8f9f7 524 * @brief Configures the eDMA TCD transfer attribute.
<> 144:ef7eb2e8f9f7 525 *
<> 144:ef7eb2e8f9f7 526 * TCD is a transfer control descriptor. The content of the TCD is the same as hardware TCD registers.
<> 144:ef7eb2e8f9f7 527 * STCD is used in scatter-gather mode.
<> 144:ef7eb2e8f9f7 528 * This function configures the TCD transfer attribute, including source address, destination address,
<> 144:ef7eb2e8f9f7 529 * transfer size, address offset, and so on. It also configures the scatter gather feature if the
<> 144:ef7eb2e8f9f7 530 * user supplies the next TCD address.
<> 144:ef7eb2e8f9f7 531 * Example:
<> 144:ef7eb2e8f9f7 532 * @code
<> 144:ef7eb2e8f9f7 533 * edma_transfer_t config = {
<> 144:ef7eb2e8f9f7 534 * ...
<> 144:ef7eb2e8f9f7 535 * }
<> 144:ef7eb2e8f9f7 536 * edma_tcd_t tcd __aligned(32);
<> 144:ef7eb2e8f9f7 537 * edma_tcd_t nextTcd __aligned(32);
<> 144:ef7eb2e8f9f7 538 * EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd);
<> 144:ef7eb2e8f9f7 539 * @endcode
<> 144:ef7eb2e8f9f7 540 *
<> 144:ef7eb2e8f9f7 541 * @param tcd Pointer to the TCD structure.
<> 144:ef7eb2e8f9f7 542 * @param config Pointer to eDMA transfer configuration structure.
<> 144:ef7eb2e8f9f7 543 * @param nextTcd Pointer to the next TCD structure. It can be NULL if user
<> 144:ef7eb2e8f9f7 544 * do not want to enable scatter/gather feature.
<> 144:ef7eb2e8f9f7 545 * @note TCD address should be 32 bytes aligned, or it will cause eDMA error.
<> 144:ef7eb2e8f9f7 546 * @note If nextTcd is not NULL, it means scatter gather feature will be enabled.
<> 144:ef7eb2e8f9f7 547 * And DREQ bit will be cleared in the previous transfer configuration which
<> 144:ef7eb2e8f9f7 548 * will be set in EDMA_TcdReset.
<> 144:ef7eb2e8f9f7 549 */
<> 144:ef7eb2e8f9f7 550 void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd);
<> 144:ef7eb2e8f9f7 551
<> 144:ef7eb2e8f9f7 552 /*!
<> 144:ef7eb2e8f9f7 553 * @brief Configures the eDMA TCD minor offset feature.
<> 144:ef7eb2e8f9f7 554 *
<> 144:ef7eb2e8f9f7 555 * Minor offset is a signed-extended value added to the source address or destination
<> 144:ef7eb2e8f9f7 556 * address after each minor loop.
<> 144:ef7eb2e8f9f7 557 *
<> 144:ef7eb2e8f9f7 558 * @param tcd Point to the TCD structure.
<> 144:ef7eb2e8f9f7 559 * @param config Pointer to Minor offset configuration structure.
<> 144:ef7eb2e8f9f7 560 */
<> 144:ef7eb2e8f9f7 561 void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config);
<> 144:ef7eb2e8f9f7 562
<> 144:ef7eb2e8f9f7 563 /*!
<> 144:ef7eb2e8f9f7 564 * @brief Sets the channel link for eDMA TCD.
<> 144:ef7eb2e8f9f7 565 *
<> 144:ef7eb2e8f9f7 566 * This function configures either a minor link or a major link. The minor link means the channel link is
<> 144:ef7eb2e8f9f7 567 * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is exhausted.
<> 144:ef7eb2e8f9f7 568 *
<> 144:ef7eb2e8f9f7 569 * @note User should ensure that DONE flag is cleared before call this interface, or the configuration will be invalid.
<> 144:ef7eb2e8f9f7 570 * @param tcd Point to the TCD structure.
<> 144:ef7eb2e8f9f7 571 * @param type Channel link type, it can be one of:
<> 144:ef7eb2e8f9f7 572 * @arg kEDMA_LinkNone
<> 144:ef7eb2e8f9f7 573 * @arg kEDMA_MinorLink
<> 144:ef7eb2e8f9f7 574 * @arg kEDMA_MajorLink
<> 144:ef7eb2e8f9f7 575 * @param linkedChannel The linked channel number.
<> 144:ef7eb2e8f9f7 576 */
<> 144:ef7eb2e8f9f7 577 void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel);
<> 144:ef7eb2e8f9f7 578
<> 144:ef7eb2e8f9f7 579 /*!
<> 144:ef7eb2e8f9f7 580 * @brief Sets the bandwidth for the eDMA TCD.
<> 144:ef7eb2e8f9f7 581 *
<> 144:ef7eb2e8f9f7 582 * In general, because the eDMA processes the minor loop, it continuously generates read/write sequences
<> 144:ef7eb2e8f9f7 583 * until the minor count is exhausted. Bandwidth forces the eDMA to stall after the completion of
<> 144:ef7eb2e8f9f7 584 * each read/write access to control the bus request bandwidth seen by the crossbar switch.
<> 144:ef7eb2e8f9f7 585 * @param tcd Point to the TCD structure.
<> 144:ef7eb2e8f9f7 586 * @param bandWidth Bandwidth setting, it can be one of:
<> 144:ef7eb2e8f9f7 587 * @arg kEDMABandwidthStallNone
<> 144:ef7eb2e8f9f7 588 * @arg kEDMABandwidthStall4Cycle
<> 144:ef7eb2e8f9f7 589 * @arg kEDMABandwidthStall8Cycle
<> 144:ef7eb2e8f9f7 590 */
<> 144:ef7eb2e8f9f7 591 static inline void EDMA_TcdSetBandWidth(edma_tcd_t *tcd, edma_bandwidth_t bandWidth)
<> 144:ef7eb2e8f9f7 592 {
<> 144:ef7eb2e8f9f7 593 assert(tcd != NULL);
<> 144:ef7eb2e8f9f7 594 assert(((uint32_t)tcd & 0x1FU) == 0);
<> 144:ef7eb2e8f9f7 595
<> 144:ef7eb2e8f9f7 596 tcd->CSR = (tcd->CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth);
<> 144:ef7eb2e8f9f7 597 }
<> 144:ef7eb2e8f9f7 598
<> 144:ef7eb2e8f9f7 599 /*!
<> 144:ef7eb2e8f9f7 600 * @brief Sets the source modulo and destination modulo for eDMA TCD.
<> 144:ef7eb2e8f9f7 601 *
<> 144:ef7eb2e8f9f7 602 * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF)
<> 144:ef7eb2e8f9f7 603 * calculation is performed or the original register value. It provides the ability to implement a circular data
<> 144:ef7eb2e8f9f7 604 * queue easily.
<> 144:ef7eb2e8f9f7 605 *
<> 144:ef7eb2e8f9f7 606 * @param tcd Point to the TCD structure.
<> 144:ef7eb2e8f9f7 607 * @param srcModulo Source modulo value.
<> 144:ef7eb2e8f9f7 608 * @param destModulo Destination modulo value.
<> 144:ef7eb2e8f9f7 609 */
<> 144:ef7eb2e8f9f7 610 void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo);
<> 144:ef7eb2e8f9f7 611
<> 144:ef7eb2e8f9f7 612 /*!
<> 144:ef7eb2e8f9f7 613 * @brief Sets the auto stop request for the eDMA TCD.
<> 144:ef7eb2e8f9f7 614 *
<> 144:ef7eb2e8f9f7 615 * If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request.
<> 144:ef7eb2e8f9f7 616 *
<> 144:ef7eb2e8f9f7 617 * @param tcd Point to the TCD structure.
<> 144:ef7eb2e8f9f7 618 * @param enable The command for enable(ture) or disable(false).
<> 144:ef7eb2e8f9f7 619 */
<> 144:ef7eb2e8f9f7 620 static inline void EDMA_TcdEnableAutoStopRequest(edma_tcd_t *tcd, bool enable)
<> 144:ef7eb2e8f9f7 621 {
<> 144:ef7eb2e8f9f7 622 assert(tcd != NULL);
<> 144:ef7eb2e8f9f7 623 assert(((uint32_t)tcd & 0x1FU) == 0);
<> 144:ef7eb2e8f9f7 624
<> 144:ef7eb2e8f9f7 625 tcd->CSR = (tcd->CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ(enable);
<> 144:ef7eb2e8f9f7 626 }
<> 144:ef7eb2e8f9f7 627
<> 144:ef7eb2e8f9f7 628 /*!
<> 144:ef7eb2e8f9f7 629 * @brief Enables the interrupt source for the eDMA TCD.
<> 144:ef7eb2e8f9f7 630 *
<> 144:ef7eb2e8f9f7 631 * @param tcd Point to the TCD structure.
<> 144:ef7eb2e8f9f7 632 * @param mask The mask of interrupt source to be set. User need to use
<> 144:ef7eb2e8f9f7 633 * the defined edma_interrupt_enable_t type.
<> 144:ef7eb2e8f9f7 634 */
<> 144:ef7eb2e8f9f7 635 void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask);
<> 144:ef7eb2e8f9f7 636
<> 144:ef7eb2e8f9f7 637 /*!
<> 144:ef7eb2e8f9f7 638 * @brief Disables the interrupt source for the eDMA TCD.
<> 144:ef7eb2e8f9f7 639 *
<> 144:ef7eb2e8f9f7 640 * @param tcd Point to the TCD structure.
<> 144:ef7eb2e8f9f7 641 * @param mask The mask of interrupt source to be set. User need to use
<> 144:ef7eb2e8f9f7 642 * the defined edma_interrupt_enable_t type.
<> 144:ef7eb2e8f9f7 643 */
<> 144:ef7eb2e8f9f7 644 void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask);
<> 144:ef7eb2e8f9f7 645
<> 144:ef7eb2e8f9f7 646 /*! @} */
<> 144:ef7eb2e8f9f7 647 /*!
<> 144:ef7eb2e8f9f7 648 * @name eDMA Channel Transfer Operation
<> 144:ef7eb2e8f9f7 649 * @{
<> 144:ef7eb2e8f9f7 650 */
<> 144:ef7eb2e8f9f7 651
<> 144:ef7eb2e8f9f7 652 /*!
<> 144:ef7eb2e8f9f7 653 * @brief Enables the eDMA hardware channel request.
<> 144:ef7eb2e8f9f7 654 *
<> 144:ef7eb2e8f9f7 655 * This function enables the hardware channel request.
<> 144:ef7eb2e8f9f7 656 *
<> 144:ef7eb2e8f9f7 657 * @param base eDMA peripheral base address.
<> 144:ef7eb2e8f9f7 658 * @param channel eDMA channel number.
<> 144:ef7eb2e8f9f7 659 */
<> 144:ef7eb2e8f9f7 660 static inline void EDMA_EnableChannelRequest(DMA_Type *base, uint32_t channel)
<> 144:ef7eb2e8f9f7 661 {
<> 144:ef7eb2e8f9f7 662 assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
<> 144:ef7eb2e8f9f7 663
<> 144:ef7eb2e8f9f7 664 base->SERQ = DMA_SERQ_SERQ(channel);
<> 144:ef7eb2e8f9f7 665 }
<> 144:ef7eb2e8f9f7 666
<> 144:ef7eb2e8f9f7 667 /*!
<> 144:ef7eb2e8f9f7 668 * @brief Disables the eDMA hardware channel request.
<> 144:ef7eb2e8f9f7 669 *
<> 144:ef7eb2e8f9f7 670 * This function disables the hardware channel request.
<> 144:ef7eb2e8f9f7 671 *
<> 144:ef7eb2e8f9f7 672 * @param base eDMA peripheral base address.
<> 144:ef7eb2e8f9f7 673 * @param channel eDMA channel number.
<> 144:ef7eb2e8f9f7 674 */
<> 144:ef7eb2e8f9f7 675 static inline void EDMA_DisableChannelRequest(DMA_Type *base, uint32_t channel)
<> 144:ef7eb2e8f9f7 676 {
<> 144:ef7eb2e8f9f7 677 assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
<> 144:ef7eb2e8f9f7 678
<> 144:ef7eb2e8f9f7 679 base->CERQ = DMA_CERQ_CERQ(channel);
<> 144:ef7eb2e8f9f7 680 }
<> 144:ef7eb2e8f9f7 681
<> 144:ef7eb2e8f9f7 682 /*!
<> 144:ef7eb2e8f9f7 683 * @brief Starts the eDMA transfer by software trigger.
<> 144:ef7eb2e8f9f7 684 *
<> 144:ef7eb2e8f9f7 685 * This function starts a minor loop transfer.
<> 144:ef7eb2e8f9f7 686 *
<> 144:ef7eb2e8f9f7 687 * @param base eDMA peripheral base address.
<> 144:ef7eb2e8f9f7 688 * @param channel eDMA channel number.
<> 144:ef7eb2e8f9f7 689 */
<> 144:ef7eb2e8f9f7 690 static inline void EDMA_TriggerChannelStart(DMA_Type *base, uint32_t channel)
<> 144:ef7eb2e8f9f7 691 {
<> 144:ef7eb2e8f9f7 692 assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
<> 144:ef7eb2e8f9f7 693
<> 144:ef7eb2e8f9f7 694 base->SSRT = DMA_SSRT_SSRT(channel);
<> 144:ef7eb2e8f9f7 695 }
<> 144:ef7eb2e8f9f7 696
<> 144:ef7eb2e8f9f7 697 /*! @} */
<> 144:ef7eb2e8f9f7 698 /*!
<> 144:ef7eb2e8f9f7 699 * @name eDMA Channel Status Operation
<> 144:ef7eb2e8f9f7 700 * @{
<> 144:ef7eb2e8f9f7 701 */
<> 144:ef7eb2e8f9f7 702
<> 144:ef7eb2e8f9f7 703 /*!
<> 144:ef7eb2e8f9f7 704 * @brief Gets the Remaining bytes from the eDMA current channel TCD.
<> 144:ef7eb2e8f9f7 705 *
<> 144:ef7eb2e8f9f7 706 * This function checks the TCD (Task Control Descriptor) status for a specified
<> 144:ef7eb2e8f9f7 707 * eDMA channel and returns the the number of bytes that have not finished.
<> 144:ef7eb2e8f9f7 708 *
<> 144:ef7eb2e8f9f7 709 * @param base eDMA peripheral base address.
<> 144:ef7eb2e8f9f7 710 * @param channel eDMA channel number.
<> 144:ef7eb2e8f9f7 711 * @return Bytes have not been transferred yet for the current TCD.
<> 144:ef7eb2e8f9f7 712 * @note This function can only be used to get unfinished bytes of transfer without
<> 144:ef7eb2e8f9f7 713 * the next TCD, or it might be inaccuracy.
<> 144:ef7eb2e8f9f7 714 */
<> 144:ef7eb2e8f9f7 715 uint32_t EDMA_GetRemainingBytes(DMA_Type *base, uint32_t channel);
<> 144:ef7eb2e8f9f7 716
<> 144:ef7eb2e8f9f7 717 /*!
<> 144:ef7eb2e8f9f7 718 * @brief Gets the eDMA channel error status flags.
<> 144:ef7eb2e8f9f7 719 *
<> 144:ef7eb2e8f9f7 720 * @param base eDMA peripheral base address.
<> 144:ef7eb2e8f9f7 721 * @return The mask of error status flags. User need to use the
<> 144:ef7eb2e8f9f7 722 * _edma_error_status_flags type to decode the return variables.
<> 144:ef7eb2e8f9f7 723 */
<> 144:ef7eb2e8f9f7 724 static inline uint32_t EDMA_GetErrorStatusFlags(DMA_Type *base)
<> 144:ef7eb2e8f9f7 725 {
<> 144:ef7eb2e8f9f7 726 return base->ES;
<> 144:ef7eb2e8f9f7 727 }
<> 144:ef7eb2e8f9f7 728
<> 144:ef7eb2e8f9f7 729 /*!
<> 144:ef7eb2e8f9f7 730 * @brief Gets the eDMA channel status flags.
<> 144:ef7eb2e8f9f7 731 *
<> 144:ef7eb2e8f9f7 732 * @param base eDMA peripheral base address.
<> 144:ef7eb2e8f9f7 733 * @param channel eDMA channel number.
<> 144:ef7eb2e8f9f7 734 * @return The mask of channel status flags. User need to use the
<> 144:ef7eb2e8f9f7 735 * _edma_channel_status_flags type to decode the return variables.
<> 144:ef7eb2e8f9f7 736 */
<> 144:ef7eb2e8f9f7 737 uint32_t EDMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel);
<> 144:ef7eb2e8f9f7 738
<> 144:ef7eb2e8f9f7 739 /*!
<> 144:ef7eb2e8f9f7 740 * @brief Clears the eDMA channel status flags.
<> 144:ef7eb2e8f9f7 741 *
<> 144:ef7eb2e8f9f7 742 * @param base eDMA peripheral base address.
<> 144:ef7eb2e8f9f7 743 * @param channel eDMA channel number.
<> 144:ef7eb2e8f9f7 744 * @param mask The mask of channel status to be cleared. User need to use
<> 144:ef7eb2e8f9f7 745 * the defined _edma_channel_status_flags type.
<> 144:ef7eb2e8f9f7 746 */
<> 144:ef7eb2e8f9f7 747 void EDMA_ClearChannelStatusFlags(DMA_Type *base, uint32_t channel, uint32_t mask);
<> 144:ef7eb2e8f9f7 748
<> 144:ef7eb2e8f9f7 749 /*! @} */
<> 144:ef7eb2e8f9f7 750 /*!
<> 144:ef7eb2e8f9f7 751 * @name eDMA Transactional Operation
<> 144:ef7eb2e8f9f7 752 */
<> 144:ef7eb2e8f9f7 753
<> 144:ef7eb2e8f9f7 754 /*!
<> 144:ef7eb2e8f9f7 755 * @brief Creates the eDMA handle.
<> 144:ef7eb2e8f9f7 756 *
<> 144:ef7eb2e8f9f7 757 * This function is called if using transaction API for eDMA. This function
<> 144:ef7eb2e8f9f7 758 * initializes the internal state of eDMA handle.
<> 144:ef7eb2e8f9f7 759 *
<> 144:ef7eb2e8f9f7 760 * @param handle eDMA handle pointer. The eDMA handle stores callback function and
<> 144:ef7eb2e8f9f7 761 * parameters.
<> 144:ef7eb2e8f9f7 762 * @param base eDMA peripheral base address.
<> 144:ef7eb2e8f9f7 763 * @param channel eDMA channel number.
<> 144:ef7eb2e8f9f7 764 */
<> 144:ef7eb2e8f9f7 765 void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel);
<> 144:ef7eb2e8f9f7 766
<> 144:ef7eb2e8f9f7 767 /*!
<> 144:ef7eb2e8f9f7 768 * @brief Installs the TCDs memory pool into eDMA handle.
<> 144:ef7eb2e8f9f7 769 *
<> 144:ef7eb2e8f9f7 770 * This function is called after the EDMA_CreateHandle to use scatter/gather feature.
<> 144:ef7eb2e8f9f7 771 *
<> 144:ef7eb2e8f9f7 772 * @param handle eDMA handle pointer.
<> 144:ef7eb2e8f9f7 773 * @param tcdPool Memory pool to store TCDs. It must be 32 bytes aligned.
<> 144:ef7eb2e8f9f7 774 * @param tcdSize The number of TCD slots.
<> 144:ef7eb2e8f9f7 775 */
<> 144:ef7eb2e8f9f7 776 void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize);
<> 144:ef7eb2e8f9f7 777
<> 144:ef7eb2e8f9f7 778 /*!
<> 144:ef7eb2e8f9f7 779 * @brief Installs a callback function for the eDMA transfer.
<> 144:ef7eb2e8f9f7 780 *
<> 144:ef7eb2e8f9f7 781 * This callback is called in eDMA IRQ handler. Use the callback to do something after
<> 144:ef7eb2e8f9f7 782 * the current major loop transfer completes.
<> 144:ef7eb2e8f9f7 783 *
<> 144:ef7eb2e8f9f7 784 * @param handle eDMA handle pointer.
<> 144:ef7eb2e8f9f7 785 * @param callback eDMA callback function pointer.
<> 144:ef7eb2e8f9f7 786 * @param userData Parameter for callback function.
<> 144:ef7eb2e8f9f7 787 */
<> 144:ef7eb2e8f9f7 788 void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData);
<> 144:ef7eb2e8f9f7 789
<> 144:ef7eb2e8f9f7 790 /*!
<> 144:ef7eb2e8f9f7 791 * @brief Prepares the eDMA transfer structure.
<> 144:ef7eb2e8f9f7 792 *
<> 144:ef7eb2e8f9f7 793 * This function prepares the transfer configuration structure according to the user input.
<> 144:ef7eb2e8f9f7 794 *
<> 144:ef7eb2e8f9f7 795 * @param config The user configuration structure of type edma_transfer_t.
<> 144:ef7eb2e8f9f7 796 * @param srcAddr eDMA transfer source address.
<> 144:ef7eb2e8f9f7 797 * @param srcWidth eDMA transfer source address width(bytes).
<> 144:ef7eb2e8f9f7 798 * @param destAddr eDMA transfer destination address.
<> 144:ef7eb2e8f9f7 799 * @param destWidth eDMA transfer destination address width(bytes).
<> 144:ef7eb2e8f9f7 800 * @param bytesEachRequest eDMA transfer bytes per channel request.
<> 144:ef7eb2e8f9f7 801 * @param transferBytes eDMA transfer bytes to be transferred.
<> 144:ef7eb2e8f9f7 802 * @param type eDMA transfer type.
<> 144:ef7eb2e8f9f7 803 * @note The data address and the data width must be consistent. For example, if the SRC
<> 144:ef7eb2e8f9f7 804 * is 4 bytes, so the source address must be 4 bytes aligned, or it shall result in
<> 144:ef7eb2e8f9f7 805 * source address error(SAE).
<> 144:ef7eb2e8f9f7 806 */
<> 144:ef7eb2e8f9f7 807 void EDMA_PrepareTransfer(edma_transfer_config_t *config,
<> 144:ef7eb2e8f9f7 808 void *srcAddr,
<> 144:ef7eb2e8f9f7 809 uint32_t srcWidth,
<> 144:ef7eb2e8f9f7 810 void *destAddr,
<> 144:ef7eb2e8f9f7 811 uint32_t destWidth,
<> 144:ef7eb2e8f9f7 812 uint32_t bytesEachRequest,
<> 144:ef7eb2e8f9f7 813 uint32_t transferBytes,
<> 144:ef7eb2e8f9f7 814 edma_transfer_type_t type);
<> 144:ef7eb2e8f9f7 815
<> 144:ef7eb2e8f9f7 816 /*!
<> 144:ef7eb2e8f9f7 817 * @brief Submits the eDMA transfer request.
<> 144:ef7eb2e8f9f7 818 *
<> 144:ef7eb2e8f9f7 819 * This function submits the eDMA transfer request according to the transfer configuration structure.
<> 144:ef7eb2e8f9f7 820 * If the user submits the transfer request repeatedly, this function packs an unprocessed request as
<> 144:ef7eb2e8f9f7 821 * a TCD and enables scatter/gather feature to process it in the next time.
<> 144:ef7eb2e8f9f7 822 *
<> 144:ef7eb2e8f9f7 823 * @param handle eDMA handle pointer.
<> 144:ef7eb2e8f9f7 824 * @param config Pointer to eDMA transfer configuration structure.
<> 144:ef7eb2e8f9f7 825 * @retval kStatus_EDMA_Success It means submit transfer request succeed.
<> 144:ef7eb2e8f9f7 826 * @retval kStatus_EDMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed.
<> 144:ef7eb2e8f9f7 827 * @retval kStatus_EDMA_Busy It means the given channel is busy, need to submit request later.
<> 144:ef7eb2e8f9f7 828 */
<> 144:ef7eb2e8f9f7 829 status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config);
<> 144:ef7eb2e8f9f7 830
<> 144:ef7eb2e8f9f7 831 /*!
<> 144:ef7eb2e8f9f7 832 * @brief eDMA start transfer.
<> 144:ef7eb2e8f9f7 833 *
<> 144:ef7eb2e8f9f7 834 * This function enables the channel request. User can call this function after submitting the transfer request
<> 144:ef7eb2e8f9f7 835 * or before submitting the transfer request.
<> 144:ef7eb2e8f9f7 836 *
<> 144:ef7eb2e8f9f7 837 * @param handle eDMA handle pointer.
<> 144:ef7eb2e8f9f7 838 */
<> 144:ef7eb2e8f9f7 839 void EDMA_StartTransfer(edma_handle_t *handle);
<> 144:ef7eb2e8f9f7 840
<> 144:ef7eb2e8f9f7 841 /*!
<> 144:ef7eb2e8f9f7 842 * @brief eDMA stop transfer.
<> 144:ef7eb2e8f9f7 843 *
<> 144:ef7eb2e8f9f7 844 * This function disables the channel request to pause the transfer. User can call EDMA_StartTransfer()
<> 144:ef7eb2e8f9f7 845 * again to resume the transfer.
<> 144:ef7eb2e8f9f7 846 *
<> 144:ef7eb2e8f9f7 847 * @param handle eDMA handle pointer.
<> 144:ef7eb2e8f9f7 848 */
<> 144:ef7eb2e8f9f7 849 void EDMA_StopTransfer(edma_handle_t *handle);
<> 144:ef7eb2e8f9f7 850
<> 144:ef7eb2e8f9f7 851 /*!
<> 144:ef7eb2e8f9f7 852 * @brief eDMA abort transfer.
<> 144:ef7eb2e8f9f7 853 *
<> 144:ef7eb2e8f9f7 854 * This function disables the channel request and clear transfer status bits.
<> 144:ef7eb2e8f9f7 855 * User can submit another transfer after calling this API.
<> 144:ef7eb2e8f9f7 856 *
<> 144:ef7eb2e8f9f7 857 * @param handle DMA handle pointer.
<> 144:ef7eb2e8f9f7 858 */
<> 144:ef7eb2e8f9f7 859 void EDMA_AbortTransfer(edma_handle_t *handle);
<> 144:ef7eb2e8f9f7 860
<> 144:ef7eb2e8f9f7 861 /*!
<> 144:ef7eb2e8f9f7 862 * @brief eDMA IRQ handler for current major loop transfer complete.
<> 144:ef7eb2e8f9f7 863 *
<> 144:ef7eb2e8f9f7 864 * This function clears the channel major interrupt flag and call
<> 144:ef7eb2e8f9f7 865 * the callback function if it is not NULL.
<> 144:ef7eb2e8f9f7 866 *
<> 144:ef7eb2e8f9f7 867 * @param handle eDMA handle pointer.
<> 144:ef7eb2e8f9f7 868 */
<> 144:ef7eb2e8f9f7 869 void EDMA_HandleIRQ(edma_handle_t *handle);
<> 144:ef7eb2e8f9f7 870
<> 144:ef7eb2e8f9f7 871 /* @} */
<> 144:ef7eb2e8f9f7 872
<> 144:ef7eb2e8f9f7 873 #if defined(__cplusplus)
<> 144:ef7eb2e8f9f7 874 }
<> 144:ef7eb2e8f9f7 875 #endif /* __cplusplus */
<> 144:ef7eb2e8f9f7 876
<> 144:ef7eb2e8f9f7 877 /* @} */
<> 144:ef7eb2e8f9f7 878
<> 144:ef7eb2e8f9f7 879 #endif /*_FSL_EDMA_H_*/