added prescaler for 16 bit pwm in LPC1347 target
Fork of mbed-dev by
targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_clock.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)
- Committer:
- <>
- Date:
- Fri Sep 02 15:07:44 2016 +0100
- Revision:
- 144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /* |
<> | 144:ef7eb2e8f9f7 | 2 | * Copyright (c) 2015, Freescale Semiconductor, Inc. |
<> | 144:ef7eb2e8f9f7 | 3 | * All rights reserved. |
<> | 144:ef7eb2e8f9f7 | 4 | * |
<> | 144:ef7eb2e8f9f7 | 5 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 144:ef7eb2e8f9f7 | 6 | * are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 7 | * |
<> | 144:ef7eb2e8f9f7 | 8 | * o Redistributions of source code must retain the above copyright notice, this list |
<> | 144:ef7eb2e8f9f7 | 9 | * of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 10 | * |
<> | 144:ef7eb2e8f9f7 | 11 | * o Redistributions in binary form must reproduce the above copyright notice, this |
<> | 144:ef7eb2e8f9f7 | 12 | * list of conditions and the following disclaimer in the documentation and/or |
<> | 144:ef7eb2e8f9f7 | 13 | * other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 14 | * |
<> | 144:ef7eb2e8f9f7 | 15 | * o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
<> | 144:ef7eb2e8f9f7 | 16 | * contributors may be used to endorse or promote products derived from this |
<> | 144:ef7eb2e8f9f7 | 17 | * software without specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 18 | * |
<> | 144:ef7eb2e8f9f7 | 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
<> | 144:ef7eb2e8f9f7 | 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
<> | 144:ef7eb2e8f9f7 | 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 144:ef7eb2e8f9f7 | 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
<> | 144:ef7eb2e8f9f7 | 23 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
<> | 144:ef7eb2e8f9f7 | 24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
<> | 144:ef7eb2e8f9f7 | 25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
<> | 144:ef7eb2e8f9f7 | 26 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
<> | 144:ef7eb2e8f9f7 | 27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
<> | 144:ef7eb2e8f9f7 | 28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 29 | */ |
<> | 144:ef7eb2e8f9f7 | 30 | |
<> | 144:ef7eb2e8f9f7 | 31 | #ifndef _FSL_CLOCK_H_ |
<> | 144:ef7eb2e8f9f7 | 32 | #define _FSL_CLOCK_H_ |
<> | 144:ef7eb2e8f9f7 | 33 | |
<> | 144:ef7eb2e8f9f7 | 34 | #include "fsl_device_registers.h" |
<> | 144:ef7eb2e8f9f7 | 35 | #include <stdint.h> |
<> | 144:ef7eb2e8f9f7 | 36 | #include <stdbool.h> |
<> | 144:ef7eb2e8f9f7 | 37 | #include <assert.h> |
<> | 144:ef7eb2e8f9f7 | 38 | |
<> | 144:ef7eb2e8f9f7 | 39 | /*! @addtogroup clock */ |
<> | 144:ef7eb2e8f9f7 | 40 | /*! @{ */ |
<> | 144:ef7eb2e8f9f7 | 41 | |
<> | 144:ef7eb2e8f9f7 | 42 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 43 | * Definitions |
<> | 144:ef7eb2e8f9f7 | 44 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 45 | |
<> | 144:ef7eb2e8f9f7 | 46 | /*! @brief Clock driver version. */ |
<> | 144:ef7eb2e8f9f7 | 47 | #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0. */ |
<> | 144:ef7eb2e8f9f7 | 48 | |
<> | 144:ef7eb2e8f9f7 | 49 | /*! @brief External XTAL0 (OSC0) clock frequency. |
<> | 144:ef7eb2e8f9f7 | 50 | * |
<> | 144:ef7eb2e8f9f7 | 51 | * The XTAL0/EXTAL0 (OSC0) clock frequency in Hz, when the clock is setup, use the |
<> | 144:ef7eb2e8f9f7 | 52 | * function CLOCK_SetXtal0Freq to set the value in to clock driver. For example, |
<> | 144:ef7eb2e8f9f7 | 53 | * if XTAL0 is 8MHz, |
<> | 144:ef7eb2e8f9f7 | 54 | * @code |
<> | 144:ef7eb2e8f9f7 | 55 | * CLOCK_InitOsc0(...); // Setup the OSC0 |
<> | 144:ef7eb2e8f9f7 | 56 | * CLOCK_SetXtal0Freq(80000000); // Set the XTAL0 value to clock driver. |
<> | 144:ef7eb2e8f9f7 | 57 | * @endcode |
<> | 144:ef7eb2e8f9f7 | 58 | * |
<> | 144:ef7eb2e8f9f7 | 59 | * This is important for the multicore platforms, only one core needs to setup |
<> | 144:ef7eb2e8f9f7 | 60 | * OSC0 using CLOCK_InitOsc0, all other cores need to call CLOCK_SetXtal0Freq |
<> | 144:ef7eb2e8f9f7 | 61 | * to get valid clock frequency. |
<> | 144:ef7eb2e8f9f7 | 62 | */ |
<> | 144:ef7eb2e8f9f7 | 63 | extern uint32_t g_xtal0Freq; |
<> | 144:ef7eb2e8f9f7 | 64 | |
<> | 144:ef7eb2e8f9f7 | 65 | /*! @brief External XTAL32/EXTAL32/RTC_CLKIN clock frequency. |
<> | 144:ef7eb2e8f9f7 | 66 | * |
<> | 144:ef7eb2e8f9f7 | 67 | * The XTAL32/EXTAL32/RTC_CLKIN clock frequency in Hz, when the clock is setup, use the |
<> | 144:ef7eb2e8f9f7 | 68 | * function CLOCK_SetXtal32Freq to set the value in to clock driver. |
<> | 144:ef7eb2e8f9f7 | 69 | * |
<> | 144:ef7eb2e8f9f7 | 70 | * This is important for the multicore platforms, only one core needs to setup |
<> | 144:ef7eb2e8f9f7 | 71 | * the clock, all other cores need to call CLOCK_SetXtal32Freq |
<> | 144:ef7eb2e8f9f7 | 72 | * to get valid clock frequency. |
<> | 144:ef7eb2e8f9f7 | 73 | */ |
<> | 144:ef7eb2e8f9f7 | 74 | extern uint32_t g_xtal32Freq; |
<> | 144:ef7eb2e8f9f7 | 75 | |
<> | 144:ef7eb2e8f9f7 | 76 | /*! @brief IRC48M clock frequency in Hz. */ |
<> | 144:ef7eb2e8f9f7 | 77 | #define MCG_INTERNAL_IRC_48M 48000000U |
<> | 144:ef7eb2e8f9f7 | 78 | |
<> | 144:ef7eb2e8f9f7 | 79 | #if (defined(OSC) && !(defined(OSC0))) |
<> | 144:ef7eb2e8f9f7 | 80 | #define OSC0 OSC |
<> | 144:ef7eb2e8f9f7 | 81 | #endif |
<> | 144:ef7eb2e8f9f7 | 82 | |
<> | 144:ef7eb2e8f9f7 | 83 | /*! @brief Clock ip name array for DMAMUX. */ |
<> | 144:ef7eb2e8f9f7 | 84 | #define DMAMUX_CLOCKS \ |
<> | 144:ef7eb2e8f9f7 | 85 | { \ |
<> | 144:ef7eb2e8f9f7 | 86 | kCLOCK_Dmamux0 \ |
<> | 144:ef7eb2e8f9f7 | 87 | } |
<> | 144:ef7eb2e8f9f7 | 88 | |
<> | 144:ef7eb2e8f9f7 | 89 | /*! @brief Clock ip name array for RTC. */ |
<> | 144:ef7eb2e8f9f7 | 90 | #define RTC_CLOCKS \ |
<> | 144:ef7eb2e8f9f7 | 91 | { \ |
<> | 144:ef7eb2e8f9f7 | 92 | kCLOCK_Rtc0 \ |
<> | 144:ef7eb2e8f9f7 | 93 | } |
<> | 144:ef7eb2e8f9f7 | 94 | |
<> | 144:ef7eb2e8f9f7 | 95 | /*! @brief Clock ip name array for ENET. */ |
<> | 144:ef7eb2e8f9f7 | 96 | #define ENET_CLOCKS \ |
<> | 144:ef7eb2e8f9f7 | 97 | { \ |
<> | 144:ef7eb2e8f9f7 | 98 | kCLOCK_Enet0 \ |
<> | 144:ef7eb2e8f9f7 | 99 | } |
<> | 144:ef7eb2e8f9f7 | 100 | |
<> | 144:ef7eb2e8f9f7 | 101 | /*! @brief Clock ip name array for PORT. */ |
<> | 144:ef7eb2e8f9f7 | 102 | #define PORT_CLOCKS \ |
<> | 144:ef7eb2e8f9f7 | 103 | { \ |
<> | 144:ef7eb2e8f9f7 | 104 | kCLOCK_PortA, kCLOCK_PortB, kCLOCK_PortC, kCLOCK_PortD, kCLOCK_PortE \ |
<> | 144:ef7eb2e8f9f7 | 105 | } |
<> | 144:ef7eb2e8f9f7 | 106 | |
<> | 144:ef7eb2e8f9f7 | 107 | /*! @brief Clock ip name array for SAI. */ |
<> | 144:ef7eb2e8f9f7 | 108 | #define SAI_CLOCKS \ |
<> | 144:ef7eb2e8f9f7 | 109 | { \ |
<> | 144:ef7eb2e8f9f7 | 110 | kCLOCK_Sai0 \ |
<> | 144:ef7eb2e8f9f7 | 111 | } |
<> | 144:ef7eb2e8f9f7 | 112 | |
<> | 144:ef7eb2e8f9f7 | 113 | /*! @brief Clock ip name array for FLEXBUS. */ |
<> | 144:ef7eb2e8f9f7 | 114 | #define FLEXBUS_CLOCKS \ |
<> | 144:ef7eb2e8f9f7 | 115 | { \ |
<> | 144:ef7eb2e8f9f7 | 116 | kCLOCK_Flexbus0 \ |
<> | 144:ef7eb2e8f9f7 | 117 | } |
<> | 144:ef7eb2e8f9f7 | 118 | |
<> | 144:ef7eb2e8f9f7 | 119 | /*! @brief Clock ip name array for TSI. */ |
<> | 144:ef7eb2e8f9f7 | 120 | #define TSI_CLOCKS \ |
<> | 144:ef7eb2e8f9f7 | 121 | { \ |
<> | 144:ef7eb2e8f9f7 | 122 | kCLOCK_Tsi0 \ |
<> | 144:ef7eb2e8f9f7 | 123 | } |
<> | 144:ef7eb2e8f9f7 | 124 | |
<> | 144:ef7eb2e8f9f7 | 125 | /*! @brief Clock ip name array for LPUART. */ |
<> | 144:ef7eb2e8f9f7 | 126 | #define LPUART_CLOCKS \ |
<> | 144:ef7eb2e8f9f7 | 127 | { \ |
<> | 144:ef7eb2e8f9f7 | 128 | kCLOCK_Lpuart0 \ |
<> | 144:ef7eb2e8f9f7 | 129 | } |
<> | 144:ef7eb2e8f9f7 | 130 | |
<> | 144:ef7eb2e8f9f7 | 131 | /*! @brief Clock ip name array for EWM. */ |
<> | 144:ef7eb2e8f9f7 | 132 | #define EWM_CLOCKS \ |
<> | 144:ef7eb2e8f9f7 | 133 | { \ |
<> | 144:ef7eb2e8f9f7 | 134 | kCLOCK_Ewm0 \ |
<> | 144:ef7eb2e8f9f7 | 135 | } |
<> | 144:ef7eb2e8f9f7 | 136 | |
<> | 144:ef7eb2e8f9f7 | 137 | /*! @brief Clock ip name array for PIT. */ |
<> | 144:ef7eb2e8f9f7 | 138 | #define PIT_CLOCKS \ |
<> | 144:ef7eb2e8f9f7 | 139 | { \ |
<> | 144:ef7eb2e8f9f7 | 140 | kCLOCK_Pit0 \ |
<> | 144:ef7eb2e8f9f7 | 141 | } |
<> | 144:ef7eb2e8f9f7 | 142 | |
<> | 144:ef7eb2e8f9f7 | 143 | /*! @brief Clock ip name array for DSPI. */ |
<> | 144:ef7eb2e8f9f7 | 144 | #define DSPI_CLOCKS \ |
<> | 144:ef7eb2e8f9f7 | 145 | { \ |
<> | 144:ef7eb2e8f9f7 | 146 | kCLOCK_Spi0, kCLOCK_Spi1, kCLOCK_Spi2 \ |
<> | 144:ef7eb2e8f9f7 | 147 | } |
<> | 144:ef7eb2e8f9f7 | 148 | |
<> | 144:ef7eb2e8f9f7 | 149 | /*! @brief Clock ip name array for LPTMR. */ |
<> | 144:ef7eb2e8f9f7 | 150 | #define LPTMR_CLOCKS \ |
<> | 144:ef7eb2e8f9f7 | 151 | { \ |
<> | 144:ef7eb2e8f9f7 | 152 | kCLOCK_Lptmr0 \ |
<> | 144:ef7eb2e8f9f7 | 153 | } |
<> | 144:ef7eb2e8f9f7 | 154 | |
<> | 144:ef7eb2e8f9f7 | 155 | /*! @brief Clock ip name array for SDHC. */ |
<> | 144:ef7eb2e8f9f7 | 156 | #define SDHC_CLOCKS \ |
<> | 144:ef7eb2e8f9f7 | 157 | { \ |
<> | 144:ef7eb2e8f9f7 | 158 | kCLOCK_Sdhc0 \ |
<> | 144:ef7eb2e8f9f7 | 159 | } |
<> | 144:ef7eb2e8f9f7 | 160 | |
<> | 144:ef7eb2e8f9f7 | 161 | /*! @brief Clock ip name array for FTM. */ |
<> | 144:ef7eb2e8f9f7 | 162 | #define FTM_CLOCKS \ |
<> | 144:ef7eb2e8f9f7 | 163 | { \ |
<> | 144:ef7eb2e8f9f7 | 164 | kCLOCK_Ftm0, kCLOCK_Ftm1, kCLOCK_Ftm2, kCLOCK_Ftm3 \ |
<> | 144:ef7eb2e8f9f7 | 165 | } |
<> | 144:ef7eb2e8f9f7 | 166 | |
<> | 144:ef7eb2e8f9f7 | 167 | /*! @brief Clock ip name array for EDMA. */ |
<> | 144:ef7eb2e8f9f7 | 168 | #define EDMA_CLOCKS \ |
<> | 144:ef7eb2e8f9f7 | 169 | { \ |
<> | 144:ef7eb2e8f9f7 | 170 | kCLOCK_Dma0 \ |
<> | 144:ef7eb2e8f9f7 | 171 | } |
<> | 144:ef7eb2e8f9f7 | 172 | |
<> | 144:ef7eb2e8f9f7 | 173 | /*! @brief Clock ip name array for FLEXCAN. */ |
<> | 144:ef7eb2e8f9f7 | 174 | #define FLEXCAN_CLOCKS \ |
<> | 144:ef7eb2e8f9f7 | 175 | { \ |
<> | 144:ef7eb2e8f9f7 | 176 | kCLOCK_Flexcan0, kCLOCK_Flexcan1 \ |
<> | 144:ef7eb2e8f9f7 | 177 | } |
<> | 144:ef7eb2e8f9f7 | 178 | |
<> | 144:ef7eb2e8f9f7 | 179 | /*! @brief Clock ip name array for DAC. */ |
<> | 144:ef7eb2e8f9f7 | 180 | #define DAC_CLOCKS \ |
<> | 144:ef7eb2e8f9f7 | 181 | { \ |
<> | 144:ef7eb2e8f9f7 | 182 | kCLOCK_Dac0, kCLOCK_Dac1 \ |
<> | 144:ef7eb2e8f9f7 | 183 | } |
<> | 144:ef7eb2e8f9f7 | 184 | |
<> | 144:ef7eb2e8f9f7 | 185 | /*! @brief Clock ip name array for ADC16. */ |
<> | 144:ef7eb2e8f9f7 | 186 | #define ADC16_CLOCKS \ |
<> | 144:ef7eb2e8f9f7 | 187 | { \ |
<> | 144:ef7eb2e8f9f7 | 188 | kCLOCK_Adc0, kCLOCK_Adc1 \ |
<> | 144:ef7eb2e8f9f7 | 189 | } |
<> | 144:ef7eb2e8f9f7 | 190 | |
<> | 144:ef7eb2e8f9f7 | 191 | /*! @brief Clock ip name array for SDRAM. */ |
<> | 144:ef7eb2e8f9f7 | 192 | #define SDRAM_CLOCKS \ |
<> | 144:ef7eb2e8f9f7 | 193 | { \ |
<> | 144:ef7eb2e8f9f7 | 194 | kCLOCK_Sdramc0 \ |
<> | 144:ef7eb2e8f9f7 | 195 | } |
<> | 144:ef7eb2e8f9f7 | 196 | |
<> | 144:ef7eb2e8f9f7 | 197 | /*! @brief Clock ip name array for MMCAU. */ |
<> | 144:ef7eb2e8f9f7 | 198 | #define MMCAU_CLOCKS \ |
<> | 144:ef7eb2e8f9f7 | 199 | { \ |
<> | 144:ef7eb2e8f9f7 | 200 | kCLOCK_Mmcau0 \ |
<> | 144:ef7eb2e8f9f7 | 201 | } |
<> | 144:ef7eb2e8f9f7 | 202 | |
<> | 144:ef7eb2e8f9f7 | 203 | /*! @brief Clock ip name array for MPU. */ |
<> | 144:ef7eb2e8f9f7 | 204 | #define MPU_CLOCKS \ |
<> | 144:ef7eb2e8f9f7 | 205 | { \ |
<> | 144:ef7eb2e8f9f7 | 206 | kCLOCK_Mpu0 \ |
<> | 144:ef7eb2e8f9f7 | 207 | } |
<> | 144:ef7eb2e8f9f7 | 208 | |
<> | 144:ef7eb2e8f9f7 | 209 | /*! @brief Clock ip name array for VREF. */ |
<> | 144:ef7eb2e8f9f7 | 210 | #define VREF_CLOCKS \ |
<> | 144:ef7eb2e8f9f7 | 211 | { \ |
<> | 144:ef7eb2e8f9f7 | 212 | kCLOCK_Vref0 \ |
<> | 144:ef7eb2e8f9f7 | 213 | } |
<> | 144:ef7eb2e8f9f7 | 214 | |
<> | 144:ef7eb2e8f9f7 | 215 | /*! @brief Clock ip name array for CMT. */ |
<> | 144:ef7eb2e8f9f7 | 216 | #define CMT_CLOCKS \ |
<> | 144:ef7eb2e8f9f7 | 217 | { \ |
<> | 144:ef7eb2e8f9f7 | 218 | kCLOCK_Cmt0 \ |
<> | 144:ef7eb2e8f9f7 | 219 | } |
<> | 144:ef7eb2e8f9f7 | 220 | |
<> | 144:ef7eb2e8f9f7 | 221 | /*! @brief Clock ip name array for UART. */ |
<> | 144:ef7eb2e8f9f7 | 222 | #define UART_CLOCKS \ |
<> | 144:ef7eb2e8f9f7 | 223 | { \ |
<> | 144:ef7eb2e8f9f7 | 224 | kCLOCK_Uart0, kCLOCK_Uart1, kCLOCK_Uart2, kCLOCK_Uart3, kCLOCK_Uart4 \ |
<> | 144:ef7eb2e8f9f7 | 225 | } |
<> | 144:ef7eb2e8f9f7 | 226 | |
<> | 144:ef7eb2e8f9f7 | 227 | /*! @brief Clock ip name array for TPM. */ |
<> | 144:ef7eb2e8f9f7 | 228 | #define TPM_CLOCKS \ |
<> | 144:ef7eb2e8f9f7 | 229 | { \ |
<> | 144:ef7eb2e8f9f7 | 230 | kCLOCK_IpInvalid, kCLOCK_Tpm1, kCLOCK_Tpm2 \ |
<> | 144:ef7eb2e8f9f7 | 231 | } |
<> | 144:ef7eb2e8f9f7 | 232 | |
<> | 144:ef7eb2e8f9f7 | 233 | /*! @brief Clock ip name array for RNGA. */ |
<> | 144:ef7eb2e8f9f7 | 234 | #define RNGA_CLOCKS \ |
<> | 144:ef7eb2e8f9f7 | 235 | { \ |
<> | 144:ef7eb2e8f9f7 | 236 | kCLOCK_Rnga0 \ |
<> | 144:ef7eb2e8f9f7 | 237 | } |
<> | 144:ef7eb2e8f9f7 | 238 | |
<> | 144:ef7eb2e8f9f7 | 239 | /*! @brief Clock ip name array for CRC. */ |
<> | 144:ef7eb2e8f9f7 | 240 | #define CRC_CLOCKS \ |
<> | 144:ef7eb2e8f9f7 | 241 | { \ |
<> | 144:ef7eb2e8f9f7 | 242 | kCLOCK_Crc0 \ |
<> | 144:ef7eb2e8f9f7 | 243 | } |
<> | 144:ef7eb2e8f9f7 | 244 | |
<> | 144:ef7eb2e8f9f7 | 245 | /*! @brief Clock ip name array for LMEM. */ |
<> | 144:ef7eb2e8f9f7 | 246 | #define LMEM_CLOCKS \ |
<> | 144:ef7eb2e8f9f7 | 247 | { \ |
<> | 144:ef7eb2e8f9f7 | 248 | kCLOCK_Lmem0 \ |
<> | 144:ef7eb2e8f9f7 | 249 | } |
<> | 144:ef7eb2e8f9f7 | 250 | |
<> | 144:ef7eb2e8f9f7 | 251 | /*! @brief Clock ip name array for I2C. */ |
<> | 144:ef7eb2e8f9f7 | 252 | #define I2C_CLOCKS \ |
<> | 144:ef7eb2e8f9f7 | 253 | { \ |
<> | 144:ef7eb2e8f9f7 | 254 | kCLOCK_I2c0, kCLOCK_I2c1, kCLOCK_I2c2, kCLOCK_I2c3 \ |
<> | 144:ef7eb2e8f9f7 | 255 | } |
<> | 144:ef7eb2e8f9f7 | 256 | |
<> | 144:ef7eb2e8f9f7 | 257 | /*! @brief Clock ip name array for PDB. */ |
<> | 144:ef7eb2e8f9f7 | 258 | #define PDB_CLOCKS \ |
<> | 144:ef7eb2e8f9f7 | 259 | { \ |
<> | 144:ef7eb2e8f9f7 | 260 | kCLOCK_Pdb0 \ |
<> | 144:ef7eb2e8f9f7 | 261 | } |
<> | 144:ef7eb2e8f9f7 | 262 | |
<> | 144:ef7eb2e8f9f7 | 263 | /*! @brief Clock ip name array for FTF. */ |
<> | 144:ef7eb2e8f9f7 | 264 | #define FTF_CLOCKS \ |
<> | 144:ef7eb2e8f9f7 | 265 | { \ |
<> | 144:ef7eb2e8f9f7 | 266 | kCLOCK_Ftf0 \ |
<> | 144:ef7eb2e8f9f7 | 267 | } |
<> | 144:ef7eb2e8f9f7 | 268 | |
<> | 144:ef7eb2e8f9f7 | 269 | /*! @brief Clock ip name array for CMP. */ |
<> | 144:ef7eb2e8f9f7 | 270 | #define CMP_CLOCKS \ |
<> | 144:ef7eb2e8f9f7 | 271 | { \ |
<> | 144:ef7eb2e8f9f7 | 272 | kCLOCK_Cmp0, kCLOCK_Cmp1, kCLOCK_Cmp2 \ |
<> | 144:ef7eb2e8f9f7 | 273 | } |
<> | 144:ef7eb2e8f9f7 | 274 | |
<> | 144:ef7eb2e8f9f7 | 275 | /*! |
<> | 144:ef7eb2e8f9f7 | 276 | * @brief LPO clock frequency. |
<> | 144:ef7eb2e8f9f7 | 277 | */ |
<> | 144:ef7eb2e8f9f7 | 278 | #define LPO_CLK_FREQ 1000U |
<> | 144:ef7eb2e8f9f7 | 279 | |
<> | 144:ef7eb2e8f9f7 | 280 | /*! @brief Peripherals clock source definition. */ |
<> | 144:ef7eb2e8f9f7 | 281 | #define SYS_CLK kCLOCK_CoreSysClk |
<> | 144:ef7eb2e8f9f7 | 282 | #define BUS_CLK kCLOCK_BusClk |
<> | 144:ef7eb2e8f9f7 | 283 | |
<> | 144:ef7eb2e8f9f7 | 284 | #define I2C0_CLK_SRC BUS_CLK |
<> | 144:ef7eb2e8f9f7 | 285 | #define I2C1_CLK_SRC BUS_CLK |
<> | 144:ef7eb2e8f9f7 | 286 | #define I2C2_CLK_SRC BUS_CLK |
<> | 144:ef7eb2e8f9f7 | 287 | #define I2C3_CLK_SRC BUS_CLK |
<> | 144:ef7eb2e8f9f7 | 288 | #define DSPI0_CLK_SRC BUS_CLK |
<> | 144:ef7eb2e8f9f7 | 289 | #define DSPI1_CLK_SRC BUS_CLK |
<> | 144:ef7eb2e8f9f7 | 290 | #define DSPI2_CLK_SRC BUS_CLK |
<> | 144:ef7eb2e8f9f7 | 291 | #define UART0_CLK_SRC SYS_CLK |
<> | 144:ef7eb2e8f9f7 | 292 | #define UART1_CLK_SRC SYS_CLK |
<> | 144:ef7eb2e8f9f7 | 293 | #define UART2_CLK_SRC BUS_CLK |
<> | 144:ef7eb2e8f9f7 | 294 | #define UART3_CLK_SRC BUS_CLK |
<> | 144:ef7eb2e8f9f7 | 295 | #define UART4_CLK_SRC BUS_CLK |
<> | 144:ef7eb2e8f9f7 | 296 | |
<> | 144:ef7eb2e8f9f7 | 297 | /*! @brief Clock name used to get clock frequency. */ |
<> | 144:ef7eb2e8f9f7 | 298 | typedef enum _clock_name |
<> | 144:ef7eb2e8f9f7 | 299 | { |
<> | 144:ef7eb2e8f9f7 | 300 | |
<> | 144:ef7eb2e8f9f7 | 301 | /* ----------------------------- System layer clock -------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 302 | kCLOCK_CoreSysClk, /*!< Core/system clock */ |
<> | 144:ef7eb2e8f9f7 | 303 | kCLOCK_PlatClk, /*!< Platform clock */ |
<> | 144:ef7eb2e8f9f7 | 304 | kCLOCK_BusClk, /*!< Bus clock */ |
<> | 144:ef7eb2e8f9f7 | 305 | kCLOCK_FlexBusClk, /*!< FlexBus clock */ |
<> | 144:ef7eb2e8f9f7 | 306 | kCLOCK_FlashClk, /*!< Flash clock */ |
<> | 144:ef7eb2e8f9f7 | 307 | kCLOCK_FastPeriphClk, /*!< Fast peripheral clock */ |
<> | 144:ef7eb2e8f9f7 | 308 | kCLOCK_PllFllSelClk, /*!< The clock after SIM[PLLFLLSEL]. */ |
<> | 144:ef7eb2e8f9f7 | 309 | |
<> | 144:ef7eb2e8f9f7 | 310 | /* ---------------------------------- OSC clock -----------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 311 | kCLOCK_Er32kClk, /*!< External reference 32K clock (ERCLK32K) */ |
<> | 144:ef7eb2e8f9f7 | 312 | kCLOCK_Osc0ErClk, /*!< OSC0 external reference clock (OSC0ERCLK) */ |
<> | 144:ef7eb2e8f9f7 | 313 | kCLOCK_Osc1ErClk, /*!< OSC1 external reference clock (OSC1ERCLK) */ |
<> | 144:ef7eb2e8f9f7 | 314 | kCLOCK_Osc0ErClkUndiv, /*!< OSC0 external reference undivided clock(OSC0ERCLK_UNDIV). */ |
<> | 144:ef7eb2e8f9f7 | 315 | |
<> | 144:ef7eb2e8f9f7 | 316 | /* ----------------------------- MCG and MCG-Lite clock ---------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 317 | kCLOCK_McgFixedFreqClk, /*!< MCG fixed frequency clock (MCGFFCLK) */ |
<> | 144:ef7eb2e8f9f7 | 318 | kCLOCK_McgInternalRefClk, /*!< MCG internal reference clock (MCGIRCLK) */ |
<> | 144:ef7eb2e8f9f7 | 319 | kCLOCK_McgFllClk, /*!< MCGFLLCLK */ |
<> | 144:ef7eb2e8f9f7 | 320 | kCLOCK_McgPll0Clk, /*!< MCGPLL0CLK */ |
<> | 144:ef7eb2e8f9f7 | 321 | kCLOCK_McgPll1Clk, /*!< MCGPLL1CLK */ |
<> | 144:ef7eb2e8f9f7 | 322 | kCLOCK_McgExtPllClk, /*!< EXT_PLLCLK */ |
<> | 144:ef7eb2e8f9f7 | 323 | kCLOCK_McgPeriphClk, /*!< MCG peripheral clock (MCGPCLK) */ |
<> | 144:ef7eb2e8f9f7 | 324 | kCLOCK_McgIrc48MClk, /*!< MCG IRC48M clock */ |
<> | 144:ef7eb2e8f9f7 | 325 | |
<> | 144:ef7eb2e8f9f7 | 326 | /* --------------------------------- Other clock ----------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 327 | kCLOCK_LpoClk, /*!< LPO clock */ |
<> | 144:ef7eb2e8f9f7 | 328 | |
<> | 144:ef7eb2e8f9f7 | 329 | } clock_name_t; |
<> | 144:ef7eb2e8f9f7 | 330 | |
<> | 144:ef7eb2e8f9f7 | 331 | /*! @brief USB clock source definition. */ |
<> | 144:ef7eb2e8f9f7 | 332 | typedef enum _clock_usb_src |
<> | 144:ef7eb2e8f9f7 | 333 | { |
<> | 144:ef7eb2e8f9f7 | 334 | kCLOCK_UsbSrcPll0 = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(1U), /*!< Use PLL0. */ |
<> | 144:ef7eb2e8f9f7 | 335 | kCLOCK_UsbSrcUsbPfd = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(2U), /*!< Use USBPFDCLK. */ |
<> | 144:ef7eb2e8f9f7 | 336 | kCLOCK_UsbSrcIrc48M = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(3U), /*!< Use IRC48M. */ |
<> | 144:ef7eb2e8f9f7 | 337 | kCLOCK_UsbSrcExt = SIM_SOPT2_USBSRC(0U) /*!< Use USB_CLKIN. */ |
<> | 144:ef7eb2e8f9f7 | 338 | } clock_usb_src_t; |
<> | 144:ef7eb2e8f9f7 | 339 | |
<> | 144:ef7eb2e8f9f7 | 340 | /*------------------------------------------------------------------------------ |
<> | 144:ef7eb2e8f9f7 | 341 | |
<> | 144:ef7eb2e8f9f7 | 342 | clock_gate_t definition: |
<> | 144:ef7eb2e8f9f7 | 343 | |
<> | 144:ef7eb2e8f9f7 | 344 | 31 16 0 |
<> | 144:ef7eb2e8f9f7 | 345 | ----------------------------------------------------------------- |
<> | 144:ef7eb2e8f9f7 | 346 | | SIM_SCGC register offset | control bit offset in SCGC | |
<> | 144:ef7eb2e8f9f7 | 347 | ----------------------------------------------------------------- |
<> | 144:ef7eb2e8f9f7 | 348 | |
<> | 144:ef7eb2e8f9f7 | 349 | For example, the SDHC clock gate is controlled by SIM_SCGC3[17], the |
<> | 144:ef7eb2e8f9f7 | 350 | SIM_SCGC3 offset in SIM is 0x1030, then kClockGateSdhc0 is defined as |
<> | 144:ef7eb2e8f9f7 | 351 | |
<> | 144:ef7eb2e8f9f7 | 352 | kClockGateSdhc0 = (0x1030 << 16) | 17; |
<> | 144:ef7eb2e8f9f7 | 353 | |
<> | 144:ef7eb2e8f9f7 | 354 | ------------------------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 355 | |
<> | 144:ef7eb2e8f9f7 | 356 | #define CLK_GATE_REG_OFFSET_SHIFT 16U |
<> | 144:ef7eb2e8f9f7 | 357 | #define CLK_GATE_REG_OFFSET_MASK 0xFFFF0000U |
<> | 144:ef7eb2e8f9f7 | 358 | #define CLK_GATE_BIT_SHIFT_SHIFT 0U |
<> | 144:ef7eb2e8f9f7 | 359 | #define CLK_GATE_BIT_SHIFT_MASK 0x0000FFFFU |
<> | 144:ef7eb2e8f9f7 | 360 | |
<> | 144:ef7eb2e8f9f7 | 361 | #define CLK_GATE_DEFINE(reg_offset, bit_shift) \ |
<> | 144:ef7eb2e8f9f7 | 362 | ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \ |
<> | 144:ef7eb2e8f9f7 | 363 | (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK)) |
<> | 144:ef7eb2e8f9f7 | 364 | |
<> | 144:ef7eb2e8f9f7 | 365 | #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 366 | #define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 367 | |
<> | 144:ef7eb2e8f9f7 | 368 | /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ |
<> | 144:ef7eb2e8f9f7 | 369 | typedef enum _clock_ip_name |
<> | 144:ef7eb2e8f9f7 | 370 | { |
<> | 144:ef7eb2e8f9f7 | 371 | kCLOCK_IpInvalid = 0U, |
<> | 144:ef7eb2e8f9f7 | 372 | kCLOCK_I2c2 = CLK_GATE_DEFINE(0x1028U, 6U), |
<> | 144:ef7eb2e8f9f7 | 373 | kCLOCK_I2c3 = CLK_GATE_DEFINE(0x1028U, 7U), |
<> | 144:ef7eb2e8f9f7 | 374 | kCLOCK_Uart4 = CLK_GATE_DEFINE(0x1028U, 10U), |
<> | 144:ef7eb2e8f9f7 | 375 | |
<> | 144:ef7eb2e8f9f7 | 376 | kCLOCK_Enet0 = CLK_GATE_DEFINE(0x102CU, 0U), |
<> | 144:ef7eb2e8f9f7 | 377 | kCLOCK_Lpuart0 = CLK_GATE_DEFINE(0x102CU, 4U), |
<> | 144:ef7eb2e8f9f7 | 378 | kCLOCK_Tpm1 = CLK_GATE_DEFINE(0x102CU, 9U), |
<> | 144:ef7eb2e8f9f7 | 379 | kCLOCK_Tpm2 = CLK_GATE_DEFINE(0x102CU, 10U), |
<> | 144:ef7eb2e8f9f7 | 380 | kCLOCK_Dac0 = CLK_GATE_DEFINE(0x102CU, 12U), |
<> | 144:ef7eb2e8f9f7 | 381 | kCLOCK_Dac1 = CLK_GATE_DEFINE(0x102CU, 13U), |
<> | 144:ef7eb2e8f9f7 | 382 | |
<> | 144:ef7eb2e8f9f7 | 383 | kCLOCK_Rnga0 = CLK_GATE_DEFINE(0x1030U, 0U), |
<> | 144:ef7eb2e8f9f7 | 384 | kCLOCK_Usbhs0 = CLK_GATE_DEFINE(0x1030U, 1U), |
<> | 144:ef7eb2e8f9f7 | 385 | kCLOCK_UsbhsPhy0 = CLK_GATE_DEFINE(0x1030U, 2U), |
<> | 144:ef7eb2e8f9f7 | 386 | kCLOCK_UsbhsDcd0 = CLK_GATE_DEFINE(0x1030U, 3U), |
<> | 144:ef7eb2e8f9f7 | 387 | kCLOCK_Flexcan1 = CLK_GATE_DEFINE(0x1030U, 4U), |
<> | 144:ef7eb2e8f9f7 | 388 | kCLOCK_Spi2 = CLK_GATE_DEFINE(0x1030U, 12U), |
<> | 144:ef7eb2e8f9f7 | 389 | kCLOCK_Sdhc0 = CLK_GATE_DEFINE(0x1030U, 17U), |
<> | 144:ef7eb2e8f9f7 | 390 | kCLOCK_Ftm3 = CLK_GATE_DEFINE(0x1030U, 25U), |
<> | 144:ef7eb2e8f9f7 | 391 | kCLOCK_Adc1 = CLK_GATE_DEFINE(0x1030U, 27U), |
<> | 144:ef7eb2e8f9f7 | 392 | |
<> | 144:ef7eb2e8f9f7 | 393 | kCLOCK_Ewm0 = CLK_GATE_DEFINE(0x1034U, 1U), |
<> | 144:ef7eb2e8f9f7 | 394 | kCLOCK_Cmt0 = CLK_GATE_DEFINE(0x1034U, 2U), |
<> | 144:ef7eb2e8f9f7 | 395 | kCLOCK_I2c0 = CLK_GATE_DEFINE(0x1034U, 6U), |
<> | 144:ef7eb2e8f9f7 | 396 | kCLOCK_I2c1 = CLK_GATE_DEFINE(0x1034U, 7U), |
<> | 144:ef7eb2e8f9f7 | 397 | kCLOCK_Uart0 = CLK_GATE_DEFINE(0x1034U, 10U), |
<> | 144:ef7eb2e8f9f7 | 398 | kCLOCK_Uart1 = CLK_GATE_DEFINE(0x1034U, 11U), |
<> | 144:ef7eb2e8f9f7 | 399 | kCLOCK_Uart2 = CLK_GATE_DEFINE(0x1034U, 12U), |
<> | 144:ef7eb2e8f9f7 | 400 | kCLOCK_Uart3 = CLK_GATE_DEFINE(0x1034U, 13U), |
<> | 144:ef7eb2e8f9f7 | 401 | kCLOCK_Usbfs0 = CLK_GATE_DEFINE(0x1034U, 18U), |
<> | 144:ef7eb2e8f9f7 | 402 | kCLOCK_Cmp0 = CLK_GATE_DEFINE(0x1034U, 19U), |
<> | 144:ef7eb2e8f9f7 | 403 | kCLOCK_Cmp1 = CLK_GATE_DEFINE(0x1034U, 19U), |
<> | 144:ef7eb2e8f9f7 | 404 | kCLOCK_Cmp2 = CLK_GATE_DEFINE(0x1034U, 19U), |
<> | 144:ef7eb2e8f9f7 | 405 | kCLOCK_Vref0 = CLK_GATE_DEFINE(0x1034U, 20U), |
<> | 144:ef7eb2e8f9f7 | 406 | |
<> | 144:ef7eb2e8f9f7 | 407 | kCLOCK_Lptmr0 = CLK_GATE_DEFINE(0x1038U, 0U), |
<> | 144:ef7eb2e8f9f7 | 408 | kCLOCK_Tsi0 = CLK_GATE_DEFINE(0x1038U, 5U), |
<> | 144:ef7eb2e8f9f7 | 409 | kCLOCK_PortA = CLK_GATE_DEFINE(0x1038U, 9U), |
<> | 144:ef7eb2e8f9f7 | 410 | kCLOCK_PortB = CLK_GATE_DEFINE(0x1038U, 10U), |
<> | 144:ef7eb2e8f9f7 | 411 | kCLOCK_PortC = CLK_GATE_DEFINE(0x1038U, 11U), |
<> | 144:ef7eb2e8f9f7 | 412 | kCLOCK_PortD = CLK_GATE_DEFINE(0x1038U, 12U), |
<> | 144:ef7eb2e8f9f7 | 413 | kCLOCK_PortE = CLK_GATE_DEFINE(0x1038U, 13U), |
<> | 144:ef7eb2e8f9f7 | 414 | |
<> | 144:ef7eb2e8f9f7 | 415 | kCLOCK_Ftf0 = CLK_GATE_DEFINE(0x103CU, 0U), |
<> | 144:ef7eb2e8f9f7 | 416 | kCLOCK_Dmamux0 = CLK_GATE_DEFINE(0x103CU, 1U), |
<> | 144:ef7eb2e8f9f7 | 417 | kCLOCK_Flexcan0 = CLK_GATE_DEFINE(0x103CU, 4U), |
<> | 144:ef7eb2e8f9f7 | 418 | kCLOCK_Spi0 = CLK_GATE_DEFINE(0x103CU, 12U), |
<> | 144:ef7eb2e8f9f7 | 419 | kCLOCK_Spi1 = CLK_GATE_DEFINE(0x103CU, 13U), |
<> | 144:ef7eb2e8f9f7 | 420 | kCLOCK_Sai0 = CLK_GATE_DEFINE(0x103CU, 15U), |
<> | 144:ef7eb2e8f9f7 | 421 | kCLOCK_Crc0 = CLK_GATE_DEFINE(0x103CU, 18U), |
<> | 144:ef7eb2e8f9f7 | 422 | kCLOCK_Usbdcd0 = CLK_GATE_DEFINE(0x103CU, 21U), |
<> | 144:ef7eb2e8f9f7 | 423 | kCLOCK_Pdb0 = CLK_GATE_DEFINE(0x103CU, 22U), |
<> | 144:ef7eb2e8f9f7 | 424 | kCLOCK_Pit0 = CLK_GATE_DEFINE(0x103CU, 23U), |
<> | 144:ef7eb2e8f9f7 | 425 | kCLOCK_Ftm0 = CLK_GATE_DEFINE(0x103CU, 24U), |
<> | 144:ef7eb2e8f9f7 | 426 | kCLOCK_Ftm1 = CLK_GATE_DEFINE(0x103CU, 25U), |
<> | 144:ef7eb2e8f9f7 | 427 | kCLOCK_Ftm2 = CLK_GATE_DEFINE(0x103CU, 26U), |
<> | 144:ef7eb2e8f9f7 | 428 | kCLOCK_Adc0 = CLK_GATE_DEFINE(0x103CU, 27U), |
<> | 144:ef7eb2e8f9f7 | 429 | kCLOCK_Rtc0 = CLK_GATE_DEFINE(0x103CU, 29U), |
<> | 144:ef7eb2e8f9f7 | 430 | |
<> | 144:ef7eb2e8f9f7 | 431 | kCLOCK_Flexbus0 = CLK_GATE_DEFINE(0x1040U, 0U), |
<> | 144:ef7eb2e8f9f7 | 432 | kCLOCK_Dma0 = CLK_GATE_DEFINE(0x1040U, 1U), |
<> | 144:ef7eb2e8f9f7 | 433 | kCLOCK_Mpu0 = CLK_GATE_DEFINE(0x1040U, 2U), |
<> | 144:ef7eb2e8f9f7 | 434 | kCLOCK_Sdramc0 = CLK_GATE_DEFINE(0x1040U, 3U), |
<> | 144:ef7eb2e8f9f7 | 435 | } clock_ip_name_t; |
<> | 144:ef7eb2e8f9f7 | 436 | |
<> | 144:ef7eb2e8f9f7 | 437 | /*!@brief SIM configuration structure for clock setting. */ |
<> | 144:ef7eb2e8f9f7 | 438 | typedef struct _sim_clock_config |
<> | 144:ef7eb2e8f9f7 | 439 | { |
<> | 144:ef7eb2e8f9f7 | 440 | uint8_t pllFllSel; /*!< PLL/FLL/IRC48M selection. */ |
<> | 144:ef7eb2e8f9f7 | 441 | uint8_t pllFllDiv; /*!< PLLFLLSEL clock divider divisor. */ |
<> | 144:ef7eb2e8f9f7 | 442 | uint8_t pllFllFrac; /*!< PLLFLLSEL clock divider fraction. */ |
<> | 144:ef7eb2e8f9f7 | 443 | uint8_t er32kSrc; /*!< ERCLK32K source selection. */ |
<> | 144:ef7eb2e8f9f7 | 444 | uint32_t clkdiv1; /*!< SIM_CLKDIV1. */ |
<> | 144:ef7eb2e8f9f7 | 445 | } sim_clock_config_t; |
<> | 144:ef7eb2e8f9f7 | 446 | |
<> | 144:ef7eb2e8f9f7 | 447 | /*! @brief OSC work mode. */ |
<> | 144:ef7eb2e8f9f7 | 448 | typedef enum _osc_mode |
<> | 144:ef7eb2e8f9f7 | 449 | { |
<> | 144:ef7eb2e8f9f7 | 450 | kOSC_ModeExt = 0U, /*!< Use external clock. */ |
<> | 144:ef7eb2e8f9f7 | 451 | #if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK))) |
<> | 144:ef7eb2e8f9f7 | 452 | kOSC_ModeOscLowPower = MCG_C2_EREFS_MASK, /*!< Oscillator low power. */ |
<> | 144:ef7eb2e8f9f7 | 453 | #else |
<> | 144:ef7eb2e8f9f7 | 454 | kOSC_ModeOscLowPower = MCG_C2_EREFS0_MASK, /*!< Oscillator low power. */ |
<> | 144:ef7eb2e8f9f7 | 455 | #endif |
<> | 144:ef7eb2e8f9f7 | 456 | kOSC_ModeOscHighGain = 0U |
<> | 144:ef7eb2e8f9f7 | 457 | #if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK))) |
<> | 144:ef7eb2e8f9f7 | 458 | | |
<> | 144:ef7eb2e8f9f7 | 459 | MCG_C2_EREFS_MASK |
<> | 144:ef7eb2e8f9f7 | 460 | #else |
<> | 144:ef7eb2e8f9f7 | 461 | | |
<> | 144:ef7eb2e8f9f7 | 462 | MCG_C2_EREFS0_MASK |
<> | 144:ef7eb2e8f9f7 | 463 | #endif |
<> | 144:ef7eb2e8f9f7 | 464 | #if (defined(MCG_C2_HGO_MASK) && !(defined(MCG_C2_HGO0_MASK))) |
<> | 144:ef7eb2e8f9f7 | 465 | | |
<> | 144:ef7eb2e8f9f7 | 466 | MCG_C2_HGO_MASK, /*!< Oscillator high gain. */ |
<> | 144:ef7eb2e8f9f7 | 467 | #else |
<> | 144:ef7eb2e8f9f7 | 468 | | |
<> | 144:ef7eb2e8f9f7 | 469 | MCG_C2_HGO0_MASK, /*!< Oscillator high gain. */ |
<> | 144:ef7eb2e8f9f7 | 470 | #endif |
<> | 144:ef7eb2e8f9f7 | 471 | } osc_mode_t; |
<> | 144:ef7eb2e8f9f7 | 472 | |
<> | 144:ef7eb2e8f9f7 | 473 | /*! @brief Oscillator capacitor load setting.*/ |
<> | 144:ef7eb2e8f9f7 | 474 | enum _osc_cap_load |
<> | 144:ef7eb2e8f9f7 | 475 | { |
<> | 144:ef7eb2e8f9f7 | 476 | kOSC_Cap2P = OSC_CR_SC2P_MASK, /*!< 2 pF capacitor load */ |
<> | 144:ef7eb2e8f9f7 | 477 | kOSC_Cap4P = OSC_CR_SC4P_MASK, /*!< 4 pF capacitor load */ |
<> | 144:ef7eb2e8f9f7 | 478 | kOSC_Cap8P = OSC_CR_SC8P_MASK, /*!< 8 pF capacitor load */ |
<> | 144:ef7eb2e8f9f7 | 479 | kOSC_Cap16P = OSC_CR_SC16P_MASK /*!< 16 pF capacitor load */ |
<> | 144:ef7eb2e8f9f7 | 480 | }; |
<> | 144:ef7eb2e8f9f7 | 481 | |
<> | 144:ef7eb2e8f9f7 | 482 | /*! @brief OSCERCLK enable mode. */ |
<> | 144:ef7eb2e8f9f7 | 483 | enum _oscer_enable_mode |
<> | 144:ef7eb2e8f9f7 | 484 | { |
<> | 144:ef7eb2e8f9f7 | 485 | kOSC_ErClkEnable = OSC_CR_ERCLKEN_MASK, /*!< Enable. */ |
<> | 144:ef7eb2e8f9f7 | 486 | kOSC_ErClkEnableInStop = OSC_CR_EREFSTEN_MASK /*!< Enable in stop mode. */ |
<> | 144:ef7eb2e8f9f7 | 487 | }; |
<> | 144:ef7eb2e8f9f7 | 488 | |
<> | 144:ef7eb2e8f9f7 | 489 | /*! @brief OSC configuration for OSCERCLK. */ |
<> | 144:ef7eb2e8f9f7 | 490 | typedef struct _oscer_config |
<> | 144:ef7eb2e8f9f7 | 491 | { |
<> | 144:ef7eb2e8f9f7 | 492 | uint8_t enableMode; /*!< OSCERCLK enable mode. OR'ed value of @ref _oscer_enable_mode. */ |
<> | 144:ef7eb2e8f9f7 | 493 | |
<> | 144:ef7eb2e8f9f7 | 494 | uint8_t erclkDiv; /*!< Divider for OSCERCLK.*/ |
<> | 144:ef7eb2e8f9f7 | 495 | } oscer_config_t; |
<> | 144:ef7eb2e8f9f7 | 496 | |
<> | 144:ef7eb2e8f9f7 | 497 | /*! |
<> | 144:ef7eb2e8f9f7 | 498 | * @brief OSC Initialization Configuration Structure |
<> | 144:ef7eb2e8f9f7 | 499 | * |
<> | 144:ef7eb2e8f9f7 | 500 | * Defines the configuration data structure to initialize the OSC. |
<> | 144:ef7eb2e8f9f7 | 501 | * When porting to a new board, please set the following members |
<> | 144:ef7eb2e8f9f7 | 502 | * according to board setting: |
<> | 144:ef7eb2e8f9f7 | 503 | * 1. freq: The external frequency. |
<> | 144:ef7eb2e8f9f7 | 504 | * 2. workMode: The OSC module mode. |
<> | 144:ef7eb2e8f9f7 | 505 | */ |
<> | 144:ef7eb2e8f9f7 | 506 | typedef struct _osc_config |
<> | 144:ef7eb2e8f9f7 | 507 | { |
<> | 144:ef7eb2e8f9f7 | 508 | uint32_t freq; /*!< External clock frequency. */ |
<> | 144:ef7eb2e8f9f7 | 509 | uint8_t capLoad; /*!< Capacitor load setting. */ |
<> | 144:ef7eb2e8f9f7 | 510 | osc_mode_t workMode; /*!< OSC work mode setting. */ |
<> | 144:ef7eb2e8f9f7 | 511 | oscer_config_t oscerConfig; /*!< Configuration for OSCERCLK. */ |
<> | 144:ef7eb2e8f9f7 | 512 | } osc_config_t; |
<> | 144:ef7eb2e8f9f7 | 513 | |
<> | 144:ef7eb2e8f9f7 | 514 | /*! @brief MCG FLL reference clock source select. */ |
<> | 144:ef7eb2e8f9f7 | 515 | typedef enum _mcg_fll_src |
<> | 144:ef7eb2e8f9f7 | 516 | { |
<> | 144:ef7eb2e8f9f7 | 517 | kMCG_FllSrcExternal, /*!< External reference clock is selected */ |
<> | 144:ef7eb2e8f9f7 | 518 | kMCG_FllSrcInternal /*!< The slow internal reference clock is selected */ |
<> | 144:ef7eb2e8f9f7 | 519 | } mcg_fll_src_t; |
<> | 144:ef7eb2e8f9f7 | 520 | |
<> | 144:ef7eb2e8f9f7 | 521 | /*! @brief MCG internal reference clock select */ |
<> | 144:ef7eb2e8f9f7 | 522 | typedef enum _mcg_irc_mode |
<> | 144:ef7eb2e8f9f7 | 523 | { |
<> | 144:ef7eb2e8f9f7 | 524 | kMCG_IrcSlow, /*!< Slow internal reference clock selected */ |
<> | 144:ef7eb2e8f9f7 | 525 | kMCG_IrcFast /*!< Fast internal reference clock selected */ |
<> | 144:ef7eb2e8f9f7 | 526 | } mcg_irc_mode_t; |
<> | 144:ef7eb2e8f9f7 | 527 | |
<> | 144:ef7eb2e8f9f7 | 528 | /*! @brief MCG DCO Maximum Frequency with 32.768 kHz Reference */ |
<> | 144:ef7eb2e8f9f7 | 529 | typedef enum _mcg_dmx32 |
<> | 144:ef7eb2e8f9f7 | 530 | { |
<> | 144:ef7eb2e8f9f7 | 531 | kMCG_Dmx32Default, /*!< DCO has a default range of 25% */ |
<> | 144:ef7eb2e8f9f7 | 532 | kMCG_Dmx32Fine /*!< DCO is fine-tuned for maximum frequency with 32.768 kHz reference */ |
<> | 144:ef7eb2e8f9f7 | 533 | } mcg_dmx32_t; |
<> | 144:ef7eb2e8f9f7 | 534 | |
<> | 144:ef7eb2e8f9f7 | 535 | /*! @brief MCG DCO range select */ |
<> | 144:ef7eb2e8f9f7 | 536 | typedef enum _mcg_drs |
<> | 144:ef7eb2e8f9f7 | 537 | { |
<> | 144:ef7eb2e8f9f7 | 538 | kMCG_DrsLow, /*!< Low frequency range */ |
<> | 144:ef7eb2e8f9f7 | 539 | kMCG_DrsMid, /*!< Mid frequency range */ |
<> | 144:ef7eb2e8f9f7 | 540 | kMCG_DrsMidHigh, /*!< Mid-High frequency range */ |
<> | 144:ef7eb2e8f9f7 | 541 | kMCG_DrsHigh /*!< High frequency range */ |
<> | 144:ef7eb2e8f9f7 | 542 | } mcg_drs_t; |
<> | 144:ef7eb2e8f9f7 | 543 | |
<> | 144:ef7eb2e8f9f7 | 544 | /*! @brief MCG PLL reference clock select */ |
<> | 144:ef7eb2e8f9f7 | 545 | typedef enum _mcg_pll_ref_src |
<> | 144:ef7eb2e8f9f7 | 546 | { |
<> | 144:ef7eb2e8f9f7 | 547 | kMCG_PllRefOsc0, /*!< Selects OSC0 as PLL reference clock */ |
<> | 144:ef7eb2e8f9f7 | 548 | kMCG_PllRefOsc1 /*!< Selects OSC1 as PLL reference clock */ |
<> | 144:ef7eb2e8f9f7 | 549 | } mcg_pll_ref_src_t; |
<> | 144:ef7eb2e8f9f7 | 550 | |
<> | 144:ef7eb2e8f9f7 | 551 | /*! @brief MCGOUT clock source. */ |
<> | 144:ef7eb2e8f9f7 | 552 | typedef enum _mcg_clkout_src |
<> | 144:ef7eb2e8f9f7 | 553 | { |
<> | 144:ef7eb2e8f9f7 | 554 | kMCG_ClkOutSrcOut, /*!< Output of the FLL is selected (reset default) */ |
<> | 144:ef7eb2e8f9f7 | 555 | kMCG_ClkOutSrcInternal, /*!< Internal reference clock is selected */ |
<> | 144:ef7eb2e8f9f7 | 556 | kMCG_ClkOutSrcExternal, /*!< External reference clock is selected */ |
<> | 144:ef7eb2e8f9f7 | 557 | } mcg_clkout_src_t; |
<> | 144:ef7eb2e8f9f7 | 558 | |
<> | 144:ef7eb2e8f9f7 | 559 | /*! @brief MCG Automatic Trim Machine Select */ |
<> | 144:ef7eb2e8f9f7 | 560 | typedef enum _mcg_atm_select |
<> | 144:ef7eb2e8f9f7 | 561 | { |
<> | 144:ef7eb2e8f9f7 | 562 | kMCG_AtmSel32k, /*!< 32 kHz Internal Reference Clock selected */ |
<> | 144:ef7eb2e8f9f7 | 563 | kMCG_AtmSel4m /*!< 4 MHz Internal Reference Clock selected */ |
<> | 144:ef7eb2e8f9f7 | 564 | } mcg_atm_select_t; |
<> | 144:ef7eb2e8f9f7 | 565 | |
<> | 144:ef7eb2e8f9f7 | 566 | /*! @brief MCG OSC Clock Select */ |
<> | 144:ef7eb2e8f9f7 | 567 | typedef enum _mcg_oscsel |
<> | 144:ef7eb2e8f9f7 | 568 | { |
<> | 144:ef7eb2e8f9f7 | 569 | kMCG_OscselOsc, /*!< Selects System Oscillator (OSCCLK) */ |
<> | 144:ef7eb2e8f9f7 | 570 | kMCG_OscselRtc, /*!< Selects 32 kHz RTC Oscillator */ |
<> | 144:ef7eb2e8f9f7 | 571 | kMCG_OscselIrc /*!< Selects 48 MHz IRC Oscillator */ |
<> | 144:ef7eb2e8f9f7 | 572 | } mcg_oscsel_t; |
<> | 144:ef7eb2e8f9f7 | 573 | |
<> | 144:ef7eb2e8f9f7 | 574 | /*! @brief MCG PLLCS select */ |
<> | 144:ef7eb2e8f9f7 | 575 | typedef enum _mcg_pll_clk_select |
<> | 144:ef7eb2e8f9f7 | 576 | { |
<> | 144:ef7eb2e8f9f7 | 577 | kMCG_PllClkSelPll0, /*!< PLL0 output clock is selected */ |
<> | 144:ef7eb2e8f9f7 | 578 | kMCG_PllClkSelExtPll /* External PLL clock is selected */ |
<> | 144:ef7eb2e8f9f7 | 579 | } mcg_pll_clk_select_t; |
<> | 144:ef7eb2e8f9f7 | 580 | |
<> | 144:ef7eb2e8f9f7 | 581 | /*! @brief MCG clock monitor mode. */ |
<> | 144:ef7eb2e8f9f7 | 582 | typedef enum _mcg_monitor_mode |
<> | 144:ef7eb2e8f9f7 | 583 | { |
<> | 144:ef7eb2e8f9f7 | 584 | kMCG_MonitorNone, /*!< Clock monitor is disabled. */ |
<> | 144:ef7eb2e8f9f7 | 585 | kMCG_MonitorInt, /*!< Trigger interrupt when clock lost. */ |
<> | 144:ef7eb2e8f9f7 | 586 | kMCG_MonitorReset /*!< System reset when clock lost. */ |
<> | 144:ef7eb2e8f9f7 | 587 | } mcg_monitor_mode_t; |
<> | 144:ef7eb2e8f9f7 | 588 | |
<> | 144:ef7eb2e8f9f7 | 589 | /*! @brief MCG status. */ |
<> | 144:ef7eb2e8f9f7 | 590 | enum _mcg_status |
<> | 144:ef7eb2e8f9f7 | 591 | { |
<> | 144:ef7eb2e8f9f7 | 592 | kStatus_MCG_ModeUnreachable = MAKE_STATUS(kStatusGroup_MCG, 0), /*!< Can't switch to target mode. */ |
<> | 144:ef7eb2e8f9f7 | 593 | kStatus_MCG_ModeInvalid = MAKE_STATUS(kStatusGroup_MCG, 1), /*!< Current mode invalid for the specific |
<> | 144:ef7eb2e8f9f7 | 594 | function. */ |
<> | 144:ef7eb2e8f9f7 | 595 | kStatus_MCG_AtmBusClockInvalid = MAKE_STATUS(kStatusGroup_MCG, 2), /*!< Invalid bus clock for ATM. */ |
<> | 144:ef7eb2e8f9f7 | 596 | kStatus_MCG_AtmDesiredFreqInvalid = MAKE_STATUS(kStatusGroup_MCG, 3), /*!< Invalid desired frequency for ATM. */ |
<> | 144:ef7eb2e8f9f7 | 597 | kStatus_MCG_AtmIrcUsed = MAKE_STATUS(kStatusGroup_MCG, 4), /*!< IRC is used when using ATM. */ |
<> | 144:ef7eb2e8f9f7 | 598 | kStatus_MCG_AtmHardwareFail = MAKE_STATUS(kStatusGroup_MCG, 5), /*!< Hardware fail occurs during ATM. */ |
<> | 144:ef7eb2e8f9f7 | 599 | kStatus_MCG_SourceUsed = MAKE_STATUS(kStatusGroup_MCG, 6) /*!< Could not change clock source because |
<> | 144:ef7eb2e8f9f7 | 600 | it is used currently. */ |
<> | 144:ef7eb2e8f9f7 | 601 | }; |
<> | 144:ef7eb2e8f9f7 | 602 | |
<> | 144:ef7eb2e8f9f7 | 603 | /*! @brief MCG status flags. */ |
<> | 144:ef7eb2e8f9f7 | 604 | enum _mcg_status_flags_t |
<> | 144:ef7eb2e8f9f7 | 605 | { |
<> | 144:ef7eb2e8f9f7 | 606 | kMCG_Osc0LostFlag = (1U << 0U), /*!< OSC0 lost. */ |
<> | 144:ef7eb2e8f9f7 | 607 | kMCG_Osc0InitFlag = (1U << 1U), /*!< OSC0 crystal initialized. */ |
<> | 144:ef7eb2e8f9f7 | 608 | kMCG_RtcOscLostFlag = (1U << 4U), /*!< RTC OSC lost. */ |
<> | 144:ef7eb2e8f9f7 | 609 | kMCG_Pll0LostFlag = (1U << 5U), /*!< PLL0 lost. */ |
<> | 144:ef7eb2e8f9f7 | 610 | kMCG_Pll0LockFlag = (1U << 6U), /*!< PLL0 locked. */ |
<> | 144:ef7eb2e8f9f7 | 611 | kMCG_ExtPllLostFlag = (1U << 9U), /*!< External PLL lost. */ |
<> | 144:ef7eb2e8f9f7 | 612 | }; |
<> | 144:ef7eb2e8f9f7 | 613 | |
<> | 144:ef7eb2e8f9f7 | 614 | /*! @brief MCG internal reference clock (MCGIRCLK) enable mode definition. */ |
<> | 144:ef7eb2e8f9f7 | 615 | enum _mcg_irclk_enable_mode |
<> | 144:ef7eb2e8f9f7 | 616 | { |
<> | 144:ef7eb2e8f9f7 | 617 | kMCG_IrclkEnable = MCG_C1_IRCLKEN_MASK, /*!< MCGIRCLK enable. */ |
<> | 144:ef7eb2e8f9f7 | 618 | kMCG_IrclkEnableInStop = MCG_C1_IREFSTEN_MASK /*!< MCGIRCLK enable in stop mode. */ |
<> | 144:ef7eb2e8f9f7 | 619 | }; |
<> | 144:ef7eb2e8f9f7 | 620 | |
<> | 144:ef7eb2e8f9f7 | 621 | /*! @brief MCG PLL clock enable mode definition. */ |
<> | 144:ef7eb2e8f9f7 | 622 | enum _mcg_pll_enable_mode |
<> | 144:ef7eb2e8f9f7 | 623 | { |
<> | 144:ef7eb2e8f9f7 | 624 | kMCG_PllEnableIndependent = MCG_C5_PLLCLKEN0_MASK, /*!< MCGPLLCLK enable indepencent of |
<> | 144:ef7eb2e8f9f7 | 625 | MCG clock mode. Generally, PLL |
<> | 144:ef7eb2e8f9f7 | 626 | is disabled in FLL modes |
<> | 144:ef7eb2e8f9f7 | 627 | (FEI/FBI/FEE/FBE), set PLL clock |
<> | 144:ef7eb2e8f9f7 | 628 | enable independent will enable |
<> | 144:ef7eb2e8f9f7 | 629 | PLL in the FLL modes. */ |
<> | 144:ef7eb2e8f9f7 | 630 | kMCG_PllEnableInStop = MCG_C5_PLLSTEN0_MASK /*!< MCGPLLCLK enable in STOP mode. */ |
<> | 144:ef7eb2e8f9f7 | 631 | }; |
<> | 144:ef7eb2e8f9f7 | 632 | |
<> | 144:ef7eb2e8f9f7 | 633 | /*! @brief MCG mode definitions */ |
<> | 144:ef7eb2e8f9f7 | 634 | typedef enum _mcg_mode |
<> | 144:ef7eb2e8f9f7 | 635 | { |
<> | 144:ef7eb2e8f9f7 | 636 | kMCG_ModeFEI = 0U, /*!< FEI - FLL Engaged Internal */ |
<> | 144:ef7eb2e8f9f7 | 637 | kMCG_ModeFBI, /*!< FBI - FLL Bypassed Internal */ |
<> | 144:ef7eb2e8f9f7 | 638 | kMCG_ModeBLPI, /*!< BLPI - Bypassed Low Power Internal */ |
<> | 144:ef7eb2e8f9f7 | 639 | kMCG_ModeFEE, /*!< FEE - FLL Engaged External */ |
<> | 144:ef7eb2e8f9f7 | 640 | kMCG_ModeFBE, /*!< FBE - FLL Bypassed External */ |
<> | 144:ef7eb2e8f9f7 | 641 | kMCG_ModeBLPE, /*!< BLPE - Bypassed Low Power External */ |
<> | 144:ef7eb2e8f9f7 | 642 | kMCG_ModePBE, /*!< PBE - PLL Bypassed External */ |
<> | 144:ef7eb2e8f9f7 | 643 | kMCG_ModePEE, /*!< PEE - PLL Engaged External */ |
<> | 144:ef7eb2e8f9f7 | 644 | kMCG_ModeError /*!< Unknown mode */ |
<> | 144:ef7eb2e8f9f7 | 645 | } mcg_mode_t; |
<> | 144:ef7eb2e8f9f7 | 646 | |
<> | 144:ef7eb2e8f9f7 | 647 | /*! @brief MCG PLL configuration. */ |
<> | 144:ef7eb2e8f9f7 | 648 | typedef struct _mcg_pll_config |
<> | 144:ef7eb2e8f9f7 | 649 | { |
<> | 144:ef7eb2e8f9f7 | 650 | uint8_t enableMode; /*!< Enable mode. OR'ed value of @ref _mcg_pll_enable_mode. */ |
<> | 144:ef7eb2e8f9f7 | 651 | uint8_t prdiv; /*!< Reference divider PRDIV. */ |
<> | 144:ef7eb2e8f9f7 | 652 | uint8_t vdiv; /*!< VCO divider VDIV. */ |
<> | 144:ef7eb2e8f9f7 | 653 | } mcg_pll_config_t; |
<> | 144:ef7eb2e8f9f7 | 654 | |
<> | 144:ef7eb2e8f9f7 | 655 | /*! @brief MCG configure structure for mode change. |
<> | 144:ef7eb2e8f9f7 | 656 | * |
<> | 144:ef7eb2e8f9f7 | 657 | * When porting to a new board, please set the following members |
<> | 144:ef7eb2e8f9f7 | 658 | * according to board setting: |
<> | 144:ef7eb2e8f9f7 | 659 | * 1. frdiv: If FLL uses the external reference clock, please set this |
<> | 144:ef7eb2e8f9f7 | 660 | * value to make sure external reference clock divided by frdiv is |
<> | 144:ef7eb2e8f9f7 | 661 | * in the range 31.25kHz to 39.0625kHz. |
<> | 144:ef7eb2e8f9f7 | 662 | * 2. The PLL reference clock divider PRDIV: PLL reference clock frequency after |
<> | 144:ef7eb2e8f9f7 | 663 | * PRDIV should be in the range of FSL_FEATURE_MCG_PLL_REF_MIN to |
<> | 144:ef7eb2e8f9f7 | 664 | * FSL_FEATURE_MCG_PLL_REF_MAX. |
<> | 144:ef7eb2e8f9f7 | 665 | */ |
<> | 144:ef7eb2e8f9f7 | 666 | typedef struct _mcg_config |
<> | 144:ef7eb2e8f9f7 | 667 | { |
<> | 144:ef7eb2e8f9f7 | 668 | mcg_mode_t mcgMode; /*!< MCG mode. */ |
<> | 144:ef7eb2e8f9f7 | 669 | |
<> | 144:ef7eb2e8f9f7 | 670 | /* ----------------------- MCGIRCCLK settings ------------------------ */ |
<> | 144:ef7eb2e8f9f7 | 671 | uint8_t irclkEnableMode; /*!< MCGIRCLK enable mode. */ |
<> | 144:ef7eb2e8f9f7 | 672 | mcg_irc_mode_t ircs; /*!< Source, MCG_C2[IRCS]. */ |
<> | 144:ef7eb2e8f9f7 | 673 | uint8_t fcrdiv; /*!< Divider, MCG_SC[FCRDIV]. */ |
<> | 144:ef7eb2e8f9f7 | 674 | |
<> | 144:ef7eb2e8f9f7 | 675 | /* ------------------------ MCG FLL settings ------------------------- */ |
<> | 144:ef7eb2e8f9f7 | 676 | uint8_t frdiv; /*!< Divider MCG_C1[FRDIV]. */ |
<> | 144:ef7eb2e8f9f7 | 677 | mcg_drs_t drs; /*!< DCO range MCG_C4[DRST_DRS]. */ |
<> | 144:ef7eb2e8f9f7 | 678 | mcg_dmx32_t dmx32; /*!< MCG_C4[DMX32]. */ |
<> | 144:ef7eb2e8f9f7 | 679 | mcg_oscsel_t oscsel; /*!< OSC select MCG_C7[OSCSEL]. */ |
<> | 144:ef7eb2e8f9f7 | 680 | |
<> | 144:ef7eb2e8f9f7 | 681 | /* ------------------------ MCG PLL settings ------------------------- */ |
<> | 144:ef7eb2e8f9f7 | 682 | mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration. */ |
<> | 144:ef7eb2e8f9f7 | 683 | |
<> | 144:ef7eb2e8f9f7 | 684 | mcg_pll_clk_select_t pllcs; /*!< PLL select as output, PLLCS.*/ |
<> | 144:ef7eb2e8f9f7 | 685 | |
<> | 144:ef7eb2e8f9f7 | 686 | } mcg_config_t; |
<> | 144:ef7eb2e8f9f7 | 687 | |
<> | 144:ef7eb2e8f9f7 | 688 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 689 | * API |
<> | 144:ef7eb2e8f9f7 | 690 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 691 | |
<> | 144:ef7eb2e8f9f7 | 692 | #if defined(__cplusplus) |
<> | 144:ef7eb2e8f9f7 | 693 | extern "C" { |
<> | 144:ef7eb2e8f9f7 | 694 | #endif /* __cplusplus */ |
<> | 144:ef7eb2e8f9f7 | 695 | |
<> | 144:ef7eb2e8f9f7 | 696 | /*! |
<> | 144:ef7eb2e8f9f7 | 697 | * @brief Set the XTAL0 frequency based on board setting. |
<> | 144:ef7eb2e8f9f7 | 698 | * |
<> | 144:ef7eb2e8f9f7 | 699 | * @param freq The XTAL0/EXTAL0 input clock frequency in Hz. |
<> | 144:ef7eb2e8f9f7 | 700 | */ |
<> | 144:ef7eb2e8f9f7 | 701 | static inline void CLOCK_SetXtal0Freq(uint32_t freq) |
<> | 144:ef7eb2e8f9f7 | 702 | { |
<> | 144:ef7eb2e8f9f7 | 703 | g_xtal0Freq = freq; |
<> | 144:ef7eb2e8f9f7 | 704 | } |
<> | 144:ef7eb2e8f9f7 | 705 | |
<> | 144:ef7eb2e8f9f7 | 706 | /*! |
<> | 144:ef7eb2e8f9f7 | 707 | * @brief Set the XTAL32/RTC_CLKIN frequency based on board setting. |
<> | 144:ef7eb2e8f9f7 | 708 | * |
<> | 144:ef7eb2e8f9f7 | 709 | * @param freq The XTAL32/EXTAL32/RTC_CLKIN input clock frequency in Hz. |
<> | 144:ef7eb2e8f9f7 | 710 | */ |
<> | 144:ef7eb2e8f9f7 | 711 | static inline void CLOCK_SetXtal32Freq(uint32_t freq) |
<> | 144:ef7eb2e8f9f7 | 712 | { |
<> | 144:ef7eb2e8f9f7 | 713 | g_xtal32Freq = freq; |
<> | 144:ef7eb2e8f9f7 | 714 | } |
<> | 144:ef7eb2e8f9f7 | 715 | |
<> | 144:ef7eb2e8f9f7 | 716 | /*! |
<> | 144:ef7eb2e8f9f7 | 717 | * @brief Enable the clock for specific IP. |
<> | 144:ef7eb2e8f9f7 | 718 | * |
<> | 144:ef7eb2e8f9f7 | 719 | * @param name Which clock to enable, see \ref clock_ip_name_t. |
<> | 144:ef7eb2e8f9f7 | 720 | */ |
<> | 144:ef7eb2e8f9f7 | 721 | static inline void CLOCK_EnableClock(clock_ip_name_t name) |
<> | 144:ef7eb2e8f9f7 | 722 | { |
<> | 144:ef7eb2e8f9f7 | 723 | uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); |
<> | 144:ef7eb2e8f9f7 | 724 | (*(volatile uint32_t *)regAddr) |= (1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name)); |
<> | 144:ef7eb2e8f9f7 | 725 | } |
<> | 144:ef7eb2e8f9f7 | 726 | |
<> | 144:ef7eb2e8f9f7 | 727 | /*! |
<> | 144:ef7eb2e8f9f7 | 728 | * @brief Disable the clock for specific IP. |
<> | 144:ef7eb2e8f9f7 | 729 | * |
<> | 144:ef7eb2e8f9f7 | 730 | * @param name Which clock to disable, see \ref clock_ip_name_t. |
<> | 144:ef7eb2e8f9f7 | 731 | */ |
<> | 144:ef7eb2e8f9f7 | 732 | static inline void CLOCK_DisableClock(clock_ip_name_t name) |
<> | 144:ef7eb2e8f9f7 | 733 | { |
<> | 144:ef7eb2e8f9f7 | 734 | uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); |
<> | 144:ef7eb2e8f9f7 | 735 | (*(volatile uint32_t *)regAddr) &= ~(1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name)); |
<> | 144:ef7eb2e8f9f7 | 736 | } |
<> | 144:ef7eb2e8f9f7 | 737 | |
<> | 144:ef7eb2e8f9f7 | 738 | /*! |
<> | 144:ef7eb2e8f9f7 | 739 | * @brief Set ERCLK32K source. |
<> | 144:ef7eb2e8f9f7 | 740 | * |
<> | 144:ef7eb2e8f9f7 | 741 | * @param src The value to set ERCLK32K clock source. |
<> | 144:ef7eb2e8f9f7 | 742 | */ |
<> | 144:ef7eb2e8f9f7 | 743 | static inline void CLOCK_SetEr32kClock(uint32_t src) |
<> | 144:ef7eb2e8f9f7 | 744 | { |
<> | 144:ef7eb2e8f9f7 | 745 | SIM->SOPT1 = ((SIM->SOPT1 & ~SIM_SOPT1_OSC32KSEL_MASK) | SIM_SOPT1_OSC32KSEL(src)); |
<> | 144:ef7eb2e8f9f7 | 746 | } |
<> | 144:ef7eb2e8f9f7 | 747 | |
<> | 144:ef7eb2e8f9f7 | 748 | /*! |
<> | 144:ef7eb2e8f9f7 | 749 | * @brief Set SDHC0 clock source. |
<> | 144:ef7eb2e8f9f7 | 750 | * |
<> | 144:ef7eb2e8f9f7 | 751 | * @param src The value to set SDHC0 clock source. |
<> | 144:ef7eb2e8f9f7 | 752 | */ |
<> | 144:ef7eb2e8f9f7 | 753 | static inline void CLOCK_SetSdhc0Clock(uint32_t src) |
<> | 144:ef7eb2e8f9f7 | 754 | { |
<> | 144:ef7eb2e8f9f7 | 755 | SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_SDHCSRC_MASK) | SIM_SOPT2_SDHCSRC(src)); |
<> | 144:ef7eb2e8f9f7 | 756 | } |
<> | 144:ef7eb2e8f9f7 | 757 | |
<> | 144:ef7eb2e8f9f7 | 758 | /*! |
<> | 144:ef7eb2e8f9f7 | 759 | * @brief Set enet timestamp clock source. |
<> | 144:ef7eb2e8f9f7 | 760 | * |
<> | 144:ef7eb2e8f9f7 | 761 | * @param src The value to set enet timestamp clock source. |
<> | 144:ef7eb2e8f9f7 | 762 | */ |
<> | 144:ef7eb2e8f9f7 | 763 | static inline void CLOCK_SetEnetTime0Clock(uint32_t src) |
<> | 144:ef7eb2e8f9f7 | 764 | { |
<> | 144:ef7eb2e8f9f7 | 765 | SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TIMESRC_MASK) | SIM_SOPT2_TIMESRC(src)); |
<> | 144:ef7eb2e8f9f7 | 766 | } |
<> | 144:ef7eb2e8f9f7 | 767 | |
<> | 144:ef7eb2e8f9f7 | 768 | /*! |
<> | 144:ef7eb2e8f9f7 | 769 | * @brief Set RMII clock source. |
<> | 144:ef7eb2e8f9f7 | 770 | * |
<> | 144:ef7eb2e8f9f7 | 771 | * @param src The value to set RMII clock source. |
<> | 144:ef7eb2e8f9f7 | 772 | */ |
<> | 144:ef7eb2e8f9f7 | 773 | static inline void CLOCK_SetRmii0Clock(uint32_t src) |
<> | 144:ef7eb2e8f9f7 | 774 | { |
<> | 144:ef7eb2e8f9f7 | 775 | SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_RMIISRC_MASK) | SIM_SOPT2_RMIISRC(src)); |
<> | 144:ef7eb2e8f9f7 | 776 | } |
<> | 144:ef7eb2e8f9f7 | 777 | |
<> | 144:ef7eb2e8f9f7 | 778 | /*! |
<> | 144:ef7eb2e8f9f7 | 779 | * @brief Set LPUART clock source. |
<> | 144:ef7eb2e8f9f7 | 780 | * |
<> | 144:ef7eb2e8f9f7 | 781 | * @param src The value to set LPUART clock source. |
<> | 144:ef7eb2e8f9f7 | 782 | */ |
<> | 144:ef7eb2e8f9f7 | 783 | static inline void CLOCK_SetLpuartClock(uint32_t src) |
<> | 144:ef7eb2e8f9f7 | 784 | { |
<> | 144:ef7eb2e8f9f7 | 785 | SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_LPUARTSRC_MASK) | SIM_SOPT2_LPUARTSRC(src)); |
<> | 144:ef7eb2e8f9f7 | 786 | } |
<> | 144:ef7eb2e8f9f7 | 787 | |
<> | 144:ef7eb2e8f9f7 | 788 | /*! |
<> | 144:ef7eb2e8f9f7 | 789 | * @brief Set TPM clock source. |
<> | 144:ef7eb2e8f9f7 | 790 | * |
<> | 144:ef7eb2e8f9f7 | 791 | * @param src The value to set TPM clock source. |
<> | 144:ef7eb2e8f9f7 | 792 | */ |
<> | 144:ef7eb2e8f9f7 | 793 | static inline void CLOCK_SetTpmClock(uint32_t src) |
<> | 144:ef7eb2e8f9f7 | 794 | { |
<> | 144:ef7eb2e8f9f7 | 795 | SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TPMSRC_MASK) | SIM_SOPT2_TPMSRC(src)); |
<> | 144:ef7eb2e8f9f7 | 796 | } |
<> | 144:ef7eb2e8f9f7 | 797 | |
<> | 144:ef7eb2e8f9f7 | 798 | /*! |
<> | 144:ef7eb2e8f9f7 | 799 | * @brief Set debug trace clock source. |
<> | 144:ef7eb2e8f9f7 | 800 | * |
<> | 144:ef7eb2e8f9f7 | 801 | * @param src The value to set debug trace clock source. |
<> | 144:ef7eb2e8f9f7 | 802 | */ |
<> | 144:ef7eb2e8f9f7 | 803 | static inline void CLOCK_SetTraceClock(uint32_t src, uint32_t divValue, uint32_t fracValue) |
<> | 144:ef7eb2e8f9f7 | 804 | { |
<> | 144:ef7eb2e8f9f7 | 805 | SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TRACECLKSEL_MASK) | SIM_SOPT2_TRACECLKSEL(src)); |
<> | 144:ef7eb2e8f9f7 | 806 | SIM->CLKDIV4 = SIM_CLKDIV4_TRACEDIV(divValue) | SIM_CLKDIV4_TRACEFRAC(fracValue); |
<> | 144:ef7eb2e8f9f7 | 807 | } |
<> | 144:ef7eb2e8f9f7 | 808 | |
<> | 144:ef7eb2e8f9f7 | 809 | /*! |
<> | 144:ef7eb2e8f9f7 | 810 | * @brief Set PLLFLLSEL clock source. |
<> | 144:ef7eb2e8f9f7 | 811 | * |
<> | 144:ef7eb2e8f9f7 | 812 | * @param src The value to set PLLFLLSEL clock source. |
<> | 144:ef7eb2e8f9f7 | 813 | */ |
<> | 144:ef7eb2e8f9f7 | 814 | static inline void CLOCK_SetPllFllSelClock(uint32_t src, uint32_t divValue, uint32_t fracValue) |
<> | 144:ef7eb2e8f9f7 | 815 | { |
<> | 144:ef7eb2e8f9f7 | 816 | SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_PLLFLLSEL_MASK) | SIM_SOPT2_PLLFLLSEL(src)); |
<> | 144:ef7eb2e8f9f7 | 817 | SIM->CLKDIV3 = SIM_CLKDIV3_PLLFLLDIV(divValue) | SIM_CLKDIV3_PLLFLLFRAC(fracValue); |
<> | 144:ef7eb2e8f9f7 | 818 | } |
<> | 144:ef7eb2e8f9f7 | 819 | |
<> | 144:ef7eb2e8f9f7 | 820 | /*! |
<> | 144:ef7eb2e8f9f7 | 821 | * @brief Set CLKOUT source. |
<> | 144:ef7eb2e8f9f7 | 822 | * |
<> | 144:ef7eb2e8f9f7 | 823 | * @param src The value to set CLKOUT source. |
<> | 144:ef7eb2e8f9f7 | 824 | */ |
<> | 144:ef7eb2e8f9f7 | 825 | static inline void CLOCK_SetClkOutClock(uint32_t src) |
<> | 144:ef7eb2e8f9f7 | 826 | { |
<> | 144:ef7eb2e8f9f7 | 827 | SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_CLKOUTSEL_MASK) | SIM_SOPT2_CLKOUTSEL(src)); |
<> | 144:ef7eb2e8f9f7 | 828 | } |
<> | 144:ef7eb2e8f9f7 | 829 | |
<> | 144:ef7eb2e8f9f7 | 830 | /*! |
<> | 144:ef7eb2e8f9f7 | 831 | * @brief Set RTC_CLKOUT source. |
<> | 144:ef7eb2e8f9f7 | 832 | * |
<> | 144:ef7eb2e8f9f7 | 833 | * @param src The value to set RTC_CLKOUT source. |
<> | 144:ef7eb2e8f9f7 | 834 | */ |
<> | 144:ef7eb2e8f9f7 | 835 | static inline void CLOCK_SetRtcClkOutClock(uint32_t src) |
<> | 144:ef7eb2e8f9f7 | 836 | { |
<> | 144:ef7eb2e8f9f7 | 837 | SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_RTCCLKOUTSEL_MASK) | SIM_SOPT2_RTCCLKOUTSEL(src)); |
<> | 144:ef7eb2e8f9f7 | 838 | } |
<> | 144:ef7eb2e8f9f7 | 839 | |
<> | 144:ef7eb2e8f9f7 | 840 | /*! @brief Enable USB HS clock. |
<> | 144:ef7eb2e8f9f7 | 841 | * |
<> | 144:ef7eb2e8f9f7 | 842 | * @param src USB HS clock source. |
<> | 144:ef7eb2e8f9f7 | 843 | * @param freq The frequency specified by src. |
<> | 144:ef7eb2e8f9f7 | 844 | * @retval true The clock is set successfully. |
<> | 144:ef7eb2e8f9f7 | 845 | * @retval false The clock source is invalid to get proper USB HS clock. |
<> | 144:ef7eb2e8f9f7 | 846 | */ |
<> | 144:ef7eb2e8f9f7 | 847 | bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq); |
<> | 144:ef7eb2e8f9f7 | 848 | |
<> | 144:ef7eb2e8f9f7 | 849 | /*! @brief Disable USB HS clock. |
<> | 144:ef7eb2e8f9f7 | 850 | * |
<> | 144:ef7eb2e8f9f7 | 851 | * Disable USB HS clock. |
<> | 144:ef7eb2e8f9f7 | 852 | */ |
<> | 144:ef7eb2e8f9f7 | 853 | static inline void CLOCK_DisableUsbhs0Clock(void) |
<> | 144:ef7eb2e8f9f7 | 854 | { |
<> | 144:ef7eb2e8f9f7 | 855 | SIM->SOPT2 &= ~SIM_SOPT2_USBREGEN_MASK; |
<> | 144:ef7eb2e8f9f7 | 856 | SIM->SCGC3 &= ~(SIM_SCGC3_USBHS_MASK | SIM_SCGC3_USBHSPHY_MASK); |
<> | 144:ef7eb2e8f9f7 | 857 | } |
<> | 144:ef7eb2e8f9f7 | 858 | |
<> | 144:ef7eb2e8f9f7 | 859 | /*! @brief Enable USB FS clock. |
<> | 144:ef7eb2e8f9f7 | 860 | * |
<> | 144:ef7eb2e8f9f7 | 861 | * @param src USB FS clock source. |
<> | 144:ef7eb2e8f9f7 | 862 | * @param freq The frequency specified by src. |
<> | 144:ef7eb2e8f9f7 | 863 | * @retval true The clock is set successfully. |
<> | 144:ef7eb2e8f9f7 | 864 | * @retval false The clock source is invalid to get proper USB FS clock. |
<> | 144:ef7eb2e8f9f7 | 865 | */ |
<> | 144:ef7eb2e8f9f7 | 866 | bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq); |
<> | 144:ef7eb2e8f9f7 | 867 | |
<> | 144:ef7eb2e8f9f7 | 868 | /*! @brief Disable USB FS clock. |
<> | 144:ef7eb2e8f9f7 | 869 | * |
<> | 144:ef7eb2e8f9f7 | 870 | * Disable USB FS clock. |
<> | 144:ef7eb2e8f9f7 | 871 | */ |
<> | 144:ef7eb2e8f9f7 | 872 | static inline void CLOCK_DisableUsbfs0Clock(void) |
<> | 144:ef7eb2e8f9f7 | 873 | { |
<> | 144:ef7eb2e8f9f7 | 874 | CLOCK_DisableClock(kCLOCK_Usbfs0); |
<> | 144:ef7eb2e8f9f7 | 875 | } |
<> | 144:ef7eb2e8f9f7 | 876 | |
<> | 144:ef7eb2e8f9f7 | 877 | /*! |
<> | 144:ef7eb2e8f9f7 | 878 | * @brief System clock divider |
<> | 144:ef7eb2e8f9f7 | 879 | * |
<> | 144:ef7eb2e8f9f7 | 880 | * Set the SIM_CLKDIV1[OUTDIV1], SIM_CLKDIV1[OUTDIV2], SIM_CLKDIV1[OUTDIV3], SIM_CLKDIV1[OUTDIV4]. |
<> | 144:ef7eb2e8f9f7 | 881 | * |
<> | 144:ef7eb2e8f9f7 | 882 | * @param outdiv1 Clock 1 output divider value. |
<> | 144:ef7eb2e8f9f7 | 883 | * |
<> | 144:ef7eb2e8f9f7 | 884 | * @param outdiv2 Clock 2 output divider value. |
<> | 144:ef7eb2e8f9f7 | 885 | * |
<> | 144:ef7eb2e8f9f7 | 886 | * @param outdiv3 Clock 3 output divider value. |
<> | 144:ef7eb2e8f9f7 | 887 | * |
<> | 144:ef7eb2e8f9f7 | 888 | * @param outdiv4 Clock 4 output divider value. |
<> | 144:ef7eb2e8f9f7 | 889 | */ |
<> | 144:ef7eb2e8f9f7 | 890 | static inline void CLOCK_SetOutDiv(uint32_t outdiv1, uint32_t outdiv2, uint32_t outdiv3, uint32_t outdiv4) |
<> | 144:ef7eb2e8f9f7 | 891 | { |
<> | 144:ef7eb2e8f9f7 | 892 | SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(outdiv1) | SIM_CLKDIV1_OUTDIV2(outdiv2) | SIM_CLKDIV1_OUTDIV3(outdiv3) | |
<> | 144:ef7eb2e8f9f7 | 893 | SIM_CLKDIV1_OUTDIV4(outdiv4); |
<> | 144:ef7eb2e8f9f7 | 894 | } |
<> | 144:ef7eb2e8f9f7 | 895 | |
<> | 144:ef7eb2e8f9f7 | 896 | /*! |
<> | 144:ef7eb2e8f9f7 | 897 | * @brief Gets the clock frequency for a specific clock name. |
<> | 144:ef7eb2e8f9f7 | 898 | * |
<> | 144:ef7eb2e8f9f7 | 899 | * This function checks the current clock configurations and then calculates |
<> | 144:ef7eb2e8f9f7 | 900 | * the clock frequency for a specific clock name defined in clock_name_t. |
<> | 144:ef7eb2e8f9f7 | 901 | * The MCG must be properly configured before using this function. |
<> | 144:ef7eb2e8f9f7 | 902 | * |
<> | 144:ef7eb2e8f9f7 | 903 | * @param clockName Clock names defined in clock_name_t |
<> | 144:ef7eb2e8f9f7 | 904 | * @return Clock frequency value in Hertz |
<> | 144:ef7eb2e8f9f7 | 905 | */ |
<> | 144:ef7eb2e8f9f7 | 906 | uint32_t CLOCK_GetFreq(clock_name_t clockName); |
<> | 144:ef7eb2e8f9f7 | 907 | |
<> | 144:ef7eb2e8f9f7 | 908 | /*! |
<> | 144:ef7eb2e8f9f7 | 909 | * @brief Get the core clock or system clock frequency. |
<> | 144:ef7eb2e8f9f7 | 910 | * |
<> | 144:ef7eb2e8f9f7 | 911 | * @return Clock frequency in Hz. |
<> | 144:ef7eb2e8f9f7 | 912 | */ |
<> | 144:ef7eb2e8f9f7 | 913 | uint32_t CLOCK_GetCoreSysClkFreq(void); |
<> | 144:ef7eb2e8f9f7 | 914 | |
<> | 144:ef7eb2e8f9f7 | 915 | /*! |
<> | 144:ef7eb2e8f9f7 | 916 | * @brief Get the platform clock frequency. |
<> | 144:ef7eb2e8f9f7 | 917 | * |
<> | 144:ef7eb2e8f9f7 | 918 | * @return Clock frequency in Hz. |
<> | 144:ef7eb2e8f9f7 | 919 | */ |
<> | 144:ef7eb2e8f9f7 | 920 | uint32_t CLOCK_GetPlatClkFreq(void); |
<> | 144:ef7eb2e8f9f7 | 921 | |
<> | 144:ef7eb2e8f9f7 | 922 | /*! |
<> | 144:ef7eb2e8f9f7 | 923 | * @brief Get the bus clock frequency. |
<> | 144:ef7eb2e8f9f7 | 924 | * |
<> | 144:ef7eb2e8f9f7 | 925 | * @return Clock frequency in Hz. |
<> | 144:ef7eb2e8f9f7 | 926 | */ |
<> | 144:ef7eb2e8f9f7 | 927 | uint32_t CLOCK_GetBusClkFreq(void); |
<> | 144:ef7eb2e8f9f7 | 928 | |
<> | 144:ef7eb2e8f9f7 | 929 | /*! |
<> | 144:ef7eb2e8f9f7 | 930 | * @brief Get the flexbus clock frequency. |
<> | 144:ef7eb2e8f9f7 | 931 | * |
<> | 144:ef7eb2e8f9f7 | 932 | * @return Clock frequency in Hz. |
<> | 144:ef7eb2e8f9f7 | 933 | */ |
<> | 144:ef7eb2e8f9f7 | 934 | uint32_t CLOCK_GetFlexBusClkFreq(void); |
<> | 144:ef7eb2e8f9f7 | 935 | |
<> | 144:ef7eb2e8f9f7 | 936 | /*! |
<> | 144:ef7eb2e8f9f7 | 937 | * @brief Get the flash clock frequency. |
<> | 144:ef7eb2e8f9f7 | 938 | * |
<> | 144:ef7eb2e8f9f7 | 939 | * @return Clock frequency in Hz. |
<> | 144:ef7eb2e8f9f7 | 940 | */ |
<> | 144:ef7eb2e8f9f7 | 941 | uint32_t CLOCK_GetFlashClkFreq(void); |
<> | 144:ef7eb2e8f9f7 | 942 | |
<> | 144:ef7eb2e8f9f7 | 943 | /*! |
<> | 144:ef7eb2e8f9f7 | 944 | * @brief Get the output clock frequency selected by SIM[PLLFLLSEL]. |
<> | 144:ef7eb2e8f9f7 | 945 | * |
<> | 144:ef7eb2e8f9f7 | 946 | * @return Clock frequency in Hz. |
<> | 144:ef7eb2e8f9f7 | 947 | */ |
<> | 144:ef7eb2e8f9f7 | 948 | uint32_t CLOCK_GetPllFllSelClkFreq(void); |
<> | 144:ef7eb2e8f9f7 | 949 | |
<> | 144:ef7eb2e8f9f7 | 950 | /*! |
<> | 144:ef7eb2e8f9f7 | 951 | * @brief Get the external reference 32K clock frequency (ERCLK32K). |
<> | 144:ef7eb2e8f9f7 | 952 | * |
<> | 144:ef7eb2e8f9f7 | 953 | * @return Clock frequency in Hz. |
<> | 144:ef7eb2e8f9f7 | 954 | */ |
<> | 144:ef7eb2e8f9f7 | 955 | uint32_t CLOCK_GetEr32kClkFreq(void); |
<> | 144:ef7eb2e8f9f7 | 956 | |
<> | 144:ef7eb2e8f9f7 | 957 | /*! |
<> | 144:ef7eb2e8f9f7 | 958 | * @brief Get the OSC0 external reference clock frequency (OSC0ERCLK). |
<> | 144:ef7eb2e8f9f7 | 959 | * |
<> | 144:ef7eb2e8f9f7 | 960 | * @return Clock frequency in Hz. |
<> | 144:ef7eb2e8f9f7 | 961 | */ |
<> | 144:ef7eb2e8f9f7 | 962 | uint32_t CLOCK_GetOsc0ErClkFreq(void); |
<> | 144:ef7eb2e8f9f7 | 963 | |
<> | 144:ef7eb2e8f9f7 | 964 | /*! |
<> | 144:ef7eb2e8f9f7 | 965 | * @brief Get the OSC0 external reference undivided clock frequency (OSC0ERCLK_UNDIV). |
<> | 144:ef7eb2e8f9f7 | 966 | * |
<> | 144:ef7eb2e8f9f7 | 967 | * @return Clock frequency in Hz. |
<> | 144:ef7eb2e8f9f7 | 968 | */ |
<> | 144:ef7eb2e8f9f7 | 969 | uint32_t CLOCK_GetOsc0ErClkUndivFreq(void); |
<> | 144:ef7eb2e8f9f7 | 970 | |
<> | 144:ef7eb2e8f9f7 | 971 | /*! |
<> | 144:ef7eb2e8f9f7 | 972 | * @brief Set the clock configure in SIM module. |
<> | 144:ef7eb2e8f9f7 | 973 | * |
<> | 144:ef7eb2e8f9f7 | 974 | * This function sets system layer clock settings in SIM module. |
<> | 144:ef7eb2e8f9f7 | 975 | * |
<> | 144:ef7eb2e8f9f7 | 976 | * @param config Pointer to the configure structure. |
<> | 144:ef7eb2e8f9f7 | 977 | */ |
<> | 144:ef7eb2e8f9f7 | 978 | void CLOCK_SetSimConfig(sim_clock_config_t const *config); |
<> | 144:ef7eb2e8f9f7 | 979 | |
<> | 144:ef7eb2e8f9f7 | 980 | /*! |
<> | 144:ef7eb2e8f9f7 | 981 | * @brief Set the system clock dividers in SIM to safe value. |
<> | 144:ef7eb2e8f9f7 | 982 | * |
<> | 144:ef7eb2e8f9f7 | 983 | * The system level clocks (core clock, bus clock, flexbus clock and flash clock) |
<> | 144:ef7eb2e8f9f7 | 984 | * must be in allowed ranges. During MCG clock mode switch, the MCG output clock |
<> | 144:ef7eb2e8f9f7 | 985 | * changes then the system level clocks may be out of range. This function could |
<> | 144:ef7eb2e8f9f7 | 986 | * be used before MCG mode change, to make sure system level clocks are in allowed |
<> | 144:ef7eb2e8f9f7 | 987 | * range. |
<> | 144:ef7eb2e8f9f7 | 988 | * |
<> | 144:ef7eb2e8f9f7 | 989 | * @param config Pointer to the configure structure. |
<> | 144:ef7eb2e8f9f7 | 990 | */ |
<> | 144:ef7eb2e8f9f7 | 991 | static inline void CLOCK_SetSimSafeDivs(void) |
<> | 144:ef7eb2e8f9f7 | 992 | { |
<> | 144:ef7eb2e8f9f7 | 993 | SIM->CLKDIV1 = 0x02260000U; |
<> | 144:ef7eb2e8f9f7 | 994 | } |
<> | 144:ef7eb2e8f9f7 | 995 | |
<> | 144:ef7eb2e8f9f7 | 996 | /*! @name MCG frequency functions. */ |
<> | 144:ef7eb2e8f9f7 | 997 | /*@{*/ |
<> | 144:ef7eb2e8f9f7 | 998 | |
<> | 144:ef7eb2e8f9f7 | 999 | /*! |
<> | 144:ef7eb2e8f9f7 | 1000 | * @brief Get the MCG output clock(MCGOUTCLK) frequency. |
<> | 144:ef7eb2e8f9f7 | 1001 | * |
<> | 144:ef7eb2e8f9f7 | 1002 | * This function gets the MCG output clock frequency (Hz) based on current MCG |
<> | 144:ef7eb2e8f9f7 | 1003 | * register value. |
<> | 144:ef7eb2e8f9f7 | 1004 | * |
<> | 144:ef7eb2e8f9f7 | 1005 | * @return The frequency of MCGOUTCLK. |
<> | 144:ef7eb2e8f9f7 | 1006 | */ |
<> | 144:ef7eb2e8f9f7 | 1007 | uint32_t CLOCK_GetOutClkFreq(void); |
<> | 144:ef7eb2e8f9f7 | 1008 | |
<> | 144:ef7eb2e8f9f7 | 1009 | /*! |
<> | 144:ef7eb2e8f9f7 | 1010 | * @brief Get the MCG FLL clock(MCGFLLCLK) frequency. |
<> | 144:ef7eb2e8f9f7 | 1011 | * |
<> | 144:ef7eb2e8f9f7 | 1012 | * This function gets the MCG FLL clock frequency (Hz) based on current MCG |
<> | 144:ef7eb2e8f9f7 | 1013 | * register value. The FLL is only enabled in FEI/FBI/FEE/FBE mode, in other |
<> | 144:ef7eb2e8f9f7 | 1014 | * modes, FLL is disabled in low power state. |
<> | 144:ef7eb2e8f9f7 | 1015 | * |
<> | 144:ef7eb2e8f9f7 | 1016 | * @return The frequency of MCGFLLCLK. |
<> | 144:ef7eb2e8f9f7 | 1017 | */ |
<> | 144:ef7eb2e8f9f7 | 1018 | uint32_t CLOCK_GetFllFreq(void); |
<> | 144:ef7eb2e8f9f7 | 1019 | |
<> | 144:ef7eb2e8f9f7 | 1020 | /*! |
<> | 144:ef7eb2e8f9f7 | 1021 | * @brief Get the MCG internal reference clock(MCGIRCLK) frequency. |
<> | 144:ef7eb2e8f9f7 | 1022 | * |
<> | 144:ef7eb2e8f9f7 | 1023 | * This function gets the MCG internal reference clock frequency (Hz) based |
<> | 144:ef7eb2e8f9f7 | 1024 | * on current MCG register value. |
<> | 144:ef7eb2e8f9f7 | 1025 | * |
<> | 144:ef7eb2e8f9f7 | 1026 | * @return The frequency of MCGIRCLK. |
<> | 144:ef7eb2e8f9f7 | 1027 | */ |
<> | 144:ef7eb2e8f9f7 | 1028 | uint32_t CLOCK_GetInternalRefClkFreq(void); |
<> | 144:ef7eb2e8f9f7 | 1029 | |
<> | 144:ef7eb2e8f9f7 | 1030 | /*! |
<> | 144:ef7eb2e8f9f7 | 1031 | * @brief Get the MCG fixed frequency clock(MCGFFCLK) frequency. |
<> | 144:ef7eb2e8f9f7 | 1032 | * |
<> | 144:ef7eb2e8f9f7 | 1033 | * This function gets the MCG fixed frequency clock frequency (Hz) based |
<> | 144:ef7eb2e8f9f7 | 1034 | * on current MCG register value. |
<> | 144:ef7eb2e8f9f7 | 1035 | * |
<> | 144:ef7eb2e8f9f7 | 1036 | * @return The frequency of MCGFFCLK. |
<> | 144:ef7eb2e8f9f7 | 1037 | */ |
<> | 144:ef7eb2e8f9f7 | 1038 | uint32_t CLOCK_GetFixedFreqClkFreq(void); |
<> | 144:ef7eb2e8f9f7 | 1039 | |
<> | 144:ef7eb2e8f9f7 | 1040 | /*! |
<> | 144:ef7eb2e8f9f7 | 1041 | * @brief Get the MCG PLL0 clock(MCGPLL0CLK) frequency. |
<> | 144:ef7eb2e8f9f7 | 1042 | * |
<> | 144:ef7eb2e8f9f7 | 1043 | * This function gets the MCG PLL0 clock frequency (Hz) based on current MCG |
<> | 144:ef7eb2e8f9f7 | 1044 | * register value. |
<> | 144:ef7eb2e8f9f7 | 1045 | * |
<> | 144:ef7eb2e8f9f7 | 1046 | * @return The frequency of MCGPLL0CLK. |
<> | 144:ef7eb2e8f9f7 | 1047 | */ |
<> | 144:ef7eb2e8f9f7 | 1048 | uint32_t CLOCK_GetPll0Freq(void); |
<> | 144:ef7eb2e8f9f7 | 1049 | |
<> | 144:ef7eb2e8f9f7 | 1050 | /*! |
<> | 144:ef7eb2e8f9f7 | 1051 | * @brief Get the MCG external PLL frequency. |
<> | 144:ef7eb2e8f9f7 | 1052 | * |
<> | 144:ef7eb2e8f9f7 | 1053 | * This function gets the MCG external PLL frequency (Hz). |
<> | 144:ef7eb2e8f9f7 | 1054 | * |
<> | 144:ef7eb2e8f9f7 | 1055 | * @return The frequency of MCG external PLL. |
<> | 144:ef7eb2e8f9f7 | 1056 | */ |
<> | 144:ef7eb2e8f9f7 | 1057 | uint32_t CLOCK_GetExtPllFreq(void); |
<> | 144:ef7eb2e8f9f7 | 1058 | |
<> | 144:ef7eb2e8f9f7 | 1059 | /*! |
<> | 144:ef7eb2e8f9f7 | 1060 | * @brief Set the MCG external PLL frequency. |
<> | 144:ef7eb2e8f9f7 | 1061 | * |
<> | 144:ef7eb2e8f9f7 | 1062 | * This function sets the MCG external PLL frequency (Hz), the MCG external PLL |
<> | 144:ef7eb2e8f9f7 | 1063 | * frequency is passed in to MCG driver through this function. Please call this |
<> | 144:ef7eb2e8f9f7 | 1064 | * function after the external PLL frequency is changed, otherwise the APIs for |
<> | 144:ef7eb2e8f9f7 | 1065 | * get frequency may returns wrong value. |
<> | 144:ef7eb2e8f9f7 | 1066 | * |
<> | 144:ef7eb2e8f9f7 | 1067 | * @param The frequency of MCG external PLL. |
<> | 144:ef7eb2e8f9f7 | 1068 | */ |
<> | 144:ef7eb2e8f9f7 | 1069 | void CLOCK_SetExtPllFreq(uint32_t freq); |
<> | 144:ef7eb2e8f9f7 | 1070 | |
<> | 144:ef7eb2e8f9f7 | 1071 | /*@}*/ |
<> | 144:ef7eb2e8f9f7 | 1072 | |
<> | 144:ef7eb2e8f9f7 | 1073 | /*! @name MCG clock configuration. */ |
<> | 144:ef7eb2e8f9f7 | 1074 | /*@{*/ |
<> | 144:ef7eb2e8f9f7 | 1075 | |
<> | 144:ef7eb2e8f9f7 | 1076 | /*! |
<> | 144:ef7eb2e8f9f7 | 1077 | * @brief Enable or disable MCG low power. |
<> | 144:ef7eb2e8f9f7 | 1078 | * |
<> | 144:ef7eb2e8f9f7 | 1079 | * Enable MCG low power will disable the PLL and FLL in bypass modes. That is, |
<> | 144:ef7eb2e8f9f7 | 1080 | * in FBE and PBE modes, enable low power will set MCG to BLPE mode, in FBI and |
<> | 144:ef7eb2e8f9f7 | 1081 | * PBI mode, enable low power will set MCG to BLPI mode. |
<> | 144:ef7eb2e8f9f7 | 1082 | * When disable MCG low power, the PLL or FLL will be enabled based on MCG setting. |
<> | 144:ef7eb2e8f9f7 | 1083 | * |
<> | 144:ef7eb2e8f9f7 | 1084 | * @param enable True to enable MCG low power, false to disable MCG low power. |
<> | 144:ef7eb2e8f9f7 | 1085 | */ |
<> | 144:ef7eb2e8f9f7 | 1086 | static inline void CLOCK_SetLowPowerEnable(bool enable) |
<> | 144:ef7eb2e8f9f7 | 1087 | { |
<> | 144:ef7eb2e8f9f7 | 1088 | if (enable) |
<> | 144:ef7eb2e8f9f7 | 1089 | { |
<> | 144:ef7eb2e8f9f7 | 1090 | MCG->C2 |= MCG_C2_LP_MASK; |
<> | 144:ef7eb2e8f9f7 | 1091 | } |
<> | 144:ef7eb2e8f9f7 | 1092 | else |
<> | 144:ef7eb2e8f9f7 | 1093 | { |
<> | 144:ef7eb2e8f9f7 | 1094 | MCG->C2 &= ~MCG_C2_LP_MASK; |
<> | 144:ef7eb2e8f9f7 | 1095 | } |
<> | 144:ef7eb2e8f9f7 | 1096 | } |
<> | 144:ef7eb2e8f9f7 | 1097 | |
<> | 144:ef7eb2e8f9f7 | 1098 | /*! |
<> | 144:ef7eb2e8f9f7 | 1099 | * @brief Configure the Internal Reference clock (MCGIRCLK) |
<> | 144:ef7eb2e8f9f7 | 1100 | * |
<> | 144:ef7eb2e8f9f7 | 1101 | * This function setups the \c MCGIRCLK base on parameters. It selects the IRC |
<> | 144:ef7eb2e8f9f7 | 1102 | * source, if fast IRC is used, this function also sets the fast IRC divider. |
<> | 144:ef7eb2e8f9f7 | 1103 | * This function also sets whether enable \c MCGIRCLK in stop mode. |
<> | 144:ef7eb2e8f9f7 | 1104 | * Calling this function in FBI/PBI/BLPI modes may change the system clock, so |
<> | 144:ef7eb2e8f9f7 | 1105 | * it is not allowed to use this in these modes. |
<> | 144:ef7eb2e8f9f7 | 1106 | * |
<> | 144:ef7eb2e8f9f7 | 1107 | * @param enableMode MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode. |
<> | 144:ef7eb2e8f9f7 | 1108 | * @param ircs MCGIRCLK clock source, choose fast or slow. |
<> | 144:ef7eb2e8f9f7 | 1109 | * @param fcrdiv Fast IRC divider setting (\c FCRDIV). |
<> | 144:ef7eb2e8f9f7 | 1110 | * @retval kStatus_MCG_SourceUsed MCGIRCLK is used as system clock, should not configure MCGIRCLK. |
<> | 144:ef7eb2e8f9f7 | 1111 | * @retval kStatus_Success MCGIRCLK configuration finished successfully. |
<> | 144:ef7eb2e8f9f7 | 1112 | */ |
<> | 144:ef7eb2e8f9f7 | 1113 | status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv); |
<> | 144:ef7eb2e8f9f7 | 1114 | |
<> | 144:ef7eb2e8f9f7 | 1115 | /*! |
<> | 144:ef7eb2e8f9f7 | 1116 | * @brief Select the MCG external reference clock. |
<> | 144:ef7eb2e8f9f7 | 1117 | * |
<> | 144:ef7eb2e8f9f7 | 1118 | * Select the MCG external reference clock source, it changes the MCG_C7[OSCSEL] |
<> | 144:ef7eb2e8f9f7 | 1119 | * and wait for the clock source stable. Should not change external reference |
<> | 144:ef7eb2e8f9f7 | 1120 | * clock in FEE/FBE/BLPE/PBE/PEE mdes, so don't call this function in these modes. |
<> | 144:ef7eb2e8f9f7 | 1121 | * |
<> | 144:ef7eb2e8f9f7 | 1122 | * @param oscsel MCG external reference clock source, MCG_C7[OSCSEL]. |
<> | 144:ef7eb2e8f9f7 | 1123 | * @retval kStatus_MCG_SourceUsed External reference clock is used, should not change. |
<> | 144:ef7eb2e8f9f7 | 1124 | * @retval kStatus_Success External reference clock set successfully. |
<> | 144:ef7eb2e8f9f7 | 1125 | */ |
<> | 144:ef7eb2e8f9f7 | 1126 | status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel); |
<> | 144:ef7eb2e8f9f7 | 1127 | |
<> | 144:ef7eb2e8f9f7 | 1128 | /*! |
<> | 144:ef7eb2e8f9f7 | 1129 | * @brief Enables the PLL0 in FLL mode. |
<> | 144:ef7eb2e8f9f7 | 1130 | * |
<> | 144:ef7eb2e8f9f7 | 1131 | * This function setups the PLL0 in FLL mode, make sure the PLL reference |
<> | 144:ef7eb2e8f9f7 | 1132 | * clock is enabled before calling this function. This function reconfigures |
<> | 144:ef7eb2e8f9f7 | 1133 | * the PLL0, make sure the PLL0 is not used as a clock source while calling |
<> | 144:ef7eb2e8f9f7 | 1134 | * this function. The function CLOCK_CalcPllDiv can help to get the proper PLL |
<> | 144:ef7eb2e8f9f7 | 1135 | * divider values. |
<> | 144:ef7eb2e8f9f7 | 1136 | * |
<> | 144:ef7eb2e8f9f7 | 1137 | * @param config Pointer to the configuration structure. |
<> | 144:ef7eb2e8f9f7 | 1138 | */ |
<> | 144:ef7eb2e8f9f7 | 1139 | void CLOCK_EnablePll0(mcg_pll_config_t const *config); |
<> | 144:ef7eb2e8f9f7 | 1140 | |
<> | 144:ef7eb2e8f9f7 | 1141 | /*! |
<> | 144:ef7eb2e8f9f7 | 1142 | * @brief Disables the PLL0 in FLL mode. |
<> | 144:ef7eb2e8f9f7 | 1143 | * |
<> | 144:ef7eb2e8f9f7 | 1144 | * This function disables the PLL0 in FLL mode, it should be used together with |
<> | 144:ef7eb2e8f9f7 | 1145 | * @ref CLOCK_EnablePll0. |
<> | 144:ef7eb2e8f9f7 | 1146 | */ |
<> | 144:ef7eb2e8f9f7 | 1147 | static inline void CLOCK_DisablePll0(void) |
<> | 144:ef7eb2e8f9f7 | 1148 | { |
<> | 144:ef7eb2e8f9f7 | 1149 | MCG->C5 &= ~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK); |
<> | 144:ef7eb2e8f9f7 | 1150 | } |
<> | 144:ef7eb2e8f9f7 | 1151 | |
<> | 144:ef7eb2e8f9f7 | 1152 | /*! |
<> | 144:ef7eb2e8f9f7 | 1153 | * @brief Calculates the PLL divider setting for desired output frequency. |
<> | 144:ef7eb2e8f9f7 | 1154 | * |
<> | 144:ef7eb2e8f9f7 | 1155 | * This function calculates the proper reference clock divider (\c PRDIV) and |
<> | 144:ef7eb2e8f9f7 | 1156 | * VCO divider (\c VDIV) to generate desired PLL output frequency. It returns the |
<> | 144:ef7eb2e8f9f7 | 1157 | * closest frequency PLL could generate, the corresponding \c PRDIV/VDIV are |
<> | 144:ef7eb2e8f9f7 | 1158 | * returned from parameters. If desired frequency is not valid, this function |
<> | 144:ef7eb2e8f9f7 | 1159 | * returns 0. |
<> | 144:ef7eb2e8f9f7 | 1160 | * |
<> | 144:ef7eb2e8f9f7 | 1161 | * @param refFreq PLL reference clock frequency. |
<> | 144:ef7eb2e8f9f7 | 1162 | * @param desireFreq Desired PLL output frequency. |
<> | 144:ef7eb2e8f9f7 | 1163 | * @param prdiv PRDIV value to generate desired PLL frequency. |
<> | 144:ef7eb2e8f9f7 | 1164 | * @param vdiv VDIV value to generate desired PLL frequency. |
<> | 144:ef7eb2e8f9f7 | 1165 | * @return Closest frequency PLL could generate. |
<> | 144:ef7eb2e8f9f7 | 1166 | */ |
<> | 144:ef7eb2e8f9f7 | 1167 | uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv); |
<> | 144:ef7eb2e8f9f7 | 1168 | |
<> | 144:ef7eb2e8f9f7 | 1169 | /*@}*/ |
<> | 144:ef7eb2e8f9f7 | 1170 | |
<> | 144:ef7eb2e8f9f7 | 1171 | /*! @name MCG clock lock monitor functions. */ |
<> | 144:ef7eb2e8f9f7 | 1172 | /*@{*/ |
<> | 144:ef7eb2e8f9f7 | 1173 | |
<> | 144:ef7eb2e8f9f7 | 1174 | /*! |
<> | 144:ef7eb2e8f9f7 | 1175 | * @brief Set the OSC0 clock monitor mode. |
<> | 144:ef7eb2e8f9f7 | 1176 | * |
<> | 144:ef7eb2e8f9f7 | 1177 | * Set the OSC0 clock monitor mode, see @ref mcg_monitor_mode_t for details. |
<> | 144:ef7eb2e8f9f7 | 1178 | * |
<> | 144:ef7eb2e8f9f7 | 1179 | * @param mode The monitor mode to set. |
<> | 144:ef7eb2e8f9f7 | 1180 | */ |
<> | 144:ef7eb2e8f9f7 | 1181 | void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode); |
<> | 144:ef7eb2e8f9f7 | 1182 | |
<> | 144:ef7eb2e8f9f7 | 1183 | /*! |
<> | 144:ef7eb2e8f9f7 | 1184 | * @brief Set the RTC OSC clock monitor mode. |
<> | 144:ef7eb2e8f9f7 | 1185 | * |
<> | 144:ef7eb2e8f9f7 | 1186 | * Set the RTC OSC clock monitor mode, see @ref mcg_monitor_mode_t for details. |
<> | 144:ef7eb2e8f9f7 | 1187 | * |
<> | 144:ef7eb2e8f9f7 | 1188 | * @param mode The monitor mode to set. |
<> | 144:ef7eb2e8f9f7 | 1189 | */ |
<> | 144:ef7eb2e8f9f7 | 1190 | void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode); |
<> | 144:ef7eb2e8f9f7 | 1191 | |
<> | 144:ef7eb2e8f9f7 | 1192 | /*! |
<> | 144:ef7eb2e8f9f7 | 1193 | * @brief Set the PLL0 clock monitor mode. |
<> | 144:ef7eb2e8f9f7 | 1194 | * |
<> | 144:ef7eb2e8f9f7 | 1195 | * Set the PLL0 clock monitor mode, see @ref mcg_monitor_mode_t for details. |
<> | 144:ef7eb2e8f9f7 | 1196 | * |
<> | 144:ef7eb2e8f9f7 | 1197 | * @param mode The monitor mode to set. |
<> | 144:ef7eb2e8f9f7 | 1198 | */ |
<> | 144:ef7eb2e8f9f7 | 1199 | void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode); |
<> | 144:ef7eb2e8f9f7 | 1200 | |
<> | 144:ef7eb2e8f9f7 | 1201 | /*! |
<> | 144:ef7eb2e8f9f7 | 1202 | * @brief Set the external PLL clock monitor mode. |
<> | 144:ef7eb2e8f9f7 | 1203 | * |
<> | 144:ef7eb2e8f9f7 | 1204 | * Set the external PLL clock monitor mode, see @ref mcg_monitor_mode_t |
<> | 144:ef7eb2e8f9f7 | 1205 | * for details. |
<> | 144:ef7eb2e8f9f7 | 1206 | * |
<> | 144:ef7eb2e8f9f7 | 1207 | * @param mode The monitor mode to set. |
<> | 144:ef7eb2e8f9f7 | 1208 | */ |
<> | 144:ef7eb2e8f9f7 | 1209 | void CLOCK_SetExtPllMonitorMode(mcg_monitor_mode_t mode); |
<> | 144:ef7eb2e8f9f7 | 1210 | |
<> | 144:ef7eb2e8f9f7 | 1211 | /*! |
<> | 144:ef7eb2e8f9f7 | 1212 | * @brief Get the MCG status flags. |
<> | 144:ef7eb2e8f9f7 | 1213 | * |
<> | 144:ef7eb2e8f9f7 | 1214 | * This function gets the MCG clock status flags, all the status flags are |
<> | 144:ef7eb2e8f9f7 | 1215 | * returned as a logical OR of the enumeration @ref _mcg_status_flags_t. To |
<> | 144:ef7eb2e8f9f7 | 1216 | * check specific flags, compare the return value with the flags. |
<> | 144:ef7eb2e8f9f7 | 1217 | * |
<> | 144:ef7eb2e8f9f7 | 1218 | * Example: |
<> | 144:ef7eb2e8f9f7 | 1219 | * @code |
<> | 144:ef7eb2e8f9f7 | 1220 | // To check the clock lost lock status of OSC0 and PLL0. |
<> | 144:ef7eb2e8f9f7 | 1221 | uint32_t mcgFlags; |
<> | 144:ef7eb2e8f9f7 | 1222 | |
<> | 144:ef7eb2e8f9f7 | 1223 | mcgFlags = CLOCK_GetStatusFlags(); |
<> | 144:ef7eb2e8f9f7 | 1224 | |
<> | 144:ef7eb2e8f9f7 | 1225 | if (mcgFlags & kMCG_Osc0LostFlag) |
<> | 144:ef7eb2e8f9f7 | 1226 | { |
<> | 144:ef7eb2e8f9f7 | 1227 | // OSC0 clock lock lost. Do something. |
<> | 144:ef7eb2e8f9f7 | 1228 | } |
<> | 144:ef7eb2e8f9f7 | 1229 | if (mcgFlags & kMCG_Pll0LostFlag) |
<> | 144:ef7eb2e8f9f7 | 1230 | { |
<> | 144:ef7eb2e8f9f7 | 1231 | // PLL0 clock lock lost. Do something. |
<> | 144:ef7eb2e8f9f7 | 1232 | } |
<> | 144:ef7eb2e8f9f7 | 1233 | @endcode |
<> | 144:ef7eb2e8f9f7 | 1234 | * |
<> | 144:ef7eb2e8f9f7 | 1235 | * @return Logical OR value of the @ref _mcg_status_flags_t. |
<> | 144:ef7eb2e8f9f7 | 1236 | */ |
<> | 144:ef7eb2e8f9f7 | 1237 | uint32_t CLOCK_GetStatusFlags(void); |
<> | 144:ef7eb2e8f9f7 | 1238 | |
<> | 144:ef7eb2e8f9f7 | 1239 | /*! |
<> | 144:ef7eb2e8f9f7 | 1240 | * @brief Clears the MCG status flags. |
<> | 144:ef7eb2e8f9f7 | 1241 | * |
<> | 144:ef7eb2e8f9f7 | 1242 | * This function clears the MCG clock lock lost status. The parameter is logical |
<> | 144:ef7eb2e8f9f7 | 1243 | * OR value of the flags to clear, see @ref _mcg_status_flags_t. |
<> | 144:ef7eb2e8f9f7 | 1244 | * |
<> | 144:ef7eb2e8f9f7 | 1245 | * Example: |
<> | 144:ef7eb2e8f9f7 | 1246 | * @code |
<> | 144:ef7eb2e8f9f7 | 1247 | // To clear the clock lost lock status flags of OSC0 and PLL0. |
<> | 144:ef7eb2e8f9f7 | 1248 | |
<> | 144:ef7eb2e8f9f7 | 1249 | CLOCK_ClearStatusFlags(kMCG_Osc0LostFlag | kMCG_Pll0LostFlag); |
<> | 144:ef7eb2e8f9f7 | 1250 | @endcode |
<> | 144:ef7eb2e8f9f7 | 1251 | * |
<> | 144:ef7eb2e8f9f7 | 1252 | * @param mask The status flags to clear. This is a logical OR of members of the |
<> | 144:ef7eb2e8f9f7 | 1253 | * enumeration @ref _mcg_status_flags_t. |
<> | 144:ef7eb2e8f9f7 | 1254 | */ |
<> | 144:ef7eb2e8f9f7 | 1255 | void CLOCK_ClearStatusFlags(uint32_t mask); |
<> | 144:ef7eb2e8f9f7 | 1256 | |
<> | 144:ef7eb2e8f9f7 | 1257 | /*@}*/ |
<> | 144:ef7eb2e8f9f7 | 1258 | |
<> | 144:ef7eb2e8f9f7 | 1259 | /*! |
<> | 144:ef7eb2e8f9f7 | 1260 | * @name OSC configuration |
<> | 144:ef7eb2e8f9f7 | 1261 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1262 | */ |
<> | 144:ef7eb2e8f9f7 | 1263 | |
<> | 144:ef7eb2e8f9f7 | 1264 | /*! |
<> | 144:ef7eb2e8f9f7 | 1265 | * @brief Configures the OSC external reference clock (OSCERCLK). |
<> | 144:ef7eb2e8f9f7 | 1266 | * |
<> | 144:ef7eb2e8f9f7 | 1267 | * This function configures the OSC external reference clock (OSCERCLK). |
<> | 144:ef7eb2e8f9f7 | 1268 | * For example, to enable the OSCERCLK in normal mode and stop mode, and also set |
<> | 144:ef7eb2e8f9f7 | 1269 | * the output divider to 1, as follows: |
<> | 144:ef7eb2e8f9f7 | 1270 | * |
<> | 144:ef7eb2e8f9f7 | 1271 | @code |
<> | 144:ef7eb2e8f9f7 | 1272 | oscer_config_t config = |
<> | 144:ef7eb2e8f9f7 | 1273 | { |
<> | 144:ef7eb2e8f9f7 | 1274 | .enableMode = kOSC_ErClkEnable | kOSC_ErClkEnableInStop, |
<> | 144:ef7eb2e8f9f7 | 1275 | .erclkDiv = 1U, |
<> | 144:ef7eb2e8f9f7 | 1276 | }; |
<> | 144:ef7eb2e8f9f7 | 1277 | |
<> | 144:ef7eb2e8f9f7 | 1278 | OSC_SetExtRefClkConfig(OSC, &config); |
<> | 144:ef7eb2e8f9f7 | 1279 | @endcode |
<> | 144:ef7eb2e8f9f7 | 1280 | * |
<> | 144:ef7eb2e8f9f7 | 1281 | * @param base OSC peripheral address. |
<> | 144:ef7eb2e8f9f7 | 1282 | * @param config Pointer to the configuration structure. |
<> | 144:ef7eb2e8f9f7 | 1283 | */ |
<> | 144:ef7eb2e8f9f7 | 1284 | static inline void OSC_SetExtRefClkConfig(OSC_Type *base, oscer_config_t const *config) |
<> | 144:ef7eb2e8f9f7 | 1285 | { |
<> | 144:ef7eb2e8f9f7 | 1286 | uint8_t reg = base->CR; |
<> | 144:ef7eb2e8f9f7 | 1287 | |
<> | 144:ef7eb2e8f9f7 | 1288 | reg &= ~(OSC_CR_ERCLKEN_MASK | OSC_CR_EREFSTEN_MASK); |
<> | 144:ef7eb2e8f9f7 | 1289 | reg |= config->enableMode; |
<> | 144:ef7eb2e8f9f7 | 1290 | |
<> | 144:ef7eb2e8f9f7 | 1291 | base->CR = reg; |
<> | 144:ef7eb2e8f9f7 | 1292 | |
<> | 144:ef7eb2e8f9f7 | 1293 | base->DIV = OSC_DIV_ERPS(config->erclkDiv); |
<> | 144:ef7eb2e8f9f7 | 1294 | } |
<> | 144:ef7eb2e8f9f7 | 1295 | |
<> | 144:ef7eb2e8f9f7 | 1296 | /*! |
<> | 144:ef7eb2e8f9f7 | 1297 | * @brief Sets the capacitor load configuration for the oscillator. |
<> | 144:ef7eb2e8f9f7 | 1298 | * |
<> | 144:ef7eb2e8f9f7 | 1299 | * This function sets the specified capacitors configuration for the oscillator. |
<> | 144:ef7eb2e8f9f7 | 1300 | * This should be done in the early system level initialization function call |
<> | 144:ef7eb2e8f9f7 | 1301 | * based on the system configuration. |
<> | 144:ef7eb2e8f9f7 | 1302 | * |
<> | 144:ef7eb2e8f9f7 | 1303 | * @param base OSC peripheral address. |
<> | 144:ef7eb2e8f9f7 | 1304 | * @param capLoad OR'ed value for the capacitor load option, see \ref _osc_cap_load. |
<> | 144:ef7eb2e8f9f7 | 1305 | * |
<> | 144:ef7eb2e8f9f7 | 1306 | * Example: |
<> | 144:ef7eb2e8f9f7 | 1307 | @code |
<> | 144:ef7eb2e8f9f7 | 1308 | // To enable only 2 pF and 8 pF capacitor load, please use like this. |
<> | 144:ef7eb2e8f9f7 | 1309 | OSC_SetCapLoad(OSC, kOSC_Cap2P | kOSC_Cap8P); |
<> | 144:ef7eb2e8f9f7 | 1310 | @endcode |
<> | 144:ef7eb2e8f9f7 | 1311 | */ |
<> | 144:ef7eb2e8f9f7 | 1312 | static inline void OSC_SetCapLoad(OSC_Type *base, uint8_t capLoad) |
<> | 144:ef7eb2e8f9f7 | 1313 | { |
<> | 144:ef7eb2e8f9f7 | 1314 | uint8_t reg = base->CR; |
<> | 144:ef7eb2e8f9f7 | 1315 | |
<> | 144:ef7eb2e8f9f7 | 1316 | reg &= ~(OSC_CR_SC2P_MASK | OSC_CR_SC4P_MASK | OSC_CR_SC8P_MASK | OSC_CR_SC16P_MASK); |
<> | 144:ef7eb2e8f9f7 | 1317 | reg |= capLoad; |
<> | 144:ef7eb2e8f9f7 | 1318 | |
<> | 144:ef7eb2e8f9f7 | 1319 | base->CR = reg; |
<> | 144:ef7eb2e8f9f7 | 1320 | } |
<> | 144:ef7eb2e8f9f7 | 1321 | |
<> | 144:ef7eb2e8f9f7 | 1322 | /*! |
<> | 144:ef7eb2e8f9f7 | 1323 | * @brief Initialize OSC0. |
<> | 144:ef7eb2e8f9f7 | 1324 | * |
<> | 144:ef7eb2e8f9f7 | 1325 | * This function initializes OSC0 according to board configuration. |
<> | 144:ef7eb2e8f9f7 | 1326 | * |
<> | 144:ef7eb2e8f9f7 | 1327 | * @param config Pointer to the OSC0 configuration structure. |
<> | 144:ef7eb2e8f9f7 | 1328 | */ |
<> | 144:ef7eb2e8f9f7 | 1329 | void CLOCK_InitOsc0(osc_config_t const *config); |
<> | 144:ef7eb2e8f9f7 | 1330 | |
<> | 144:ef7eb2e8f9f7 | 1331 | /*! |
<> | 144:ef7eb2e8f9f7 | 1332 | * @brief Deinitialize OSC0. |
<> | 144:ef7eb2e8f9f7 | 1333 | * |
<> | 144:ef7eb2e8f9f7 | 1334 | * This function deinitializes OSC0. |
<> | 144:ef7eb2e8f9f7 | 1335 | */ |
<> | 144:ef7eb2e8f9f7 | 1336 | void CLOCK_DeinitOsc0(void); |
<> | 144:ef7eb2e8f9f7 | 1337 | |
<> | 144:ef7eb2e8f9f7 | 1338 | /* @} */ |
<> | 144:ef7eb2e8f9f7 | 1339 | |
<> | 144:ef7eb2e8f9f7 | 1340 | /*! |
<> | 144:ef7eb2e8f9f7 | 1341 | * @name MCG auto-trim machine. |
<> | 144:ef7eb2e8f9f7 | 1342 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1343 | */ |
<> | 144:ef7eb2e8f9f7 | 1344 | |
<> | 144:ef7eb2e8f9f7 | 1345 | /*! |
<> | 144:ef7eb2e8f9f7 | 1346 | * @brief Auto trim the internal reference clock. |
<> | 144:ef7eb2e8f9f7 | 1347 | * |
<> | 144:ef7eb2e8f9f7 | 1348 | * This function trims the internal reference clock using external clock. If |
<> | 144:ef7eb2e8f9f7 | 1349 | * successful, it returns the kStatus_Success and the frequency after |
<> | 144:ef7eb2e8f9f7 | 1350 | * trimming is received in the parameter @p actualFreq. If an error occurs, |
<> | 144:ef7eb2e8f9f7 | 1351 | * the error code is returned. |
<> | 144:ef7eb2e8f9f7 | 1352 | * |
<> | 144:ef7eb2e8f9f7 | 1353 | * @param extFreq External clock frequency, should be bus clock. |
<> | 144:ef7eb2e8f9f7 | 1354 | * @param desireFreq Frequency want to trim to. |
<> | 144:ef7eb2e8f9f7 | 1355 | * @param actualFreq Actual frequency after trim. |
<> | 144:ef7eb2e8f9f7 | 1356 | * @param atms Trim fast or slow internal reference clock. |
<> | 144:ef7eb2e8f9f7 | 1357 | * @retval kStatus_Success ATM success. |
<> | 144:ef7eb2e8f9f7 | 1358 | * @retval kStatus_MCG_AtmBusClockInvalid The bus clock is not in allowed range for ATM. |
<> | 144:ef7eb2e8f9f7 | 1359 | * @retval kStatus_MCG_AtmDesiredFreqInvalid MCGIRCLK could not be trimmed to the desired frequency. |
<> | 144:ef7eb2e8f9f7 | 1360 | * @retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as bus clock source. |
<> | 144:ef7eb2e8f9f7 | 1361 | * @retval kStatus_MCG_AtmHardwareFail Hardware fails during trim. |
<> | 144:ef7eb2e8f9f7 | 1362 | */ |
<> | 144:ef7eb2e8f9f7 | 1363 | status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms); |
<> | 144:ef7eb2e8f9f7 | 1364 | /* @} */ |
<> | 144:ef7eb2e8f9f7 | 1365 | |
<> | 144:ef7eb2e8f9f7 | 1366 | /*! @name MCG mode functions. */ |
<> | 144:ef7eb2e8f9f7 | 1367 | /*@{*/ |
<> | 144:ef7eb2e8f9f7 | 1368 | |
<> | 144:ef7eb2e8f9f7 | 1369 | /*! |
<> | 144:ef7eb2e8f9f7 | 1370 | * @brief Gets the current MCG mode. |
<> | 144:ef7eb2e8f9f7 | 1371 | * |
<> | 144:ef7eb2e8f9f7 | 1372 | * This function checks the MCG registers and determine current MCG mode. |
<> | 144:ef7eb2e8f9f7 | 1373 | * |
<> | 144:ef7eb2e8f9f7 | 1374 | * @return Current MCG mode or error code, see @ref mcg_mode_t. |
<> | 144:ef7eb2e8f9f7 | 1375 | */ |
<> | 144:ef7eb2e8f9f7 | 1376 | mcg_mode_t CLOCK_GetMode(void); |
<> | 144:ef7eb2e8f9f7 | 1377 | |
<> | 144:ef7eb2e8f9f7 | 1378 | /*! |
<> | 144:ef7eb2e8f9f7 | 1379 | * @brief Set MCG to FEI mode. |
<> | 144:ef7eb2e8f9f7 | 1380 | * |
<> | 144:ef7eb2e8f9f7 | 1381 | * This function sets MCG to FEI mode. If could not set to FEI mode directly |
<> | 144:ef7eb2e8f9f7 | 1382 | * from current mode, this function returns error. @ref kMCG_Dmx32Default is used in this |
<> | 144:ef7eb2e8f9f7 | 1383 | * mode because using kMCG_Dmx32Fine with internal reference clock source |
<> | 144:ef7eb2e8f9f7 | 1384 | * might damage hardware. |
<> | 144:ef7eb2e8f9f7 | 1385 | * |
<> | 144:ef7eb2e8f9f7 | 1386 | * @param drs The DCO range selection. |
<> | 144:ef7eb2e8f9f7 | 1387 | * @param fllStableDelay Delay function to make sure FLL is stable, if pass |
<> | 144:ef7eb2e8f9f7 | 1388 | * in NULL, then does not delay. |
<> | 144:ef7eb2e8f9f7 | 1389 | * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. |
<> | 144:ef7eb2e8f9f7 | 1390 | * @retval kStatus_Success Switch to target mode successfully. |
<> | 144:ef7eb2e8f9f7 | 1391 | */ |
<> | 144:ef7eb2e8f9f7 | 1392 | status_t CLOCK_SetFeiMode(mcg_drs_t drs, void (*fllStableDelay)(void)); |
<> | 144:ef7eb2e8f9f7 | 1393 | |
<> | 144:ef7eb2e8f9f7 | 1394 | /*! |
<> | 144:ef7eb2e8f9f7 | 1395 | * @brief Set MCG to FEE mode. |
<> | 144:ef7eb2e8f9f7 | 1396 | * |
<> | 144:ef7eb2e8f9f7 | 1397 | * This function sets MCG to FEE mode. If could not set to FEE mode directly |
<> | 144:ef7eb2e8f9f7 | 1398 | * from current mode, this function returns error. |
<> | 144:ef7eb2e8f9f7 | 1399 | * |
<> | 144:ef7eb2e8f9f7 | 1400 | * @param frdiv FLL reference clock divider setting, FRDIV. |
<> | 144:ef7eb2e8f9f7 | 1401 | * @param dmx32 DMX32 in FEE mode. |
<> | 144:ef7eb2e8f9f7 | 1402 | * @param drs The DCO range selection. |
<> | 144:ef7eb2e8f9f7 | 1403 | * @param fllStableDelay Delay function to make sure FLL is stable, if pass |
<> | 144:ef7eb2e8f9f7 | 1404 | * in NULL, then does not delay. |
<> | 144:ef7eb2e8f9f7 | 1405 | * |
<> | 144:ef7eb2e8f9f7 | 1406 | * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. |
<> | 144:ef7eb2e8f9f7 | 1407 | * @retval kStatus_Success Switch to target mode successfully. |
<> | 144:ef7eb2e8f9f7 | 1408 | */ |
<> | 144:ef7eb2e8f9f7 | 1409 | status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)); |
<> | 144:ef7eb2e8f9f7 | 1410 | |
<> | 144:ef7eb2e8f9f7 | 1411 | /*! |
<> | 144:ef7eb2e8f9f7 | 1412 | * @brief Set MCG to FBI mode. |
<> | 144:ef7eb2e8f9f7 | 1413 | * |
<> | 144:ef7eb2e8f9f7 | 1414 | * This function sets MCG to FBI mode. If could not set to FBI mode directly |
<> | 144:ef7eb2e8f9f7 | 1415 | * from current mode, this function returns error. |
<> | 144:ef7eb2e8f9f7 | 1416 | * |
<> | 144:ef7eb2e8f9f7 | 1417 | * @param drs The DCO range selection. |
<> | 144:ef7eb2e8f9f7 | 1418 | * @param fllStableDelay Delay function to make sure FLL is stable. If FLL |
<> | 144:ef7eb2e8f9f7 | 1419 | * is not used in FBI mode, this parameter could be NULL. Pass in |
<> | 144:ef7eb2e8f9f7 | 1420 | * NULL does not delay. |
<> | 144:ef7eb2e8f9f7 | 1421 | * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. |
<> | 144:ef7eb2e8f9f7 | 1422 | * @retval kStatus_Success Switch to target mode successfully. |
<> | 144:ef7eb2e8f9f7 | 1423 | */ |
<> | 144:ef7eb2e8f9f7 | 1424 | status_t CLOCK_SetFbiMode(mcg_drs_t drs, void (*fllStableDelay)(void)); |
<> | 144:ef7eb2e8f9f7 | 1425 | |
<> | 144:ef7eb2e8f9f7 | 1426 | /*! |
<> | 144:ef7eb2e8f9f7 | 1427 | * @brief Set MCG to FBE mode. |
<> | 144:ef7eb2e8f9f7 | 1428 | * |
<> | 144:ef7eb2e8f9f7 | 1429 | * This function sets MCG to FBE mode. If could not set to FBE mode directly |
<> | 144:ef7eb2e8f9f7 | 1430 | * from current mode, this function returns error. |
<> | 144:ef7eb2e8f9f7 | 1431 | * |
<> | 144:ef7eb2e8f9f7 | 1432 | * @param frdiv FLL reference clock divider setting, FRDIV. |
<> | 144:ef7eb2e8f9f7 | 1433 | * @param dmx32 DMX32 in FBE mode. |
<> | 144:ef7eb2e8f9f7 | 1434 | * @param drs The DCO range selection. |
<> | 144:ef7eb2e8f9f7 | 1435 | * @param fllStableDelay Delay function to make sure FLL is stable. If FLL |
<> | 144:ef7eb2e8f9f7 | 1436 | * is not used in FBE mode, this parameter could be NULL. Pass in NULL |
<> | 144:ef7eb2e8f9f7 | 1437 | * does not delay. |
<> | 144:ef7eb2e8f9f7 | 1438 | * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. |
<> | 144:ef7eb2e8f9f7 | 1439 | * @retval kStatus_Success Switch to target mode successfully. |
<> | 144:ef7eb2e8f9f7 | 1440 | */ |
<> | 144:ef7eb2e8f9f7 | 1441 | status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)); |
<> | 144:ef7eb2e8f9f7 | 1442 | |
<> | 144:ef7eb2e8f9f7 | 1443 | /*! |
<> | 144:ef7eb2e8f9f7 | 1444 | * @brief Set MCG to BLPI mode. |
<> | 144:ef7eb2e8f9f7 | 1445 | * |
<> | 144:ef7eb2e8f9f7 | 1446 | * This function sets MCG to BLPI mode. If could not set to BLPI mode directly |
<> | 144:ef7eb2e8f9f7 | 1447 | * from current mode, this function returns error. |
<> | 144:ef7eb2e8f9f7 | 1448 | * |
<> | 144:ef7eb2e8f9f7 | 1449 | * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. |
<> | 144:ef7eb2e8f9f7 | 1450 | * @retval kStatus_Success Switch to target mode successfully. |
<> | 144:ef7eb2e8f9f7 | 1451 | */ |
<> | 144:ef7eb2e8f9f7 | 1452 | status_t CLOCK_SetBlpiMode(void); |
<> | 144:ef7eb2e8f9f7 | 1453 | |
<> | 144:ef7eb2e8f9f7 | 1454 | /*! |
<> | 144:ef7eb2e8f9f7 | 1455 | * @brief Set MCG to BLPE mode. |
<> | 144:ef7eb2e8f9f7 | 1456 | * |
<> | 144:ef7eb2e8f9f7 | 1457 | * This function sets MCG to BLPE mode. If could not set to BLPE mode directly |
<> | 144:ef7eb2e8f9f7 | 1458 | * from current mode, this function returns error. |
<> | 144:ef7eb2e8f9f7 | 1459 | * |
<> | 144:ef7eb2e8f9f7 | 1460 | * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. |
<> | 144:ef7eb2e8f9f7 | 1461 | * @retval kStatus_Success Switch to target mode successfully. |
<> | 144:ef7eb2e8f9f7 | 1462 | */ |
<> | 144:ef7eb2e8f9f7 | 1463 | status_t CLOCK_SetBlpeMode(void); |
<> | 144:ef7eb2e8f9f7 | 1464 | |
<> | 144:ef7eb2e8f9f7 | 1465 | /*! |
<> | 144:ef7eb2e8f9f7 | 1466 | * @brief Set MCG to PBE mode. |
<> | 144:ef7eb2e8f9f7 | 1467 | * |
<> | 144:ef7eb2e8f9f7 | 1468 | * This function sets MCG to PBE mode. If could not set to PBE mode directly |
<> | 144:ef7eb2e8f9f7 | 1469 | * from current mode, this function returns error. |
<> | 144:ef7eb2e8f9f7 | 1470 | * |
<> | 144:ef7eb2e8f9f7 | 1471 | * @param pllcs The PLL selection, PLLCS. |
<> | 144:ef7eb2e8f9f7 | 1472 | * @param config Pointer to the PLL configuration. |
<> | 144:ef7eb2e8f9f7 | 1473 | * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. |
<> | 144:ef7eb2e8f9f7 | 1474 | * @retval kStatus_Success Switch to target mode successfully. |
<> | 144:ef7eb2e8f9f7 | 1475 | * |
<> | 144:ef7eb2e8f9f7 | 1476 | * @note |
<> | 144:ef7eb2e8f9f7 | 1477 | * 1. The parameter \c pllcs selects the PLL, for some platforms, there is |
<> | 144:ef7eb2e8f9f7 | 1478 | * only one PLL, the parameter pllcs is kept for interface compatible. |
<> | 144:ef7eb2e8f9f7 | 1479 | * 2. The parameter \c config is the PLL configuration structure, on some |
<> | 144:ef7eb2e8f9f7 | 1480 | * platforms, could choose the external PLL directly. This means that the |
<> | 144:ef7eb2e8f9f7 | 1481 | * configuration structure is not necessary, pass in NULL for this case. |
<> | 144:ef7eb2e8f9f7 | 1482 | * For example: CLOCK_SetPbeMode(kMCG_OscselOsc, kMCG_PllClkSelExtPll, NULL); |
<> | 144:ef7eb2e8f9f7 | 1483 | */ |
<> | 144:ef7eb2e8f9f7 | 1484 | status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config); |
<> | 144:ef7eb2e8f9f7 | 1485 | |
<> | 144:ef7eb2e8f9f7 | 1486 | /*! |
<> | 144:ef7eb2e8f9f7 | 1487 | * @brief Set MCG to PEE mode. |
<> | 144:ef7eb2e8f9f7 | 1488 | * |
<> | 144:ef7eb2e8f9f7 | 1489 | * This function sets MCG to PEE mode. |
<> | 144:ef7eb2e8f9f7 | 1490 | * |
<> | 144:ef7eb2e8f9f7 | 1491 | * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. |
<> | 144:ef7eb2e8f9f7 | 1492 | * @retval kStatus_Success Switch to target mode successfully. |
<> | 144:ef7eb2e8f9f7 | 1493 | * |
<> | 144:ef7eb2e8f9f7 | 1494 | * @note This function only change CLKS to use PLL/FLL output. If the |
<> | 144:ef7eb2e8f9f7 | 1495 | * PRDIV/VDIV are different from PBE mode, please setup these |
<> | 144:ef7eb2e8f9f7 | 1496 | * settings in PBE mode and wait for stable then switch to PEE mode. |
<> | 144:ef7eb2e8f9f7 | 1497 | */ |
<> | 144:ef7eb2e8f9f7 | 1498 | status_t CLOCK_SetPeeMode(void); |
<> | 144:ef7eb2e8f9f7 | 1499 | |
<> | 144:ef7eb2e8f9f7 | 1500 | /*! |
<> | 144:ef7eb2e8f9f7 | 1501 | * @brief Switch MCG to FBE mode quickly from external mode. |
<> | 144:ef7eb2e8f9f7 | 1502 | * |
<> | 144:ef7eb2e8f9f7 | 1503 | * This function changes MCG from external modes (PEE/PBE/BLPE/FEE) to FBE mode quickly. |
<> | 144:ef7eb2e8f9f7 | 1504 | * It only changes to use external clock as the system clock souce and disable PLL, but does not |
<> | 144:ef7eb2e8f9f7 | 1505 | * configure FLL settings. This is a lite function with small code size, it is useful |
<> | 144:ef7eb2e8f9f7 | 1506 | * during mode switch. For example, to switch from PEE mode to FEI mode: |
<> | 144:ef7eb2e8f9f7 | 1507 | * |
<> | 144:ef7eb2e8f9f7 | 1508 | * @code |
<> | 144:ef7eb2e8f9f7 | 1509 | * CLOCK_ExternalModeToFbeModeQuick(); |
<> | 144:ef7eb2e8f9f7 | 1510 | * CLOCK_SetFeiMode(...); |
<> | 144:ef7eb2e8f9f7 | 1511 | * @endcode |
<> | 144:ef7eb2e8f9f7 | 1512 | * |
<> | 144:ef7eb2e8f9f7 | 1513 | * @retval kStatus_Success Change successfully. |
<> | 144:ef7eb2e8f9f7 | 1514 | * @retval kStatus_MCG_ModeInvalid Current mode is not external modes, should not call this function. |
<> | 144:ef7eb2e8f9f7 | 1515 | */ |
<> | 144:ef7eb2e8f9f7 | 1516 | status_t CLOCK_ExternalModeToFbeModeQuick(void); |
<> | 144:ef7eb2e8f9f7 | 1517 | |
<> | 144:ef7eb2e8f9f7 | 1518 | /*! |
<> | 144:ef7eb2e8f9f7 | 1519 | * @brief Switch MCG to FBI mode quickly from internal modes. |
<> | 144:ef7eb2e8f9f7 | 1520 | * |
<> | 144:ef7eb2e8f9f7 | 1521 | * This function changes MCG from internal modes (PEI/PBI/BLPI/FEI) to FBI mode quickly. |
<> | 144:ef7eb2e8f9f7 | 1522 | * It only changes to use MCGIRCLK as the system clock souce and disable PLL, but does not |
<> | 144:ef7eb2e8f9f7 | 1523 | * configure FLL settings. This is a lite function with small code size, it is useful |
<> | 144:ef7eb2e8f9f7 | 1524 | * during mode switch. For example, to switch from PEI mode to FEE mode: |
<> | 144:ef7eb2e8f9f7 | 1525 | * |
<> | 144:ef7eb2e8f9f7 | 1526 | * @code |
<> | 144:ef7eb2e8f9f7 | 1527 | * CLOCK_InternalModeToFbiModeQuick(); |
<> | 144:ef7eb2e8f9f7 | 1528 | * CLOCK_SetFeeMode(...); |
<> | 144:ef7eb2e8f9f7 | 1529 | * @endcode |
<> | 144:ef7eb2e8f9f7 | 1530 | * |
<> | 144:ef7eb2e8f9f7 | 1531 | * @retval kStatus_Success Change successfully. |
<> | 144:ef7eb2e8f9f7 | 1532 | * @retval kStatus_MCG_ModeInvalid Current mode is not internal mode, should not call this function. |
<> | 144:ef7eb2e8f9f7 | 1533 | */ |
<> | 144:ef7eb2e8f9f7 | 1534 | status_t CLOCK_InternalModeToFbiModeQuick(void); |
<> | 144:ef7eb2e8f9f7 | 1535 | |
<> | 144:ef7eb2e8f9f7 | 1536 | /*! |
<> | 144:ef7eb2e8f9f7 | 1537 | * @brief Set MCG to FEI mode during system boot up. |
<> | 144:ef7eb2e8f9f7 | 1538 | * |
<> | 144:ef7eb2e8f9f7 | 1539 | * This function sets MCG to FEI mode from reset mode, it could be used to |
<> | 144:ef7eb2e8f9f7 | 1540 | * set up MCG during system boot up. @ref kMCG_Dmx32Default is used in this |
<> | 144:ef7eb2e8f9f7 | 1541 | * mode because using kMCG_Dmx32Fine with internal reference clock source |
<> | 144:ef7eb2e8f9f7 | 1542 | * might damage hardware. |
<> | 144:ef7eb2e8f9f7 | 1543 | * |
<> | 144:ef7eb2e8f9f7 | 1544 | * @param drs The DCO range selection. |
<> | 144:ef7eb2e8f9f7 | 1545 | * @param fllStableDelay Delay function to make sure FLL is stable. |
<> | 144:ef7eb2e8f9f7 | 1546 | * |
<> | 144:ef7eb2e8f9f7 | 1547 | * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. |
<> | 144:ef7eb2e8f9f7 | 1548 | * @retval kStatus_Success Switch to target mode successfully. |
<> | 144:ef7eb2e8f9f7 | 1549 | */ |
<> | 144:ef7eb2e8f9f7 | 1550 | status_t CLOCK_BootToFeiMode(mcg_drs_t drs, void (*fllStableDelay)(void)); |
<> | 144:ef7eb2e8f9f7 | 1551 | |
<> | 144:ef7eb2e8f9f7 | 1552 | /*! |
<> | 144:ef7eb2e8f9f7 | 1553 | * @brief Set MCG to FEE mode during system bootup. |
<> | 144:ef7eb2e8f9f7 | 1554 | * |
<> | 144:ef7eb2e8f9f7 | 1555 | * This function sets MCG to FEE mode from reset mode, it could be used to |
<> | 144:ef7eb2e8f9f7 | 1556 | * set up MCG during system boot up. |
<> | 144:ef7eb2e8f9f7 | 1557 | * |
<> | 144:ef7eb2e8f9f7 | 1558 | * @param oscsel OSC clock select, OSCSEL. |
<> | 144:ef7eb2e8f9f7 | 1559 | * @param frdiv FLL reference clock divider setting, FRDIV. |
<> | 144:ef7eb2e8f9f7 | 1560 | * @param dmx32 DMX32 in FEE mode. |
<> | 144:ef7eb2e8f9f7 | 1561 | * @param drs The DCO range selection. |
<> | 144:ef7eb2e8f9f7 | 1562 | * @param fllStableDelay Delay function to make sure FLL is stable. |
<> | 144:ef7eb2e8f9f7 | 1563 | * |
<> | 144:ef7eb2e8f9f7 | 1564 | * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. |
<> | 144:ef7eb2e8f9f7 | 1565 | * @retval kStatus_Success Switch to target mode successfully. |
<> | 144:ef7eb2e8f9f7 | 1566 | */ |
<> | 144:ef7eb2e8f9f7 | 1567 | status_t CLOCK_BootToFeeMode( |
<> | 144:ef7eb2e8f9f7 | 1568 | mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)); |
<> | 144:ef7eb2e8f9f7 | 1569 | |
<> | 144:ef7eb2e8f9f7 | 1570 | /*! |
<> | 144:ef7eb2e8f9f7 | 1571 | * @brief Set MCG to BLPI mode during system boot up. |
<> | 144:ef7eb2e8f9f7 | 1572 | * |
<> | 144:ef7eb2e8f9f7 | 1573 | * This function sets MCG to BLPI mode from reset mode, it could be used to |
<> | 144:ef7eb2e8f9f7 | 1574 | * setup MCG during sytem boot up. |
<> | 144:ef7eb2e8f9f7 | 1575 | * |
<> | 144:ef7eb2e8f9f7 | 1576 | * @param fcrdiv Fast IRC divider, FCRDIV. |
<> | 144:ef7eb2e8f9f7 | 1577 | * @param ircs The internal reference clock to select, IRCS. |
<> | 144:ef7eb2e8f9f7 | 1578 | * @param ircEnableMode The MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode. |
<> | 144:ef7eb2e8f9f7 | 1579 | * |
<> | 144:ef7eb2e8f9f7 | 1580 | * @retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting. |
<> | 144:ef7eb2e8f9f7 | 1581 | * @retval kStatus_Success Switch to target mode successfully. |
<> | 144:ef7eb2e8f9f7 | 1582 | */ |
<> | 144:ef7eb2e8f9f7 | 1583 | status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode); |
<> | 144:ef7eb2e8f9f7 | 1584 | |
<> | 144:ef7eb2e8f9f7 | 1585 | /*! |
<> | 144:ef7eb2e8f9f7 | 1586 | * @brief Set MCG to BLPE mode during sytem boot up. |
<> | 144:ef7eb2e8f9f7 | 1587 | * |
<> | 144:ef7eb2e8f9f7 | 1588 | * This function sets MCG to BLPE mode from reset mode, it could be used to |
<> | 144:ef7eb2e8f9f7 | 1589 | * setup MCG during sytem boot up. |
<> | 144:ef7eb2e8f9f7 | 1590 | * |
<> | 144:ef7eb2e8f9f7 | 1591 | * @param oscsel OSC clock select, MCG_C7[OSCSEL]. |
<> | 144:ef7eb2e8f9f7 | 1592 | * |
<> | 144:ef7eb2e8f9f7 | 1593 | * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. |
<> | 144:ef7eb2e8f9f7 | 1594 | * @retval kStatus_Success Switch to target mode successfully. |
<> | 144:ef7eb2e8f9f7 | 1595 | */ |
<> | 144:ef7eb2e8f9f7 | 1596 | status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel); |
<> | 144:ef7eb2e8f9f7 | 1597 | |
<> | 144:ef7eb2e8f9f7 | 1598 | /*! |
<> | 144:ef7eb2e8f9f7 | 1599 | * @brief Set MCG to PEE mode during system boot up. |
<> | 144:ef7eb2e8f9f7 | 1600 | * |
<> | 144:ef7eb2e8f9f7 | 1601 | * This function sets MCG to PEE mode from reset mode, it could be used to |
<> | 144:ef7eb2e8f9f7 | 1602 | * setup MCG during system boot up. |
<> | 144:ef7eb2e8f9f7 | 1603 | * |
<> | 144:ef7eb2e8f9f7 | 1604 | * @param oscsel OSC clock select, MCG_C7[OSCSEL]. |
<> | 144:ef7eb2e8f9f7 | 1605 | * @param pllcs The PLL selection, PLLCS. |
<> | 144:ef7eb2e8f9f7 | 1606 | * @param config Pointer to the PLL configuration. |
<> | 144:ef7eb2e8f9f7 | 1607 | * |
<> | 144:ef7eb2e8f9f7 | 1608 | * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. |
<> | 144:ef7eb2e8f9f7 | 1609 | * @retval kStatus_Success Switch to target mode successfully. |
<> | 144:ef7eb2e8f9f7 | 1610 | */ |
<> | 144:ef7eb2e8f9f7 | 1611 | status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config); |
<> | 144:ef7eb2e8f9f7 | 1612 | |
<> | 144:ef7eb2e8f9f7 | 1613 | /*! |
<> | 144:ef7eb2e8f9f7 | 1614 | * @brief Set MCG to some target mode. |
<> | 144:ef7eb2e8f9f7 | 1615 | * |
<> | 144:ef7eb2e8f9f7 | 1616 | * This function sets MCG to some target mode defined by the configure |
<> | 144:ef7eb2e8f9f7 | 1617 | * structure, if cannot switch to target mode directly, this function will |
<> | 144:ef7eb2e8f9f7 | 1618 | * choose the proper path. |
<> | 144:ef7eb2e8f9f7 | 1619 | * |
<> | 144:ef7eb2e8f9f7 | 1620 | * @param config Pointer to the target MCG mode configuration structure. |
<> | 144:ef7eb2e8f9f7 | 1621 | * @return Return kStatus_Success if switch successfully, otherwise return error code #_mcg_status. |
<> | 144:ef7eb2e8f9f7 | 1622 | * |
<> | 144:ef7eb2e8f9f7 | 1623 | * @note If external clock is used in the target mode, please make sure it is |
<> | 144:ef7eb2e8f9f7 | 1624 | * enabled, for example, if the OSC0 is used, please setup OSC0 correctly before |
<> | 144:ef7eb2e8f9f7 | 1625 | * this funciton. |
<> | 144:ef7eb2e8f9f7 | 1626 | */ |
<> | 144:ef7eb2e8f9f7 | 1627 | status_t CLOCK_SetMcgConfig(mcg_config_t const *config); |
<> | 144:ef7eb2e8f9f7 | 1628 | |
<> | 144:ef7eb2e8f9f7 | 1629 | /*@}*/ |
<> | 144:ef7eb2e8f9f7 | 1630 | |
<> | 144:ef7eb2e8f9f7 | 1631 | #if defined(__cplusplus) |
<> | 144:ef7eb2e8f9f7 | 1632 | } |
<> | 144:ef7eb2e8f9f7 | 1633 | #endif /* __cplusplus */ |
<> | 144:ef7eb2e8f9f7 | 1634 | |
<> | 144:ef7eb2e8f9f7 | 1635 | /*! @} */ |
<> | 144:ef7eb2e8f9f7 | 1636 | |
<> | 144:ef7eb2e8f9f7 | 1637 | #endif /* _FSL_CLOCK_H_ */ |