added prescaler for 16 bit pwm in LPC1347 target
Fork of mbed-dev by
targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_clock.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)
- Committer:
- <>
- Date:
- Fri Sep 02 15:07:44 2016 +0100
- Revision:
- 144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /* |
<> | 144:ef7eb2e8f9f7 | 2 | * Copyright (c) 2015, Freescale Semiconductor, Inc. |
<> | 144:ef7eb2e8f9f7 | 3 | * All rights reserved. |
<> | 144:ef7eb2e8f9f7 | 4 | * |
<> | 144:ef7eb2e8f9f7 | 5 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 144:ef7eb2e8f9f7 | 6 | * are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 7 | * |
<> | 144:ef7eb2e8f9f7 | 8 | * o Redistributions of source code must retain the above copyright notice, this list |
<> | 144:ef7eb2e8f9f7 | 9 | * of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 10 | * |
<> | 144:ef7eb2e8f9f7 | 11 | * o Redistributions in binary form must reproduce the above copyright notice, this |
<> | 144:ef7eb2e8f9f7 | 12 | * list of conditions and the following disclaimer in the documentation and/or |
<> | 144:ef7eb2e8f9f7 | 13 | * other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 14 | * |
<> | 144:ef7eb2e8f9f7 | 15 | * o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
<> | 144:ef7eb2e8f9f7 | 16 | * contributors may be used to endorse or promote products derived from this |
<> | 144:ef7eb2e8f9f7 | 17 | * software without specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 18 | * |
<> | 144:ef7eb2e8f9f7 | 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
<> | 144:ef7eb2e8f9f7 | 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
<> | 144:ef7eb2e8f9f7 | 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 144:ef7eb2e8f9f7 | 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
<> | 144:ef7eb2e8f9f7 | 23 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
<> | 144:ef7eb2e8f9f7 | 24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
<> | 144:ef7eb2e8f9f7 | 25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
<> | 144:ef7eb2e8f9f7 | 26 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
<> | 144:ef7eb2e8f9f7 | 27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
<> | 144:ef7eb2e8f9f7 | 28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 29 | */ |
<> | 144:ef7eb2e8f9f7 | 30 | |
<> | 144:ef7eb2e8f9f7 | 31 | #include "fsl_common.h" |
<> | 144:ef7eb2e8f9f7 | 32 | #include "fsl_clock.h" |
<> | 144:ef7eb2e8f9f7 | 33 | |
<> | 144:ef7eb2e8f9f7 | 34 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 35 | * Definitions |
<> | 144:ef7eb2e8f9f7 | 36 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 37 | |
<> | 144:ef7eb2e8f9f7 | 38 | /* Macro definition remap workaround. */ |
<> | 144:ef7eb2e8f9f7 | 39 | #if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK))) |
<> | 144:ef7eb2e8f9f7 | 40 | #define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK |
<> | 144:ef7eb2e8f9f7 | 41 | #endif |
<> | 144:ef7eb2e8f9f7 | 42 | #if (defined(MCG_C2_HGO_MASK) && !(defined(MCG_C2_HGO0_MASK))) |
<> | 144:ef7eb2e8f9f7 | 43 | #define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK |
<> | 144:ef7eb2e8f9f7 | 44 | #endif |
<> | 144:ef7eb2e8f9f7 | 45 | #if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK))) |
<> | 144:ef7eb2e8f9f7 | 46 | #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK |
<> | 144:ef7eb2e8f9f7 | 47 | #endif |
<> | 144:ef7eb2e8f9f7 | 48 | #if (defined(MCG_C6_CME_MASK) && !(defined(MCG_C6_CME0_MASK))) |
<> | 144:ef7eb2e8f9f7 | 49 | #define MCG_C6_CME0_MASK MCG_C6_CME_MASK |
<> | 144:ef7eb2e8f9f7 | 50 | #endif |
<> | 144:ef7eb2e8f9f7 | 51 | |
<> | 144:ef7eb2e8f9f7 | 52 | /* PLL fixed multiplier when there is not PRDIV and VDIV. */ |
<> | 144:ef7eb2e8f9f7 | 53 | #define PLL_FIXED_MULT (375U) |
<> | 144:ef7eb2e8f9f7 | 54 | /* Max frequency of the reference clock used for internal clock trim. */ |
<> | 144:ef7eb2e8f9f7 | 55 | #define TRIM_REF_CLK_MIN (8000000U) |
<> | 144:ef7eb2e8f9f7 | 56 | /* Min frequency of the reference clock used for internal clock trim. */ |
<> | 144:ef7eb2e8f9f7 | 57 | #define TRIM_REF_CLK_MAX (16000000U) |
<> | 144:ef7eb2e8f9f7 | 58 | /* Max trim value of fast internal reference clock. */ |
<> | 144:ef7eb2e8f9f7 | 59 | #define TRIM_FIRC_MAX (5000000U) |
<> | 144:ef7eb2e8f9f7 | 60 | /* Min trim value of fast internal reference clock. */ |
<> | 144:ef7eb2e8f9f7 | 61 | #define TRIM_FIRC_MIN (3000000U) |
<> | 144:ef7eb2e8f9f7 | 62 | /* Max trim value of fast internal reference clock. */ |
<> | 144:ef7eb2e8f9f7 | 63 | #define TRIM_SIRC_MAX (39063U) |
<> | 144:ef7eb2e8f9f7 | 64 | /* Min trim value of fast internal reference clock. */ |
<> | 144:ef7eb2e8f9f7 | 65 | #define TRIM_SIRC_MIN (31250U) |
<> | 144:ef7eb2e8f9f7 | 66 | |
<> | 144:ef7eb2e8f9f7 | 67 | #define MCG_S_IRCST_VAL ((MCG->S & MCG_S_IRCST_MASK) >> MCG_S_IRCST_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 68 | #define MCG_S_CLKST_VAL ((MCG->S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 69 | #define MCG_S_IREFST_VAL ((MCG->S & MCG_S_IREFST_MASK) >> MCG_S_IREFST_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 70 | #define MCG_S_PLLST_VAL ((MCG->S & MCG_S_PLLST_MASK) >> MCG_S_PLLST_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 71 | #define MCG_C1_FRDIV_VAL ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 72 | #define MCG_C2_LP_VAL ((MCG->C2 & MCG_C2_LP_MASK) >> MCG_C2_LP_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 73 | #define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 74 | #define MCG_SC_FCRDIV_VAL ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 75 | #define MCG_S2_PLLCST_VAL ((MCG->S2 & MCG_S2_PLLCST_MASK) >> MCG_S2_PLLCST_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 76 | #define MCG_C7_OSCSEL_VAL ((MCG->C7 & MCG_C7_OSCSEL_MASK) >> MCG_C7_OSCSEL_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 77 | #define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 78 | #define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 79 | #define MCG_C7_PLL32KREFSEL_VAL ((MCG->C7 & MCG_C7_PLL32KREFSEL_MASK) >> MCG_C7_PLL32KREFSEL_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 80 | #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 81 | #define MCG_C11_PLLREFSEL1_VAL ((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) >> MCG_C11_PLLREFSEL1_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 82 | #define MCG_C11_PRDIV1_VAL ((MCG->C11 & MCG_C11_PRDIV1_MASK) >> MCG_C11_PRDIV1_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 83 | #define MCG_C12_VDIV1_VAL ((MCG->C12 & MCG_C12_VDIV1_MASK) >> MCG_C12_VDIV1_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 84 | #define MCG_C5_PRDIV0_VAL ((MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 85 | #define MCG_C6_VDIV0_VAL ((MCG->C6 & MCG_C6_VDIV0_MASK) >> MCG_C6_VDIV0_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 86 | |
<> | 144:ef7eb2e8f9f7 | 87 | #define OSC_MODE_MASK (MCG_C2_EREFS0_MASK | MCG_C2_HGO0_MASK | MCG_C2_RANGE0_MASK) |
<> | 144:ef7eb2e8f9f7 | 88 | |
<> | 144:ef7eb2e8f9f7 | 89 | #define SIM_CLKDIV1_OUTDIV1_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 90 | #define SIM_CLKDIV1_OUTDIV2_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV2_MASK) >> SIM_CLKDIV1_OUTDIV2_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 91 | #define SIM_CLKDIV1_OUTDIV3_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV3_MASK) >> SIM_CLKDIV1_OUTDIV3_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 92 | #define SIM_CLKDIV1_OUTDIV4_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 93 | #define SIM_SOPT1_OSC32KSEL_VAL ((SIM->SOPT1 & SIM_SOPT1_OSC32KSEL_MASK) >> SIM_SOPT1_OSC32KSEL_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 94 | #define SIM_SOPT2_PLLFLLSEL_VAL ((SIM->SOPT2 & SIM_SOPT2_PLLFLLSEL_MASK) >> SIM_SOPT2_PLLFLLSEL_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 95 | #define SIM_CLKDIV3_PLLFLLDIV_VAL ((SIM->CLKDIV3 & SIM_CLKDIV3_PLLFLLDIV_MASK) >> SIM_CLKDIV3_PLLFLLDIV_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 96 | #define SIM_CLKDIV3_PLLFLLFRAC_VAL ((SIM->CLKDIV3 & SIM_CLKDIV3_PLLFLLFRAC_MASK) >> SIM_CLKDIV3_PLLFLLFRAC_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 97 | |
<> | 144:ef7eb2e8f9f7 | 98 | /* MCG_S_CLKST definition. */ |
<> | 144:ef7eb2e8f9f7 | 99 | enum _mcg_clkout_stat |
<> | 144:ef7eb2e8f9f7 | 100 | { |
<> | 144:ef7eb2e8f9f7 | 101 | kMCG_ClkOutStatFll, /* FLL. */ |
<> | 144:ef7eb2e8f9f7 | 102 | kMCG_ClkOutStatInt, /* Internal clock. */ |
<> | 144:ef7eb2e8f9f7 | 103 | kMCG_ClkOutStatExt, /* External clock. */ |
<> | 144:ef7eb2e8f9f7 | 104 | kMCG_ClkOutStatPll /* PLL. */ |
<> | 144:ef7eb2e8f9f7 | 105 | }; |
<> | 144:ef7eb2e8f9f7 | 106 | |
<> | 144:ef7eb2e8f9f7 | 107 | /* MCG_S_PLLST definition. */ |
<> | 144:ef7eb2e8f9f7 | 108 | enum _mcg_pllst |
<> | 144:ef7eb2e8f9f7 | 109 | { |
<> | 144:ef7eb2e8f9f7 | 110 | kMCG_PllstFll, /* FLL is used. */ |
<> | 144:ef7eb2e8f9f7 | 111 | kMCG_PllstPll /* PLL is used. */ |
<> | 144:ef7eb2e8f9f7 | 112 | }; |
<> | 144:ef7eb2e8f9f7 | 113 | |
<> | 144:ef7eb2e8f9f7 | 114 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 115 | * Variables |
<> | 144:ef7eb2e8f9f7 | 116 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 117 | |
<> | 144:ef7eb2e8f9f7 | 118 | /* Slow internal reference clock frequency. */ |
<> | 144:ef7eb2e8f9f7 | 119 | static uint32_t s_slowIrcFreq = 32768U; |
<> | 144:ef7eb2e8f9f7 | 120 | /* Fast internal reference clock frequency. */ |
<> | 144:ef7eb2e8f9f7 | 121 | static uint32_t s_fastIrcFreq = 4000000U; |
<> | 144:ef7eb2e8f9f7 | 122 | /* The MCG external PLL clock frequency. */ |
<> | 144:ef7eb2e8f9f7 | 123 | static uint32_t s_extPllFreq = 0U; |
<> | 144:ef7eb2e8f9f7 | 124 | |
<> | 144:ef7eb2e8f9f7 | 125 | /* External XTAL0 (OSC0) clock frequency. */ |
<> | 144:ef7eb2e8f9f7 | 126 | uint32_t g_xtal0Freq; |
<> | 144:ef7eb2e8f9f7 | 127 | |
<> | 144:ef7eb2e8f9f7 | 128 | /* External XTAL32K clock frequency. */ |
<> | 144:ef7eb2e8f9f7 | 129 | uint32_t g_xtal32Freq; |
<> | 144:ef7eb2e8f9f7 | 130 | |
<> | 144:ef7eb2e8f9f7 | 131 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 132 | * Prototypes |
<> | 144:ef7eb2e8f9f7 | 133 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 134 | |
<> | 144:ef7eb2e8f9f7 | 135 | /*! |
<> | 144:ef7eb2e8f9f7 | 136 | * @brief Get the MCG external reference clock frequency. |
<> | 144:ef7eb2e8f9f7 | 137 | * |
<> | 144:ef7eb2e8f9f7 | 138 | * Get the current MCG external reference clock frequency in Hz. It is |
<> | 144:ef7eb2e8f9f7 | 139 | * the frequency select by MCG_C7[OSCSEL]. This is an internal function. |
<> | 144:ef7eb2e8f9f7 | 140 | * |
<> | 144:ef7eb2e8f9f7 | 141 | * @return MCG external reference clock frequency in Hz. |
<> | 144:ef7eb2e8f9f7 | 142 | */ |
<> | 144:ef7eb2e8f9f7 | 143 | static uint32_t CLOCK_GetMcgExtClkFreq(void); |
<> | 144:ef7eb2e8f9f7 | 144 | |
<> | 144:ef7eb2e8f9f7 | 145 | /*! |
<> | 144:ef7eb2e8f9f7 | 146 | * @brief Get the MCG FLL external reference clock frequency. |
<> | 144:ef7eb2e8f9f7 | 147 | * |
<> | 144:ef7eb2e8f9f7 | 148 | * Get the current MCG FLL external reference clock frequency in Hz. It is |
<> | 144:ef7eb2e8f9f7 | 149 | * the frequency after by MCG_C1[FRDIV]. This is an internal function. |
<> | 144:ef7eb2e8f9f7 | 150 | * |
<> | 144:ef7eb2e8f9f7 | 151 | * @return MCG FLL external reference clock frequency in Hz. |
<> | 144:ef7eb2e8f9f7 | 152 | */ |
<> | 144:ef7eb2e8f9f7 | 153 | static uint32_t CLOCK_GetFllExtRefClkFreq(void); |
<> | 144:ef7eb2e8f9f7 | 154 | |
<> | 144:ef7eb2e8f9f7 | 155 | /*! |
<> | 144:ef7eb2e8f9f7 | 156 | * @brief Get the MCG FLL reference clock frequency. |
<> | 144:ef7eb2e8f9f7 | 157 | * |
<> | 144:ef7eb2e8f9f7 | 158 | * Get the current MCG FLL reference clock frequency in Hz. It is |
<> | 144:ef7eb2e8f9f7 | 159 | * the frequency select by MCG_C1[IREFS]. This is an internal function. |
<> | 144:ef7eb2e8f9f7 | 160 | * |
<> | 144:ef7eb2e8f9f7 | 161 | * @return MCG FLL reference clock frequency in Hz. |
<> | 144:ef7eb2e8f9f7 | 162 | */ |
<> | 144:ef7eb2e8f9f7 | 163 | static uint32_t CLOCK_GetFllRefClkFreq(void); |
<> | 144:ef7eb2e8f9f7 | 164 | |
<> | 144:ef7eb2e8f9f7 | 165 | /*! |
<> | 144:ef7eb2e8f9f7 | 166 | * @brief Get the frequency of clock selected by MCG_C2[IRCS]. |
<> | 144:ef7eb2e8f9f7 | 167 | * |
<> | 144:ef7eb2e8f9f7 | 168 | * This clock's two output: |
<> | 144:ef7eb2e8f9f7 | 169 | * 1. MCGOUTCLK when MCG_S[CLKST]=0. |
<> | 144:ef7eb2e8f9f7 | 170 | * 2. MCGIRCLK when MCG_C1[IRCLKEN]=1. |
<> | 144:ef7eb2e8f9f7 | 171 | * |
<> | 144:ef7eb2e8f9f7 | 172 | * @return The frequency in Hz. |
<> | 144:ef7eb2e8f9f7 | 173 | */ |
<> | 144:ef7eb2e8f9f7 | 174 | static uint32_t CLOCK_GetInternalRefClkSelectFreq(void); |
<> | 144:ef7eb2e8f9f7 | 175 | |
<> | 144:ef7eb2e8f9f7 | 176 | /*! |
<> | 144:ef7eb2e8f9f7 | 177 | * @brief Get the MCG PLL/PLL0 reference clock frequency. |
<> | 144:ef7eb2e8f9f7 | 178 | * |
<> | 144:ef7eb2e8f9f7 | 179 | * Get the current MCG PLL/PLL0 reference clock frequency in Hz. |
<> | 144:ef7eb2e8f9f7 | 180 | * This is an internal function. |
<> | 144:ef7eb2e8f9f7 | 181 | * |
<> | 144:ef7eb2e8f9f7 | 182 | * @return MCG PLL/PLL0 reference clock frequency in Hz. |
<> | 144:ef7eb2e8f9f7 | 183 | */ |
<> | 144:ef7eb2e8f9f7 | 184 | static uint32_t CLOCK_GetPll0RefFreq(void); |
<> | 144:ef7eb2e8f9f7 | 185 | |
<> | 144:ef7eb2e8f9f7 | 186 | /*! |
<> | 144:ef7eb2e8f9f7 | 187 | * @brief Calculate the RANGE value base on crystal frequency. |
<> | 144:ef7eb2e8f9f7 | 188 | * |
<> | 144:ef7eb2e8f9f7 | 189 | * To setup external crystal oscillator, must set the register bits RANGE |
<> | 144:ef7eb2e8f9f7 | 190 | * base on the crystal frequency. This function returns the RANGE base on the |
<> | 144:ef7eb2e8f9f7 | 191 | * input frequency. This is an internal function. |
<> | 144:ef7eb2e8f9f7 | 192 | * |
<> | 144:ef7eb2e8f9f7 | 193 | * @param freq Crystal frequency in Hz. |
<> | 144:ef7eb2e8f9f7 | 194 | * @return The RANGE value. |
<> | 144:ef7eb2e8f9f7 | 195 | */ |
<> | 144:ef7eb2e8f9f7 | 196 | static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq); |
<> | 144:ef7eb2e8f9f7 | 197 | |
<> | 144:ef7eb2e8f9f7 | 198 | /*! |
<> | 144:ef7eb2e8f9f7 | 199 | * @brief Delay function to wait FLL stable. |
<> | 144:ef7eb2e8f9f7 | 200 | * |
<> | 144:ef7eb2e8f9f7 | 201 | * Delay function to wait FLL stable in FEI mode or FEE mode, should wait at least |
<> | 144:ef7eb2e8f9f7 | 202 | * 1ms. Every time changes FLL setting, should wait this time for FLL stable. |
<> | 144:ef7eb2e8f9f7 | 203 | */ |
<> | 144:ef7eb2e8f9f7 | 204 | static void CLOCK_FllStableDelay(void); |
<> | 144:ef7eb2e8f9f7 | 205 | |
<> | 144:ef7eb2e8f9f7 | 206 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 207 | * Code |
<> | 144:ef7eb2e8f9f7 | 208 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 209 | |
<> | 144:ef7eb2e8f9f7 | 210 | static uint32_t CLOCK_GetMcgExtClkFreq(void) |
<> | 144:ef7eb2e8f9f7 | 211 | { |
<> | 144:ef7eb2e8f9f7 | 212 | uint32_t freq; |
<> | 144:ef7eb2e8f9f7 | 213 | |
<> | 144:ef7eb2e8f9f7 | 214 | switch (MCG_C7_OSCSEL_VAL) |
<> | 144:ef7eb2e8f9f7 | 215 | { |
<> | 144:ef7eb2e8f9f7 | 216 | case 0U: |
<> | 144:ef7eb2e8f9f7 | 217 | /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */ |
<> | 144:ef7eb2e8f9f7 | 218 | assert(g_xtal0Freq); |
<> | 144:ef7eb2e8f9f7 | 219 | freq = g_xtal0Freq; |
<> | 144:ef7eb2e8f9f7 | 220 | break; |
<> | 144:ef7eb2e8f9f7 | 221 | case 1U: |
<> | 144:ef7eb2e8f9f7 | 222 | /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */ |
<> | 144:ef7eb2e8f9f7 | 223 | assert(g_xtal32Freq); |
<> | 144:ef7eb2e8f9f7 | 224 | freq = g_xtal32Freq; |
<> | 144:ef7eb2e8f9f7 | 225 | break; |
<> | 144:ef7eb2e8f9f7 | 226 | case 2U: |
<> | 144:ef7eb2e8f9f7 | 227 | freq = MCG_INTERNAL_IRC_48M; |
<> | 144:ef7eb2e8f9f7 | 228 | break; |
<> | 144:ef7eb2e8f9f7 | 229 | default: |
<> | 144:ef7eb2e8f9f7 | 230 | freq = 0U; |
<> | 144:ef7eb2e8f9f7 | 231 | break; |
<> | 144:ef7eb2e8f9f7 | 232 | } |
<> | 144:ef7eb2e8f9f7 | 233 | |
<> | 144:ef7eb2e8f9f7 | 234 | return freq; |
<> | 144:ef7eb2e8f9f7 | 235 | } |
<> | 144:ef7eb2e8f9f7 | 236 | |
<> | 144:ef7eb2e8f9f7 | 237 | static uint32_t CLOCK_GetFllExtRefClkFreq(void) |
<> | 144:ef7eb2e8f9f7 | 238 | { |
<> | 144:ef7eb2e8f9f7 | 239 | /* FllExtRef = McgExtRef / FllExtRefDiv */ |
<> | 144:ef7eb2e8f9f7 | 240 | uint8_t frdiv; |
<> | 144:ef7eb2e8f9f7 | 241 | uint8_t range; |
<> | 144:ef7eb2e8f9f7 | 242 | uint8_t oscsel; |
<> | 144:ef7eb2e8f9f7 | 243 | |
<> | 144:ef7eb2e8f9f7 | 244 | uint32_t freq = CLOCK_GetMcgExtClkFreq(); |
<> | 144:ef7eb2e8f9f7 | 245 | |
<> | 144:ef7eb2e8f9f7 | 246 | if (!freq) |
<> | 144:ef7eb2e8f9f7 | 247 | { |
<> | 144:ef7eb2e8f9f7 | 248 | return freq; |
<> | 144:ef7eb2e8f9f7 | 249 | } |
<> | 144:ef7eb2e8f9f7 | 250 | |
<> | 144:ef7eb2e8f9f7 | 251 | frdiv = MCG_C1_FRDIV_VAL; |
<> | 144:ef7eb2e8f9f7 | 252 | freq >>= frdiv; |
<> | 144:ef7eb2e8f9f7 | 253 | |
<> | 144:ef7eb2e8f9f7 | 254 | range = MCG_C2_RANGE_VAL; |
<> | 144:ef7eb2e8f9f7 | 255 | oscsel = MCG_C7_OSCSEL_VAL; |
<> | 144:ef7eb2e8f9f7 | 256 | |
<> | 144:ef7eb2e8f9f7 | 257 | /* |
<> | 144:ef7eb2e8f9f7 | 258 | When should use divider 32, 64, 128, 256, 512, 1024, 1280, 1536. |
<> | 144:ef7eb2e8f9f7 | 259 | 1. MCG_C7[OSCSEL] selects IRC48M. |
<> | 144:ef7eb2e8f9f7 | 260 | 2. MCG_C7[OSCSEL] selects OSC0 and MCG_C2[RANGE] is not 0. |
<> | 144:ef7eb2e8f9f7 | 261 | */ |
<> | 144:ef7eb2e8f9f7 | 262 | if (((0U != range) && (kMCG_OscselOsc == oscsel)) || (kMCG_OscselIrc == oscsel)) |
<> | 144:ef7eb2e8f9f7 | 263 | { |
<> | 144:ef7eb2e8f9f7 | 264 | switch (frdiv) |
<> | 144:ef7eb2e8f9f7 | 265 | { |
<> | 144:ef7eb2e8f9f7 | 266 | case 0: |
<> | 144:ef7eb2e8f9f7 | 267 | case 1: |
<> | 144:ef7eb2e8f9f7 | 268 | case 2: |
<> | 144:ef7eb2e8f9f7 | 269 | case 3: |
<> | 144:ef7eb2e8f9f7 | 270 | case 4: |
<> | 144:ef7eb2e8f9f7 | 271 | case 5: |
<> | 144:ef7eb2e8f9f7 | 272 | freq >>= 5u; |
<> | 144:ef7eb2e8f9f7 | 273 | break; |
<> | 144:ef7eb2e8f9f7 | 274 | case 6: |
<> | 144:ef7eb2e8f9f7 | 275 | /* 64*20=1280 */ |
<> | 144:ef7eb2e8f9f7 | 276 | freq /= 20u; |
<> | 144:ef7eb2e8f9f7 | 277 | break; |
<> | 144:ef7eb2e8f9f7 | 278 | case 7: |
<> | 144:ef7eb2e8f9f7 | 279 | /* 128*12=1536 */ |
<> | 144:ef7eb2e8f9f7 | 280 | freq /= 12u; |
<> | 144:ef7eb2e8f9f7 | 281 | break; |
<> | 144:ef7eb2e8f9f7 | 282 | default: |
<> | 144:ef7eb2e8f9f7 | 283 | freq = 0u; |
<> | 144:ef7eb2e8f9f7 | 284 | break; |
<> | 144:ef7eb2e8f9f7 | 285 | } |
<> | 144:ef7eb2e8f9f7 | 286 | } |
<> | 144:ef7eb2e8f9f7 | 287 | |
<> | 144:ef7eb2e8f9f7 | 288 | return freq; |
<> | 144:ef7eb2e8f9f7 | 289 | } |
<> | 144:ef7eb2e8f9f7 | 290 | |
<> | 144:ef7eb2e8f9f7 | 291 | static uint32_t CLOCK_GetInternalRefClkSelectFreq(void) |
<> | 144:ef7eb2e8f9f7 | 292 | { |
<> | 144:ef7eb2e8f9f7 | 293 | if (kMCG_IrcSlow == MCG_S_IRCST_VAL) |
<> | 144:ef7eb2e8f9f7 | 294 | { |
<> | 144:ef7eb2e8f9f7 | 295 | /* Slow internal reference clock selected*/ |
<> | 144:ef7eb2e8f9f7 | 296 | return s_slowIrcFreq; |
<> | 144:ef7eb2e8f9f7 | 297 | } |
<> | 144:ef7eb2e8f9f7 | 298 | else |
<> | 144:ef7eb2e8f9f7 | 299 | { |
<> | 144:ef7eb2e8f9f7 | 300 | /* Fast internal reference clock selected*/ |
<> | 144:ef7eb2e8f9f7 | 301 | return s_fastIrcFreq >> MCG_SC_FCRDIV_VAL; |
<> | 144:ef7eb2e8f9f7 | 302 | } |
<> | 144:ef7eb2e8f9f7 | 303 | } |
<> | 144:ef7eb2e8f9f7 | 304 | |
<> | 144:ef7eb2e8f9f7 | 305 | static uint32_t CLOCK_GetFllRefClkFreq(void) |
<> | 144:ef7eb2e8f9f7 | 306 | { |
<> | 144:ef7eb2e8f9f7 | 307 | /* If use external reference clock. */ |
<> | 144:ef7eb2e8f9f7 | 308 | if (kMCG_FllSrcExternal == MCG_S_IREFST_VAL) |
<> | 144:ef7eb2e8f9f7 | 309 | { |
<> | 144:ef7eb2e8f9f7 | 310 | return CLOCK_GetFllExtRefClkFreq(); |
<> | 144:ef7eb2e8f9f7 | 311 | } |
<> | 144:ef7eb2e8f9f7 | 312 | /* If use internal reference clock. */ |
<> | 144:ef7eb2e8f9f7 | 313 | else |
<> | 144:ef7eb2e8f9f7 | 314 | { |
<> | 144:ef7eb2e8f9f7 | 315 | return s_slowIrcFreq; |
<> | 144:ef7eb2e8f9f7 | 316 | } |
<> | 144:ef7eb2e8f9f7 | 317 | } |
<> | 144:ef7eb2e8f9f7 | 318 | |
<> | 144:ef7eb2e8f9f7 | 319 | static uint32_t CLOCK_GetPll0RefFreq(void) |
<> | 144:ef7eb2e8f9f7 | 320 | { |
<> | 144:ef7eb2e8f9f7 | 321 | /* MCG external reference clock. */ |
<> | 144:ef7eb2e8f9f7 | 322 | return CLOCK_GetMcgExtClkFreq(); |
<> | 144:ef7eb2e8f9f7 | 323 | } |
<> | 144:ef7eb2e8f9f7 | 324 | |
<> | 144:ef7eb2e8f9f7 | 325 | static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq) |
<> | 144:ef7eb2e8f9f7 | 326 | { |
<> | 144:ef7eb2e8f9f7 | 327 | uint8_t range; |
<> | 144:ef7eb2e8f9f7 | 328 | |
<> | 144:ef7eb2e8f9f7 | 329 | if (freq <= 39063U) |
<> | 144:ef7eb2e8f9f7 | 330 | { |
<> | 144:ef7eb2e8f9f7 | 331 | range = 0U; |
<> | 144:ef7eb2e8f9f7 | 332 | } |
<> | 144:ef7eb2e8f9f7 | 333 | else if (freq <= 8000000U) |
<> | 144:ef7eb2e8f9f7 | 334 | { |
<> | 144:ef7eb2e8f9f7 | 335 | range = 1U; |
<> | 144:ef7eb2e8f9f7 | 336 | } |
<> | 144:ef7eb2e8f9f7 | 337 | else |
<> | 144:ef7eb2e8f9f7 | 338 | { |
<> | 144:ef7eb2e8f9f7 | 339 | range = 2U; |
<> | 144:ef7eb2e8f9f7 | 340 | } |
<> | 144:ef7eb2e8f9f7 | 341 | |
<> | 144:ef7eb2e8f9f7 | 342 | return range; |
<> | 144:ef7eb2e8f9f7 | 343 | } |
<> | 144:ef7eb2e8f9f7 | 344 | |
<> | 144:ef7eb2e8f9f7 | 345 | static void CLOCK_FllStableDelay(void) |
<> | 144:ef7eb2e8f9f7 | 346 | { |
<> | 144:ef7eb2e8f9f7 | 347 | /* |
<> | 144:ef7eb2e8f9f7 | 348 | Should wait at least 1ms. Because in these modes, the core clock is 100MHz |
<> | 144:ef7eb2e8f9f7 | 349 | at most, so this function could obtain the 1ms delay. |
<> | 144:ef7eb2e8f9f7 | 350 | */ |
<> | 144:ef7eb2e8f9f7 | 351 | volatile uint32_t i = 30000U; |
<> | 144:ef7eb2e8f9f7 | 352 | while (i--) |
<> | 144:ef7eb2e8f9f7 | 353 | { |
<> | 144:ef7eb2e8f9f7 | 354 | __NOP(); |
<> | 144:ef7eb2e8f9f7 | 355 | } |
<> | 144:ef7eb2e8f9f7 | 356 | } |
<> | 144:ef7eb2e8f9f7 | 357 | |
<> | 144:ef7eb2e8f9f7 | 358 | uint32_t CLOCK_GetOsc0ErClkUndivFreq(void) |
<> | 144:ef7eb2e8f9f7 | 359 | { |
<> | 144:ef7eb2e8f9f7 | 360 | if (OSC0->CR & OSC_CR_ERCLKEN_MASK) |
<> | 144:ef7eb2e8f9f7 | 361 | { |
<> | 144:ef7eb2e8f9f7 | 362 | /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */ |
<> | 144:ef7eb2e8f9f7 | 363 | assert(g_xtal0Freq); |
<> | 144:ef7eb2e8f9f7 | 364 | return g_xtal0Freq; |
<> | 144:ef7eb2e8f9f7 | 365 | } |
<> | 144:ef7eb2e8f9f7 | 366 | else |
<> | 144:ef7eb2e8f9f7 | 367 | { |
<> | 144:ef7eb2e8f9f7 | 368 | return 0U; |
<> | 144:ef7eb2e8f9f7 | 369 | } |
<> | 144:ef7eb2e8f9f7 | 370 | } |
<> | 144:ef7eb2e8f9f7 | 371 | |
<> | 144:ef7eb2e8f9f7 | 372 | uint32_t CLOCK_GetOsc0ErClkDivFreq(void) |
<> | 144:ef7eb2e8f9f7 | 373 | { |
<> | 144:ef7eb2e8f9f7 | 374 | if (OSC0->CR & OSC_CR_ERCLKEN_MASK) |
<> | 144:ef7eb2e8f9f7 | 375 | { |
<> | 144:ef7eb2e8f9f7 | 376 | /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */ |
<> | 144:ef7eb2e8f9f7 | 377 | assert(g_xtal0Freq); |
<> | 144:ef7eb2e8f9f7 | 378 | return g_xtal0Freq >> ((OSC0->DIV & OSC_DIV_ERPS_MASK) >> OSC_DIV_ERPS_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 379 | } |
<> | 144:ef7eb2e8f9f7 | 380 | else |
<> | 144:ef7eb2e8f9f7 | 381 | { |
<> | 144:ef7eb2e8f9f7 | 382 | return 0U; |
<> | 144:ef7eb2e8f9f7 | 383 | } |
<> | 144:ef7eb2e8f9f7 | 384 | } |
<> | 144:ef7eb2e8f9f7 | 385 | |
<> | 144:ef7eb2e8f9f7 | 386 | uint32_t CLOCK_GetEr32kClkFreq(void) |
<> | 144:ef7eb2e8f9f7 | 387 | { |
<> | 144:ef7eb2e8f9f7 | 388 | uint32_t freq; |
<> | 144:ef7eb2e8f9f7 | 389 | |
<> | 144:ef7eb2e8f9f7 | 390 | switch (SIM_SOPT1_OSC32KSEL_VAL) |
<> | 144:ef7eb2e8f9f7 | 391 | { |
<> | 144:ef7eb2e8f9f7 | 392 | case 0U: /* OSC 32k clock */ |
<> | 144:ef7eb2e8f9f7 | 393 | freq = (CLOCK_GetOsc0ErClkDivFreq() == 32768U) ? 32768U : 0U; |
<> | 144:ef7eb2e8f9f7 | 394 | break; |
<> | 144:ef7eb2e8f9f7 | 395 | case 2U: /* RTC 32k clock */ |
<> | 144:ef7eb2e8f9f7 | 396 | /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */ |
<> | 144:ef7eb2e8f9f7 | 397 | assert(g_xtal32Freq); |
<> | 144:ef7eb2e8f9f7 | 398 | freq = g_xtal32Freq; |
<> | 144:ef7eb2e8f9f7 | 399 | break; |
<> | 144:ef7eb2e8f9f7 | 400 | case 3U: /* LPO clock */ |
<> | 144:ef7eb2e8f9f7 | 401 | freq = LPO_CLK_FREQ; |
<> | 144:ef7eb2e8f9f7 | 402 | break; |
<> | 144:ef7eb2e8f9f7 | 403 | default: |
<> | 144:ef7eb2e8f9f7 | 404 | freq = 0U; |
<> | 144:ef7eb2e8f9f7 | 405 | break; |
<> | 144:ef7eb2e8f9f7 | 406 | } |
<> | 144:ef7eb2e8f9f7 | 407 | return freq; |
<> | 144:ef7eb2e8f9f7 | 408 | } |
<> | 144:ef7eb2e8f9f7 | 409 | |
<> | 144:ef7eb2e8f9f7 | 410 | uint32_t CLOCK_GetPllFllSelClkFreq(void) |
<> | 144:ef7eb2e8f9f7 | 411 | { |
<> | 144:ef7eb2e8f9f7 | 412 | uint32_t freq; |
<> | 144:ef7eb2e8f9f7 | 413 | |
<> | 144:ef7eb2e8f9f7 | 414 | switch (SIM_SOPT2_PLLFLLSEL_VAL) |
<> | 144:ef7eb2e8f9f7 | 415 | { |
<> | 144:ef7eb2e8f9f7 | 416 | case 0U: /* FLL. */ |
<> | 144:ef7eb2e8f9f7 | 417 | freq = CLOCK_GetFllFreq(); |
<> | 144:ef7eb2e8f9f7 | 418 | break; |
<> | 144:ef7eb2e8f9f7 | 419 | case 1U: /* PLL. */ |
<> | 144:ef7eb2e8f9f7 | 420 | freq = CLOCK_GetPll0Freq(); |
<> | 144:ef7eb2e8f9f7 | 421 | break; |
<> | 144:ef7eb2e8f9f7 | 422 | case 3U: /* MCG IRC48M. */ |
<> | 144:ef7eb2e8f9f7 | 423 | freq = MCG_INTERNAL_IRC_48M; |
<> | 144:ef7eb2e8f9f7 | 424 | break; |
<> | 144:ef7eb2e8f9f7 | 425 | default: |
<> | 144:ef7eb2e8f9f7 | 426 | freq = 0U; |
<> | 144:ef7eb2e8f9f7 | 427 | break; |
<> | 144:ef7eb2e8f9f7 | 428 | } |
<> | 144:ef7eb2e8f9f7 | 429 | |
<> | 144:ef7eb2e8f9f7 | 430 | return freq * (SIM_CLKDIV3_PLLFLLFRAC_VAL + 1U) / (SIM_CLKDIV3_PLLFLLDIV_VAL + 1U); |
<> | 144:ef7eb2e8f9f7 | 431 | } |
<> | 144:ef7eb2e8f9f7 | 432 | |
<> | 144:ef7eb2e8f9f7 | 433 | uint32_t CLOCK_GetOsc0ErClkFreq(void) |
<> | 144:ef7eb2e8f9f7 | 434 | { |
<> | 144:ef7eb2e8f9f7 | 435 | return CLOCK_GetOsc0ErClkDivFreq(); |
<> | 144:ef7eb2e8f9f7 | 436 | } |
<> | 144:ef7eb2e8f9f7 | 437 | |
<> | 144:ef7eb2e8f9f7 | 438 | uint32_t CLOCK_GetPlatClkFreq(void) |
<> | 144:ef7eb2e8f9f7 | 439 | { |
<> | 144:ef7eb2e8f9f7 | 440 | return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1); |
<> | 144:ef7eb2e8f9f7 | 441 | } |
<> | 144:ef7eb2e8f9f7 | 442 | |
<> | 144:ef7eb2e8f9f7 | 443 | uint32_t CLOCK_GetFlashClkFreq(void) |
<> | 144:ef7eb2e8f9f7 | 444 | { |
<> | 144:ef7eb2e8f9f7 | 445 | return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1); |
<> | 144:ef7eb2e8f9f7 | 446 | } |
<> | 144:ef7eb2e8f9f7 | 447 | |
<> | 144:ef7eb2e8f9f7 | 448 | uint32_t CLOCK_GetFlexBusClkFreq(void) |
<> | 144:ef7eb2e8f9f7 | 449 | { |
<> | 144:ef7eb2e8f9f7 | 450 | return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1); |
<> | 144:ef7eb2e8f9f7 | 451 | } |
<> | 144:ef7eb2e8f9f7 | 452 | |
<> | 144:ef7eb2e8f9f7 | 453 | uint32_t CLOCK_GetBusClkFreq(void) |
<> | 144:ef7eb2e8f9f7 | 454 | { |
<> | 144:ef7eb2e8f9f7 | 455 | return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1); |
<> | 144:ef7eb2e8f9f7 | 456 | } |
<> | 144:ef7eb2e8f9f7 | 457 | |
<> | 144:ef7eb2e8f9f7 | 458 | uint32_t CLOCK_GetCoreSysClkFreq(void) |
<> | 144:ef7eb2e8f9f7 | 459 | { |
<> | 144:ef7eb2e8f9f7 | 460 | return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1); |
<> | 144:ef7eb2e8f9f7 | 461 | } |
<> | 144:ef7eb2e8f9f7 | 462 | |
<> | 144:ef7eb2e8f9f7 | 463 | uint32_t CLOCK_GetFreq(clock_name_t clockName) |
<> | 144:ef7eb2e8f9f7 | 464 | { |
<> | 144:ef7eb2e8f9f7 | 465 | uint32_t freq; |
<> | 144:ef7eb2e8f9f7 | 466 | |
<> | 144:ef7eb2e8f9f7 | 467 | switch (clockName) |
<> | 144:ef7eb2e8f9f7 | 468 | { |
<> | 144:ef7eb2e8f9f7 | 469 | case kCLOCK_CoreSysClk: |
<> | 144:ef7eb2e8f9f7 | 470 | case kCLOCK_PlatClk: |
<> | 144:ef7eb2e8f9f7 | 471 | freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1); |
<> | 144:ef7eb2e8f9f7 | 472 | break; |
<> | 144:ef7eb2e8f9f7 | 473 | case kCLOCK_BusClk: |
<> | 144:ef7eb2e8f9f7 | 474 | freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1); |
<> | 144:ef7eb2e8f9f7 | 475 | break; |
<> | 144:ef7eb2e8f9f7 | 476 | case kCLOCK_FlexBusClk: |
<> | 144:ef7eb2e8f9f7 | 477 | freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1); |
<> | 144:ef7eb2e8f9f7 | 478 | break; |
<> | 144:ef7eb2e8f9f7 | 479 | case kCLOCK_FlashClk: |
<> | 144:ef7eb2e8f9f7 | 480 | freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1); |
<> | 144:ef7eb2e8f9f7 | 481 | break; |
<> | 144:ef7eb2e8f9f7 | 482 | case kCLOCK_PllFllSelClk: |
<> | 144:ef7eb2e8f9f7 | 483 | freq = CLOCK_GetPllFllSelClkFreq(); |
<> | 144:ef7eb2e8f9f7 | 484 | break; |
<> | 144:ef7eb2e8f9f7 | 485 | case kCLOCK_Er32kClk: |
<> | 144:ef7eb2e8f9f7 | 486 | freq = CLOCK_GetEr32kClkFreq(); |
<> | 144:ef7eb2e8f9f7 | 487 | break; |
<> | 144:ef7eb2e8f9f7 | 488 | case kCLOCK_Osc0ErClk: |
<> | 144:ef7eb2e8f9f7 | 489 | freq = CLOCK_GetOsc0ErClkDivFreq(); |
<> | 144:ef7eb2e8f9f7 | 490 | break; |
<> | 144:ef7eb2e8f9f7 | 491 | case kCLOCK_Osc0ErClkUndiv: |
<> | 144:ef7eb2e8f9f7 | 492 | freq = CLOCK_GetOsc0ErClkUndivFreq(); |
<> | 144:ef7eb2e8f9f7 | 493 | break; |
<> | 144:ef7eb2e8f9f7 | 494 | case kCLOCK_McgFixedFreqClk: |
<> | 144:ef7eb2e8f9f7 | 495 | freq = CLOCK_GetFixedFreqClkFreq(); |
<> | 144:ef7eb2e8f9f7 | 496 | break; |
<> | 144:ef7eb2e8f9f7 | 497 | case kCLOCK_McgInternalRefClk: |
<> | 144:ef7eb2e8f9f7 | 498 | freq = CLOCK_GetInternalRefClkFreq(); |
<> | 144:ef7eb2e8f9f7 | 499 | break; |
<> | 144:ef7eb2e8f9f7 | 500 | case kCLOCK_McgFllClk: |
<> | 144:ef7eb2e8f9f7 | 501 | freq = CLOCK_GetFllFreq(); |
<> | 144:ef7eb2e8f9f7 | 502 | break; |
<> | 144:ef7eb2e8f9f7 | 503 | case kCLOCK_McgPll0Clk: |
<> | 144:ef7eb2e8f9f7 | 504 | freq = CLOCK_GetPll0Freq(); |
<> | 144:ef7eb2e8f9f7 | 505 | break; |
<> | 144:ef7eb2e8f9f7 | 506 | case kCLOCK_McgIrc48MClk: |
<> | 144:ef7eb2e8f9f7 | 507 | freq = MCG_INTERNAL_IRC_48M; |
<> | 144:ef7eb2e8f9f7 | 508 | break; |
<> | 144:ef7eb2e8f9f7 | 509 | case kCLOCK_LpoClk: |
<> | 144:ef7eb2e8f9f7 | 510 | freq = LPO_CLK_FREQ; |
<> | 144:ef7eb2e8f9f7 | 511 | break; |
<> | 144:ef7eb2e8f9f7 | 512 | default: |
<> | 144:ef7eb2e8f9f7 | 513 | freq = 0U; |
<> | 144:ef7eb2e8f9f7 | 514 | break; |
<> | 144:ef7eb2e8f9f7 | 515 | } |
<> | 144:ef7eb2e8f9f7 | 516 | |
<> | 144:ef7eb2e8f9f7 | 517 | return freq; |
<> | 144:ef7eb2e8f9f7 | 518 | } |
<> | 144:ef7eb2e8f9f7 | 519 | |
<> | 144:ef7eb2e8f9f7 | 520 | void CLOCK_SetSimConfig(sim_clock_config_t const *config) |
<> | 144:ef7eb2e8f9f7 | 521 | { |
<> | 144:ef7eb2e8f9f7 | 522 | SIM->CLKDIV1 = config->clkdiv1; |
<> | 144:ef7eb2e8f9f7 | 523 | CLOCK_SetPllFllSelClock(config->pllFllSel, config->pllFllDiv, config->pllFllFrac); |
<> | 144:ef7eb2e8f9f7 | 524 | CLOCK_SetEr32kClock(config->er32kSrc); |
<> | 144:ef7eb2e8f9f7 | 525 | } |
<> | 144:ef7eb2e8f9f7 | 526 | |
<> | 144:ef7eb2e8f9f7 | 527 | bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq) |
<> | 144:ef7eb2e8f9f7 | 528 | { |
<> | 144:ef7eb2e8f9f7 | 529 | /* In current implementation, USBPFDCLK is not used for USB FS. */ |
<> | 144:ef7eb2e8f9f7 | 530 | assert(kCLOCK_UsbSrcUsbPfd != src); |
<> | 144:ef7eb2e8f9f7 | 531 | |
<> | 144:ef7eb2e8f9f7 | 532 | bool ret = true; |
<> | 144:ef7eb2e8f9f7 | 533 | |
<> | 144:ef7eb2e8f9f7 | 534 | CLOCK_DisableClock(kCLOCK_Usbfs0); |
<> | 144:ef7eb2e8f9f7 | 535 | |
<> | 144:ef7eb2e8f9f7 | 536 | if (kCLOCK_UsbSrcExt == src) |
<> | 144:ef7eb2e8f9f7 | 537 | { |
<> | 144:ef7eb2e8f9f7 | 538 | SIM->SOPT2 &= ~SIM_SOPT2_USBSRC_MASK; |
<> | 144:ef7eb2e8f9f7 | 539 | } |
<> | 144:ef7eb2e8f9f7 | 540 | else |
<> | 144:ef7eb2e8f9f7 | 541 | { |
<> | 144:ef7eb2e8f9f7 | 542 | switch (freq) |
<> | 144:ef7eb2e8f9f7 | 543 | { |
<> | 144:ef7eb2e8f9f7 | 544 | case 120000000U: |
<> | 144:ef7eb2e8f9f7 | 545 | SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC(1); |
<> | 144:ef7eb2e8f9f7 | 546 | break; |
<> | 144:ef7eb2e8f9f7 | 547 | case 96000000U: |
<> | 144:ef7eb2e8f9f7 | 548 | SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(1) | SIM_CLKDIV2_USBFRAC(0); |
<> | 144:ef7eb2e8f9f7 | 549 | break; |
<> | 144:ef7eb2e8f9f7 | 550 | case 72000000U: |
<> | 144:ef7eb2e8f9f7 | 551 | SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC(1); |
<> | 144:ef7eb2e8f9f7 | 552 | break; |
<> | 144:ef7eb2e8f9f7 | 553 | case 48000000U: |
<> | 144:ef7eb2e8f9f7 | 554 | SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0) | SIM_CLKDIV2_USBFRAC(0); |
<> | 144:ef7eb2e8f9f7 | 555 | break; |
<> | 144:ef7eb2e8f9f7 | 556 | default: |
<> | 144:ef7eb2e8f9f7 | 557 | ret = false; |
<> | 144:ef7eb2e8f9f7 | 558 | break; |
<> | 144:ef7eb2e8f9f7 | 559 | } |
<> | 144:ef7eb2e8f9f7 | 560 | |
<> | 144:ef7eb2e8f9f7 | 561 | SIM->SOPT2 = ((SIM->SOPT2 & ~(SIM_SOPT2_PLLFLLSEL_MASK | SIM_SOPT2_USBSRC_MASK)) | (uint32_t)src); |
<> | 144:ef7eb2e8f9f7 | 562 | } |
<> | 144:ef7eb2e8f9f7 | 563 | |
<> | 144:ef7eb2e8f9f7 | 564 | CLOCK_EnableClock(kCLOCK_Usbfs0); |
<> | 144:ef7eb2e8f9f7 | 565 | |
<> | 144:ef7eb2e8f9f7 | 566 | if (kCLOCK_UsbSrcIrc48M == src) |
<> | 144:ef7eb2e8f9f7 | 567 | { |
<> | 144:ef7eb2e8f9f7 | 568 | USB0->CLK_RECOVER_IRC_EN = 0x03U; |
<> | 144:ef7eb2e8f9f7 | 569 | USB0->CLK_RECOVER_CTRL |= USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK; |
<> | 144:ef7eb2e8f9f7 | 570 | } |
<> | 144:ef7eb2e8f9f7 | 571 | return ret; |
<> | 144:ef7eb2e8f9f7 | 572 | } |
<> | 144:ef7eb2e8f9f7 | 573 | |
<> | 144:ef7eb2e8f9f7 | 574 | bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq) |
<> | 144:ef7eb2e8f9f7 | 575 | { |
<> | 144:ef7eb2e8f9f7 | 576 | volatile uint32_t i; |
<> | 144:ef7eb2e8f9f7 | 577 | |
<> | 144:ef7eb2e8f9f7 | 578 | /* |
<> | 144:ef7eb2e8f9f7 | 579 | * In order to bring up the internal 480MHz USB PLL clock, should make sure: |
<> | 144:ef7eb2e8f9f7 | 580 | * 1. 32kHz IRC clock enable by setting IRCLKEN bit in MCG_C1 register. |
<> | 144:ef7eb2e8f9f7 | 581 | * 2. External reference clock enable on XTAL by setting ERCLKEN bit in OSC_CR register. |
<> | 144:ef7eb2e8f9f7 | 582 | */ |
<> | 144:ef7eb2e8f9f7 | 583 | assert(MCG->C1 & MCG_C1_IRCLKEN_MASK); |
<> | 144:ef7eb2e8f9f7 | 584 | assert(!(MCG->C2 & MCG_C2_IRCS_MASK)); |
<> | 144:ef7eb2e8f9f7 | 585 | assert(OSC0->CR & OSC_CR_ERCLKEN_MASK); |
<> | 144:ef7eb2e8f9f7 | 586 | |
<> | 144:ef7eb2e8f9f7 | 587 | /* Source and freq are not used for USB HS. */ |
<> | 144:ef7eb2e8f9f7 | 588 | src = src; |
<> | 144:ef7eb2e8f9f7 | 589 | freq = freq; |
<> | 144:ef7eb2e8f9f7 | 590 | |
<> | 144:ef7eb2e8f9f7 | 591 | SIM->SOPT2 |= SIM_SOPT2_USBREGEN_MASK; |
<> | 144:ef7eb2e8f9f7 | 592 | SIM->SCGC3 |= (SIM_SCGC3_USBHS_MASK | SIM_SCGC3_USBHSPHY_MASK); |
<> | 144:ef7eb2e8f9f7 | 593 | |
<> | 144:ef7eb2e8f9f7 | 594 | i = 500000U; |
<> | 144:ef7eb2e8f9f7 | 595 | while (i--) |
<> | 144:ef7eb2e8f9f7 | 596 | { |
<> | 144:ef7eb2e8f9f7 | 597 | __NOP(); |
<> | 144:ef7eb2e8f9f7 | 598 | } |
<> | 144:ef7eb2e8f9f7 | 599 | |
<> | 144:ef7eb2e8f9f7 | 600 | SIM->USBPHYCTL = ((SIM->USBPHYCTL & ~(SIM_USBPHYCTL_USB3VOUTTRG_MASK)) | SIM_USBPHYCTL_USB3VOUTTRG(6U) /* 3.310V */ |
<> | 144:ef7eb2e8f9f7 | 601 | | SIM_USBPHYCTL_USBVREGSEL_MASK); /* VREG_IN1 */ |
<> | 144:ef7eb2e8f9f7 | 602 | |
<> | 144:ef7eb2e8f9f7 | 603 | return true; |
<> | 144:ef7eb2e8f9f7 | 604 | } |
<> | 144:ef7eb2e8f9f7 | 605 | |
<> | 144:ef7eb2e8f9f7 | 606 | uint32_t CLOCK_GetOutClkFreq(void) |
<> | 144:ef7eb2e8f9f7 | 607 | { |
<> | 144:ef7eb2e8f9f7 | 608 | uint32_t mcgoutclk; |
<> | 144:ef7eb2e8f9f7 | 609 | uint32_t clkst = MCG_S_CLKST_VAL; |
<> | 144:ef7eb2e8f9f7 | 610 | uint32_t pllcst = MCG_S2_PLLCST_VAL; |
<> | 144:ef7eb2e8f9f7 | 611 | |
<> | 144:ef7eb2e8f9f7 | 612 | switch (clkst) |
<> | 144:ef7eb2e8f9f7 | 613 | { |
<> | 144:ef7eb2e8f9f7 | 614 | case kMCG_ClkOutStatPll: |
<> | 144:ef7eb2e8f9f7 | 615 | switch (pllcst) |
<> | 144:ef7eb2e8f9f7 | 616 | { |
<> | 144:ef7eb2e8f9f7 | 617 | case kMCG_PllClkSelExtPll: |
<> | 144:ef7eb2e8f9f7 | 618 | mcgoutclk = CLOCK_GetExtPllFreq(); |
<> | 144:ef7eb2e8f9f7 | 619 | break; |
<> | 144:ef7eb2e8f9f7 | 620 | case kMCG_PllClkSelPll0: |
<> | 144:ef7eb2e8f9f7 | 621 | mcgoutclk = CLOCK_GetPll0Freq(); |
<> | 144:ef7eb2e8f9f7 | 622 | break; |
<> | 144:ef7eb2e8f9f7 | 623 | default: |
<> | 144:ef7eb2e8f9f7 | 624 | mcgoutclk = 0U; |
<> | 144:ef7eb2e8f9f7 | 625 | break; |
<> | 144:ef7eb2e8f9f7 | 626 | } |
<> | 144:ef7eb2e8f9f7 | 627 | break; |
<> | 144:ef7eb2e8f9f7 | 628 | case kMCG_ClkOutStatFll: |
<> | 144:ef7eb2e8f9f7 | 629 | mcgoutclk = CLOCK_GetFllFreq(); |
<> | 144:ef7eb2e8f9f7 | 630 | break; |
<> | 144:ef7eb2e8f9f7 | 631 | case kMCG_ClkOutStatInt: |
<> | 144:ef7eb2e8f9f7 | 632 | mcgoutclk = CLOCK_GetInternalRefClkSelectFreq(); |
<> | 144:ef7eb2e8f9f7 | 633 | break; |
<> | 144:ef7eb2e8f9f7 | 634 | case kMCG_ClkOutStatExt: |
<> | 144:ef7eb2e8f9f7 | 635 | mcgoutclk = CLOCK_GetMcgExtClkFreq(); |
<> | 144:ef7eb2e8f9f7 | 636 | break; |
<> | 144:ef7eb2e8f9f7 | 637 | default: |
<> | 144:ef7eb2e8f9f7 | 638 | mcgoutclk = 0U; |
<> | 144:ef7eb2e8f9f7 | 639 | break; |
<> | 144:ef7eb2e8f9f7 | 640 | } |
<> | 144:ef7eb2e8f9f7 | 641 | return mcgoutclk; |
<> | 144:ef7eb2e8f9f7 | 642 | } |
<> | 144:ef7eb2e8f9f7 | 643 | |
<> | 144:ef7eb2e8f9f7 | 644 | uint32_t CLOCK_GetFllFreq(void) |
<> | 144:ef7eb2e8f9f7 | 645 | { |
<> | 144:ef7eb2e8f9f7 | 646 | static const uint16_t fllFactorTable[4][2] = {{640, 732}, {1280, 1464}, {1920, 2197}, {2560, 2929}}; |
<> | 144:ef7eb2e8f9f7 | 647 | |
<> | 144:ef7eb2e8f9f7 | 648 | uint8_t drs, dmx32; |
<> | 144:ef7eb2e8f9f7 | 649 | uint32_t freq; |
<> | 144:ef7eb2e8f9f7 | 650 | |
<> | 144:ef7eb2e8f9f7 | 651 | /* If FLL is not enabled currently, then return 0U. */ |
<> | 144:ef7eb2e8f9f7 | 652 | if ((MCG->C2 & MCG_C2_LP_MASK) || (MCG->S & MCG_S_PLLST_MASK)) |
<> | 144:ef7eb2e8f9f7 | 653 | { |
<> | 144:ef7eb2e8f9f7 | 654 | return 0U; |
<> | 144:ef7eb2e8f9f7 | 655 | } |
<> | 144:ef7eb2e8f9f7 | 656 | |
<> | 144:ef7eb2e8f9f7 | 657 | /* Get FLL reference clock frequency. */ |
<> | 144:ef7eb2e8f9f7 | 658 | freq = CLOCK_GetFllRefClkFreq(); |
<> | 144:ef7eb2e8f9f7 | 659 | if (!freq) |
<> | 144:ef7eb2e8f9f7 | 660 | { |
<> | 144:ef7eb2e8f9f7 | 661 | return freq; |
<> | 144:ef7eb2e8f9f7 | 662 | } |
<> | 144:ef7eb2e8f9f7 | 663 | |
<> | 144:ef7eb2e8f9f7 | 664 | drs = MCG_C4_DRST_DRS_VAL; |
<> | 144:ef7eb2e8f9f7 | 665 | dmx32 = MCG_C4_DMX32_VAL; |
<> | 144:ef7eb2e8f9f7 | 666 | |
<> | 144:ef7eb2e8f9f7 | 667 | return freq * fllFactorTable[drs][dmx32]; |
<> | 144:ef7eb2e8f9f7 | 668 | } |
<> | 144:ef7eb2e8f9f7 | 669 | |
<> | 144:ef7eb2e8f9f7 | 670 | uint32_t CLOCK_GetInternalRefClkFreq(void) |
<> | 144:ef7eb2e8f9f7 | 671 | { |
<> | 144:ef7eb2e8f9f7 | 672 | /* If MCGIRCLK is gated. */ |
<> | 144:ef7eb2e8f9f7 | 673 | if (!(MCG->C1 & MCG_C1_IRCLKEN_MASK)) |
<> | 144:ef7eb2e8f9f7 | 674 | { |
<> | 144:ef7eb2e8f9f7 | 675 | return 0U; |
<> | 144:ef7eb2e8f9f7 | 676 | } |
<> | 144:ef7eb2e8f9f7 | 677 | |
<> | 144:ef7eb2e8f9f7 | 678 | return CLOCK_GetInternalRefClkSelectFreq(); |
<> | 144:ef7eb2e8f9f7 | 679 | } |
<> | 144:ef7eb2e8f9f7 | 680 | |
<> | 144:ef7eb2e8f9f7 | 681 | uint32_t CLOCK_GetFixedFreqClkFreq(void) |
<> | 144:ef7eb2e8f9f7 | 682 | { |
<> | 144:ef7eb2e8f9f7 | 683 | uint32_t freq = CLOCK_GetFllRefClkFreq(); |
<> | 144:ef7eb2e8f9f7 | 684 | |
<> | 144:ef7eb2e8f9f7 | 685 | /* MCGFFCLK must be no more than MCGOUTCLK/8. */ |
<> | 144:ef7eb2e8f9f7 | 686 | if ((freq) && (freq <= (CLOCK_GetOutClkFreq() / 8U))) |
<> | 144:ef7eb2e8f9f7 | 687 | { |
<> | 144:ef7eb2e8f9f7 | 688 | return freq; |
<> | 144:ef7eb2e8f9f7 | 689 | } |
<> | 144:ef7eb2e8f9f7 | 690 | else |
<> | 144:ef7eb2e8f9f7 | 691 | { |
<> | 144:ef7eb2e8f9f7 | 692 | return 0U; |
<> | 144:ef7eb2e8f9f7 | 693 | } |
<> | 144:ef7eb2e8f9f7 | 694 | } |
<> | 144:ef7eb2e8f9f7 | 695 | |
<> | 144:ef7eb2e8f9f7 | 696 | uint32_t CLOCK_GetPll0Freq(void) |
<> | 144:ef7eb2e8f9f7 | 697 | { |
<> | 144:ef7eb2e8f9f7 | 698 | uint32_t mcgpll0clk; |
<> | 144:ef7eb2e8f9f7 | 699 | |
<> | 144:ef7eb2e8f9f7 | 700 | /* If PLL0 is not enabled, return 0. */ |
<> | 144:ef7eb2e8f9f7 | 701 | if (!(MCG->S & MCG_S_LOCK0_MASK)) |
<> | 144:ef7eb2e8f9f7 | 702 | { |
<> | 144:ef7eb2e8f9f7 | 703 | return 0U; |
<> | 144:ef7eb2e8f9f7 | 704 | } |
<> | 144:ef7eb2e8f9f7 | 705 | |
<> | 144:ef7eb2e8f9f7 | 706 | mcgpll0clk = CLOCK_GetPll0RefFreq(); |
<> | 144:ef7eb2e8f9f7 | 707 | |
<> | 144:ef7eb2e8f9f7 | 708 | mcgpll0clk /= (FSL_FEATURE_MCG_PLL_PRDIV_BASE + MCG_C5_PRDIV0_VAL); |
<> | 144:ef7eb2e8f9f7 | 709 | mcgpll0clk *= (FSL_FEATURE_MCG_PLL_VDIV_BASE + MCG_C6_VDIV0_VAL); |
<> | 144:ef7eb2e8f9f7 | 710 | |
<> | 144:ef7eb2e8f9f7 | 711 | mcgpll0clk >>= 1U; |
<> | 144:ef7eb2e8f9f7 | 712 | return mcgpll0clk; |
<> | 144:ef7eb2e8f9f7 | 713 | } |
<> | 144:ef7eb2e8f9f7 | 714 | |
<> | 144:ef7eb2e8f9f7 | 715 | uint32_t CLOCK_GetExtPllFreq(void) |
<> | 144:ef7eb2e8f9f7 | 716 | { |
<> | 144:ef7eb2e8f9f7 | 717 | return s_extPllFreq; |
<> | 144:ef7eb2e8f9f7 | 718 | } |
<> | 144:ef7eb2e8f9f7 | 719 | |
<> | 144:ef7eb2e8f9f7 | 720 | void CLOCK_SetExtPllFreq(uint32_t freq) |
<> | 144:ef7eb2e8f9f7 | 721 | { |
<> | 144:ef7eb2e8f9f7 | 722 | s_extPllFreq = freq; |
<> | 144:ef7eb2e8f9f7 | 723 | } |
<> | 144:ef7eb2e8f9f7 | 724 | |
<> | 144:ef7eb2e8f9f7 | 725 | status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel) |
<> | 144:ef7eb2e8f9f7 | 726 | { |
<> | 144:ef7eb2e8f9f7 | 727 | bool needDelay; |
<> | 144:ef7eb2e8f9f7 | 728 | uint32_t i; |
<> | 144:ef7eb2e8f9f7 | 729 | |
<> | 144:ef7eb2e8f9f7 | 730 | #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) |
<> | 144:ef7eb2e8f9f7 | 731 | /* If change MCG_C7[OSCSEL] and external reference clock is system clock source, return error. */ |
<> | 144:ef7eb2e8f9f7 | 732 | if ((MCG_C7_OSCSEL_VAL != oscsel) && (!(MCG->S & MCG_S_IREFST_MASK))) |
<> | 144:ef7eb2e8f9f7 | 733 | { |
<> | 144:ef7eb2e8f9f7 | 734 | return kStatus_MCG_SourceUsed; |
<> | 144:ef7eb2e8f9f7 | 735 | } |
<> | 144:ef7eb2e8f9f7 | 736 | #endif /* MCG_CONFIG_CHECK_PARAM */ |
<> | 144:ef7eb2e8f9f7 | 737 | |
<> | 144:ef7eb2e8f9f7 | 738 | if (MCG_C7_OSCSEL_VAL != oscsel) |
<> | 144:ef7eb2e8f9f7 | 739 | { |
<> | 144:ef7eb2e8f9f7 | 740 | /* If change OSCSEL, need to delay, ERR009878. */ |
<> | 144:ef7eb2e8f9f7 | 741 | needDelay = true; |
<> | 144:ef7eb2e8f9f7 | 742 | } |
<> | 144:ef7eb2e8f9f7 | 743 | else |
<> | 144:ef7eb2e8f9f7 | 744 | { |
<> | 144:ef7eb2e8f9f7 | 745 | needDelay = false; |
<> | 144:ef7eb2e8f9f7 | 746 | } |
<> | 144:ef7eb2e8f9f7 | 747 | |
<> | 144:ef7eb2e8f9f7 | 748 | MCG->C7 = (MCG->C7 & ~MCG_C7_OSCSEL_MASK) | MCG_C7_OSCSEL(oscsel); |
<> | 144:ef7eb2e8f9f7 | 749 | if (kMCG_OscselOsc == oscsel) |
<> | 144:ef7eb2e8f9f7 | 750 | { |
<> | 144:ef7eb2e8f9f7 | 751 | if (MCG->C2 & MCG_C2_EREFS_MASK) |
<> | 144:ef7eb2e8f9f7 | 752 | { |
<> | 144:ef7eb2e8f9f7 | 753 | while (!(MCG->S & MCG_S_OSCINIT0_MASK)) |
<> | 144:ef7eb2e8f9f7 | 754 | { |
<> | 144:ef7eb2e8f9f7 | 755 | } |
<> | 144:ef7eb2e8f9f7 | 756 | } |
<> | 144:ef7eb2e8f9f7 | 757 | } |
<> | 144:ef7eb2e8f9f7 | 758 | |
<> | 144:ef7eb2e8f9f7 | 759 | if (needDelay) |
<> | 144:ef7eb2e8f9f7 | 760 | { |
<> | 144:ef7eb2e8f9f7 | 761 | /* ERR009878 Delay at least 50 micro-seconds for external clock change valid. */ |
<> | 144:ef7eb2e8f9f7 | 762 | i = 1500U; |
<> | 144:ef7eb2e8f9f7 | 763 | while (i--) |
<> | 144:ef7eb2e8f9f7 | 764 | { |
<> | 144:ef7eb2e8f9f7 | 765 | __NOP(); |
<> | 144:ef7eb2e8f9f7 | 766 | } |
<> | 144:ef7eb2e8f9f7 | 767 | } |
<> | 144:ef7eb2e8f9f7 | 768 | |
<> | 144:ef7eb2e8f9f7 | 769 | return kStatus_Success; |
<> | 144:ef7eb2e8f9f7 | 770 | } |
<> | 144:ef7eb2e8f9f7 | 771 | |
<> | 144:ef7eb2e8f9f7 | 772 | status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv) |
<> | 144:ef7eb2e8f9f7 | 773 | { |
<> | 144:ef7eb2e8f9f7 | 774 | uint32_t mcgOutClkState = MCG_S_CLKST_VAL; |
<> | 144:ef7eb2e8f9f7 | 775 | mcg_irc_mode_t curIrcs = (mcg_irc_mode_t)MCG_S_IRCST_VAL; |
<> | 144:ef7eb2e8f9f7 | 776 | uint8_t curFcrdiv = MCG_SC_FCRDIV_VAL; |
<> | 144:ef7eb2e8f9f7 | 777 | |
<> | 144:ef7eb2e8f9f7 | 778 | #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) |
<> | 144:ef7eb2e8f9f7 | 779 | /* If MCGIRCLK is used as system clock source. */ |
<> | 144:ef7eb2e8f9f7 | 780 | if (kMCG_ClkOutStatInt == mcgOutClkState) |
<> | 144:ef7eb2e8f9f7 | 781 | { |
<> | 144:ef7eb2e8f9f7 | 782 | /* If need to change MCGIRCLK source or driver, return error. */ |
<> | 144:ef7eb2e8f9f7 | 783 | if (((kMCG_IrcFast == curIrcs) && (fcrdiv != curFcrdiv)) || (ircs != curIrcs)) |
<> | 144:ef7eb2e8f9f7 | 784 | { |
<> | 144:ef7eb2e8f9f7 | 785 | return kStatus_MCG_SourceUsed; |
<> | 144:ef7eb2e8f9f7 | 786 | } |
<> | 144:ef7eb2e8f9f7 | 787 | } |
<> | 144:ef7eb2e8f9f7 | 788 | #endif |
<> | 144:ef7eb2e8f9f7 | 789 | |
<> | 144:ef7eb2e8f9f7 | 790 | /* If need to update the FCRDIV. */ |
<> | 144:ef7eb2e8f9f7 | 791 | if (fcrdiv != curFcrdiv) |
<> | 144:ef7eb2e8f9f7 | 792 | { |
<> | 144:ef7eb2e8f9f7 | 793 | /* If fast IRC is in use currently, change to slow IRC. */ |
<> | 144:ef7eb2e8f9f7 | 794 | if ((kMCG_IrcFast == curIrcs) && ((mcgOutClkState == kMCG_ClkOutStatInt) || (MCG->C1 & MCG_C1_IRCLKEN_MASK))) |
<> | 144:ef7eb2e8f9f7 | 795 | { |
<> | 144:ef7eb2e8f9f7 | 796 | MCG->C2 = ((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow))); |
<> | 144:ef7eb2e8f9f7 | 797 | while (MCG_S_IRCST_VAL != kMCG_IrcSlow) |
<> | 144:ef7eb2e8f9f7 | 798 | { |
<> | 144:ef7eb2e8f9f7 | 799 | } |
<> | 144:ef7eb2e8f9f7 | 800 | } |
<> | 144:ef7eb2e8f9f7 | 801 | /* Update FCRDIV. */ |
<> | 144:ef7eb2e8f9f7 | 802 | MCG->SC = (MCG->SC & ~(MCG_SC_FCRDIV_MASK | MCG_SC_ATMF_MASK | MCG_SC_LOCS0_MASK)) | MCG_SC_FCRDIV(fcrdiv); |
<> | 144:ef7eb2e8f9f7 | 803 | } |
<> | 144:ef7eb2e8f9f7 | 804 | |
<> | 144:ef7eb2e8f9f7 | 805 | /* Set internal reference clock selection. */ |
<> | 144:ef7eb2e8f9f7 | 806 | MCG->C2 = (MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(ircs)); |
<> | 144:ef7eb2e8f9f7 | 807 | MCG->C1 = (MCG->C1 & ~(MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK)) | (uint8_t)enableMode; |
<> | 144:ef7eb2e8f9f7 | 808 | |
<> | 144:ef7eb2e8f9f7 | 809 | /* If MCGIRCLK is used, need to wait for MCG_S_IRCST. */ |
<> | 144:ef7eb2e8f9f7 | 810 | if ((mcgOutClkState == kMCG_ClkOutStatInt) || (enableMode & kMCG_IrclkEnable)) |
<> | 144:ef7eb2e8f9f7 | 811 | { |
<> | 144:ef7eb2e8f9f7 | 812 | while (MCG_S_IRCST_VAL != ircs) |
<> | 144:ef7eb2e8f9f7 | 813 | { |
<> | 144:ef7eb2e8f9f7 | 814 | } |
<> | 144:ef7eb2e8f9f7 | 815 | } |
<> | 144:ef7eb2e8f9f7 | 816 | |
<> | 144:ef7eb2e8f9f7 | 817 | return kStatus_Success; |
<> | 144:ef7eb2e8f9f7 | 818 | } |
<> | 144:ef7eb2e8f9f7 | 819 | |
<> | 144:ef7eb2e8f9f7 | 820 | uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv) |
<> | 144:ef7eb2e8f9f7 | 821 | { |
<> | 144:ef7eb2e8f9f7 | 822 | uint8_t ret_prdiv; /* PRDIV to return. */ |
<> | 144:ef7eb2e8f9f7 | 823 | uint8_t ret_vdiv; /* VDIV to return. */ |
<> | 144:ef7eb2e8f9f7 | 824 | uint8_t prdiv_min; /* Min PRDIV value to make reference clock in allowed range. */ |
<> | 144:ef7eb2e8f9f7 | 825 | uint8_t prdiv_max; /* Max PRDIV value to make reference clock in allowed range. */ |
<> | 144:ef7eb2e8f9f7 | 826 | uint8_t prdiv_cur; /* PRDIV value for iteration. */ |
<> | 144:ef7eb2e8f9f7 | 827 | uint8_t vdiv_cur; /* VDIV value for iteration. */ |
<> | 144:ef7eb2e8f9f7 | 828 | uint32_t ret_freq = 0U; /* PLL output fequency to return. */ |
<> | 144:ef7eb2e8f9f7 | 829 | uint32_t diff = 0xFFFFFFFFU; /* Difference between desireFreq and return frequency. */ |
<> | 144:ef7eb2e8f9f7 | 830 | uint32_t ref_div; /* Reference frequency after PRDIV. */ |
<> | 144:ef7eb2e8f9f7 | 831 | |
<> | 144:ef7eb2e8f9f7 | 832 | /* |
<> | 144:ef7eb2e8f9f7 | 833 | Steps: |
<> | 144:ef7eb2e8f9f7 | 834 | 1. Get allowed prdiv with such rules: |
<> | 144:ef7eb2e8f9f7 | 835 | 1). refFreq / prdiv >= FSL_FEATURE_MCG_PLL_REF_MIN. |
<> | 144:ef7eb2e8f9f7 | 836 | 2). refFreq / prdiv <= FSL_FEATURE_MCG_PLL_REF_MAX. |
<> | 144:ef7eb2e8f9f7 | 837 | 2. For each allowed prdiv, there are two candidate vdiv values: |
<> | 144:ef7eb2e8f9f7 | 838 | 1). (desireFreq / (refFreq / prdiv)). |
<> | 144:ef7eb2e8f9f7 | 839 | 2). (desireFreq / (refFreq / prdiv)) + 1. |
<> | 144:ef7eb2e8f9f7 | 840 | If could get the precise desired frequency, return current prdiv and |
<> | 144:ef7eb2e8f9f7 | 841 | vdiv directly. Otherwise choose the one which is closer to desired |
<> | 144:ef7eb2e8f9f7 | 842 | frequency. |
<> | 144:ef7eb2e8f9f7 | 843 | */ |
<> | 144:ef7eb2e8f9f7 | 844 | |
<> | 144:ef7eb2e8f9f7 | 845 | /* Reference frequency is out of range. */ |
<> | 144:ef7eb2e8f9f7 | 846 | if ((refFreq < FSL_FEATURE_MCG_PLL_REF_MIN) || |
<> | 144:ef7eb2e8f9f7 | 847 | (refFreq > (FSL_FEATURE_MCG_PLL_REF_MAX * (FSL_FEATURE_MCG_PLL_PRDIV_MAX + FSL_FEATURE_MCG_PLL_PRDIV_BASE)))) |
<> | 144:ef7eb2e8f9f7 | 848 | { |
<> | 144:ef7eb2e8f9f7 | 849 | return 0U; |
<> | 144:ef7eb2e8f9f7 | 850 | } |
<> | 144:ef7eb2e8f9f7 | 851 | |
<> | 144:ef7eb2e8f9f7 | 852 | /* refFreq/PRDIV must in a range. First get the allowed PRDIV range. */ |
<> | 144:ef7eb2e8f9f7 | 853 | prdiv_max = refFreq / FSL_FEATURE_MCG_PLL_REF_MIN; |
<> | 144:ef7eb2e8f9f7 | 854 | prdiv_min = (refFreq + FSL_FEATURE_MCG_PLL_REF_MAX - 1U) / FSL_FEATURE_MCG_PLL_REF_MAX; |
<> | 144:ef7eb2e8f9f7 | 855 | |
<> | 144:ef7eb2e8f9f7 | 856 | desireFreq *= 2U; |
<> | 144:ef7eb2e8f9f7 | 857 | |
<> | 144:ef7eb2e8f9f7 | 858 | /* PRDIV traversal. */ |
<> | 144:ef7eb2e8f9f7 | 859 | for (prdiv_cur = prdiv_max; prdiv_cur >= prdiv_min; prdiv_cur--) |
<> | 144:ef7eb2e8f9f7 | 860 | { |
<> | 144:ef7eb2e8f9f7 | 861 | /* Reference frequency after PRDIV. */ |
<> | 144:ef7eb2e8f9f7 | 862 | ref_div = refFreq / prdiv_cur; |
<> | 144:ef7eb2e8f9f7 | 863 | |
<> | 144:ef7eb2e8f9f7 | 864 | vdiv_cur = desireFreq / ref_div; |
<> | 144:ef7eb2e8f9f7 | 865 | |
<> | 144:ef7eb2e8f9f7 | 866 | if ((vdiv_cur < FSL_FEATURE_MCG_PLL_VDIV_BASE - 1U) || (vdiv_cur > FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) |
<> | 144:ef7eb2e8f9f7 | 867 | { |
<> | 144:ef7eb2e8f9f7 | 868 | /* No VDIV is available with this PRDIV. */ |
<> | 144:ef7eb2e8f9f7 | 869 | continue; |
<> | 144:ef7eb2e8f9f7 | 870 | } |
<> | 144:ef7eb2e8f9f7 | 871 | |
<> | 144:ef7eb2e8f9f7 | 872 | ret_freq = vdiv_cur * ref_div; |
<> | 144:ef7eb2e8f9f7 | 873 | |
<> | 144:ef7eb2e8f9f7 | 874 | if (vdiv_cur >= FSL_FEATURE_MCG_PLL_VDIV_BASE) |
<> | 144:ef7eb2e8f9f7 | 875 | { |
<> | 144:ef7eb2e8f9f7 | 876 | if (ret_freq == desireFreq) /* If desire frequency is got. */ |
<> | 144:ef7eb2e8f9f7 | 877 | { |
<> | 144:ef7eb2e8f9f7 | 878 | *prdiv = prdiv_cur - FSL_FEATURE_MCG_PLL_PRDIV_BASE; |
<> | 144:ef7eb2e8f9f7 | 879 | *vdiv = vdiv_cur - FSL_FEATURE_MCG_PLL_VDIV_BASE; |
<> | 144:ef7eb2e8f9f7 | 880 | return ret_freq / 2U; |
<> | 144:ef7eb2e8f9f7 | 881 | } |
<> | 144:ef7eb2e8f9f7 | 882 | /* New PRDIV/VDIV is closer. */ |
<> | 144:ef7eb2e8f9f7 | 883 | if (diff > desireFreq - ret_freq) |
<> | 144:ef7eb2e8f9f7 | 884 | { |
<> | 144:ef7eb2e8f9f7 | 885 | diff = desireFreq - ret_freq; |
<> | 144:ef7eb2e8f9f7 | 886 | ret_prdiv = prdiv_cur; |
<> | 144:ef7eb2e8f9f7 | 887 | ret_vdiv = vdiv_cur; |
<> | 144:ef7eb2e8f9f7 | 888 | } |
<> | 144:ef7eb2e8f9f7 | 889 | } |
<> | 144:ef7eb2e8f9f7 | 890 | vdiv_cur++; |
<> | 144:ef7eb2e8f9f7 | 891 | if (vdiv_cur <= (FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) |
<> | 144:ef7eb2e8f9f7 | 892 | { |
<> | 144:ef7eb2e8f9f7 | 893 | ret_freq += ref_div; |
<> | 144:ef7eb2e8f9f7 | 894 | /* New PRDIV/VDIV is closer. */ |
<> | 144:ef7eb2e8f9f7 | 895 | if (diff > ret_freq - desireFreq) |
<> | 144:ef7eb2e8f9f7 | 896 | { |
<> | 144:ef7eb2e8f9f7 | 897 | diff = ret_freq - desireFreq; |
<> | 144:ef7eb2e8f9f7 | 898 | ret_prdiv = prdiv_cur; |
<> | 144:ef7eb2e8f9f7 | 899 | ret_vdiv = vdiv_cur; |
<> | 144:ef7eb2e8f9f7 | 900 | } |
<> | 144:ef7eb2e8f9f7 | 901 | } |
<> | 144:ef7eb2e8f9f7 | 902 | } |
<> | 144:ef7eb2e8f9f7 | 903 | |
<> | 144:ef7eb2e8f9f7 | 904 | if (0xFFFFFFFFU != diff) |
<> | 144:ef7eb2e8f9f7 | 905 | { |
<> | 144:ef7eb2e8f9f7 | 906 | /* PRDIV/VDIV found. */ |
<> | 144:ef7eb2e8f9f7 | 907 | *prdiv = ret_prdiv - FSL_FEATURE_MCG_PLL_PRDIV_BASE; |
<> | 144:ef7eb2e8f9f7 | 908 | *vdiv = ret_vdiv - FSL_FEATURE_MCG_PLL_VDIV_BASE; |
<> | 144:ef7eb2e8f9f7 | 909 | ret_freq = (refFreq / ret_prdiv) * ret_vdiv; |
<> | 144:ef7eb2e8f9f7 | 910 | return ret_freq / 2U; |
<> | 144:ef7eb2e8f9f7 | 911 | } |
<> | 144:ef7eb2e8f9f7 | 912 | else |
<> | 144:ef7eb2e8f9f7 | 913 | { |
<> | 144:ef7eb2e8f9f7 | 914 | /* No proper PRDIV/VDIV found. */ |
<> | 144:ef7eb2e8f9f7 | 915 | return 0U; |
<> | 144:ef7eb2e8f9f7 | 916 | } |
<> | 144:ef7eb2e8f9f7 | 917 | } |
<> | 144:ef7eb2e8f9f7 | 918 | |
<> | 144:ef7eb2e8f9f7 | 919 | void CLOCK_EnablePll0(mcg_pll_config_t const *config) |
<> | 144:ef7eb2e8f9f7 | 920 | { |
<> | 144:ef7eb2e8f9f7 | 921 | assert(config); |
<> | 144:ef7eb2e8f9f7 | 922 | |
<> | 144:ef7eb2e8f9f7 | 923 | uint8_t mcg_c5 = 0U; |
<> | 144:ef7eb2e8f9f7 | 924 | |
<> | 144:ef7eb2e8f9f7 | 925 | mcg_c5 |= MCG_C5_PRDIV0(config->prdiv); |
<> | 144:ef7eb2e8f9f7 | 926 | MCG->C5 = mcg_c5; /* Disable the PLL first. */ |
<> | 144:ef7eb2e8f9f7 | 927 | |
<> | 144:ef7eb2e8f9f7 | 928 | MCG->C6 = (MCG->C6 & ~MCG_C6_VDIV0_MASK) | MCG_C6_VDIV0(config->vdiv); |
<> | 144:ef7eb2e8f9f7 | 929 | |
<> | 144:ef7eb2e8f9f7 | 930 | /* Set enable mode. */ |
<> | 144:ef7eb2e8f9f7 | 931 | MCG->C5 |= ((uint32_t)kMCG_PllEnableIndependent | (uint32_t)config->enableMode); |
<> | 144:ef7eb2e8f9f7 | 932 | |
<> | 144:ef7eb2e8f9f7 | 933 | /* Wait for PLL lock. */ |
<> | 144:ef7eb2e8f9f7 | 934 | while (!(MCG->S & MCG_S_LOCK0_MASK)) |
<> | 144:ef7eb2e8f9f7 | 935 | { |
<> | 144:ef7eb2e8f9f7 | 936 | } |
<> | 144:ef7eb2e8f9f7 | 937 | } |
<> | 144:ef7eb2e8f9f7 | 938 | |
<> | 144:ef7eb2e8f9f7 | 939 | void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode) |
<> | 144:ef7eb2e8f9f7 | 940 | { |
<> | 144:ef7eb2e8f9f7 | 941 | /* Clear the previous flag, MCG_SC[LOCS0]. */ |
<> | 144:ef7eb2e8f9f7 | 942 | MCG->SC &= ~MCG_SC_ATMF_MASK; |
<> | 144:ef7eb2e8f9f7 | 943 | |
<> | 144:ef7eb2e8f9f7 | 944 | if (kMCG_MonitorNone == mode) |
<> | 144:ef7eb2e8f9f7 | 945 | { |
<> | 144:ef7eb2e8f9f7 | 946 | MCG->C6 &= ~MCG_C6_CME0_MASK; |
<> | 144:ef7eb2e8f9f7 | 947 | } |
<> | 144:ef7eb2e8f9f7 | 948 | else |
<> | 144:ef7eb2e8f9f7 | 949 | { |
<> | 144:ef7eb2e8f9f7 | 950 | if (kMCG_MonitorInt == mode) |
<> | 144:ef7eb2e8f9f7 | 951 | { |
<> | 144:ef7eb2e8f9f7 | 952 | MCG->C2 &= ~MCG_C2_LOCRE0_MASK; |
<> | 144:ef7eb2e8f9f7 | 953 | } |
<> | 144:ef7eb2e8f9f7 | 954 | else |
<> | 144:ef7eb2e8f9f7 | 955 | { |
<> | 144:ef7eb2e8f9f7 | 956 | MCG->C2 |= MCG_C2_LOCRE0_MASK; |
<> | 144:ef7eb2e8f9f7 | 957 | } |
<> | 144:ef7eb2e8f9f7 | 958 | MCG->C6 |= MCG_C6_CME0_MASK; |
<> | 144:ef7eb2e8f9f7 | 959 | } |
<> | 144:ef7eb2e8f9f7 | 960 | } |
<> | 144:ef7eb2e8f9f7 | 961 | |
<> | 144:ef7eb2e8f9f7 | 962 | void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode) |
<> | 144:ef7eb2e8f9f7 | 963 | { |
<> | 144:ef7eb2e8f9f7 | 964 | uint8_t mcg_c8 = MCG->C8; |
<> | 144:ef7eb2e8f9f7 | 965 | |
<> | 144:ef7eb2e8f9f7 | 966 | mcg_c8 &= ~(MCG_C8_CME1_MASK | MCG_C8_LOCRE1_MASK); |
<> | 144:ef7eb2e8f9f7 | 967 | |
<> | 144:ef7eb2e8f9f7 | 968 | if (kMCG_MonitorNone != mode) |
<> | 144:ef7eb2e8f9f7 | 969 | { |
<> | 144:ef7eb2e8f9f7 | 970 | if (kMCG_MonitorReset == mode) |
<> | 144:ef7eb2e8f9f7 | 971 | { |
<> | 144:ef7eb2e8f9f7 | 972 | mcg_c8 |= MCG_C8_LOCRE1_MASK; |
<> | 144:ef7eb2e8f9f7 | 973 | } |
<> | 144:ef7eb2e8f9f7 | 974 | mcg_c8 |= MCG_C8_CME1_MASK; |
<> | 144:ef7eb2e8f9f7 | 975 | } |
<> | 144:ef7eb2e8f9f7 | 976 | MCG->C8 = mcg_c8; |
<> | 144:ef7eb2e8f9f7 | 977 | } |
<> | 144:ef7eb2e8f9f7 | 978 | |
<> | 144:ef7eb2e8f9f7 | 979 | void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode) |
<> | 144:ef7eb2e8f9f7 | 980 | { |
<> | 144:ef7eb2e8f9f7 | 981 | uint8_t mcg_c8; |
<> | 144:ef7eb2e8f9f7 | 982 | |
<> | 144:ef7eb2e8f9f7 | 983 | /* Clear previous flag. */ |
<> | 144:ef7eb2e8f9f7 | 984 | MCG->S = MCG_S_LOLS0_MASK; |
<> | 144:ef7eb2e8f9f7 | 985 | |
<> | 144:ef7eb2e8f9f7 | 986 | if (kMCG_MonitorNone == mode) |
<> | 144:ef7eb2e8f9f7 | 987 | { |
<> | 144:ef7eb2e8f9f7 | 988 | MCG->C6 &= ~MCG_C6_LOLIE0_MASK; |
<> | 144:ef7eb2e8f9f7 | 989 | } |
<> | 144:ef7eb2e8f9f7 | 990 | else |
<> | 144:ef7eb2e8f9f7 | 991 | { |
<> | 144:ef7eb2e8f9f7 | 992 | mcg_c8 = MCG->C8; |
<> | 144:ef7eb2e8f9f7 | 993 | |
<> | 144:ef7eb2e8f9f7 | 994 | mcg_c8 &= ~MCG_C8_LOCS1_MASK; |
<> | 144:ef7eb2e8f9f7 | 995 | |
<> | 144:ef7eb2e8f9f7 | 996 | if (kMCG_MonitorInt == mode) |
<> | 144:ef7eb2e8f9f7 | 997 | { |
<> | 144:ef7eb2e8f9f7 | 998 | mcg_c8 &= ~MCG_C8_LOLRE_MASK; |
<> | 144:ef7eb2e8f9f7 | 999 | } |
<> | 144:ef7eb2e8f9f7 | 1000 | else |
<> | 144:ef7eb2e8f9f7 | 1001 | { |
<> | 144:ef7eb2e8f9f7 | 1002 | mcg_c8 |= MCG_C8_LOLRE_MASK; |
<> | 144:ef7eb2e8f9f7 | 1003 | } |
<> | 144:ef7eb2e8f9f7 | 1004 | MCG->C8 = mcg_c8; |
<> | 144:ef7eb2e8f9f7 | 1005 | MCG->C6 |= MCG_C6_LOLIE0_MASK; |
<> | 144:ef7eb2e8f9f7 | 1006 | } |
<> | 144:ef7eb2e8f9f7 | 1007 | } |
<> | 144:ef7eb2e8f9f7 | 1008 | |
<> | 144:ef7eb2e8f9f7 | 1009 | void CLOCK_SetExtPllMonitorMode(mcg_monitor_mode_t mode) |
<> | 144:ef7eb2e8f9f7 | 1010 | { |
<> | 144:ef7eb2e8f9f7 | 1011 | uint8_t mcg_c9 = MCG->C9; |
<> | 144:ef7eb2e8f9f7 | 1012 | |
<> | 144:ef7eb2e8f9f7 | 1013 | mcg_c9 &= ~(MCG_C9_PLL_LOCRE_MASK | MCG_C9_PLL_CME_MASK); |
<> | 144:ef7eb2e8f9f7 | 1014 | |
<> | 144:ef7eb2e8f9f7 | 1015 | if (kMCG_MonitorNone != mode) |
<> | 144:ef7eb2e8f9f7 | 1016 | { |
<> | 144:ef7eb2e8f9f7 | 1017 | if (kMCG_MonitorReset == mode) |
<> | 144:ef7eb2e8f9f7 | 1018 | { |
<> | 144:ef7eb2e8f9f7 | 1019 | mcg_c9 |= MCG_C9_PLL_LOCRE_MASK; |
<> | 144:ef7eb2e8f9f7 | 1020 | } |
<> | 144:ef7eb2e8f9f7 | 1021 | mcg_c9 |= MCG_C9_PLL_CME_MASK; |
<> | 144:ef7eb2e8f9f7 | 1022 | } |
<> | 144:ef7eb2e8f9f7 | 1023 | MCG->C9 = mcg_c9; |
<> | 144:ef7eb2e8f9f7 | 1024 | } |
<> | 144:ef7eb2e8f9f7 | 1025 | |
<> | 144:ef7eb2e8f9f7 | 1026 | uint32_t CLOCK_GetStatusFlags(void) |
<> | 144:ef7eb2e8f9f7 | 1027 | { |
<> | 144:ef7eb2e8f9f7 | 1028 | uint32_t ret = 0U; |
<> | 144:ef7eb2e8f9f7 | 1029 | uint8_t mcg_s = MCG->S; |
<> | 144:ef7eb2e8f9f7 | 1030 | |
<> | 144:ef7eb2e8f9f7 | 1031 | if (MCG->SC & MCG_SC_LOCS0_MASK) |
<> | 144:ef7eb2e8f9f7 | 1032 | { |
<> | 144:ef7eb2e8f9f7 | 1033 | ret |= kMCG_Osc0LostFlag; |
<> | 144:ef7eb2e8f9f7 | 1034 | } |
<> | 144:ef7eb2e8f9f7 | 1035 | if (mcg_s & MCG_S_OSCINIT0_MASK) |
<> | 144:ef7eb2e8f9f7 | 1036 | { |
<> | 144:ef7eb2e8f9f7 | 1037 | ret |= kMCG_Osc0InitFlag; |
<> | 144:ef7eb2e8f9f7 | 1038 | } |
<> | 144:ef7eb2e8f9f7 | 1039 | if (MCG->C8 & MCG_C8_LOCS1_MASK) |
<> | 144:ef7eb2e8f9f7 | 1040 | { |
<> | 144:ef7eb2e8f9f7 | 1041 | ret |= kMCG_RtcOscLostFlag; |
<> | 144:ef7eb2e8f9f7 | 1042 | } |
<> | 144:ef7eb2e8f9f7 | 1043 | if (mcg_s & MCG_S_LOLS0_MASK) |
<> | 144:ef7eb2e8f9f7 | 1044 | { |
<> | 144:ef7eb2e8f9f7 | 1045 | ret |= kMCG_Pll0LostFlag; |
<> | 144:ef7eb2e8f9f7 | 1046 | } |
<> | 144:ef7eb2e8f9f7 | 1047 | if (mcg_s & MCG_S_LOCK0_MASK) |
<> | 144:ef7eb2e8f9f7 | 1048 | { |
<> | 144:ef7eb2e8f9f7 | 1049 | ret |= kMCG_Pll0LockFlag; |
<> | 144:ef7eb2e8f9f7 | 1050 | } |
<> | 144:ef7eb2e8f9f7 | 1051 | if (MCG->C9 & MCG_C9_EXT_PLL_LOCS_MASK) |
<> | 144:ef7eb2e8f9f7 | 1052 | { |
<> | 144:ef7eb2e8f9f7 | 1053 | ret |= kMCG_ExtPllLostFlag; |
<> | 144:ef7eb2e8f9f7 | 1054 | } |
<> | 144:ef7eb2e8f9f7 | 1055 | return ret; |
<> | 144:ef7eb2e8f9f7 | 1056 | } |
<> | 144:ef7eb2e8f9f7 | 1057 | |
<> | 144:ef7eb2e8f9f7 | 1058 | void CLOCK_ClearStatusFlags(uint32_t mask) |
<> | 144:ef7eb2e8f9f7 | 1059 | { |
<> | 144:ef7eb2e8f9f7 | 1060 | uint8_t reg; |
<> | 144:ef7eb2e8f9f7 | 1061 | |
<> | 144:ef7eb2e8f9f7 | 1062 | if (mask & kMCG_Osc0LostFlag) |
<> | 144:ef7eb2e8f9f7 | 1063 | { |
<> | 144:ef7eb2e8f9f7 | 1064 | MCG->SC &= ~MCG_SC_ATMF_MASK; |
<> | 144:ef7eb2e8f9f7 | 1065 | } |
<> | 144:ef7eb2e8f9f7 | 1066 | if (mask & kMCG_RtcOscLostFlag) |
<> | 144:ef7eb2e8f9f7 | 1067 | { |
<> | 144:ef7eb2e8f9f7 | 1068 | reg = MCG->C8; |
<> | 144:ef7eb2e8f9f7 | 1069 | MCG->C8 = reg; |
<> | 144:ef7eb2e8f9f7 | 1070 | } |
<> | 144:ef7eb2e8f9f7 | 1071 | if (mask & kMCG_Pll0LostFlag) |
<> | 144:ef7eb2e8f9f7 | 1072 | { |
<> | 144:ef7eb2e8f9f7 | 1073 | MCG->S = MCG_S_LOLS0_MASK; |
<> | 144:ef7eb2e8f9f7 | 1074 | } |
<> | 144:ef7eb2e8f9f7 | 1075 | if (mask & kMCG_ExtPllLostFlag) |
<> | 144:ef7eb2e8f9f7 | 1076 | { |
<> | 144:ef7eb2e8f9f7 | 1077 | reg = MCG->C9; |
<> | 144:ef7eb2e8f9f7 | 1078 | MCG->C9 = reg; |
<> | 144:ef7eb2e8f9f7 | 1079 | } |
<> | 144:ef7eb2e8f9f7 | 1080 | } |
<> | 144:ef7eb2e8f9f7 | 1081 | |
<> | 144:ef7eb2e8f9f7 | 1082 | void CLOCK_InitOsc0(osc_config_t const *config) |
<> | 144:ef7eb2e8f9f7 | 1083 | { |
<> | 144:ef7eb2e8f9f7 | 1084 | uint8_t range = CLOCK_GetOscRangeFromFreq(config->freq); |
<> | 144:ef7eb2e8f9f7 | 1085 | |
<> | 144:ef7eb2e8f9f7 | 1086 | OSC_SetCapLoad(OSC0, config->capLoad); |
<> | 144:ef7eb2e8f9f7 | 1087 | OSC_SetExtRefClkConfig(OSC0, &config->oscerConfig); |
<> | 144:ef7eb2e8f9f7 | 1088 | |
<> | 144:ef7eb2e8f9f7 | 1089 | MCG->C2 = ((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode); |
<> | 144:ef7eb2e8f9f7 | 1090 | |
<> | 144:ef7eb2e8f9f7 | 1091 | if ((kOSC_ModeExt != config->workMode) && (OSC0->CR & OSC_CR_ERCLKEN_MASK)) |
<> | 144:ef7eb2e8f9f7 | 1092 | { |
<> | 144:ef7eb2e8f9f7 | 1093 | /* Wait for stable. */ |
<> | 144:ef7eb2e8f9f7 | 1094 | while (!(MCG->S & MCG_S_OSCINIT0_MASK)) |
<> | 144:ef7eb2e8f9f7 | 1095 | { |
<> | 144:ef7eb2e8f9f7 | 1096 | } |
<> | 144:ef7eb2e8f9f7 | 1097 | } |
<> | 144:ef7eb2e8f9f7 | 1098 | } |
<> | 144:ef7eb2e8f9f7 | 1099 | |
<> | 144:ef7eb2e8f9f7 | 1100 | void CLOCK_DeinitOsc0(void) |
<> | 144:ef7eb2e8f9f7 | 1101 | { |
<> | 144:ef7eb2e8f9f7 | 1102 | OSC0->CR = 0U; |
<> | 144:ef7eb2e8f9f7 | 1103 | MCG->C2 &= ~OSC_MODE_MASK; |
<> | 144:ef7eb2e8f9f7 | 1104 | } |
<> | 144:ef7eb2e8f9f7 | 1105 | |
<> | 144:ef7eb2e8f9f7 | 1106 | status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms) |
<> | 144:ef7eb2e8f9f7 | 1107 | { |
<> | 144:ef7eb2e8f9f7 | 1108 | uint32_t multi; /* extFreq / desireFreq */ |
<> | 144:ef7eb2e8f9f7 | 1109 | uint32_t actv; /* Auto trim value. */ |
<> | 144:ef7eb2e8f9f7 | 1110 | uint8_t mcg_sc; |
<> | 144:ef7eb2e8f9f7 | 1111 | |
<> | 144:ef7eb2e8f9f7 | 1112 | static const uint32_t trimRange[2][2] = { |
<> | 144:ef7eb2e8f9f7 | 1113 | /* Min Max */ |
<> | 144:ef7eb2e8f9f7 | 1114 | {TRIM_SIRC_MIN, TRIM_SIRC_MAX}, /* Slow IRC. */ |
<> | 144:ef7eb2e8f9f7 | 1115 | {TRIM_FIRC_MIN, TRIM_FIRC_MAX} /* Fast IRC. */ |
<> | 144:ef7eb2e8f9f7 | 1116 | }; |
<> | 144:ef7eb2e8f9f7 | 1117 | |
<> | 144:ef7eb2e8f9f7 | 1118 | if ((extFreq > TRIM_REF_CLK_MAX) || (extFreq < TRIM_REF_CLK_MIN)) |
<> | 144:ef7eb2e8f9f7 | 1119 | { |
<> | 144:ef7eb2e8f9f7 | 1120 | return kStatus_MCG_AtmBusClockInvalid; |
<> | 144:ef7eb2e8f9f7 | 1121 | } |
<> | 144:ef7eb2e8f9f7 | 1122 | |
<> | 144:ef7eb2e8f9f7 | 1123 | /* Check desired frequency range. */ |
<> | 144:ef7eb2e8f9f7 | 1124 | if ((desireFreq < trimRange[atms][0]) || (desireFreq > trimRange[atms][1])) |
<> | 144:ef7eb2e8f9f7 | 1125 | { |
<> | 144:ef7eb2e8f9f7 | 1126 | return kStatus_MCG_AtmDesiredFreqInvalid; |
<> | 144:ef7eb2e8f9f7 | 1127 | } |
<> | 144:ef7eb2e8f9f7 | 1128 | |
<> | 144:ef7eb2e8f9f7 | 1129 | /* |
<> | 144:ef7eb2e8f9f7 | 1130 | Make sure internal reference clock is not used to generate bus clock. |
<> | 144:ef7eb2e8f9f7 | 1131 | Here only need to check (MCG_S_IREFST == 1). |
<> | 144:ef7eb2e8f9f7 | 1132 | */ |
<> | 144:ef7eb2e8f9f7 | 1133 | if (MCG_S_IREFST(kMCG_FllSrcInternal) == (MCG->S & MCG_S_IREFST_MASK)) |
<> | 144:ef7eb2e8f9f7 | 1134 | { |
<> | 144:ef7eb2e8f9f7 | 1135 | return kStatus_MCG_AtmIrcUsed; |
<> | 144:ef7eb2e8f9f7 | 1136 | } |
<> | 144:ef7eb2e8f9f7 | 1137 | |
<> | 144:ef7eb2e8f9f7 | 1138 | multi = extFreq / desireFreq; |
<> | 144:ef7eb2e8f9f7 | 1139 | actv = multi * 21U; |
<> | 144:ef7eb2e8f9f7 | 1140 | |
<> | 144:ef7eb2e8f9f7 | 1141 | if (kMCG_AtmSel4m == atms) |
<> | 144:ef7eb2e8f9f7 | 1142 | { |
<> | 144:ef7eb2e8f9f7 | 1143 | actv *= 128U; |
<> | 144:ef7eb2e8f9f7 | 1144 | } |
<> | 144:ef7eb2e8f9f7 | 1145 | |
<> | 144:ef7eb2e8f9f7 | 1146 | /* Now begin to start trim. */ |
<> | 144:ef7eb2e8f9f7 | 1147 | MCG->ATCVL = (uint8_t)actv; |
<> | 144:ef7eb2e8f9f7 | 1148 | MCG->ATCVH = (uint8_t)(actv >> 8U); |
<> | 144:ef7eb2e8f9f7 | 1149 | |
<> | 144:ef7eb2e8f9f7 | 1150 | mcg_sc = MCG->SC; |
<> | 144:ef7eb2e8f9f7 | 1151 | mcg_sc &= ~(MCG_SC_ATMS_MASK | MCG_SC_LOCS0_MASK); |
<> | 144:ef7eb2e8f9f7 | 1152 | mcg_sc |= (MCG_SC_ATMF_MASK | MCG_SC_ATMS(atms)); |
<> | 144:ef7eb2e8f9f7 | 1153 | MCG->SC = (mcg_sc | MCG_SC_ATME_MASK); |
<> | 144:ef7eb2e8f9f7 | 1154 | |
<> | 144:ef7eb2e8f9f7 | 1155 | /* Wait for finished. */ |
<> | 144:ef7eb2e8f9f7 | 1156 | while (MCG->SC & MCG_SC_ATME_MASK) |
<> | 144:ef7eb2e8f9f7 | 1157 | { |
<> | 144:ef7eb2e8f9f7 | 1158 | } |
<> | 144:ef7eb2e8f9f7 | 1159 | |
<> | 144:ef7eb2e8f9f7 | 1160 | /* Error occurs? */ |
<> | 144:ef7eb2e8f9f7 | 1161 | if (MCG->SC & MCG_SC_ATMF_MASK) |
<> | 144:ef7eb2e8f9f7 | 1162 | { |
<> | 144:ef7eb2e8f9f7 | 1163 | /* Clear the failed flag. */ |
<> | 144:ef7eb2e8f9f7 | 1164 | MCG->SC = mcg_sc; |
<> | 144:ef7eb2e8f9f7 | 1165 | return kStatus_MCG_AtmHardwareFail; |
<> | 144:ef7eb2e8f9f7 | 1166 | } |
<> | 144:ef7eb2e8f9f7 | 1167 | |
<> | 144:ef7eb2e8f9f7 | 1168 | *actualFreq = extFreq / multi; |
<> | 144:ef7eb2e8f9f7 | 1169 | |
<> | 144:ef7eb2e8f9f7 | 1170 | if (kMCG_AtmSel4m == atms) |
<> | 144:ef7eb2e8f9f7 | 1171 | { |
<> | 144:ef7eb2e8f9f7 | 1172 | s_fastIrcFreq = *actualFreq; |
<> | 144:ef7eb2e8f9f7 | 1173 | } |
<> | 144:ef7eb2e8f9f7 | 1174 | else |
<> | 144:ef7eb2e8f9f7 | 1175 | { |
<> | 144:ef7eb2e8f9f7 | 1176 | s_slowIrcFreq = *actualFreq; |
<> | 144:ef7eb2e8f9f7 | 1177 | } |
<> | 144:ef7eb2e8f9f7 | 1178 | |
<> | 144:ef7eb2e8f9f7 | 1179 | return kStatus_Success; |
<> | 144:ef7eb2e8f9f7 | 1180 | } |
<> | 144:ef7eb2e8f9f7 | 1181 | |
<> | 144:ef7eb2e8f9f7 | 1182 | mcg_mode_t CLOCK_GetMode(void) |
<> | 144:ef7eb2e8f9f7 | 1183 | { |
<> | 144:ef7eb2e8f9f7 | 1184 | mcg_mode_t mode = kMCG_ModeError; |
<> | 144:ef7eb2e8f9f7 | 1185 | uint32_t clkst = MCG_S_CLKST_VAL; |
<> | 144:ef7eb2e8f9f7 | 1186 | uint32_t irefst = MCG_S_IREFST_VAL; |
<> | 144:ef7eb2e8f9f7 | 1187 | uint32_t lp = MCG_C2_LP_VAL; |
<> | 144:ef7eb2e8f9f7 | 1188 | uint32_t pllst = MCG_S_PLLST_VAL; |
<> | 144:ef7eb2e8f9f7 | 1189 | |
<> | 144:ef7eb2e8f9f7 | 1190 | /*------------------------------------------------------------------ |
<> | 144:ef7eb2e8f9f7 | 1191 | Mode and Registers |
<> | 144:ef7eb2e8f9f7 | 1192 | ____________________________________________________________________ |
<> | 144:ef7eb2e8f9f7 | 1193 | |
<> | 144:ef7eb2e8f9f7 | 1194 | Mode | CLKST | IREFST | PLLST | LP |
<> | 144:ef7eb2e8f9f7 | 1195 | ____________________________________________________________________ |
<> | 144:ef7eb2e8f9f7 | 1196 | |
<> | 144:ef7eb2e8f9f7 | 1197 | FEI | 00(FLL) | 1(INT) | 0(FLL) | X |
<> | 144:ef7eb2e8f9f7 | 1198 | ____________________________________________________________________ |
<> | 144:ef7eb2e8f9f7 | 1199 | |
<> | 144:ef7eb2e8f9f7 | 1200 | FEE | 00(FLL) | 0(EXT) | 0(FLL) | X |
<> | 144:ef7eb2e8f9f7 | 1201 | ____________________________________________________________________ |
<> | 144:ef7eb2e8f9f7 | 1202 | |
<> | 144:ef7eb2e8f9f7 | 1203 | FBE | 10(EXT) | 0(EXT) | 0(FLL) | 0(NORMAL) |
<> | 144:ef7eb2e8f9f7 | 1204 | ____________________________________________________________________ |
<> | 144:ef7eb2e8f9f7 | 1205 | |
<> | 144:ef7eb2e8f9f7 | 1206 | FBI | 01(INT) | 1(INT) | 0(FLL) | 0(NORMAL) |
<> | 144:ef7eb2e8f9f7 | 1207 | ____________________________________________________________________ |
<> | 144:ef7eb2e8f9f7 | 1208 | |
<> | 144:ef7eb2e8f9f7 | 1209 | BLPI | 01(INT) | 1(INT) | 0(FLL) | 1(LOW POWER) |
<> | 144:ef7eb2e8f9f7 | 1210 | ____________________________________________________________________ |
<> | 144:ef7eb2e8f9f7 | 1211 | |
<> | 144:ef7eb2e8f9f7 | 1212 | BLPE | 10(EXT) | 0(EXT) | X | 1(LOW POWER) |
<> | 144:ef7eb2e8f9f7 | 1213 | ____________________________________________________________________ |
<> | 144:ef7eb2e8f9f7 | 1214 | |
<> | 144:ef7eb2e8f9f7 | 1215 | PEE | 11(PLL) | 0(EXT) | 1(PLL) | X |
<> | 144:ef7eb2e8f9f7 | 1216 | ____________________________________________________________________ |
<> | 144:ef7eb2e8f9f7 | 1217 | |
<> | 144:ef7eb2e8f9f7 | 1218 | PBE | 10(EXT) | 0(EXT) | 1(PLL) | O(NORMAL) |
<> | 144:ef7eb2e8f9f7 | 1219 | ____________________________________________________________________ |
<> | 144:ef7eb2e8f9f7 | 1220 | |
<> | 144:ef7eb2e8f9f7 | 1221 | PBI | 01(INT) | 1(INT) | 1(PLL) | 0(NORMAL) |
<> | 144:ef7eb2e8f9f7 | 1222 | ____________________________________________________________________ |
<> | 144:ef7eb2e8f9f7 | 1223 | |
<> | 144:ef7eb2e8f9f7 | 1224 | PEI | 11(PLL) | 1(INT) | 1(PLL) | X |
<> | 144:ef7eb2e8f9f7 | 1225 | ____________________________________________________________________ |
<> | 144:ef7eb2e8f9f7 | 1226 | |
<> | 144:ef7eb2e8f9f7 | 1227 | ----------------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 1228 | |
<> | 144:ef7eb2e8f9f7 | 1229 | switch (clkst) |
<> | 144:ef7eb2e8f9f7 | 1230 | { |
<> | 144:ef7eb2e8f9f7 | 1231 | case kMCG_ClkOutStatFll: |
<> | 144:ef7eb2e8f9f7 | 1232 | if (kMCG_FllSrcExternal == irefst) |
<> | 144:ef7eb2e8f9f7 | 1233 | { |
<> | 144:ef7eb2e8f9f7 | 1234 | mode = kMCG_ModeFEE; |
<> | 144:ef7eb2e8f9f7 | 1235 | } |
<> | 144:ef7eb2e8f9f7 | 1236 | else |
<> | 144:ef7eb2e8f9f7 | 1237 | { |
<> | 144:ef7eb2e8f9f7 | 1238 | mode = kMCG_ModeFEI; |
<> | 144:ef7eb2e8f9f7 | 1239 | } |
<> | 144:ef7eb2e8f9f7 | 1240 | break; |
<> | 144:ef7eb2e8f9f7 | 1241 | case kMCG_ClkOutStatInt: |
<> | 144:ef7eb2e8f9f7 | 1242 | if (lp) |
<> | 144:ef7eb2e8f9f7 | 1243 | { |
<> | 144:ef7eb2e8f9f7 | 1244 | mode = kMCG_ModeBLPI; |
<> | 144:ef7eb2e8f9f7 | 1245 | } |
<> | 144:ef7eb2e8f9f7 | 1246 | else |
<> | 144:ef7eb2e8f9f7 | 1247 | { |
<> | 144:ef7eb2e8f9f7 | 1248 | { |
<> | 144:ef7eb2e8f9f7 | 1249 | mode = kMCG_ModeFBI; |
<> | 144:ef7eb2e8f9f7 | 1250 | } |
<> | 144:ef7eb2e8f9f7 | 1251 | } |
<> | 144:ef7eb2e8f9f7 | 1252 | break; |
<> | 144:ef7eb2e8f9f7 | 1253 | case kMCG_ClkOutStatExt: |
<> | 144:ef7eb2e8f9f7 | 1254 | if (lp) |
<> | 144:ef7eb2e8f9f7 | 1255 | { |
<> | 144:ef7eb2e8f9f7 | 1256 | mode = kMCG_ModeBLPE; |
<> | 144:ef7eb2e8f9f7 | 1257 | } |
<> | 144:ef7eb2e8f9f7 | 1258 | else |
<> | 144:ef7eb2e8f9f7 | 1259 | { |
<> | 144:ef7eb2e8f9f7 | 1260 | if (kMCG_PllstPll == pllst) |
<> | 144:ef7eb2e8f9f7 | 1261 | { |
<> | 144:ef7eb2e8f9f7 | 1262 | mode = kMCG_ModePBE; |
<> | 144:ef7eb2e8f9f7 | 1263 | } |
<> | 144:ef7eb2e8f9f7 | 1264 | else |
<> | 144:ef7eb2e8f9f7 | 1265 | { |
<> | 144:ef7eb2e8f9f7 | 1266 | mode = kMCG_ModeFBE; |
<> | 144:ef7eb2e8f9f7 | 1267 | } |
<> | 144:ef7eb2e8f9f7 | 1268 | } |
<> | 144:ef7eb2e8f9f7 | 1269 | break; |
<> | 144:ef7eb2e8f9f7 | 1270 | case kMCG_ClkOutStatPll: |
<> | 144:ef7eb2e8f9f7 | 1271 | { |
<> | 144:ef7eb2e8f9f7 | 1272 | mode = kMCG_ModePEE; |
<> | 144:ef7eb2e8f9f7 | 1273 | } |
<> | 144:ef7eb2e8f9f7 | 1274 | break; |
<> | 144:ef7eb2e8f9f7 | 1275 | default: |
<> | 144:ef7eb2e8f9f7 | 1276 | break; |
<> | 144:ef7eb2e8f9f7 | 1277 | } |
<> | 144:ef7eb2e8f9f7 | 1278 | |
<> | 144:ef7eb2e8f9f7 | 1279 | return mode; |
<> | 144:ef7eb2e8f9f7 | 1280 | } |
<> | 144:ef7eb2e8f9f7 | 1281 | |
<> | 144:ef7eb2e8f9f7 | 1282 | status_t CLOCK_SetFeiMode(mcg_drs_t drs, void (*fllStableDelay)(void)) |
<> | 144:ef7eb2e8f9f7 | 1283 | { |
<> | 144:ef7eb2e8f9f7 | 1284 | uint8_t mcg_c4; |
<> | 144:ef7eb2e8f9f7 | 1285 | bool change_drs = false; |
<> | 144:ef7eb2e8f9f7 | 1286 | |
<> | 144:ef7eb2e8f9f7 | 1287 | #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) |
<> | 144:ef7eb2e8f9f7 | 1288 | mcg_mode_t mode = CLOCK_GetMode(); |
<> | 144:ef7eb2e8f9f7 | 1289 | if (!((kMCG_ModeFEI == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEE == mode))) |
<> | 144:ef7eb2e8f9f7 | 1290 | { |
<> | 144:ef7eb2e8f9f7 | 1291 | return kStatus_MCG_ModeUnreachable; |
<> | 144:ef7eb2e8f9f7 | 1292 | } |
<> | 144:ef7eb2e8f9f7 | 1293 | #endif |
<> | 144:ef7eb2e8f9f7 | 1294 | mcg_c4 = MCG->C4; |
<> | 144:ef7eb2e8f9f7 | 1295 | |
<> | 144:ef7eb2e8f9f7 | 1296 | /* |
<> | 144:ef7eb2e8f9f7 | 1297 | Errata: ERR007993 |
<> | 144:ef7eb2e8f9f7 | 1298 | Workaround: Invert MCG_C4[DMX32] or change MCG_C4[DRST_DRS] before |
<> | 144:ef7eb2e8f9f7 | 1299 | reference clock source changes, then reset to previous value after |
<> | 144:ef7eb2e8f9f7 | 1300 | reference clock changes. |
<> | 144:ef7eb2e8f9f7 | 1301 | */ |
<> | 144:ef7eb2e8f9f7 | 1302 | if (kMCG_FllSrcExternal == MCG_S_IREFST_VAL) |
<> | 144:ef7eb2e8f9f7 | 1303 | { |
<> | 144:ef7eb2e8f9f7 | 1304 | change_drs = true; |
<> | 144:ef7eb2e8f9f7 | 1305 | /* Change the LSB of DRST_DRS. */ |
<> | 144:ef7eb2e8f9f7 | 1306 | MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1307 | } |
<> | 144:ef7eb2e8f9f7 | 1308 | |
<> | 144:ef7eb2e8f9f7 | 1309 | /* Set CLKS and IREFS. */ |
<> | 144:ef7eb2e8f9f7 | 1310 | MCG->C1 = |
<> | 144:ef7eb2e8f9f7 | 1311 | ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK))) | (MCG_C1_CLKS(kMCG_ClkOutSrcOut) /* CLKS = 0 */ |
<> | 144:ef7eb2e8f9f7 | 1312 | | MCG_C1_IREFS(kMCG_FllSrcInternal)); /* IREFS = 1 */ |
<> | 144:ef7eb2e8f9f7 | 1313 | |
<> | 144:ef7eb2e8f9f7 | 1314 | /* Wait and check status. */ |
<> | 144:ef7eb2e8f9f7 | 1315 | while (kMCG_FllSrcInternal != MCG_S_IREFST_VAL) |
<> | 144:ef7eb2e8f9f7 | 1316 | { |
<> | 144:ef7eb2e8f9f7 | 1317 | } |
<> | 144:ef7eb2e8f9f7 | 1318 | |
<> | 144:ef7eb2e8f9f7 | 1319 | /* Errata: ERR007993 */ |
<> | 144:ef7eb2e8f9f7 | 1320 | if (change_drs) |
<> | 144:ef7eb2e8f9f7 | 1321 | { |
<> | 144:ef7eb2e8f9f7 | 1322 | MCG->C4 = mcg_c4; |
<> | 144:ef7eb2e8f9f7 | 1323 | } |
<> | 144:ef7eb2e8f9f7 | 1324 | |
<> | 144:ef7eb2e8f9f7 | 1325 | /* In FEI mode, the MCG_C4[DMX32] is set to 0U. */ |
<> | 144:ef7eb2e8f9f7 | 1326 | MCG->C4 = (mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DRST_DRS(drs)); |
<> | 144:ef7eb2e8f9f7 | 1327 | |
<> | 144:ef7eb2e8f9f7 | 1328 | /* Check MCG_S[CLKST] */ |
<> | 144:ef7eb2e8f9f7 | 1329 | while (kMCG_ClkOutStatFll != MCG_S_CLKST_VAL) |
<> | 144:ef7eb2e8f9f7 | 1330 | { |
<> | 144:ef7eb2e8f9f7 | 1331 | } |
<> | 144:ef7eb2e8f9f7 | 1332 | |
<> | 144:ef7eb2e8f9f7 | 1333 | /* Wait for FLL stable time. */ |
<> | 144:ef7eb2e8f9f7 | 1334 | if (fllStableDelay) |
<> | 144:ef7eb2e8f9f7 | 1335 | { |
<> | 144:ef7eb2e8f9f7 | 1336 | fllStableDelay(); |
<> | 144:ef7eb2e8f9f7 | 1337 | } |
<> | 144:ef7eb2e8f9f7 | 1338 | |
<> | 144:ef7eb2e8f9f7 | 1339 | return kStatus_Success; |
<> | 144:ef7eb2e8f9f7 | 1340 | } |
<> | 144:ef7eb2e8f9f7 | 1341 | |
<> | 144:ef7eb2e8f9f7 | 1342 | status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) |
<> | 144:ef7eb2e8f9f7 | 1343 | { |
<> | 144:ef7eb2e8f9f7 | 1344 | uint8_t mcg_c4; |
<> | 144:ef7eb2e8f9f7 | 1345 | bool change_drs = false; |
<> | 144:ef7eb2e8f9f7 | 1346 | |
<> | 144:ef7eb2e8f9f7 | 1347 | #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) |
<> | 144:ef7eb2e8f9f7 | 1348 | mcg_mode_t mode = CLOCK_GetMode(); |
<> | 144:ef7eb2e8f9f7 | 1349 | if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode))) |
<> | 144:ef7eb2e8f9f7 | 1350 | { |
<> | 144:ef7eb2e8f9f7 | 1351 | return kStatus_MCG_ModeUnreachable; |
<> | 144:ef7eb2e8f9f7 | 1352 | } |
<> | 144:ef7eb2e8f9f7 | 1353 | #endif |
<> | 144:ef7eb2e8f9f7 | 1354 | mcg_c4 = MCG->C4; |
<> | 144:ef7eb2e8f9f7 | 1355 | |
<> | 144:ef7eb2e8f9f7 | 1356 | /* |
<> | 144:ef7eb2e8f9f7 | 1357 | Errata: ERR007993 |
<> | 144:ef7eb2e8f9f7 | 1358 | Workaround: Invert MCG_C4[DMX32] or change MCG_C4[DRST_DRS] before |
<> | 144:ef7eb2e8f9f7 | 1359 | reference clock source changes, then reset to previous value after |
<> | 144:ef7eb2e8f9f7 | 1360 | reference clock changes. |
<> | 144:ef7eb2e8f9f7 | 1361 | */ |
<> | 144:ef7eb2e8f9f7 | 1362 | if (kMCG_FllSrcInternal == MCG_S_IREFST_VAL) |
<> | 144:ef7eb2e8f9f7 | 1363 | { |
<> | 144:ef7eb2e8f9f7 | 1364 | change_drs = true; |
<> | 144:ef7eb2e8f9f7 | 1365 | /* Change the LSB of DRST_DRS. */ |
<> | 144:ef7eb2e8f9f7 | 1366 | MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1367 | } |
<> | 144:ef7eb2e8f9f7 | 1368 | |
<> | 144:ef7eb2e8f9f7 | 1369 | /* Set CLKS and IREFS. */ |
<> | 144:ef7eb2e8f9f7 | 1370 | MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | |
<> | 144:ef7eb2e8f9f7 | 1371 | (MCG_C1_CLKS(kMCG_ClkOutSrcOut) /* CLKS = 0 */ |
<> | 144:ef7eb2e8f9f7 | 1372 | | MCG_C1_FRDIV(frdiv) /* FRDIV */ |
<> | 144:ef7eb2e8f9f7 | 1373 | | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */ |
<> | 144:ef7eb2e8f9f7 | 1374 | |
<> | 144:ef7eb2e8f9f7 | 1375 | /* Wait and check status. */ |
<> | 144:ef7eb2e8f9f7 | 1376 | while (kMCG_FllSrcExternal != MCG_S_IREFST_VAL) |
<> | 144:ef7eb2e8f9f7 | 1377 | { |
<> | 144:ef7eb2e8f9f7 | 1378 | } |
<> | 144:ef7eb2e8f9f7 | 1379 | |
<> | 144:ef7eb2e8f9f7 | 1380 | /* Errata: ERR007993 */ |
<> | 144:ef7eb2e8f9f7 | 1381 | if (change_drs) |
<> | 144:ef7eb2e8f9f7 | 1382 | { |
<> | 144:ef7eb2e8f9f7 | 1383 | MCG->C4 = mcg_c4; |
<> | 144:ef7eb2e8f9f7 | 1384 | } |
<> | 144:ef7eb2e8f9f7 | 1385 | |
<> | 144:ef7eb2e8f9f7 | 1386 | /* Set DRS and DMX32. */ |
<> | 144:ef7eb2e8f9f7 | 1387 | mcg_c4 = ((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs))); |
<> | 144:ef7eb2e8f9f7 | 1388 | MCG->C4 = mcg_c4; |
<> | 144:ef7eb2e8f9f7 | 1389 | |
<> | 144:ef7eb2e8f9f7 | 1390 | /* Wait for DRST_DRS update. */ |
<> | 144:ef7eb2e8f9f7 | 1391 | while (MCG->C4 != mcg_c4) |
<> | 144:ef7eb2e8f9f7 | 1392 | { |
<> | 144:ef7eb2e8f9f7 | 1393 | } |
<> | 144:ef7eb2e8f9f7 | 1394 | |
<> | 144:ef7eb2e8f9f7 | 1395 | /* Check MCG_S[CLKST] */ |
<> | 144:ef7eb2e8f9f7 | 1396 | while (kMCG_ClkOutStatFll != MCG_S_CLKST_VAL) |
<> | 144:ef7eb2e8f9f7 | 1397 | { |
<> | 144:ef7eb2e8f9f7 | 1398 | } |
<> | 144:ef7eb2e8f9f7 | 1399 | |
<> | 144:ef7eb2e8f9f7 | 1400 | /* Wait for FLL stable time. */ |
<> | 144:ef7eb2e8f9f7 | 1401 | if (fllStableDelay) |
<> | 144:ef7eb2e8f9f7 | 1402 | { |
<> | 144:ef7eb2e8f9f7 | 1403 | fllStableDelay(); |
<> | 144:ef7eb2e8f9f7 | 1404 | } |
<> | 144:ef7eb2e8f9f7 | 1405 | |
<> | 144:ef7eb2e8f9f7 | 1406 | return kStatus_Success; |
<> | 144:ef7eb2e8f9f7 | 1407 | } |
<> | 144:ef7eb2e8f9f7 | 1408 | |
<> | 144:ef7eb2e8f9f7 | 1409 | status_t CLOCK_SetFbiMode(mcg_drs_t drs, void (*fllStableDelay)(void)) |
<> | 144:ef7eb2e8f9f7 | 1410 | { |
<> | 144:ef7eb2e8f9f7 | 1411 | uint8_t mcg_c4; |
<> | 144:ef7eb2e8f9f7 | 1412 | bool change_drs = false; |
<> | 144:ef7eb2e8f9f7 | 1413 | |
<> | 144:ef7eb2e8f9f7 | 1414 | #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) |
<> | 144:ef7eb2e8f9f7 | 1415 | mcg_mode_t mode = CLOCK_GetMode(); |
<> | 144:ef7eb2e8f9f7 | 1416 | |
<> | 144:ef7eb2e8f9f7 | 1417 | if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode) || |
<> | 144:ef7eb2e8f9f7 | 1418 | (kMCG_ModeBLPI == mode))) |
<> | 144:ef7eb2e8f9f7 | 1419 | |
<> | 144:ef7eb2e8f9f7 | 1420 | { |
<> | 144:ef7eb2e8f9f7 | 1421 | return kStatus_MCG_ModeUnreachable; |
<> | 144:ef7eb2e8f9f7 | 1422 | } |
<> | 144:ef7eb2e8f9f7 | 1423 | #endif |
<> | 144:ef7eb2e8f9f7 | 1424 | |
<> | 144:ef7eb2e8f9f7 | 1425 | mcg_c4 = MCG->C4; |
<> | 144:ef7eb2e8f9f7 | 1426 | |
<> | 144:ef7eb2e8f9f7 | 1427 | MCG->C2 &= ~MCG_C2_LP_MASK; /* Disable lowpower. */ |
<> | 144:ef7eb2e8f9f7 | 1428 | |
<> | 144:ef7eb2e8f9f7 | 1429 | /* |
<> | 144:ef7eb2e8f9f7 | 1430 | Errata: ERR007993 |
<> | 144:ef7eb2e8f9f7 | 1431 | Workaround: Invert MCG_C4[DMX32] or change MCG_C4[DRST_DRS] before |
<> | 144:ef7eb2e8f9f7 | 1432 | reference clock source changes, then reset to previous value after |
<> | 144:ef7eb2e8f9f7 | 1433 | reference clock changes. |
<> | 144:ef7eb2e8f9f7 | 1434 | */ |
<> | 144:ef7eb2e8f9f7 | 1435 | if (kMCG_FllSrcExternal == MCG_S_IREFST_VAL) |
<> | 144:ef7eb2e8f9f7 | 1436 | { |
<> | 144:ef7eb2e8f9f7 | 1437 | change_drs = true; |
<> | 144:ef7eb2e8f9f7 | 1438 | /* Change the LSB of DRST_DRS. */ |
<> | 144:ef7eb2e8f9f7 | 1439 | MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1440 | } |
<> | 144:ef7eb2e8f9f7 | 1441 | |
<> | 144:ef7eb2e8f9f7 | 1442 | /* Set CLKS and IREFS. */ |
<> | 144:ef7eb2e8f9f7 | 1443 | MCG->C1 = |
<> | 144:ef7eb2e8f9f7 | 1444 | ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | (MCG_C1_CLKS(kMCG_ClkOutSrcInternal) /* CLKS = 1 */ |
<> | 144:ef7eb2e8f9f7 | 1445 | | MCG_C1_IREFS(kMCG_FllSrcInternal))); /* IREFS = 1 */ |
<> | 144:ef7eb2e8f9f7 | 1446 | |
<> | 144:ef7eb2e8f9f7 | 1447 | /* Wait and check status. */ |
<> | 144:ef7eb2e8f9f7 | 1448 | while (kMCG_FllSrcInternal != MCG_S_IREFST_VAL) |
<> | 144:ef7eb2e8f9f7 | 1449 | { |
<> | 144:ef7eb2e8f9f7 | 1450 | } |
<> | 144:ef7eb2e8f9f7 | 1451 | |
<> | 144:ef7eb2e8f9f7 | 1452 | /* Errata: ERR007993 */ |
<> | 144:ef7eb2e8f9f7 | 1453 | if (change_drs) |
<> | 144:ef7eb2e8f9f7 | 1454 | { |
<> | 144:ef7eb2e8f9f7 | 1455 | MCG->C4 = mcg_c4; |
<> | 144:ef7eb2e8f9f7 | 1456 | } |
<> | 144:ef7eb2e8f9f7 | 1457 | |
<> | 144:ef7eb2e8f9f7 | 1458 | while (kMCG_ClkOutStatInt != MCG_S_CLKST_VAL) |
<> | 144:ef7eb2e8f9f7 | 1459 | { |
<> | 144:ef7eb2e8f9f7 | 1460 | } |
<> | 144:ef7eb2e8f9f7 | 1461 | |
<> | 144:ef7eb2e8f9f7 | 1462 | MCG->C4 = (mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DRST_DRS(drs)); |
<> | 144:ef7eb2e8f9f7 | 1463 | |
<> | 144:ef7eb2e8f9f7 | 1464 | /* Wait for FLL stable time. */ |
<> | 144:ef7eb2e8f9f7 | 1465 | if (fllStableDelay) |
<> | 144:ef7eb2e8f9f7 | 1466 | { |
<> | 144:ef7eb2e8f9f7 | 1467 | fllStableDelay(); |
<> | 144:ef7eb2e8f9f7 | 1468 | } |
<> | 144:ef7eb2e8f9f7 | 1469 | |
<> | 144:ef7eb2e8f9f7 | 1470 | return kStatus_Success; |
<> | 144:ef7eb2e8f9f7 | 1471 | } |
<> | 144:ef7eb2e8f9f7 | 1472 | |
<> | 144:ef7eb2e8f9f7 | 1473 | status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) |
<> | 144:ef7eb2e8f9f7 | 1474 | { |
<> | 144:ef7eb2e8f9f7 | 1475 | uint8_t mcg_c4; |
<> | 144:ef7eb2e8f9f7 | 1476 | bool change_drs = false; |
<> | 144:ef7eb2e8f9f7 | 1477 | |
<> | 144:ef7eb2e8f9f7 | 1478 | #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) |
<> | 144:ef7eb2e8f9f7 | 1479 | mcg_mode_t mode = CLOCK_GetMode(); |
<> | 144:ef7eb2e8f9f7 | 1480 | if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode) || |
<> | 144:ef7eb2e8f9f7 | 1481 | (kMCG_ModePBE == mode) || (kMCG_ModeBLPE == mode))) |
<> | 144:ef7eb2e8f9f7 | 1482 | { |
<> | 144:ef7eb2e8f9f7 | 1483 | return kStatus_MCG_ModeUnreachable; |
<> | 144:ef7eb2e8f9f7 | 1484 | } |
<> | 144:ef7eb2e8f9f7 | 1485 | #endif |
<> | 144:ef7eb2e8f9f7 | 1486 | |
<> | 144:ef7eb2e8f9f7 | 1487 | /* Change to FLL mode. */ |
<> | 144:ef7eb2e8f9f7 | 1488 | MCG->C6 &= ~MCG_C6_PLLS_MASK; |
<> | 144:ef7eb2e8f9f7 | 1489 | while (MCG->S & MCG_S_PLLST_MASK) |
<> | 144:ef7eb2e8f9f7 | 1490 | { |
<> | 144:ef7eb2e8f9f7 | 1491 | } |
<> | 144:ef7eb2e8f9f7 | 1492 | |
<> | 144:ef7eb2e8f9f7 | 1493 | /* Set LP bit to enable the FLL */ |
<> | 144:ef7eb2e8f9f7 | 1494 | MCG->C2 &= ~MCG_C2_LP_MASK; |
<> | 144:ef7eb2e8f9f7 | 1495 | |
<> | 144:ef7eb2e8f9f7 | 1496 | mcg_c4 = MCG->C4; |
<> | 144:ef7eb2e8f9f7 | 1497 | |
<> | 144:ef7eb2e8f9f7 | 1498 | /* |
<> | 144:ef7eb2e8f9f7 | 1499 | Errata: ERR007993 |
<> | 144:ef7eb2e8f9f7 | 1500 | Workaround: Invert MCG_C4[DMX32] or change MCG_C4[DRST_DRS] before |
<> | 144:ef7eb2e8f9f7 | 1501 | reference clock source changes, then reset to previous value after |
<> | 144:ef7eb2e8f9f7 | 1502 | reference clock changes. |
<> | 144:ef7eb2e8f9f7 | 1503 | */ |
<> | 144:ef7eb2e8f9f7 | 1504 | if (kMCG_FllSrcInternal == MCG_S_IREFST_VAL) |
<> | 144:ef7eb2e8f9f7 | 1505 | { |
<> | 144:ef7eb2e8f9f7 | 1506 | change_drs = true; |
<> | 144:ef7eb2e8f9f7 | 1507 | /* Change the LSB of DRST_DRS. */ |
<> | 144:ef7eb2e8f9f7 | 1508 | MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1509 | } |
<> | 144:ef7eb2e8f9f7 | 1510 | |
<> | 144:ef7eb2e8f9f7 | 1511 | /* Set CLKS and IREFS. */ |
<> | 144:ef7eb2e8f9f7 | 1512 | MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | |
<> | 144:ef7eb2e8f9f7 | 1513 | (MCG_C1_CLKS(kMCG_ClkOutSrcExternal) /* CLKS = 2 */ |
<> | 144:ef7eb2e8f9f7 | 1514 | | MCG_C1_FRDIV(frdiv) /* FRDIV = frdiv */ |
<> | 144:ef7eb2e8f9f7 | 1515 | | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */ |
<> | 144:ef7eb2e8f9f7 | 1516 | |
<> | 144:ef7eb2e8f9f7 | 1517 | /* Wait for Reference clock Status bit to clear */ |
<> | 144:ef7eb2e8f9f7 | 1518 | while (kMCG_FllSrcExternal != MCG_S_IREFST_VAL) |
<> | 144:ef7eb2e8f9f7 | 1519 | { |
<> | 144:ef7eb2e8f9f7 | 1520 | } |
<> | 144:ef7eb2e8f9f7 | 1521 | |
<> | 144:ef7eb2e8f9f7 | 1522 | /* Errata: ERR007993 */ |
<> | 144:ef7eb2e8f9f7 | 1523 | if (change_drs) |
<> | 144:ef7eb2e8f9f7 | 1524 | { |
<> | 144:ef7eb2e8f9f7 | 1525 | MCG->C4 = mcg_c4; |
<> | 144:ef7eb2e8f9f7 | 1526 | } |
<> | 144:ef7eb2e8f9f7 | 1527 | |
<> | 144:ef7eb2e8f9f7 | 1528 | /* Set DRST_DRS and DMX32. */ |
<> | 144:ef7eb2e8f9f7 | 1529 | mcg_c4 = ((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs))); |
<> | 144:ef7eb2e8f9f7 | 1530 | |
<> | 144:ef7eb2e8f9f7 | 1531 | /* Wait for clock status bits to show clock source is ext ref clk */ |
<> | 144:ef7eb2e8f9f7 | 1532 | while (kMCG_ClkOutStatExt != MCG_S_CLKST_VAL) |
<> | 144:ef7eb2e8f9f7 | 1533 | { |
<> | 144:ef7eb2e8f9f7 | 1534 | } |
<> | 144:ef7eb2e8f9f7 | 1535 | |
<> | 144:ef7eb2e8f9f7 | 1536 | /* Wait for fll stable time. */ |
<> | 144:ef7eb2e8f9f7 | 1537 | if (fllStableDelay) |
<> | 144:ef7eb2e8f9f7 | 1538 | { |
<> | 144:ef7eb2e8f9f7 | 1539 | fllStableDelay(); |
<> | 144:ef7eb2e8f9f7 | 1540 | } |
<> | 144:ef7eb2e8f9f7 | 1541 | |
<> | 144:ef7eb2e8f9f7 | 1542 | return kStatus_Success; |
<> | 144:ef7eb2e8f9f7 | 1543 | } |
<> | 144:ef7eb2e8f9f7 | 1544 | |
<> | 144:ef7eb2e8f9f7 | 1545 | status_t CLOCK_SetBlpiMode(void) |
<> | 144:ef7eb2e8f9f7 | 1546 | { |
<> | 144:ef7eb2e8f9f7 | 1547 | #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) |
<> | 144:ef7eb2e8f9f7 | 1548 | if (MCG_S_CLKST_VAL != kMCG_ClkOutStatInt) |
<> | 144:ef7eb2e8f9f7 | 1549 | { |
<> | 144:ef7eb2e8f9f7 | 1550 | return kStatus_MCG_ModeUnreachable; |
<> | 144:ef7eb2e8f9f7 | 1551 | } |
<> | 144:ef7eb2e8f9f7 | 1552 | #endif /* MCG_CONFIG_CHECK_PARAM */ |
<> | 144:ef7eb2e8f9f7 | 1553 | |
<> | 144:ef7eb2e8f9f7 | 1554 | /* Set LP. */ |
<> | 144:ef7eb2e8f9f7 | 1555 | MCG->C2 |= MCG_C2_LP_MASK; |
<> | 144:ef7eb2e8f9f7 | 1556 | |
<> | 144:ef7eb2e8f9f7 | 1557 | return kStatus_Success; |
<> | 144:ef7eb2e8f9f7 | 1558 | } |
<> | 144:ef7eb2e8f9f7 | 1559 | |
<> | 144:ef7eb2e8f9f7 | 1560 | status_t CLOCK_SetBlpeMode(void) |
<> | 144:ef7eb2e8f9f7 | 1561 | { |
<> | 144:ef7eb2e8f9f7 | 1562 | #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) |
<> | 144:ef7eb2e8f9f7 | 1563 | if (MCG_S_CLKST_VAL != kMCG_ClkOutStatExt) |
<> | 144:ef7eb2e8f9f7 | 1564 | { |
<> | 144:ef7eb2e8f9f7 | 1565 | return kStatus_MCG_ModeUnreachable; |
<> | 144:ef7eb2e8f9f7 | 1566 | } |
<> | 144:ef7eb2e8f9f7 | 1567 | #endif |
<> | 144:ef7eb2e8f9f7 | 1568 | |
<> | 144:ef7eb2e8f9f7 | 1569 | /* Set LP bit to enter BLPE mode. */ |
<> | 144:ef7eb2e8f9f7 | 1570 | MCG->C2 |= MCG_C2_LP_MASK; |
<> | 144:ef7eb2e8f9f7 | 1571 | |
<> | 144:ef7eb2e8f9f7 | 1572 | return kStatus_Success; |
<> | 144:ef7eb2e8f9f7 | 1573 | } |
<> | 144:ef7eb2e8f9f7 | 1574 | |
<> | 144:ef7eb2e8f9f7 | 1575 | status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config) |
<> | 144:ef7eb2e8f9f7 | 1576 | { |
<> | 144:ef7eb2e8f9f7 | 1577 | /* |
<> | 144:ef7eb2e8f9f7 | 1578 | This function is designed to change MCG to PBE mode from PEE/BLPE/FBE, |
<> | 144:ef7eb2e8f9f7 | 1579 | but with this workflow, the source mode could be all modes except PEI/PBI. |
<> | 144:ef7eb2e8f9f7 | 1580 | */ |
<> | 144:ef7eb2e8f9f7 | 1581 | MCG->C2 &= ~MCG_C2_LP_MASK; /* Disable lowpower. */ |
<> | 144:ef7eb2e8f9f7 | 1582 | |
<> | 144:ef7eb2e8f9f7 | 1583 | /* Change to use external clock first. */ |
<> | 144:ef7eb2e8f9f7 | 1584 | MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal)); |
<> | 144:ef7eb2e8f9f7 | 1585 | |
<> | 144:ef7eb2e8f9f7 | 1586 | /* Wait for CLKST clock status bits to show clock source is ext ref clk */ |
<> | 144:ef7eb2e8f9f7 | 1587 | while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) != |
<> | 144:ef7eb2e8f9f7 | 1588 | (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt))) |
<> | 144:ef7eb2e8f9f7 | 1589 | { |
<> | 144:ef7eb2e8f9f7 | 1590 | } |
<> | 144:ef7eb2e8f9f7 | 1591 | |
<> | 144:ef7eb2e8f9f7 | 1592 | /* Disable PLL first, then configure PLL. */ |
<> | 144:ef7eb2e8f9f7 | 1593 | MCG->C6 &= ~MCG_C6_PLLS_MASK; |
<> | 144:ef7eb2e8f9f7 | 1594 | while (MCG->S & MCG_S_PLLST_MASK) |
<> | 144:ef7eb2e8f9f7 | 1595 | { |
<> | 144:ef7eb2e8f9f7 | 1596 | } |
<> | 144:ef7eb2e8f9f7 | 1597 | |
<> | 144:ef7eb2e8f9f7 | 1598 | /* Configure the PLL. */ |
<> | 144:ef7eb2e8f9f7 | 1599 | if (kMCG_PllClkSelPll0 == pllcs) |
<> | 144:ef7eb2e8f9f7 | 1600 | { |
<> | 144:ef7eb2e8f9f7 | 1601 | CLOCK_EnablePll0(config); |
<> | 144:ef7eb2e8f9f7 | 1602 | } |
<> | 144:ef7eb2e8f9f7 | 1603 | |
<> | 144:ef7eb2e8f9f7 | 1604 | MCG->C11 = ((MCG->C11 & ~MCG_C11_PLLCS_MASK)) | MCG_C11_PLLCS(pllcs); |
<> | 144:ef7eb2e8f9f7 | 1605 | while (pllcs != MCG_S2_PLLCST_VAL) |
<> | 144:ef7eb2e8f9f7 | 1606 | { |
<> | 144:ef7eb2e8f9f7 | 1607 | } |
<> | 144:ef7eb2e8f9f7 | 1608 | |
<> | 144:ef7eb2e8f9f7 | 1609 | /* Change to PLL mode. */ |
<> | 144:ef7eb2e8f9f7 | 1610 | MCG->C6 |= MCG_C6_PLLS_MASK; |
<> | 144:ef7eb2e8f9f7 | 1611 | while (!(MCG->S & MCG_S_PLLST_MASK)) |
<> | 144:ef7eb2e8f9f7 | 1612 | { |
<> | 144:ef7eb2e8f9f7 | 1613 | } |
<> | 144:ef7eb2e8f9f7 | 1614 | |
<> | 144:ef7eb2e8f9f7 | 1615 | return kStatus_Success; |
<> | 144:ef7eb2e8f9f7 | 1616 | } |
<> | 144:ef7eb2e8f9f7 | 1617 | |
<> | 144:ef7eb2e8f9f7 | 1618 | status_t CLOCK_SetPeeMode(void) |
<> | 144:ef7eb2e8f9f7 | 1619 | { |
<> | 144:ef7eb2e8f9f7 | 1620 | #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) |
<> | 144:ef7eb2e8f9f7 | 1621 | mcg_mode_t mode = CLOCK_GetMode(); |
<> | 144:ef7eb2e8f9f7 | 1622 | if (kMCG_ModePBE != mode) |
<> | 144:ef7eb2e8f9f7 | 1623 | { |
<> | 144:ef7eb2e8f9f7 | 1624 | return kStatus_MCG_ModeUnreachable; |
<> | 144:ef7eb2e8f9f7 | 1625 | } |
<> | 144:ef7eb2e8f9f7 | 1626 | #endif |
<> | 144:ef7eb2e8f9f7 | 1627 | |
<> | 144:ef7eb2e8f9f7 | 1628 | /* Change to use PLL/FLL output clock first. */ |
<> | 144:ef7eb2e8f9f7 | 1629 | MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut); |
<> | 144:ef7eb2e8f9f7 | 1630 | |
<> | 144:ef7eb2e8f9f7 | 1631 | /* Wait for clock status bits to update */ |
<> | 144:ef7eb2e8f9f7 | 1632 | while (MCG_S_CLKST_VAL != kMCG_ClkOutStatPll) |
<> | 144:ef7eb2e8f9f7 | 1633 | { |
<> | 144:ef7eb2e8f9f7 | 1634 | } |
<> | 144:ef7eb2e8f9f7 | 1635 | |
<> | 144:ef7eb2e8f9f7 | 1636 | return kStatus_Success; |
<> | 144:ef7eb2e8f9f7 | 1637 | } |
<> | 144:ef7eb2e8f9f7 | 1638 | |
<> | 144:ef7eb2e8f9f7 | 1639 | status_t CLOCK_ExternalModeToFbeModeQuick(void) |
<> | 144:ef7eb2e8f9f7 | 1640 | { |
<> | 144:ef7eb2e8f9f7 | 1641 | #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) |
<> | 144:ef7eb2e8f9f7 | 1642 | if (MCG->S & MCG_S_IREFST_MASK) |
<> | 144:ef7eb2e8f9f7 | 1643 | { |
<> | 144:ef7eb2e8f9f7 | 1644 | return kStatus_MCG_ModeInvalid; |
<> | 144:ef7eb2e8f9f7 | 1645 | } |
<> | 144:ef7eb2e8f9f7 | 1646 | #endif /* MCG_CONFIG_CHECK_PARAM */ |
<> | 144:ef7eb2e8f9f7 | 1647 | |
<> | 144:ef7eb2e8f9f7 | 1648 | /* Disable low power */ |
<> | 144:ef7eb2e8f9f7 | 1649 | MCG->C2 &= ~MCG_C2_LP_MASK; |
<> | 144:ef7eb2e8f9f7 | 1650 | |
<> | 144:ef7eb2e8f9f7 | 1651 | MCG->C1 = ((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal)); |
<> | 144:ef7eb2e8f9f7 | 1652 | while (MCG_S_CLKST_VAL != kMCG_ClkOutStatExt) |
<> | 144:ef7eb2e8f9f7 | 1653 | { |
<> | 144:ef7eb2e8f9f7 | 1654 | } |
<> | 144:ef7eb2e8f9f7 | 1655 | |
<> | 144:ef7eb2e8f9f7 | 1656 | /* Disable PLL. */ |
<> | 144:ef7eb2e8f9f7 | 1657 | MCG->C6 &= ~MCG_C6_PLLS_MASK; |
<> | 144:ef7eb2e8f9f7 | 1658 | while (MCG->S & MCG_S_PLLST_MASK) |
<> | 144:ef7eb2e8f9f7 | 1659 | { |
<> | 144:ef7eb2e8f9f7 | 1660 | } |
<> | 144:ef7eb2e8f9f7 | 1661 | |
<> | 144:ef7eb2e8f9f7 | 1662 | return kStatus_Success; |
<> | 144:ef7eb2e8f9f7 | 1663 | } |
<> | 144:ef7eb2e8f9f7 | 1664 | |
<> | 144:ef7eb2e8f9f7 | 1665 | status_t CLOCK_InternalModeToFbiModeQuick(void) |
<> | 144:ef7eb2e8f9f7 | 1666 | { |
<> | 144:ef7eb2e8f9f7 | 1667 | #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) |
<> | 144:ef7eb2e8f9f7 | 1668 | if (!(MCG->S & MCG_S_IREFST_MASK)) |
<> | 144:ef7eb2e8f9f7 | 1669 | { |
<> | 144:ef7eb2e8f9f7 | 1670 | return kStatus_MCG_ModeInvalid; |
<> | 144:ef7eb2e8f9f7 | 1671 | } |
<> | 144:ef7eb2e8f9f7 | 1672 | #endif |
<> | 144:ef7eb2e8f9f7 | 1673 | |
<> | 144:ef7eb2e8f9f7 | 1674 | /* Disable low power */ |
<> | 144:ef7eb2e8f9f7 | 1675 | MCG->C2 &= ~MCG_C2_LP_MASK; |
<> | 144:ef7eb2e8f9f7 | 1676 | |
<> | 144:ef7eb2e8f9f7 | 1677 | MCG->C1 = ((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal)); |
<> | 144:ef7eb2e8f9f7 | 1678 | while (MCG_S_CLKST_VAL != kMCG_ClkOutStatInt) |
<> | 144:ef7eb2e8f9f7 | 1679 | { |
<> | 144:ef7eb2e8f9f7 | 1680 | } |
<> | 144:ef7eb2e8f9f7 | 1681 | |
<> | 144:ef7eb2e8f9f7 | 1682 | return kStatus_Success; |
<> | 144:ef7eb2e8f9f7 | 1683 | } |
<> | 144:ef7eb2e8f9f7 | 1684 | |
<> | 144:ef7eb2e8f9f7 | 1685 | status_t CLOCK_BootToFeiMode(mcg_drs_t drs, void (*fllStableDelay)(void)) |
<> | 144:ef7eb2e8f9f7 | 1686 | { |
<> | 144:ef7eb2e8f9f7 | 1687 | return CLOCK_SetFeiMode(drs, fllStableDelay); |
<> | 144:ef7eb2e8f9f7 | 1688 | } |
<> | 144:ef7eb2e8f9f7 | 1689 | |
<> | 144:ef7eb2e8f9f7 | 1690 | status_t CLOCK_BootToFeeMode( |
<> | 144:ef7eb2e8f9f7 | 1691 | mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) |
<> | 144:ef7eb2e8f9f7 | 1692 | { |
<> | 144:ef7eb2e8f9f7 | 1693 | CLOCK_SetExternalRefClkConfig(oscsel); |
<> | 144:ef7eb2e8f9f7 | 1694 | |
<> | 144:ef7eb2e8f9f7 | 1695 | return CLOCK_SetFeeMode(frdiv, dmx32, drs, fllStableDelay); |
<> | 144:ef7eb2e8f9f7 | 1696 | } |
<> | 144:ef7eb2e8f9f7 | 1697 | |
<> | 144:ef7eb2e8f9f7 | 1698 | status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode) |
<> | 144:ef7eb2e8f9f7 | 1699 | { |
<> | 144:ef7eb2e8f9f7 | 1700 | /* If reset mode is FEI mode, set MCGIRCLK and always success. */ |
<> | 144:ef7eb2e8f9f7 | 1701 | CLOCK_SetInternalRefClkConfig(ircEnableMode, ircs, fcrdiv); |
<> | 144:ef7eb2e8f9f7 | 1702 | |
<> | 144:ef7eb2e8f9f7 | 1703 | /* If reset mode is not BLPI, first enter FBI mode. */ |
<> | 144:ef7eb2e8f9f7 | 1704 | MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal); |
<> | 144:ef7eb2e8f9f7 | 1705 | while (MCG_S_CLKST_VAL != kMCG_ClkOutStatInt) |
<> | 144:ef7eb2e8f9f7 | 1706 | { |
<> | 144:ef7eb2e8f9f7 | 1707 | } |
<> | 144:ef7eb2e8f9f7 | 1708 | |
<> | 144:ef7eb2e8f9f7 | 1709 | /* Enter BLPI mode. */ |
<> | 144:ef7eb2e8f9f7 | 1710 | MCG->C2 |= MCG_C2_LP_MASK; |
<> | 144:ef7eb2e8f9f7 | 1711 | |
<> | 144:ef7eb2e8f9f7 | 1712 | return kStatus_Success; |
<> | 144:ef7eb2e8f9f7 | 1713 | } |
<> | 144:ef7eb2e8f9f7 | 1714 | |
<> | 144:ef7eb2e8f9f7 | 1715 | status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel) |
<> | 144:ef7eb2e8f9f7 | 1716 | { |
<> | 144:ef7eb2e8f9f7 | 1717 | CLOCK_SetExternalRefClkConfig(oscsel); |
<> | 144:ef7eb2e8f9f7 | 1718 | |
<> | 144:ef7eb2e8f9f7 | 1719 | /* Set to FBE mode. */ |
<> | 144:ef7eb2e8f9f7 | 1720 | MCG->C1 = |
<> | 144:ef7eb2e8f9f7 | 1721 | ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | (MCG_C1_CLKS(kMCG_ClkOutSrcExternal) /* CLKS = 2 */ |
<> | 144:ef7eb2e8f9f7 | 1722 | | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */ |
<> | 144:ef7eb2e8f9f7 | 1723 | |
<> | 144:ef7eb2e8f9f7 | 1724 | /* Wait for MCG_S[CLKST] and MCG_S[IREFST]. */ |
<> | 144:ef7eb2e8f9f7 | 1725 | while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) != |
<> | 144:ef7eb2e8f9f7 | 1726 | (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt))) |
<> | 144:ef7eb2e8f9f7 | 1727 | { |
<> | 144:ef7eb2e8f9f7 | 1728 | } |
<> | 144:ef7eb2e8f9f7 | 1729 | |
<> | 144:ef7eb2e8f9f7 | 1730 | /* In FBE now, start to enter BLPE. */ |
<> | 144:ef7eb2e8f9f7 | 1731 | MCG->C2 |= MCG_C2_LP_MASK; |
<> | 144:ef7eb2e8f9f7 | 1732 | |
<> | 144:ef7eb2e8f9f7 | 1733 | return kStatus_Success; |
<> | 144:ef7eb2e8f9f7 | 1734 | } |
<> | 144:ef7eb2e8f9f7 | 1735 | |
<> | 144:ef7eb2e8f9f7 | 1736 | status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config) |
<> | 144:ef7eb2e8f9f7 | 1737 | { |
<> | 144:ef7eb2e8f9f7 | 1738 | assert(config); |
<> | 144:ef7eb2e8f9f7 | 1739 | |
<> | 144:ef7eb2e8f9f7 | 1740 | CLOCK_SetExternalRefClkConfig(oscsel); |
<> | 144:ef7eb2e8f9f7 | 1741 | |
<> | 144:ef7eb2e8f9f7 | 1742 | CLOCK_SetPbeMode(pllcs, config); |
<> | 144:ef7eb2e8f9f7 | 1743 | |
<> | 144:ef7eb2e8f9f7 | 1744 | /* Change to use PLL output clock. */ |
<> | 144:ef7eb2e8f9f7 | 1745 | MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut); |
<> | 144:ef7eb2e8f9f7 | 1746 | while (MCG_S_CLKST_VAL != kMCG_ClkOutStatPll) |
<> | 144:ef7eb2e8f9f7 | 1747 | { |
<> | 144:ef7eb2e8f9f7 | 1748 | } |
<> | 144:ef7eb2e8f9f7 | 1749 | |
<> | 144:ef7eb2e8f9f7 | 1750 | return kStatus_Success; |
<> | 144:ef7eb2e8f9f7 | 1751 | } |
<> | 144:ef7eb2e8f9f7 | 1752 | |
<> | 144:ef7eb2e8f9f7 | 1753 | /* |
<> | 144:ef7eb2e8f9f7 | 1754 | The transaction matrix. It defines the path for mode switch, the row is for |
<> | 144:ef7eb2e8f9f7 | 1755 | current mode and the column is target mode. |
<> | 144:ef7eb2e8f9f7 | 1756 | For example, switch from FEI to PEE: |
<> | 144:ef7eb2e8f9f7 | 1757 | 1. Current mode FEI, next mode is mcgModeMatrix[FEI][PEE] = FBE, so swith to FBE. |
<> | 144:ef7eb2e8f9f7 | 1758 | 2. Current mode FBE, next mode is mcgModeMatrix[FBE][PEE] = PBE, so swith to PBE. |
<> | 144:ef7eb2e8f9f7 | 1759 | 3. Current mode PBE, next mode is mcgModeMatrix[PBE][PEE] = PEE, so swith to PEE. |
<> | 144:ef7eb2e8f9f7 | 1760 | Thus the MCG mode has changed from FEI to PEE. |
<> | 144:ef7eb2e8f9f7 | 1761 | */ |
<> | 144:ef7eb2e8f9f7 | 1762 | static const mcg_mode_t mcgModeMatrix[8][8] = { |
<> | 144:ef7eb2e8f9f7 | 1763 | {kMCG_ModeFEI, kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeFEE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, |
<> | 144:ef7eb2e8f9f7 | 1764 | kMCG_ModeFBE}, /* FEI */ |
<> | 144:ef7eb2e8f9f7 | 1765 | {kMCG_ModeFEI, kMCG_ModeFBI, kMCG_ModeBLPI, kMCG_ModeFEE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, |
<> | 144:ef7eb2e8f9f7 | 1766 | kMCG_ModeFBE}, /* FBI */ |
<> | 144:ef7eb2e8f9f7 | 1767 | {kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeBLPI, kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeFBI, |
<> | 144:ef7eb2e8f9f7 | 1768 | kMCG_ModeFBI}, /* BLPI */ |
<> | 144:ef7eb2e8f9f7 | 1769 | {kMCG_ModeFEI, kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeFEE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, |
<> | 144:ef7eb2e8f9f7 | 1770 | kMCG_ModeFBE}, /* FEE */ |
<> | 144:ef7eb2e8f9f7 | 1771 | {kMCG_ModeFEI, kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeFEE, kMCG_ModeFBE, kMCG_ModeBLPE, kMCG_ModePBE, |
<> | 144:ef7eb2e8f9f7 | 1772 | kMCG_ModePBE}, /* FBE */ |
<> | 144:ef7eb2e8f9f7 | 1773 | {kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeBLPE, kMCG_ModePBE, |
<> | 144:ef7eb2e8f9f7 | 1774 | kMCG_ModePBE}, /* BLPE */ |
<> | 144:ef7eb2e8f9f7 | 1775 | {kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeBLPE, kMCG_ModePBE, |
<> | 144:ef7eb2e8f9f7 | 1776 | kMCG_ModePEE}, /* PBE */ |
<> | 144:ef7eb2e8f9f7 | 1777 | {kMCG_ModePBE, kMCG_ModePBE, kMCG_ModePBE, kMCG_ModePBE, kMCG_ModePBE, kMCG_ModePBE, kMCG_ModePBE, |
<> | 144:ef7eb2e8f9f7 | 1778 | kMCG_ModePBE} /* PEE */ |
<> | 144:ef7eb2e8f9f7 | 1779 | /* FEI FBI BLPI FEE FBE BLPE PBE PEE */ |
<> | 144:ef7eb2e8f9f7 | 1780 | }; |
<> | 144:ef7eb2e8f9f7 | 1781 | |
<> | 144:ef7eb2e8f9f7 | 1782 | status_t CLOCK_SetMcgConfig(const mcg_config_t *config) |
<> | 144:ef7eb2e8f9f7 | 1783 | { |
<> | 144:ef7eb2e8f9f7 | 1784 | mcg_mode_t next_mode; |
<> | 144:ef7eb2e8f9f7 | 1785 | status_t status = kStatus_Success; |
<> | 144:ef7eb2e8f9f7 | 1786 | |
<> | 144:ef7eb2e8f9f7 | 1787 | mcg_pll_clk_select_t pllcs = config->pllcs; |
<> | 144:ef7eb2e8f9f7 | 1788 | |
<> | 144:ef7eb2e8f9f7 | 1789 | /* If need to change external clock, MCG_C7[OSCSEL]. */ |
<> | 144:ef7eb2e8f9f7 | 1790 | if (MCG_C7_OSCSEL_VAL != config->oscsel) |
<> | 144:ef7eb2e8f9f7 | 1791 | { |
<> | 144:ef7eb2e8f9f7 | 1792 | /* If external clock is in use, change to FEI first. */ |
<> | 144:ef7eb2e8f9f7 | 1793 | if (!(MCG->S & MCG_S_IRCST_MASK)) |
<> | 144:ef7eb2e8f9f7 | 1794 | { |
<> | 144:ef7eb2e8f9f7 | 1795 | CLOCK_ExternalModeToFbeModeQuick(); |
<> | 144:ef7eb2e8f9f7 | 1796 | CLOCK_SetFeiMode(config->drs, (void (*)(void))0); |
<> | 144:ef7eb2e8f9f7 | 1797 | } |
<> | 144:ef7eb2e8f9f7 | 1798 | |
<> | 144:ef7eb2e8f9f7 | 1799 | CLOCK_SetExternalRefClkConfig(config->oscsel); |
<> | 144:ef7eb2e8f9f7 | 1800 | } |
<> | 144:ef7eb2e8f9f7 | 1801 | |
<> | 144:ef7eb2e8f9f7 | 1802 | /* Re-configure MCGIRCLK, if MCGIRCLK is used as system clock source, then change to FEI/PEI first. */ |
<> | 144:ef7eb2e8f9f7 | 1803 | if (MCG_S_CLKST_VAL == kMCG_ClkOutStatInt) |
<> | 144:ef7eb2e8f9f7 | 1804 | { |
<> | 144:ef7eb2e8f9f7 | 1805 | MCG->C2 &= ~MCG_C2_LP_MASK; /* Disable lowpower. */ |
<> | 144:ef7eb2e8f9f7 | 1806 | |
<> | 144:ef7eb2e8f9f7 | 1807 | { |
<> | 144:ef7eb2e8f9f7 | 1808 | CLOCK_SetFeiMode(config->drs, CLOCK_FllStableDelay); |
<> | 144:ef7eb2e8f9f7 | 1809 | } |
<> | 144:ef7eb2e8f9f7 | 1810 | } |
<> | 144:ef7eb2e8f9f7 | 1811 | |
<> | 144:ef7eb2e8f9f7 | 1812 | /* Configure MCGIRCLK. */ |
<> | 144:ef7eb2e8f9f7 | 1813 | CLOCK_SetInternalRefClkConfig(config->irclkEnableMode, config->ircs, config->fcrdiv); |
<> | 144:ef7eb2e8f9f7 | 1814 | |
<> | 144:ef7eb2e8f9f7 | 1815 | next_mode = CLOCK_GetMode(); |
<> | 144:ef7eb2e8f9f7 | 1816 | |
<> | 144:ef7eb2e8f9f7 | 1817 | do |
<> | 144:ef7eb2e8f9f7 | 1818 | { |
<> | 144:ef7eb2e8f9f7 | 1819 | next_mode = mcgModeMatrix[next_mode][config->mcgMode]; |
<> | 144:ef7eb2e8f9f7 | 1820 | |
<> | 144:ef7eb2e8f9f7 | 1821 | switch (next_mode) |
<> | 144:ef7eb2e8f9f7 | 1822 | { |
<> | 144:ef7eb2e8f9f7 | 1823 | case kMCG_ModeFEI: |
<> | 144:ef7eb2e8f9f7 | 1824 | status = CLOCK_SetFeiMode(config->drs, CLOCK_FllStableDelay); |
<> | 144:ef7eb2e8f9f7 | 1825 | break; |
<> | 144:ef7eb2e8f9f7 | 1826 | case kMCG_ModeFEE: |
<> | 144:ef7eb2e8f9f7 | 1827 | status = CLOCK_SetFeeMode(config->frdiv, config->dmx32, config->drs, CLOCK_FllStableDelay); |
<> | 144:ef7eb2e8f9f7 | 1828 | break; |
<> | 144:ef7eb2e8f9f7 | 1829 | case kMCG_ModeFBI: |
<> | 144:ef7eb2e8f9f7 | 1830 | status = CLOCK_SetFbiMode(config->drs, (void (*)(void))0); |
<> | 144:ef7eb2e8f9f7 | 1831 | break; |
<> | 144:ef7eb2e8f9f7 | 1832 | case kMCG_ModeFBE: |
<> | 144:ef7eb2e8f9f7 | 1833 | status = CLOCK_SetFbeMode(config->frdiv, config->dmx32, config->drs, (void (*)(void))0); |
<> | 144:ef7eb2e8f9f7 | 1834 | break; |
<> | 144:ef7eb2e8f9f7 | 1835 | case kMCG_ModeBLPI: |
<> | 144:ef7eb2e8f9f7 | 1836 | status = CLOCK_SetBlpiMode(); |
<> | 144:ef7eb2e8f9f7 | 1837 | break; |
<> | 144:ef7eb2e8f9f7 | 1838 | case kMCG_ModeBLPE: |
<> | 144:ef7eb2e8f9f7 | 1839 | status = CLOCK_SetBlpeMode(); |
<> | 144:ef7eb2e8f9f7 | 1840 | break; |
<> | 144:ef7eb2e8f9f7 | 1841 | case kMCG_ModePBE: |
<> | 144:ef7eb2e8f9f7 | 1842 | /* If target mode is not PBE or PEE, then only need to set CLKS = EXT here. */ |
<> | 144:ef7eb2e8f9f7 | 1843 | if ((kMCG_ModePEE == config->mcgMode) || (kMCG_ModePBE == config->mcgMode)) |
<> | 144:ef7eb2e8f9f7 | 1844 | { |
<> | 144:ef7eb2e8f9f7 | 1845 | if (kMCG_PllClkSelPll0 == pllcs) |
<> | 144:ef7eb2e8f9f7 | 1846 | { |
<> | 144:ef7eb2e8f9f7 | 1847 | status = CLOCK_SetPbeMode(pllcs, &config->pll0Config); |
<> | 144:ef7eb2e8f9f7 | 1848 | } |
<> | 144:ef7eb2e8f9f7 | 1849 | else if (kMCG_PllClkSelExtPll == pllcs) |
<> | 144:ef7eb2e8f9f7 | 1850 | { |
<> | 144:ef7eb2e8f9f7 | 1851 | status = CLOCK_SetPbeMode(pllcs, NULL); |
<> | 144:ef7eb2e8f9f7 | 1852 | } |
<> | 144:ef7eb2e8f9f7 | 1853 | else |
<> | 144:ef7eb2e8f9f7 | 1854 | { |
<> | 144:ef7eb2e8f9f7 | 1855 | } |
<> | 144:ef7eb2e8f9f7 | 1856 | } |
<> | 144:ef7eb2e8f9f7 | 1857 | else |
<> | 144:ef7eb2e8f9f7 | 1858 | { |
<> | 144:ef7eb2e8f9f7 | 1859 | MCG->C1 = ((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal)); |
<> | 144:ef7eb2e8f9f7 | 1860 | while (MCG_S_CLKST_VAL != kMCG_ClkOutStatExt) |
<> | 144:ef7eb2e8f9f7 | 1861 | { |
<> | 144:ef7eb2e8f9f7 | 1862 | } |
<> | 144:ef7eb2e8f9f7 | 1863 | } |
<> | 144:ef7eb2e8f9f7 | 1864 | break; |
<> | 144:ef7eb2e8f9f7 | 1865 | case kMCG_ModePEE: |
<> | 144:ef7eb2e8f9f7 | 1866 | status = CLOCK_SetPeeMode(); |
<> | 144:ef7eb2e8f9f7 | 1867 | break; |
<> | 144:ef7eb2e8f9f7 | 1868 | default: |
<> | 144:ef7eb2e8f9f7 | 1869 | break; |
<> | 144:ef7eb2e8f9f7 | 1870 | } |
<> | 144:ef7eb2e8f9f7 | 1871 | if (kStatus_Success != status) |
<> | 144:ef7eb2e8f9f7 | 1872 | { |
<> | 144:ef7eb2e8f9f7 | 1873 | return status; |
<> | 144:ef7eb2e8f9f7 | 1874 | } |
<> | 144:ef7eb2e8f9f7 | 1875 | } while (next_mode != config->mcgMode); |
<> | 144:ef7eb2e8f9f7 | 1876 | |
<> | 144:ef7eb2e8f9f7 | 1877 | if (config->pll0Config.enableMode & kMCG_PllEnableIndependent) |
<> | 144:ef7eb2e8f9f7 | 1878 | { |
<> | 144:ef7eb2e8f9f7 | 1879 | CLOCK_EnablePll0(&config->pll0Config); |
<> | 144:ef7eb2e8f9f7 | 1880 | } |
<> | 144:ef7eb2e8f9f7 | 1881 | else |
<> | 144:ef7eb2e8f9f7 | 1882 | { |
<> | 144:ef7eb2e8f9f7 | 1883 | MCG->C5 &= ~(uint32_t)kMCG_PllEnableIndependent; |
<> | 144:ef7eb2e8f9f7 | 1884 | } |
<> | 144:ef7eb2e8f9f7 | 1885 | return kStatus_Success; |
<> | 144:ef7eb2e8f9f7 | 1886 | } |