Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_adc16.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 144:ef7eb2e8f9f7 3 * All rights reserved.
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 6 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 9 * of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 12 * list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 13 * other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 144:ef7eb2e8f9f7 16 * contributors may be used to endorse or promote products derived from this
<> 144:ef7eb2e8f9f7 17 * software without specific prior written permission.
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 29 */
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 #include "fsl_adc16.h"
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 /*******************************************************************************
<> 144:ef7eb2e8f9f7 34 * Prototypes
<> 144:ef7eb2e8f9f7 35 ******************************************************************************/
<> 144:ef7eb2e8f9f7 36 /*!
<> 144:ef7eb2e8f9f7 37 * @brief Get instance number for ADC16 module.
<> 144:ef7eb2e8f9f7 38 *
<> 144:ef7eb2e8f9f7 39 * @param base ADC16 peripheral base address
<> 144:ef7eb2e8f9f7 40 */
<> 144:ef7eb2e8f9f7 41 static uint32_t ADC16_GetInstance(ADC_Type *base);
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /*******************************************************************************
<> 144:ef7eb2e8f9f7 44 * Variables
<> 144:ef7eb2e8f9f7 45 ******************************************************************************/
<> 144:ef7eb2e8f9f7 46 /*! @brief Pointers to ADC16 bases for each instance. */
<> 144:ef7eb2e8f9f7 47 static ADC_Type *const s_adc16Bases[] = ADC_BASE_PTRS;
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /*! @brief Pointers to ADC16 clocks for each instance. */
<> 144:ef7eb2e8f9f7 50 const clock_ip_name_t s_adc16Clocks[] = ADC16_CLOCKS;
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 /*******************************************************************************
<> 144:ef7eb2e8f9f7 53 * Code
<> 144:ef7eb2e8f9f7 54 ******************************************************************************/
<> 144:ef7eb2e8f9f7 55 static uint32_t ADC16_GetInstance(ADC_Type *base)
<> 144:ef7eb2e8f9f7 56 {
<> 144:ef7eb2e8f9f7 57 uint32_t instance;
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /* Find the instance index from base address mappings. */
<> 144:ef7eb2e8f9f7 60 for (instance = 0; instance < FSL_FEATURE_SOC_ADC16_COUNT; instance++)
<> 144:ef7eb2e8f9f7 61 {
<> 144:ef7eb2e8f9f7 62 if (s_adc16Bases[instance] == base)
<> 144:ef7eb2e8f9f7 63 {
<> 144:ef7eb2e8f9f7 64 break;
<> 144:ef7eb2e8f9f7 65 }
<> 144:ef7eb2e8f9f7 66 }
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 assert(instance < FSL_FEATURE_SOC_ADC16_COUNT);
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 return instance;
<> 144:ef7eb2e8f9f7 71 }
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 void ADC16_Init(ADC_Type *base, const adc16_config_t *config)
<> 144:ef7eb2e8f9f7 74 {
<> 144:ef7eb2e8f9f7 75 assert(NULL != config);
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 uint32_t tmp32;
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 /* Enable the clock. */
<> 144:ef7eb2e8f9f7 80 CLOCK_EnableClock(s_adc16Clocks[ADC16_GetInstance(base)]);
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 /* ADCx_CFG1. */
<> 144:ef7eb2e8f9f7 83 tmp32 = ADC_CFG1_ADICLK(config->clockSource) | ADC_CFG1_MODE(config->resolution);
<> 144:ef7eb2e8f9f7 84 if (kADC16_LongSampleDisabled != config->longSampleMode)
<> 144:ef7eb2e8f9f7 85 {
<> 144:ef7eb2e8f9f7 86 tmp32 |= ADC_CFG1_ADLSMP_MASK;
<> 144:ef7eb2e8f9f7 87 }
<> 144:ef7eb2e8f9f7 88 tmp32 |= ADC_CFG1_ADIV(config->clockDivider);
<> 144:ef7eb2e8f9f7 89 if (config->enableLowPower)
<> 144:ef7eb2e8f9f7 90 {
<> 144:ef7eb2e8f9f7 91 tmp32 |= ADC_CFG1_ADLPC_MASK;
<> 144:ef7eb2e8f9f7 92 }
<> 144:ef7eb2e8f9f7 93 base->CFG1 = tmp32;
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 /* ADCx_CFG2. */
<> 144:ef7eb2e8f9f7 96 tmp32 = base->CFG2 & ~(ADC_CFG2_ADACKEN_MASK | ADC_CFG2_ADHSC_MASK | ADC_CFG2_ADLSTS_MASK);
<> 144:ef7eb2e8f9f7 97 if (kADC16_LongSampleDisabled != config->longSampleMode)
<> 144:ef7eb2e8f9f7 98 {
<> 144:ef7eb2e8f9f7 99 tmp32 |= ADC_CFG2_ADLSTS(config->longSampleMode);
<> 144:ef7eb2e8f9f7 100 }
<> 144:ef7eb2e8f9f7 101 if (config->enableHighSpeed)
<> 144:ef7eb2e8f9f7 102 {
<> 144:ef7eb2e8f9f7 103 tmp32 |= ADC_CFG2_ADHSC_MASK;
<> 144:ef7eb2e8f9f7 104 }
<> 144:ef7eb2e8f9f7 105 if (config->enableAsynchronousClock)
<> 144:ef7eb2e8f9f7 106 {
<> 144:ef7eb2e8f9f7 107 tmp32 |= ADC_CFG2_ADACKEN_MASK;
<> 144:ef7eb2e8f9f7 108 }
<> 144:ef7eb2e8f9f7 109 base->CFG2 = tmp32;
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 /* ADCx_SC2. */
<> 144:ef7eb2e8f9f7 112 tmp32 = base->SC2 & ~(ADC_SC2_REFSEL_MASK);
<> 144:ef7eb2e8f9f7 113 tmp32 |= ADC_SC2_REFSEL(config->referenceVoltageSource);
<> 144:ef7eb2e8f9f7 114 base->SC2 = tmp32;
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 /* ADCx_SC3. */
<> 144:ef7eb2e8f9f7 117 if (config->enableContinuousConversion)
<> 144:ef7eb2e8f9f7 118 {
<> 144:ef7eb2e8f9f7 119 base->SC3 |= ADC_SC3_ADCO_MASK;
<> 144:ef7eb2e8f9f7 120 }
<> 144:ef7eb2e8f9f7 121 else
<> 144:ef7eb2e8f9f7 122 {
<> 144:ef7eb2e8f9f7 123 base->SC3 &= ~ADC_SC3_ADCO_MASK;
<> 144:ef7eb2e8f9f7 124 }
<> 144:ef7eb2e8f9f7 125 }
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 void ADC16_Deinit(ADC_Type *base)
<> 144:ef7eb2e8f9f7 128 {
<> 144:ef7eb2e8f9f7 129 /* Disable the clock. */
<> 144:ef7eb2e8f9f7 130 CLOCK_DisableClock(s_adc16Clocks[ADC16_GetInstance(base)]);
<> 144:ef7eb2e8f9f7 131 }
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 void ADC16_GetDefaultConfig(adc16_config_t *config)
<> 144:ef7eb2e8f9f7 134 {
<> 144:ef7eb2e8f9f7 135 assert(NULL != config);
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 config->referenceVoltageSource = kADC16_ReferenceVoltageSourceVref;
<> 144:ef7eb2e8f9f7 138 config->clockSource = kADC16_ClockSourceAsynchronousClock;
<> 144:ef7eb2e8f9f7 139 config->enableAsynchronousClock = true;
<> 144:ef7eb2e8f9f7 140 config->clockDivider = kADC16_ClockDivider8;
<> 144:ef7eb2e8f9f7 141 config->resolution = kADC16_ResolutionSE12Bit;
<> 144:ef7eb2e8f9f7 142 config->longSampleMode = kADC16_LongSampleDisabled;
<> 144:ef7eb2e8f9f7 143 config->enableHighSpeed = false;
<> 144:ef7eb2e8f9f7 144 config->enableLowPower = false;
<> 144:ef7eb2e8f9f7 145 config->enableContinuousConversion = false;
<> 144:ef7eb2e8f9f7 146 }
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 #if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION
<> 144:ef7eb2e8f9f7 149 status_t ADC16_DoAutoCalibration(ADC_Type *base)
<> 144:ef7eb2e8f9f7 150 {
<> 144:ef7eb2e8f9f7 151 bool bHWTrigger = false;
<> 144:ef7eb2e8f9f7 152 uint32_t tmp32;
<> 144:ef7eb2e8f9f7 153 status_t status = kStatus_Success;
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 /* The calibration would be failed when in hardwar mode.
<> 144:ef7eb2e8f9f7 156 * Remember the hardware trigger state here and restore it later if the hardware trigger is enabled.*/
<> 144:ef7eb2e8f9f7 157 if (0U != (ADC_SC2_ADTRG_MASK & base->SC2))
<> 144:ef7eb2e8f9f7 158 {
<> 144:ef7eb2e8f9f7 159 bHWTrigger = true;
<> 144:ef7eb2e8f9f7 160 base->SC2 &= ~ADC_SC2_ADTRG_MASK;
<> 144:ef7eb2e8f9f7 161 }
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 /* Clear the CALF and launch the calibration. */
<> 144:ef7eb2e8f9f7 164 base->SC3 |= ADC_SC3_CAL_MASK | ADC_SC3_CALF_MASK;
<> 144:ef7eb2e8f9f7 165 while (0U == (kADC16_ChannelConversionDoneFlag & ADC16_GetChannelStatusFlags(base, 0U)))
<> 144:ef7eb2e8f9f7 166 {
<> 144:ef7eb2e8f9f7 167 /* Check the CALF when the calibration is active. */
<> 144:ef7eb2e8f9f7 168 if (0U != (kADC16_CalibrationFailedFlag & ADC16_GetStatusFlags(base)))
<> 144:ef7eb2e8f9f7 169 {
<> 144:ef7eb2e8f9f7 170 status = kStatus_Fail;
<> 144:ef7eb2e8f9f7 171 break;
<> 144:ef7eb2e8f9f7 172 }
<> 144:ef7eb2e8f9f7 173 }
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 /* Restore the hardware trigger setting if it was enabled before. */
<> 144:ef7eb2e8f9f7 176 if (bHWTrigger)
<> 144:ef7eb2e8f9f7 177 {
<> 144:ef7eb2e8f9f7 178 base->SC2 |= ADC_SC2_ADTRG_MASK;
<> 144:ef7eb2e8f9f7 179 }
<> 144:ef7eb2e8f9f7 180 /* Check the CALF at the end of calibration. */
<> 144:ef7eb2e8f9f7 181 if (0U != (kADC16_CalibrationFailedFlag & ADC16_GetStatusFlags(base)))
<> 144:ef7eb2e8f9f7 182 {
<> 144:ef7eb2e8f9f7 183 status = kStatus_Fail;
<> 144:ef7eb2e8f9f7 184 }
<> 144:ef7eb2e8f9f7 185 if (kStatus_Success != status) /* Check if the calibration process is succeed. */
<> 144:ef7eb2e8f9f7 186 {
<> 144:ef7eb2e8f9f7 187 return status;
<> 144:ef7eb2e8f9f7 188 }
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 /* Calculate the calibration values. */
<> 144:ef7eb2e8f9f7 191 tmp32 = base->CLP0 + base->CLP1 + base->CLP2 + base->CLP3 + base->CLP4 + base->CLPS;
<> 144:ef7eb2e8f9f7 192 tmp32 = 0x8000U | (tmp32 >> 1U);
<> 144:ef7eb2e8f9f7 193 base->PG = tmp32;
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 #if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE
<> 144:ef7eb2e8f9f7 196 tmp32 = base->CLM0 + base->CLM1 + base->CLM2 + base->CLM3 + base->CLM4 + base->CLMS;
<> 144:ef7eb2e8f9f7 197 tmp32 = 0x8000U | (tmp32 >> 1U);
<> 144:ef7eb2e8f9f7 198 base->MG = tmp32;
<> 144:ef7eb2e8f9f7 199 #endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 return kStatus_Success;
<> 144:ef7eb2e8f9f7 202 }
<> 144:ef7eb2e8f9f7 203 #endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 #if defined(FSL_FEATURE_ADC16_HAS_MUX_SELECT) && FSL_FEATURE_ADC16_HAS_MUX_SELECT
<> 144:ef7eb2e8f9f7 206 void ADC16_SetChannelMuxMode(ADC_Type *base, adc16_channel_mux_mode_t mode)
<> 144:ef7eb2e8f9f7 207 {
<> 144:ef7eb2e8f9f7 208 if (kADC16_ChannelMuxA == mode)
<> 144:ef7eb2e8f9f7 209 {
<> 144:ef7eb2e8f9f7 210 base->CFG2 &= ~ADC_CFG2_MUXSEL_MASK;
<> 144:ef7eb2e8f9f7 211 }
<> 144:ef7eb2e8f9f7 212 else /* kADC16_ChannelMuxB. */
<> 144:ef7eb2e8f9f7 213 {
<> 144:ef7eb2e8f9f7 214 base->CFG2 |= ADC_CFG2_MUXSEL_MASK;
<> 144:ef7eb2e8f9f7 215 }
<> 144:ef7eb2e8f9f7 216 }
<> 144:ef7eb2e8f9f7 217 #endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 void ADC16_SetHardwareCompareConfig(ADC_Type *base, const adc16_hardware_compare_config_t *config)
<> 144:ef7eb2e8f9f7 220 {
<> 144:ef7eb2e8f9f7 221 uint32_t tmp32 = base->SC2 & ~(ADC_SC2_ACFE_MASK | ADC_SC2_ACFGT_MASK | ADC_SC2_ACREN_MASK);
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 if (!config) /* Pass "NULL" to disable the feature. */
<> 144:ef7eb2e8f9f7 224 {
<> 144:ef7eb2e8f9f7 225 base->SC2 = tmp32;
<> 144:ef7eb2e8f9f7 226 return;
<> 144:ef7eb2e8f9f7 227 }
<> 144:ef7eb2e8f9f7 228 /* Enable the feature. */
<> 144:ef7eb2e8f9f7 229 tmp32 |= ADC_SC2_ACFE_MASK;
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 /* Select the hardware compare working mode. */
<> 144:ef7eb2e8f9f7 232 switch (config->hardwareCompareMode)
<> 144:ef7eb2e8f9f7 233 {
<> 144:ef7eb2e8f9f7 234 case kADC16_HardwareCompareMode0:
<> 144:ef7eb2e8f9f7 235 break;
<> 144:ef7eb2e8f9f7 236 case kADC16_HardwareCompareMode1:
<> 144:ef7eb2e8f9f7 237 tmp32 |= ADC_SC2_ACFGT_MASK;
<> 144:ef7eb2e8f9f7 238 break;
<> 144:ef7eb2e8f9f7 239 case kADC16_HardwareCompareMode2:
<> 144:ef7eb2e8f9f7 240 tmp32 |= ADC_SC2_ACREN_MASK;
<> 144:ef7eb2e8f9f7 241 break;
<> 144:ef7eb2e8f9f7 242 case kADC16_HardwareCompareMode3:
<> 144:ef7eb2e8f9f7 243 tmp32 |= ADC_SC2_ACFGT_MASK | ADC_SC2_ACREN_MASK;
<> 144:ef7eb2e8f9f7 244 break;
<> 144:ef7eb2e8f9f7 245 default:
<> 144:ef7eb2e8f9f7 246 break;
<> 144:ef7eb2e8f9f7 247 }
<> 144:ef7eb2e8f9f7 248 base->SC2 = tmp32;
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250 /* Load the compare values. */
<> 144:ef7eb2e8f9f7 251 base->CV1 = ADC_CV1_CV(config->value1);
<> 144:ef7eb2e8f9f7 252 base->CV2 = ADC_CV2_CV(config->value2);
<> 144:ef7eb2e8f9f7 253 }
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 #if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE
<> 144:ef7eb2e8f9f7 256 void ADC16_SetHardwareAverage(ADC_Type *base, adc16_hardware_average_mode_t mode)
<> 144:ef7eb2e8f9f7 257 {
<> 144:ef7eb2e8f9f7 258 uint32_t tmp32 = base->SC3 & ~(ADC_SC3_AVGE_MASK | ADC_SC3_AVGS_MASK);
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 if (kADC16_HardwareAverageDisabled != mode)
<> 144:ef7eb2e8f9f7 261 {
<> 144:ef7eb2e8f9f7 262 tmp32 |= ADC_SC3_AVGE_MASK | ADC_SC3_AVGS(mode);
<> 144:ef7eb2e8f9f7 263 }
<> 144:ef7eb2e8f9f7 264 base->SC3 = tmp32;
<> 144:ef7eb2e8f9f7 265 }
<> 144:ef7eb2e8f9f7 266 #endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 #if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA
<> 144:ef7eb2e8f9f7 269 void ADC16_SetPGAConfig(ADC_Type *base, const adc16_pga_config_t *config)
<> 144:ef7eb2e8f9f7 270 {
<> 144:ef7eb2e8f9f7 271 uint32_t tmp32;
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 if (!config) /* Passing "NULL" is to disable the feature. */
<> 144:ef7eb2e8f9f7 274 {
<> 144:ef7eb2e8f9f7 275 base->PGA = 0U;
<> 144:ef7eb2e8f9f7 276 return;
<> 144:ef7eb2e8f9f7 277 }
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 /* Enable the PGA and set the gain value. */
<> 144:ef7eb2e8f9f7 280 tmp32 = ADC_PGA_PGAEN_MASK | ADC_PGA_PGAG(config->pgaGain);
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 /* Configure the misc features for PGA. */
<> 144:ef7eb2e8f9f7 283 if (config->enableRunInNormalMode)
<> 144:ef7eb2e8f9f7 284 {
<> 144:ef7eb2e8f9f7 285 tmp32 |= ADC_PGA_PGALPb_MASK;
<> 144:ef7eb2e8f9f7 286 }
<> 144:ef7eb2e8f9f7 287 #if defined(FSL_FEATURE_ADC16_HAS_PGA_CHOPPING) && FSL_FEATURE_ADC16_HAS_PGA_CHOPPING
<> 144:ef7eb2e8f9f7 288 if (config->disablePgaChopping)
<> 144:ef7eb2e8f9f7 289 {
<> 144:ef7eb2e8f9f7 290 tmp32 |= ADC_PGA_PGACHPb_MASK;
<> 144:ef7eb2e8f9f7 291 }
<> 144:ef7eb2e8f9f7 292 #endif /* FSL_FEATURE_ADC16_HAS_PGA_CHOPPING */
<> 144:ef7eb2e8f9f7 293 #if defined(FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT) && FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT
<> 144:ef7eb2e8f9f7 294 if (config->enableRunInOffsetMeasurement)
<> 144:ef7eb2e8f9f7 295 {
<> 144:ef7eb2e8f9f7 296 tmp32 |= ADC_PGA_PGAOFSM_MASK;
<> 144:ef7eb2e8f9f7 297 }
<> 144:ef7eb2e8f9f7 298 #endif /* FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT */
<> 144:ef7eb2e8f9f7 299 base->PGA = tmp32;
<> 144:ef7eb2e8f9f7 300 }
<> 144:ef7eb2e8f9f7 301 #endif /* FSL_FEATURE_ADC16_HAS_PGA */
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 uint32_t ADC16_GetStatusFlags(ADC_Type *base)
<> 144:ef7eb2e8f9f7 304 {
<> 144:ef7eb2e8f9f7 305 uint32_t ret = 0;
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 if (0U != (base->SC2 & ADC_SC2_ADACT_MASK))
<> 144:ef7eb2e8f9f7 308 {
<> 144:ef7eb2e8f9f7 309 ret |= kADC16_ActiveFlag;
<> 144:ef7eb2e8f9f7 310 }
<> 144:ef7eb2e8f9f7 311 #if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION
<> 144:ef7eb2e8f9f7 312 if (0U != (base->SC3 & ADC_SC3_CALF_MASK))
<> 144:ef7eb2e8f9f7 313 {
<> 144:ef7eb2e8f9f7 314 ret |= kADC16_CalibrationFailedFlag;
<> 144:ef7eb2e8f9f7 315 }
<> 144:ef7eb2e8f9f7 316 #endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */
<> 144:ef7eb2e8f9f7 317 return ret;
<> 144:ef7eb2e8f9f7 318 }
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320 void ADC16_ClearStatusFlags(ADC_Type *base, uint32_t mask)
<> 144:ef7eb2e8f9f7 321 {
<> 144:ef7eb2e8f9f7 322 #if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION
<> 144:ef7eb2e8f9f7 323 if (0U != (mask & kADC16_CalibrationFailedFlag))
<> 144:ef7eb2e8f9f7 324 {
<> 144:ef7eb2e8f9f7 325 base->SC3 |= ADC_SC3_CALF_MASK;
<> 144:ef7eb2e8f9f7 326 }
<> 144:ef7eb2e8f9f7 327 #endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */
<> 144:ef7eb2e8f9f7 328 }
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 void ADC16_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc16_channel_config_t *config)
<> 144:ef7eb2e8f9f7 331 {
<> 144:ef7eb2e8f9f7 332 assert(channelGroup < ADC_SC1_COUNT);
<> 144:ef7eb2e8f9f7 333 assert(NULL != config);
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 uint32_t sc1 = ADC_SC1_ADCH(config->channelNumber); /* Set the channel number. */
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 #if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE
<> 144:ef7eb2e8f9f7 338 /* Enable the differential conversion. */
<> 144:ef7eb2e8f9f7 339 if (config->enableDifferentialConversion)
<> 144:ef7eb2e8f9f7 340 {
<> 144:ef7eb2e8f9f7 341 sc1 |= ADC_SC1_DIFF_MASK;
<> 144:ef7eb2e8f9f7 342 }
<> 144:ef7eb2e8f9f7 343 #endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */
<> 144:ef7eb2e8f9f7 344 /* Enable the interrupt when the conversion is done. */
<> 144:ef7eb2e8f9f7 345 if (config->enableInterruptOnConversionCompleted)
<> 144:ef7eb2e8f9f7 346 {
<> 144:ef7eb2e8f9f7 347 sc1 |= ADC_SC1_AIEN_MASK;
<> 144:ef7eb2e8f9f7 348 }
<> 144:ef7eb2e8f9f7 349 base->SC1[channelGroup] = sc1;
<> 144:ef7eb2e8f9f7 350 }
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 uint32_t ADC16_GetChannelStatusFlags(ADC_Type *base, uint32_t channelGroup)
<> 144:ef7eb2e8f9f7 353 {
<> 144:ef7eb2e8f9f7 354 assert(channelGroup < ADC_SC1_COUNT);
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 uint32_t ret = 0U;
<> 144:ef7eb2e8f9f7 357
<> 144:ef7eb2e8f9f7 358 if (0U != (base->SC1[channelGroup] & ADC_SC1_COCO_MASK))
<> 144:ef7eb2e8f9f7 359 {
<> 144:ef7eb2e8f9f7 360 ret |= kADC16_ChannelConversionDoneFlag;
<> 144:ef7eb2e8f9f7 361 }
<> 144:ef7eb2e8f9f7 362 return ret;
<> 144:ef7eb2e8f9f7 363 }