mbed-dev - added prescaler for 16 bit pwm in LPC1347 target

Users » JojoS » Code » mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc_ex.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:: <>
Date:: Fri Sep 02 15:07:44 2016 +0100
Revision:: 144:ef7eb2e8f9f7
Parent:: 83:a036322b8637

This updates the lib to the mbed lib v125

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32f7xx_hal_rcc_ex.c
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	144:ef7eb2e8f9f7	5	* @version V1.1.0
<>	144:ef7eb2e8f9f7	6	* @date 22-April-2016
<>	144:ef7eb2e8f9f7	7	* @brief Extension RCC HAL module driver.
<>	144:ef7eb2e8f9f7	8	* This file provides firmware functions to manage the following
<>	144:ef7eb2e8f9f7	9	* functionalities RCC extension peripheral:
<>	144:ef7eb2e8f9f7	10	* + Extended Peripheral Control functions
<>	144:ef7eb2e8f9f7	11	*
<>	144:ef7eb2e8f9f7	12	******************************************************************************
<>	144:ef7eb2e8f9f7	13	* @attention
<>	144:ef7eb2e8f9f7	14	*
<>	144:ef7eb2e8f9f7	15	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	16	*
<>	144:ef7eb2e8f9f7	17	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	18	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	19	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	20	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	21	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	22	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	23	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	24	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	25	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	26	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	27	*
<>	144:ef7eb2e8f9f7	28	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	29	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	30	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	31	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	32	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	33	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	34	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	35	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	36	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	37	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	38	*
<>	144:ef7eb2e8f9f7	39	******************************************************************************
<>	144:ef7eb2e8f9f7	40	*/
<>	144:ef7eb2e8f9f7	41
<>	144:ef7eb2e8f9f7	42	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	43	#include "stm32f7xx_hal.h"
<>	144:ef7eb2e8f9f7	44
<>	144:ef7eb2e8f9f7	45	/** @addtogroup STM32F7xx_HAL_Driver
<>	144:ef7eb2e8f9f7	46	* @{
<>	144:ef7eb2e8f9f7	47	*/
<>	144:ef7eb2e8f9f7	48
<>	144:ef7eb2e8f9f7	49	/** @defgroup RCCEx RCCEx
<>	144:ef7eb2e8f9f7	50	* @brief RCCEx HAL module driver
<>	144:ef7eb2e8f9f7	51	* @{
<>	144:ef7eb2e8f9f7	52	*/
<>	144:ef7eb2e8f9f7	53
<>	144:ef7eb2e8f9f7	54	#ifdef HAL_RCC_MODULE_ENABLED
<>	144:ef7eb2e8f9f7	55
<>	144:ef7eb2e8f9f7	56	/* Private typedef -----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	57	/* Private define ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	58	/** @defgroup RCCEx_Private_Defines RCCEx Private Defines
<>	144:ef7eb2e8f9f7	59	* @{
<>	144:ef7eb2e8f9f7	60	*/
<>	144:ef7eb2e8f9f7	61
<>	144:ef7eb2e8f9f7	62	#define PLLI2S_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */
<>	144:ef7eb2e8f9f7	63	#define PLLSAI_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */
<>	144:ef7eb2e8f9f7	64
<>	144:ef7eb2e8f9f7	65	/**
<>	144:ef7eb2e8f9f7	66	* @}
<>	144:ef7eb2e8f9f7	67	*/
<>	144:ef7eb2e8f9f7	68	/* Private macro -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	69	/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
<>	144:ef7eb2e8f9f7	70	* @{
<>	144:ef7eb2e8f9f7	71	*/
<>	144:ef7eb2e8f9f7	72	/**
<>	144:ef7eb2e8f9f7	73	* @}
<>	144:ef7eb2e8f9f7	74	*/
<>	144:ef7eb2e8f9f7	75
<>	144:ef7eb2e8f9f7	76	/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
<>	144:ef7eb2e8f9f7	77	* @{
<>	144:ef7eb2e8f9f7	78	*/
<>	144:ef7eb2e8f9f7	79
<>	144:ef7eb2e8f9f7	80	/**
<>	144:ef7eb2e8f9f7	81	* @}
<>	144:ef7eb2e8f9f7	82	*/
<>	144:ef7eb2e8f9f7	83
<>	144:ef7eb2e8f9f7	84
<>	144:ef7eb2e8f9f7	85	/* Private variables ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	86	/* Private function prototypes -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	87	/* Private functions ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	88
<>	144:ef7eb2e8f9f7	89	/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
<>	144:ef7eb2e8f9f7	90	* @{
<>	144:ef7eb2e8f9f7	91	*/
<>	144:ef7eb2e8f9f7	92
<>	144:ef7eb2e8f9f7	93	/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
<>	144:ef7eb2e8f9f7	94	* @brief Extended Peripheral Control functions
<>	144:ef7eb2e8f9f7	95	*
<>	144:ef7eb2e8f9f7	96	@verbatim
<>	144:ef7eb2e8f9f7	97	===============================================================================
<>	144:ef7eb2e8f9f7	98	##### Extended Peripheral Control functions #####
<>	144:ef7eb2e8f9f7	99	===============================================================================
<>	144:ef7eb2e8f9f7	100	[..]
<>	144:ef7eb2e8f9f7	101	This subsection provides a set of functions allowing to control the RCC Clocks
<>	144:ef7eb2e8f9f7	102	frequencies.
<>	144:ef7eb2e8f9f7	103	[..]
<>	144:ef7eb2e8f9f7	104	(@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
<>	144:ef7eb2e8f9f7	105	select the RTC clock source; in this case the Backup domain will be reset in
<>	144:ef7eb2e8f9f7	106	order to modify the RTC Clock source, as consequence RTC registers (including
<>	144:ef7eb2e8f9f7	107	the backup registers) and RCC_BDCR register will be set to their reset values.
<>	144:ef7eb2e8f9f7	108
<>	144:ef7eb2e8f9f7	109	@endverbatim
<>	144:ef7eb2e8f9f7	110	* @{
<>	144:ef7eb2e8f9f7	111	*/
<>	144:ef7eb2e8f9f7	112	/**
<>	144:ef7eb2e8f9f7	113	* @brief Initializes the RCC extended peripherals clocks according to the specified
<>	144:ef7eb2e8f9f7	114	* parameters in the RCC_PeriphCLKInitTypeDef.
<>	144:ef7eb2e8f9f7	115	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
<>	144:ef7eb2e8f9f7	116	* contains the configuration information for the Extended Peripherals
<>	144:ef7eb2e8f9f7	117	* clocks(I2S, SAI, LTDC, RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...).
<>	144:ef7eb2e8f9f7	118	*
<>	144:ef7eb2e8f9f7	119	* @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
<>	144:ef7eb2e8f9f7	120	* the RTC clock source; in this case the Backup domain will be reset in
<>	144:ef7eb2e8f9f7	121	* order to modify the RTC Clock source, as consequence RTC registers (including
<>	144:ef7eb2e8f9f7	122	* the backup registers) are set to their reset values.
<>	144:ef7eb2e8f9f7	123	*
<>	144:ef7eb2e8f9f7	124	* @retval HAL status
<>	144:ef7eb2e8f9f7	125	*/
<>	144:ef7eb2e8f9f7	126	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
<>	144:ef7eb2e8f9f7	127	{
<>	144:ef7eb2e8f9f7	128	uint32_t tickstart = 0;
<>	144:ef7eb2e8f9f7	129	uint32_t tmpreg0 = 0;
<>	144:ef7eb2e8f9f7	130	uint32_t tmpreg1 = 0;
<>	144:ef7eb2e8f9f7	131	uint32_t plli2sused = 0;
<>	144:ef7eb2e8f9f7	132	uint32_t pllsaiused = 0;
<>	144:ef7eb2e8f9f7	133
<>	144:ef7eb2e8f9f7	134	/* Check the parameters */
<>	144:ef7eb2e8f9f7	135	assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
<>	144:ef7eb2e8f9f7	136
<>	144:ef7eb2e8f9f7	137	/----------------------------------- I2S configuration ----------------------------------/
<>	144:ef7eb2e8f9f7	138	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
<>	144:ef7eb2e8f9f7	139	{
<>	144:ef7eb2e8f9f7	140	/* Check the parameters */
<>	144:ef7eb2e8f9f7	141	assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
<>	144:ef7eb2e8f9f7	142
<>	144:ef7eb2e8f9f7	143	/* Configure I2S Clock source */
<>	144:ef7eb2e8f9f7	144	__HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
<>	144:ef7eb2e8f9f7	145
<>	144:ef7eb2e8f9f7	146	/* Enable the PLLI2S when it's used as clock source for I2S */
<>	144:ef7eb2e8f9f7	147	if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)
<>	144:ef7eb2e8f9f7	148	{
<>	144:ef7eb2e8f9f7	149	plli2sused = 1;
<>	144:ef7eb2e8f9f7	150	}
<>	144:ef7eb2e8f9f7	151	}
<>	144:ef7eb2e8f9f7	152
<>	144:ef7eb2e8f9f7	153	/------------------------------------ SAI1 configuration --------------------------------------/
<>	144:ef7eb2e8f9f7	154	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
<>	144:ef7eb2e8f9f7	155	{
<>	144:ef7eb2e8f9f7	156	/* Check the parameters */
<>	144:ef7eb2e8f9f7	157	assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
<>	144:ef7eb2e8f9f7	158
<>	144:ef7eb2e8f9f7	159	/* Configure SAI1 Clock source */
<>	144:ef7eb2e8f9f7	160	__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
<>	144:ef7eb2e8f9f7	161	/* Enable the PLLI2S when it's used as clock source for SAI */
<>	144:ef7eb2e8f9f7	162	if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
<>	144:ef7eb2e8f9f7	163	{
<>	144:ef7eb2e8f9f7	164	plli2sused = 1;
<>	144:ef7eb2e8f9f7	165	}
<>	144:ef7eb2e8f9f7	166	/* Enable the PLLSAI when it's used as clock source for SAI */
<>	144:ef7eb2e8f9f7	167	if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
<>	144:ef7eb2e8f9f7	168	{
<>	144:ef7eb2e8f9f7	169	pllsaiused = 1;
<>	144:ef7eb2e8f9f7	170	}
<>	144:ef7eb2e8f9f7	171	}
<>	144:ef7eb2e8f9f7	172
<>	144:ef7eb2e8f9f7	173	/------------------------------------ SAI2 configuration --------------------------------------/
<>	144:ef7eb2e8f9f7	174	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
<>	144:ef7eb2e8f9f7	175	{
<>	144:ef7eb2e8f9f7	176	/* Check the parameters */
<>	144:ef7eb2e8f9f7	177	assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
<>	144:ef7eb2e8f9f7	178
<>	144:ef7eb2e8f9f7	179	/* Configure SAI2 Clock source */
<>	144:ef7eb2e8f9f7	180	__HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
<>	144:ef7eb2e8f9f7	181
<>	144:ef7eb2e8f9f7	182	/* Enable the PLLI2S when it's used as clock source for SAI */
<>	144:ef7eb2e8f9f7	183	if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
<>	144:ef7eb2e8f9f7	184	{
<>	144:ef7eb2e8f9f7	185	plli2sused = 1;
<>	144:ef7eb2e8f9f7	186	}
<>	144:ef7eb2e8f9f7	187	/* Enable the PLLSAI when it's used as clock source for SAI */
<>	144:ef7eb2e8f9f7	188	if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
<>	144:ef7eb2e8f9f7	189	{
<>	144:ef7eb2e8f9f7	190	pllsaiused = 1;
<>	144:ef7eb2e8f9f7	191	}
<>	144:ef7eb2e8f9f7	192	}
<>	144:ef7eb2e8f9f7	193
<>	144:ef7eb2e8f9f7	194	/-------------------------------------- SPDIF-RX Configuration -----------------------------------/
<>	144:ef7eb2e8f9f7	195	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
<>	144:ef7eb2e8f9f7	196	{
<>	144:ef7eb2e8f9f7	197	plli2sused = 1;
<>	144:ef7eb2e8f9f7	198	}
<>	144:ef7eb2e8f9f7	199
<>	144:ef7eb2e8f9f7	200	/------------------------------------ RTC configuration --------------------------------------/
<>	144:ef7eb2e8f9f7	201	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
<>	144:ef7eb2e8f9f7	202	{
<>	144:ef7eb2e8f9f7	203	/* Check for RTC Parameters used to output RTCCLK */
<>	144:ef7eb2e8f9f7	204	assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
<>	144:ef7eb2e8f9f7	205
<>	144:ef7eb2e8f9f7	206	/* Enable Power Clock*/
<>	144:ef7eb2e8f9f7	207	__HAL_RCC_PWR_CLK_ENABLE();
<>	144:ef7eb2e8f9f7	208
<>	144:ef7eb2e8f9f7	209	/* Enable write access to Backup domain */
<>	144:ef7eb2e8f9f7	210	PWR->CR1 \|= PWR_CR1_DBP;
<>	144:ef7eb2e8f9f7	211
<>	144:ef7eb2e8f9f7	212	/* Get Start Tick*/
<>	144:ef7eb2e8f9f7	213	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	214
<>	144:ef7eb2e8f9f7	215	/* Wait for Backup domain Write protection disable */
<>	144:ef7eb2e8f9f7	216	while((PWR->CR1 & PWR_CR1_DBP) == RESET)
<>	144:ef7eb2e8f9f7	217	{
<>	144:ef7eb2e8f9f7	218	if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
<>	144:ef7eb2e8f9f7	219	{
<>	144:ef7eb2e8f9f7	220	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	221	}
<>	144:ef7eb2e8f9f7	222	}
<>	144:ef7eb2e8f9f7	223
<>	144:ef7eb2e8f9f7	224	/* Reset the Backup domain only if the RTC Clock source selection is modified */
<>	144:ef7eb2e8f9f7	225	tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL);
<>	144:ef7eb2e8f9f7	226
<>	144:ef7eb2e8f9f7	227	if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
<>	144:ef7eb2e8f9f7	228	{
<>	144:ef7eb2e8f9f7	229	/* Store the content of BDCR register before the reset of Backup Domain */
<>	144:ef7eb2e8f9f7	230	tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
<>	144:ef7eb2e8f9f7	231
<>	144:ef7eb2e8f9f7	232	/* RTC Clock selection can be changed only if the Backup Domain is reset */
<>	144:ef7eb2e8f9f7	233	__HAL_RCC_BACKUPRESET_FORCE();
<>	144:ef7eb2e8f9f7	234	__HAL_RCC_BACKUPRESET_RELEASE();
<>	144:ef7eb2e8f9f7	235
<>	144:ef7eb2e8f9f7	236	/* Restore the Content of BDCR register */
<>	144:ef7eb2e8f9f7	237	RCC->BDCR = tmpreg0;
<>	144:ef7eb2e8f9f7	238
<>	144:ef7eb2e8f9f7	239	/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
<>	144:ef7eb2e8f9f7	240	if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
<>	144:ef7eb2e8f9f7	241	{
<>	144:ef7eb2e8f9f7	242	/* Get Start Tick*/
<>	144:ef7eb2e8f9f7	243	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	244
<>	144:ef7eb2e8f9f7	245	/* Wait till LSE is ready */
<>	144:ef7eb2e8f9f7	246	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
<>	144:ef7eb2e8f9f7	247	{
<>	144:ef7eb2e8f9f7	248	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
<>	144:ef7eb2e8f9f7	249	{
<>	144:ef7eb2e8f9f7	250	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	251	}
<>	144:ef7eb2e8f9f7	252	}
<>	144:ef7eb2e8f9f7	253	}
<>	144:ef7eb2e8f9f7	254	}
<>	144:ef7eb2e8f9f7	255	__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
<>	144:ef7eb2e8f9f7	256	}
<>	144:ef7eb2e8f9f7	257
<>	144:ef7eb2e8f9f7	258	/------------------------------------ TIM configuration --------------------------------------/
<>	144:ef7eb2e8f9f7	259	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
<>	144:ef7eb2e8f9f7	260	{
<>	144:ef7eb2e8f9f7	261	/* Check the parameters */
<>	144:ef7eb2e8f9f7	262	assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
<>	144:ef7eb2e8f9f7	263
<>	144:ef7eb2e8f9f7	264	/* Configure Timer Prescaler */
<>	144:ef7eb2e8f9f7	265	__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
<>	144:ef7eb2e8f9f7	266	}
<>	144:ef7eb2e8f9f7	267
<>	144:ef7eb2e8f9f7	268	/-------------------------------------- I2C1 Configuration -----------------------------------/
<>	144:ef7eb2e8f9f7	269	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
<>	144:ef7eb2e8f9f7	270	{
<>	144:ef7eb2e8f9f7	271	/* Check the parameters */
<>	144:ef7eb2e8f9f7	272	assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
<>	144:ef7eb2e8f9f7	273
<>	144:ef7eb2e8f9f7	274	/* Configure the I2C1 clock source */
<>	144:ef7eb2e8f9f7	275	__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
<>	144:ef7eb2e8f9f7	276	}
<>	144:ef7eb2e8f9f7	277
<>	144:ef7eb2e8f9f7	278	/-------------------------------------- I2C2 Configuration -----------------------------------/
<>	144:ef7eb2e8f9f7	279	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
<>	144:ef7eb2e8f9f7	280	{
<>	144:ef7eb2e8f9f7	281	/* Check the parameters */
<>	144:ef7eb2e8f9f7	282	assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
<>	144:ef7eb2e8f9f7	283
<>	144:ef7eb2e8f9f7	284	/* Configure the I2C2 clock source */
<>	144:ef7eb2e8f9f7	285	__HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
<>	144:ef7eb2e8f9f7	286	}
<>	144:ef7eb2e8f9f7	287
<>	144:ef7eb2e8f9f7	288	/-------------------------------------- I2C3 Configuration -----------------------------------/
<>	144:ef7eb2e8f9f7	289	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
<>	144:ef7eb2e8f9f7	290	{
<>	144:ef7eb2e8f9f7	291	/* Check the parameters */
<>	144:ef7eb2e8f9f7	292	assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
<>	144:ef7eb2e8f9f7	293
<>	144:ef7eb2e8f9f7	294	/* Configure the I2C3 clock source */
<>	144:ef7eb2e8f9f7	295	__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
<>	144:ef7eb2e8f9f7	296	}
<>	144:ef7eb2e8f9f7	297
<>	144:ef7eb2e8f9f7	298	/-------------------------------------- I2C4 Configuration -----------------------------------/
<>	144:ef7eb2e8f9f7	299	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
<>	144:ef7eb2e8f9f7	300	{
<>	144:ef7eb2e8f9f7	301	/* Check the parameters */
<>	144:ef7eb2e8f9f7	302	assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
<>	144:ef7eb2e8f9f7	303
<>	144:ef7eb2e8f9f7	304	/* Configure the I2C4 clock source */
<>	144:ef7eb2e8f9f7	305	__HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
<>	144:ef7eb2e8f9f7	306	}
<>	144:ef7eb2e8f9f7	307
<>	144:ef7eb2e8f9f7	308	/-------------------------------------- USART1 Configuration -----------------------------------/
<>	144:ef7eb2e8f9f7	309	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
<>	144:ef7eb2e8f9f7	310	{
<>	144:ef7eb2e8f9f7	311	/* Check the parameters */
<>	144:ef7eb2e8f9f7	312	assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
<>	144:ef7eb2e8f9f7	313
<>	144:ef7eb2e8f9f7	314	/* Configure the USART1 clock source */
<>	144:ef7eb2e8f9f7	315	__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
<>	144:ef7eb2e8f9f7	316	}
<>	144:ef7eb2e8f9f7	317
<>	144:ef7eb2e8f9f7	318	/-------------------------------------- USART2 Configuration -----------------------------------/
<>	144:ef7eb2e8f9f7	319	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
<>	144:ef7eb2e8f9f7	320	{
<>	144:ef7eb2e8f9f7	321	/* Check the parameters */
<>	144:ef7eb2e8f9f7	322	assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
<>	144:ef7eb2e8f9f7	323
<>	144:ef7eb2e8f9f7	324	/* Configure the USART2 clock source */
<>	144:ef7eb2e8f9f7	325	__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
<>	144:ef7eb2e8f9f7	326	}
<>	144:ef7eb2e8f9f7	327
<>	144:ef7eb2e8f9f7	328	/-------------------------------------- USART3 Configuration -----------------------------------/
<>	144:ef7eb2e8f9f7	329	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
<>	144:ef7eb2e8f9f7	330	{
<>	144:ef7eb2e8f9f7	331	/* Check the parameters */
<>	144:ef7eb2e8f9f7	332	assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
<>	144:ef7eb2e8f9f7	333
<>	144:ef7eb2e8f9f7	334	/* Configure the USART3 clock source */
<>	144:ef7eb2e8f9f7	335	__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
<>	144:ef7eb2e8f9f7	336	}
<>	144:ef7eb2e8f9f7	337
<>	144:ef7eb2e8f9f7	338	/-------------------------------------- UART4 Configuration -----------------------------------/
<>	144:ef7eb2e8f9f7	339	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
<>	144:ef7eb2e8f9f7	340	{
<>	144:ef7eb2e8f9f7	341	/* Check the parameters */
<>	144:ef7eb2e8f9f7	342	assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
<>	144:ef7eb2e8f9f7	343
<>	144:ef7eb2e8f9f7	344	/* Configure the UART4 clock source */
<>	144:ef7eb2e8f9f7	345	__HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
<>	144:ef7eb2e8f9f7	346	}
<>	144:ef7eb2e8f9f7	347
<>	144:ef7eb2e8f9f7	348	/-------------------------------------- UART5 Configuration -----------------------------------/
<>	144:ef7eb2e8f9f7	349	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
<>	144:ef7eb2e8f9f7	350	{
<>	144:ef7eb2e8f9f7	351	/* Check the parameters */
<>	144:ef7eb2e8f9f7	352	assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
<>	144:ef7eb2e8f9f7	353
<>	144:ef7eb2e8f9f7	354	/* Configure the UART5 clock source */
<>	144:ef7eb2e8f9f7	355	__HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
<>	144:ef7eb2e8f9f7	356	}
<>	144:ef7eb2e8f9f7	357
<>	144:ef7eb2e8f9f7	358	/-------------------------------------- USART6 Configuration -----------------------------------/
<>	144:ef7eb2e8f9f7	359	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)
<>	144:ef7eb2e8f9f7	360	{
<>	144:ef7eb2e8f9f7	361	/* Check the parameters */
<>	144:ef7eb2e8f9f7	362	assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection));
<>	144:ef7eb2e8f9f7	363
<>	144:ef7eb2e8f9f7	364	/* Configure the USART6 clock source */
<>	144:ef7eb2e8f9f7	365	__HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);
<>	144:ef7eb2e8f9f7	366	}
<>	144:ef7eb2e8f9f7	367
<>	144:ef7eb2e8f9f7	368	/-------------------------------------- UART7 Configuration -----------------------------------/
<>	144:ef7eb2e8f9f7	369	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7)
<>	144:ef7eb2e8f9f7	370	{
<>	144:ef7eb2e8f9f7	371	/* Check the parameters */
<>	144:ef7eb2e8f9f7	372	assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection));
<>	144:ef7eb2e8f9f7	373
<>	144:ef7eb2e8f9f7	374	/* Configure the UART7 clock source */
<>	144:ef7eb2e8f9f7	375	__HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection);
<>	144:ef7eb2e8f9f7	376	}
<>	144:ef7eb2e8f9f7	377
<>	144:ef7eb2e8f9f7	378	/-------------------------------------- UART8 Configuration -----------------------------------/
<>	144:ef7eb2e8f9f7	379	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8)
<>	144:ef7eb2e8f9f7	380	{
<>	144:ef7eb2e8f9f7	381	/* Check the parameters */
<>	144:ef7eb2e8f9f7	382	assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection));
<>	144:ef7eb2e8f9f7	383
<>	144:ef7eb2e8f9f7	384	/* Configure the UART8 clock source */
<>	144:ef7eb2e8f9f7	385	__HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection);
<>	144:ef7eb2e8f9f7	386	}
<>	144:ef7eb2e8f9f7	387
<>	144:ef7eb2e8f9f7	388	/--------------------------------------- CEC Configuration -----------------------------------/
<>	144:ef7eb2e8f9f7	389	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
<>	144:ef7eb2e8f9f7	390	{
<>	144:ef7eb2e8f9f7	391	/* Check the parameters */
<>	144:ef7eb2e8f9f7	392	assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
<>	144:ef7eb2e8f9f7	393
<>	144:ef7eb2e8f9f7	394	/* Configure the CEC clock source */
<>	144:ef7eb2e8f9f7	395	__HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
<>	144:ef7eb2e8f9f7	396	}
<>	144:ef7eb2e8f9f7	397
<>	144:ef7eb2e8f9f7	398	/-------------------------------------- CK48 Configuration -----------------------------------/
<>	144:ef7eb2e8f9f7	399	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
<>	144:ef7eb2e8f9f7	400	{
<>	144:ef7eb2e8f9f7	401	/* Check the parameters */
<>	144:ef7eb2e8f9f7	402	assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection));
<>	144:ef7eb2e8f9f7	403
<>	144:ef7eb2e8f9f7	404	/* Configure the CLK48 source */
<>	144:ef7eb2e8f9f7	405	__HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
<>	144:ef7eb2e8f9f7	406
<>	144:ef7eb2e8f9f7	407	/* Enable the PLLSAI when it's used as clock source for CK48 */
<>	144:ef7eb2e8f9f7	408	if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)
<>	144:ef7eb2e8f9f7	409	{
<>	144:ef7eb2e8f9f7	410	pllsaiused = 1;
<>	144:ef7eb2e8f9f7	411	}
<>	144:ef7eb2e8f9f7	412	}
<>	144:ef7eb2e8f9f7	413
<>	144:ef7eb2e8f9f7	414	/-------------------------------------- LTDC Configuration -----------------------------------/
<>	144:ef7eb2e8f9f7	415	#if defined(STM32F746xx) \|\| defined(STM32F756xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	416	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
<>	144:ef7eb2e8f9f7	417	{
<>	144:ef7eb2e8f9f7	418	pllsaiused = 1;
<>	144:ef7eb2e8f9f7	419	}
<>	144:ef7eb2e8f9f7	420	#endif /* STM32F746xx \|\| STM32F756xx \|\| STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	421
<>	144:ef7eb2e8f9f7	422	/-------------------------------------- LPTIM1 Configuration -----------------------------------/
<>	144:ef7eb2e8f9f7	423	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
<>	144:ef7eb2e8f9f7	424	{
<>	144:ef7eb2e8f9f7	425	/* Check the parameters */
<>	144:ef7eb2e8f9f7	426	assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
<>	144:ef7eb2e8f9f7	427
<>	144:ef7eb2e8f9f7	428	/* Configure the LTPIM1 clock source */
<>	144:ef7eb2e8f9f7	429	__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
<>	144:ef7eb2e8f9f7	430	}
<>	144:ef7eb2e8f9f7	431
<>	144:ef7eb2e8f9f7	432	/------------------------------------- SDMMC1 Configuration ------------------------------------/
<>	144:ef7eb2e8f9f7	433	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)
<>	144:ef7eb2e8f9f7	434	{
<>	144:ef7eb2e8f9f7	435	/* Check the parameters */
<>	144:ef7eb2e8f9f7	436	assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
<>	144:ef7eb2e8f9f7	437
<>	144:ef7eb2e8f9f7	438	/* Configure the SDMMC1 clock source */
<>	144:ef7eb2e8f9f7	439	__HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
<>	144:ef7eb2e8f9f7	440	}
<>	144:ef7eb2e8f9f7	441
<>	144:ef7eb2e8f9f7	442	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	443	/------------------------------------- SDMMC2 Configuration ------------------------------------/
<>	144:ef7eb2e8f9f7	444	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2)
<>	144:ef7eb2e8f9f7	445	{
<>	144:ef7eb2e8f9f7	446	/* Check the parameters */
<>	144:ef7eb2e8f9f7	447	assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection));
<>	144:ef7eb2e8f9f7	448
<>	144:ef7eb2e8f9f7	449	/* Configure the SDMMC2 clock source */
<>	144:ef7eb2e8f9f7	450	__HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection);
<>	144:ef7eb2e8f9f7	451	}
<>	144:ef7eb2e8f9f7	452
<>	144:ef7eb2e8f9f7	453	/------------------------------------- DFSDM1 Configuration -------------------------------------/
<>	144:ef7eb2e8f9f7	454	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
<>	144:ef7eb2e8f9f7	455	{
<>	144:ef7eb2e8f9f7	456	/* Check the parameters */
<>	144:ef7eb2e8f9f7	457	assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
<>	144:ef7eb2e8f9f7	458
<>	144:ef7eb2e8f9f7	459	/* Configure the DFSDM1 interface clock source */
<>	144:ef7eb2e8f9f7	460	__HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
<>	144:ef7eb2e8f9f7	461	}
<>	144:ef7eb2e8f9f7	462
<>	144:ef7eb2e8f9f7	463	/------------------------------------- DFSDM AUDIO Configuration -------------------------------------/
<>	144:ef7eb2e8f9f7	464	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO)
<>	144:ef7eb2e8f9f7	465	{
<>	144:ef7eb2e8f9f7	466	/* Check the parameters */
<>	144:ef7eb2e8f9f7	467	assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection));
<>	144:ef7eb2e8f9f7	468
<>	144:ef7eb2e8f9f7	469	/* Configure the DFSDM interface clock source */
<>	144:ef7eb2e8f9f7	470	__HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection);
<>	144:ef7eb2e8f9f7	471	}
<>	144:ef7eb2e8f9f7	472	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	473
<>	144:ef7eb2e8f9f7	474	/-------------------------------------- PLLI2S Configuration ---------------------------------/
<>	144:ef7eb2e8f9f7	475	/* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */
<>	144:ef7eb2e8f9f7	476	if((plli2sused == 1) \|\| (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
<>	144:ef7eb2e8f9f7	477	{
<>	144:ef7eb2e8f9f7	478	/* Disable the PLLI2S */
<>	144:ef7eb2e8f9f7	479	__HAL_RCC_PLLI2S_DISABLE();
<>	144:ef7eb2e8f9f7	480
<>	144:ef7eb2e8f9f7	481	/* Get Start Tick*/
<>	144:ef7eb2e8f9f7	482	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	483
<>	144:ef7eb2e8f9f7	484	/* Wait till PLLI2S is disabled */
<>	144:ef7eb2e8f9f7	485	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
<>	144:ef7eb2e8f9f7	486	{
<>	144:ef7eb2e8f9f7	487	if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
<>	144:ef7eb2e8f9f7	488	{
<>	144:ef7eb2e8f9f7	489	/* return in case of Timeout detected */
<>	144:ef7eb2e8f9f7	490	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	491	}
<>	144:ef7eb2e8f9f7	492	}
<>	144:ef7eb2e8f9f7	493
<>	144:ef7eb2e8f9f7	494	/* check for common PLLI2S Parameters */
<>	144:ef7eb2e8f9f7	495	assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
<>	144:ef7eb2e8f9f7	496
<>	144:ef7eb2e8f9f7	497	/----------------- In Case of PLLI2S is selected as source clock for I2S -------------------/
<>	144:ef7eb2e8f9f7	498	if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)))
<>	144:ef7eb2e8f9f7	499	{
<>	144:ef7eb2e8f9f7	500	/* check for Parameters */
<>	144:ef7eb2e8f9f7	501	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
<>	144:ef7eb2e8f9f7	502
<>	144:ef7eb2e8f9f7	503	/* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
<>	144:ef7eb2e8f9f7	504	tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP));
<>	144:ef7eb2e8f9f7	505	tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
<>	144:ef7eb2e8f9f7	506	/* Configure the PLLI2S division factors */
<>	144:ef7eb2e8f9f7	507	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
<>	144:ef7eb2e8f9f7	508	/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
<>	144:ef7eb2e8f9f7	509	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR);
<>	144:ef7eb2e8f9f7	510	}
<>	144:ef7eb2e8f9f7	511
<>	144:ef7eb2e8f9f7	512	/----------------- In Case of PLLI2S is selected as source clock for SAI -------------------/
<>	144:ef7eb2e8f9f7	513	if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) \|\|
<>	144:ef7eb2e8f9f7	514	((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
<>	144:ef7eb2e8f9f7	515	{
<>	144:ef7eb2e8f9f7	516	/* Check for PLLI2S Parameters */
<>	144:ef7eb2e8f9f7	517	assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
<>	144:ef7eb2e8f9f7	518	/* Check for PLLI2S/DIVQ parameters */
<>	144:ef7eb2e8f9f7	519	assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
<>	144:ef7eb2e8f9f7	520
<>	144:ef7eb2e8f9f7	521	/* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */
<>	144:ef7eb2e8f9f7	522	tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP));
<>	144:ef7eb2e8f9f7	523	tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
<>	144:ef7eb2e8f9f7	524	/* Configure the PLLI2S division factors */
<>	144:ef7eb2e8f9f7	525	/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
<>	144:ef7eb2e8f9f7	526	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
<>	144:ef7eb2e8f9f7	527	/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
<>	144:ef7eb2e8f9f7	528	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1);
<>	144:ef7eb2e8f9f7	529
<>	144:ef7eb2e8f9f7	530	/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
<>	144:ef7eb2e8f9f7	531	__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
<>	144:ef7eb2e8f9f7	532	}
<>	144:ef7eb2e8f9f7	533
<>	144:ef7eb2e8f9f7	534	/----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------/
<>	144:ef7eb2e8f9f7	535	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
<>	144:ef7eb2e8f9f7	536	{
<>	144:ef7eb2e8f9f7	537	/* check for Parameters */
<>	144:ef7eb2e8f9f7	538	assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
<>	144:ef7eb2e8f9f7	539
<>	144:ef7eb2e8f9f7	540	/* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */
<>	144:ef7eb2e8f9f7	541	tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
<>	144:ef7eb2e8f9f7	542	tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
<>	144:ef7eb2e8f9f7	543	/* Configure the PLLI2S division factors */
<>	144:ef7eb2e8f9f7	544	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
<>	144:ef7eb2e8f9f7	545	/* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
<>	144:ef7eb2e8f9f7	546	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1);
<>	144:ef7eb2e8f9f7	547	}
<>	144:ef7eb2e8f9f7	548
<>	144:ef7eb2e8f9f7	549	/----------------- In Case of PLLI2S is just selected -----------------/
<>	144:ef7eb2e8f9f7	550	if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
<>	144:ef7eb2e8f9f7	551	{
<>	144:ef7eb2e8f9f7	552	/* Check for Parameters */
<>	144:ef7eb2e8f9f7	553	assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
<>	144:ef7eb2e8f9f7	554	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
<>	144:ef7eb2e8f9f7	555	assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
<>	144:ef7eb2e8f9f7	556
<>	144:ef7eb2e8f9f7	557	/* Configure the PLLI2S division factors */
<>	144:ef7eb2e8f9f7	558	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */
<>	144:ef7eb2e8f9f7	559	/* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
<>	144:ef7eb2e8f9f7	560	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
<>	144:ef7eb2e8f9f7	561	}
<>	144:ef7eb2e8f9f7	562
<>	144:ef7eb2e8f9f7	563	/* Enable the PLLI2S */
<>	144:ef7eb2e8f9f7	564	__HAL_RCC_PLLI2S_ENABLE();
<>	144:ef7eb2e8f9f7	565
<>	144:ef7eb2e8f9f7	566	/* Get Start Tick*/
<>	144:ef7eb2e8f9f7	567	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	568
<>	144:ef7eb2e8f9f7	569	/* Wait till PLLI2S is ready */
<>	144:ef7eb2e8f9f7	570	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
<>	144:ef7eb2e8f9f7	571	{
<>	144:ef7eb2e8f9f7	572	if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
<>	144:ef7eb2e8f9f7	573	{
<>	144:ef7eb2e8f9f7	574	/* return in case of Timeout detected */
<>	144:ef7eb2e8f9f7	575	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	576	}
<>	144:ef7eb2e8f9f7	577	}
<>	144:ef7eb2e8f9f7	578	}
<>	144:ef7eb2e8f9f7	579
<>	144:ef7eb2e8f9f7	580	/-------------------------------------- PLLSAI Configuration ---------------------------------/
<>	144:ef7eb2e8f9f7	581	/* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */
<>	144:ef7eb2e8f9f7	582	if(pllsaiused == 1)
<>	144:ef7eb2e8f9f7	583	{
<>	144:ef7eb2e8f9f7	584	/* Disable PLLSAI Clock */
<>	144:ef7eb2e8f9f7	585	__HAL_RCC_PLLSAI_DISABLE();
<>	144:ef7eb2e8f9f7	586
<>	144:ef7eb2e8f9f7	587	/* Get Start Tick*/
<>	144:ef7eb2e8f9f7	588	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	589
<>	144:ef7eb2e8f9f7	590	/* Wait till PLLSAI is disabled */
<>	144:ef7eb2e8f9f7	591	while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
<>	144:ef7eb2e8f9f7	592	{
<>	144:ef7eb2e8f9f7	593	if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
<>	144:ef7eb2e8f9f7	594	{
<>	144:ef7eb2e8f9f7	595	/* return in case of Timeout detected */
<>	144:ef7eb2e8f9f7	596	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	597	}
<>	144:ef7eb2e8f9f7	598	}
<>	144:ef7eb2e8f9f7	599
<>	144:ef7eb2e8f9f7	600	/* Check the PLLSAI division factors */
<>	144:ef7eb2e8f9f7	601	assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
<>	144:ef7eb2e8f9f7	602
<>	144:ef7eb2e8f9f7	603	/----------------- In Case of PLLSAI is selected as source clock for SAI -------------------/
<>	144:ef7eb2e8f9f7	604	if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) \|\|\
<>	144:ef7eb2e8f9f7	605	((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
<>	144:ef7eb2e8f9f7	606	{
<>	144:ef7eb2e8f9f7	607	/* check for PLLSAIQ Parameter */
<>	144:ef7eb2e8f9f7	608	assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
<>	144:ef7eb2e8f9f7	609	/* check for PLLSAI/DIVQ Parameter */
<>	144:ef7eb2e8f9f7	610	assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
<>	144:ef7eb2e8f9f7	611
<>	144:ef7eb2e8f9f7	612	/* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
<>	144:ef7eb2e8f9f7	613	tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP));
<>	144:ef7eb2e8f9f7	614	tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
<>	144:ef7eb2e8f9f7	615	/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
<>	144:ef7eb2e8f9f7	616	/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
<>	144:ef7eb2e8f9f7	617	/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
<>	144:ef7eb2e8f9f7	618	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
<>	144:ef7eb2e8f9f7	619
<>	144:ef7eb2e8f9f7	620	/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
<>	144:ef7eb2e8f9f7	621	__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
<>	144:ef7eb2e8f9f7	622	}
<>	144:ef7eb2e8f9f7	623
<>	144:ef7eb2e8f9f7	624	/----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------/
<>	144:ef7eb2e8f9f7	625	/* In Case of PLLI2S is selected as source clock for CK48 */
<>	144:ef7eb2e8f9f7	626	if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP))
<>	144:ef7eb2e8f9f7	627	{
<>	144:ef7eb2e8f9f7	628	/* check for Parameters */
<>	144:ef7eb2e8f9f7	629	assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
<>	144:ef7eb2e8f9f7	630	/* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */
<>	144:ef7eb2e8f9f7	631	tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
<>	144:ef7eb2e8f9f7	632	tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
<>	144:ef7eb2e8f9f7	633
<>	144:ef7eb2e8f9f7	634	/* Configure the PLLSAI division factors */
<>	144:ef7eb2e8f9f7	635	/* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */
<>	144:ef7eb2e8f9f7	636	/* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
<>	144:ef7eb2e8f9f7	637	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1);
<>	144:ef7eb2e8f9f7	638	}
<>	144:ef7eb2e8f9f7	639
<>	144:ef7eb2e8f9f7	640	#if defined(STM32F746xx) \|\| defined(STM32F756xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	641	/---------------------------- LTDC configuration -------------------------------/
<>	144:ef7eb2e8f9f7	642	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
<>	144:ef7eb2e8f9f7	643	{
<>	144:ef7eb2e8f9f7	644	assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
<>	144:ef7eb2e8f9f7	645	assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
<>	144:ef7eb2e8f9f7	646
<>	144:ef7eb2e8f9f7	647	/* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */
<>	144:ef7eb2e8f9f7	648	tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
<>	144:ef7eb2e8f9f7	649	tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP));
<>	144:ef7eb2e8f9f7	650
<>	144:ef7eb2e8f9f7	651	/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
<>	144:ef7eb2e8f9f7	652	/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
<>	144:ef7eb2e8f9f7	653	/* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
<>	144:ef7eb2e8f9f7	654	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR);
<>	144:ef7eb2e8f9f7	655
<>	144:ef7eb2e8f9f7	656	/* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
<>	144:ef7eb2e8f9f7	657	__HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
<>	144:ef7eb2e8f9f7	658	}
<>	144:ef7eb2e8f9f7	659	#endif /* STM32F746xx \|\| STM32F756xx \|\| STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	660
<>	144:ef7eb2e8f9f7	661	/* Enable PLLSAI Clock */
<>	144:ef7eb2e8f9f7	662	__HAL_RCC_PLLSAI_ENABLE();
<>	144:ef7eb2e8f9f7	663
<>	144:ef7eb2e8f9f7	664	/* Get Start Tick*/
<>	144:ef7eb2e8f9f7	665	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	666
<>	144:ef7eb2e8f9f7	667	/* Wait till PLLSAI is ready */
<>	144:ef7eb2e8f9f7	668	while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
<>	144:ef7eb2e8f9f7	669	{
<>	144:ef7eb2e8f9f7	670	if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
<>	144:ef7eb2e8f9f7	671	{
<>	144:ef7eb2e8f9f7	672	/* return in case of Timeout detected */
<>	144:ef7eb2e8f9f7	673	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	674	}
<>	144:ef7eb2e8f9f7	675	}
<>	144:ef7eb2e8f9f7	676	}
<>	144:ef7eb2e8f9f7	677	return HAL_OK;
<>	144:ef7eb2e8f9f7	678	}
<>	144:ef7eb2e8f9f7	679
<>	144:ef7eb2e8f9f7	680	/**
<>	144:ef7eb2e8f9f7	681	* @brief Get the RCC_PeriphCLKInitTypeDef according to the internal
<>	144:ef7eb2e8f9f7	682	* RCC configuration registers.
<>	144:ef7eb2e8f9f7	683	* @param PeriphClkInit: pointer to the configured RCC_PeriphCLKInitTypeDef structure
<>	144:ef7eb2e8f9f7	684	* @retval None
<>	144:ef7eb2e8f9f7	685	*/
<>	144:ef7eb2e8f9f7	686	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
<>	144:ef7eb2e8f9f7	687	{
<>	144:ef7eb2e8f9f7	688	uint32_t tempreg = 0;
<>	144:ef7eb2e8f9f7	689
<>	144:ef7eb2e8f9f7	690	/* Set all possible values for the extended clock type parameter------------*/
<>	144:ef7eb2e8f9f7	691	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	692	PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S \| RCC_PERIPHCLK_LPTIM1 \|\
<>	144:ef7eb2e8f9f7	693	RCC_PERIPHCLK_SAI1 \| RCC_PERIPHCLK_SAI2 \|\
<>	144:ef7eb2e8f9f7	694	RCC_PERIPHCLK_TIM \| RCC_PERIPHCLK_RTC \|\
<>	144:ef7eb2e8f9f7	695	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_I2C4 \|\
<>	144:ef7eb2e8f9f7	696	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \|\
<>	144:ef7eb2e8f9f7	697	RCC_PERIPHCLK_I2C3 \| RCC_PERIPHCLK_USART1 \|\
<>	144:ef7eb2e8f9f7	698	RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \|\
<>	144:ef7eb2e8f9f7	699	RCC_PERIPHCLK_UART4 \| RCC_PERIPHCLK_UART5 \|\
<>	144:ef7eb2e8f9f7	700	RCC_PERIPHCLK_USART6 \| RCC_PERIPHCLK_UART7 \|\
<>	144:ef7eb2e8f9f7	701	RCC_PERIPHCLK_UART8 \| RCC_PERIPHCLK_SDMMC1 \|\
<>	144:ef7eb2e8f9f7	702	RCC_PERIPHCLK_CLK48 \| RCC_PERIPHCLK_SDMMC2 \|\
<>	144:ef7eb2e8f9f7	703	RCC_PERIPHCLK_DFSDM1 \| RCC_PERIPHCLK_DFSDM1_AUDIO;
<>	144:ef7eb2e8f9f7	704	#else
<>	144:ef7eb2e8f9f7	705	PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S \| RCC_PERIPHCLK_LPTIM1 \|\
<>	144:ef7eb2e8f9f7	706	RCC_PERIPHCLK_SAI1 \| RCC_PERIPHCLK_SAI2 \|\
<>	144:ef7eb2e8f9f7	707	RCC_PERIPHCLK_TIM \| RCC_PERIPHCLK_RTC \|\
<>	144:ef7eb2e8f9f7	708	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_I2C4 \|\
<>	144:ef7eb2e8f9f7	709	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \|\
<>	144:ef7eb2e8f9f7	710	RCC_PERIPHCLK_I2C3 \| RCC_PERIPHCLK_USART1 \|\
<>	144:ef7eb2e8f9f7	711	RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \|\
<>	144:ef7eb2e8f9f7	712	RCC_PERIPHCLK_UART4 \| RCC_PERIPHCLK_UART5 \|\
<>	144:ef7eb2e8f9f7	713	RCC_PERIPHCLK_USART6 \| RCC_PERIPHCLK_UART7 \|\
<>	144:ef7eb2e8f9f7	714	RCC_PERIPHCLK_UART8 \| RCC_PERIPHCLK_SDMMC1 \|\
<>	144:ef7eb2e8f9f7	715	RCC_PERIPHCLK_CLK48;
<>	144:ef7eb2e8f9f7	716	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	717
<>	144:ef7eb2e8f9f7	718	/* Get the PLLI2S Clock configuration -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	719	PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
<>	144:ef7eb2e8f9f7	720	PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP));
<>	144:ef7eb2e8f9f7	721	PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
<>	144:ef7eb2e8f9f7	722	PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
<>	144:ef7eb2e8f9f7	723
<>	144:ef7eb2e8f9f7	724	/* Get the PLLSAI Clock configuration -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	725	PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));
<>	144:ef7eb2e8f9f7	726	PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP));
<>	144:ef7eb2e8f9f7	727	PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
<>	144:ef7eb2e8f9f7	728	PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
<>	144:ef7eb2e8f9f7	729
<>	144:ef7eb2e8f9f7	730	/* Get the PLLSAI/PLLI2S division factors -------------------------------------------*/
<>	144:ef7eb2e8f9f7	731	PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR1_PLLI2SDIVQ));
<>	144:ef7eb2e8f9f7	732	PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR1_PLLSAIDIVQ));
<>	144:ef7eb2e8f9f7	733	PeriphClkInit->PLLSAIDivR = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVR) >> POSITION_VAL(RCC_DCKCFGR1_PLLSAIDIVR));
<>	144:ef7eb2e8f9f7	734
<>	144:ef7eb2e8f9f7	735	/* Get the SAI1 clock configuration ----------------------------------------------*/
<>	144:ef7eb2e8f9f7	736	PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
<>	144:ef7eb2e8f9f7	737
<>	144:ef7eb2e8f9f7	738	/* Get the SAI2 clock configuration ----------------------------------------------*/
<>	144:ef7eb2e8f9f7	739	PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
<>	144:ef7eb2e8f9f7	740
<>	144:ef7eb2e8f9f7	741	/* Get the I2S clock configuration ------------------------------------------*/
<>	144:ef7eb2e8f9f7	742	PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2SCLKSOURCE();
<>	144:ef7eb2e8f9f7	743
<>	144:ef7eb2e8f9f7	744	/* Get the I2C1 clock configuration ------------------------------------------*/
<>	144:ef7eb2e8f9f7	745	PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
<>	144:ef7eb2e8f9f7	746
<>	144:ef7eb2e8f9f7	747	/* Get the I2C2 clock configuration ------------------------------------------*/
<>	144:ef7eb2e8f9f7	748	PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();
<>	144:ef7eb2e8f9f7	749
<>	144:ef7eb2e8f9f7	750	/* Get the I2C3 clock configuration ------------------------------------------*/
<>	144:ef7eb2e8f9f7	751	PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();
<>	144:ef7eb2e8f9f7	752
<>	144:ef7eb2e8f9f7	753	/* Get the I2C4 clock configuration ------------------------------------------*/
<>	144:ef7eb2e8f9f7	754	PeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE();
<>	144:ef7eb2e8f9f7	755
<>	144:ef7eb2e8f9f7	756	/* Get the USART1 clock configuration ------------------------------------------*/
<>	144:ef7eb2e8f9f7	757	PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
<>	144:ef7eb2e8f9f7	758
<>	144:ef7eb2e8f9f7	759	/* Get the USART2 clock configuration ------------------------------------------*/
<>	144:ef7eb2e8f9f7	760	PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
<>	144:ef7eb2e8f9f7	761
<>	144:ef7eb2e8f9f7	762	/* Get the USART3 clock configuration ------------------------------------------*/
<>	144:ef7eb2e8f9f7	763	PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
<>	144:ef7eb2e8f9f7	764
<>	144:ef7eb2e8f9f7	765	/* Get the UART4 clock configuration ------------------------------------------*/
<>	144:ef7eb2e8f9f7	766	PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();
<>	144:ef7eb2e8f9f7	767
<>	144:ef7eb2e8f9f7	768	/* Get the UART5 clock configuration ------------------------------------------*/
<>	144:ef7eb2e8f9f7	769	PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();
<>	144:ef7eb2e8f9f7	770
<>	144:ef7eb2e8f9f7	771	/* Get the USART6 clock configuration ------------------------------------------*/
<>	144:ef7eb2e8f9f7	772	PeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE();
<>	144:ef7eb2e8f9f7	773
<>	144:ef7eb2e8f9f7	774	/* Get the UART7 clock configuration ------------------------------------------*/
<>	144:ef7eb2e8f9f7	775	PeriphClkInit->Uart7ClockSelection = __HAL_RCC_GET_UART7_SOURCE();
<>	144:ef7eb2e8f9f7	776
<>	144:ef7eb2e8f9f7	777	/* Get the UART8 clock configuration ------------------------------------------*/
<>	144:ef7eb2e8f9f7	778	PeriphClkInit->Uart8ClockSelection = __HAL_RCC_GET_UART8_SOURCE();
<>	144:ef7eb2e8f9f7	779
<>	144:ef7eb2e8f9f7	780	/* Get the LPTIM1 clock configuration ------------------------------------------*/
<>	144:ef7eb2e8f9f7	781	PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
<>	144:ef7eb2e8f9f7	782
<>	144:ef7eb2e8f9f7	783	/* Get the CEC clock configuration -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	784	PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
<>	144:ef7eb2e8f9f7	785
<>	144:ef7eb2e8f9f7	786	/* Get the CK48 clock configuration -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	787	PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
<>	144:ef7eb2e8f9f7	788
<>	144:ef7eb2e8f9f7	789	/* Get the SDMMC1 clock configuration -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	790	PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE();
<>	144:ef7eb2e8f9f7	791
<>	144:ef7eb2e8f9f7	792	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	793	/* Get the SDMMC2 clock configuration -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	794	PeriphClkInit->Sdmmc2ClockSelection = __HAL_RCC_GET_SDMMC2_SOURCE();
<>	144:ef7eb2e8f9f7	795
<>	144:ef7eb2e8f9f7	796	/* Get the DFSDM clock configuration -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	797	PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE();
<>	144:ef7eb2e8f9f7	798
<>	144:ef7eb2e8f9f7	799	/* Get the DFSDM AUDIO clock configuration -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	800	PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE();
<>	144:ef7eb2e8f9f7	801	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	802
<>	144:ef7eb2e8f9f7	803	/* Get the RTC Clock configuration -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	804	tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
<>	144:ef7eb2e8f9f7	805	PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) \| (RCC->BDCR & RCC_BDCR_RTCSEL));
<>	144:ef7eb2e8f9f7	806
<>	144:ef7eb2e8f9f7	807	/* Get the TIM Prescaler configuration --------------------------------------------*/
<>	144:ef7eb2e8f9f7	808	if ((RCC->DCKCFGR1 & RCC_DCKCFGR1_TIMPRE) == RESET)
<>	144:ef7eb2e8f9f7	809	{
<>	144:ef7eb2e8f9f7	810	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
<>	144:ef7eb2e8f9f7	811	}
<>	144:ef7eb2e8f9f7	812	else
<>	144:ef7eb2e8f9f7	813	{
<>	144:ef7eb2e8f9f7	814	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
<>	144:ef7eb2e8f9f7	815	}
<>	144:ef7eb2e8f9f7	816	}
<>	144:ef7eb2e8f9f7	817
<>	144:ef7eb2e8f9f7	818	/**
<>	144:ef7eb2e8f9f7	819	* @brief Return the peripheral clock frequency for a given peripheral(SAI..)
<>	144:ef7eb2e8f9f7	820	* @note Return 0 if peripheral clock identifier not managed by this API
<>	144:ef7eb2e8f9f7	821	* @param PeriphClk: Peripheral clock identifier
<>	144:ef7eb2e8f9f7	822	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	823	* @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock
<>	144:ef7eb2e8f9f7	824	* @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock
<>	144:ef7eb2e8f9f7	825	* @retval Frequency in KHz
<>	144:ef7eb2e8f9f7	826	*/
<>	144:ef7eb2e8f9f7	827	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
<>	144:ef7eb2e8f9f7	828	{
<>	144:ef7eb2e8f9f7	829	uint32_t tmpreg = 0;
<>	144:ef7eb2e8f9f7	830	/* This variable is used to store the SAI clock frequency (value in Hz) */
<>	144:ef7eb2e8f9f7	831	uint32_t frequency = 0;
<>	144:ef7eb2e8f9f7	832	/* This variable is used to store the VCO Input (value in Hz) */
<>	144:ef7eb2e8f9f7	833	uint32_t vcoinput = 0;
<>	144:ef7eb2e8f9f7	834	/* This variable is used to store the SAI clock source */
<>	144:ef7eb2e8f9f7	835	uint32_t saiclocksource = 0;
<>	144:ef7eb2e8f9f7	836
<>	144:ef7eb2e8f9f7	837	if (PeriphClk == RCC_PERIPHCLK_SAI1)
<>	144:ef7eb2e8f9f7	838	{
<>	144:ef7eb2e8f9f7	839	saiclocksource = RCC->DCKCFGR1;
<>	144:ef7eb2e8f9f7	840	saiclocksource &= RCC_DCKCFGR1_SAI1SEL;
<>	144:ef7eb2e8f9f7	841	switch (saiclocksource)
<>	144:ef7eb2e8f9f7	842	{
<>	144:ef7eb2e8f9f7	843	case 0: /* PLLSAI is the clock source for SAI1 */
<>	144:ef7eb2e8f9f7	844	{
<>	144:ef7eb2e8f9f7	845	/* Configure the PLLSAI division factor */
<>	144:ef7eb2e8f9f7	846	/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
<>	144:ef7eb2e8f9f7	847	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
<>	144:ef7eb2e8f9f7	848	{
<>	144:ef7eb2e8f9f7	849	/* In Case the PLL Source is HSI (Internal Clock) */
<>	144:ef7eb2e8f9f7	850	vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
<>	144:ef7eb2e8f9f7	851	}
<>	144:ef7eb2e8f9f7	852	else
<>	144:ef7eb2e8f9f7	853	{
<>	144:ef7eb2e8f9f7	854	/* In Case the PLL Source is HSE (External Clock) */
<>	144:ef7eb2e8f9f7	855	vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
<>	144:ef7eb2e8f9f7	856	}
<>	144:ef7eb2e8f9f7	857	/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
<>	144:ef7eb2e8f9f7	858	/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
<>	144:ef7eb2e8f9f7	859	tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24;
<>	144:ef7eb2e8f9f7	860	frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg);
<>	144:ef7eb2e8f9f7	861
<>	144:ef7eb2e8f9f7	862	/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
<>	144:ef7eb2e8f9f7	863	tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1);
<>	144:ef7eb2e8f9f7	864	frequency = frequency/(tmpreg);
<>	144:ef7eb2e8f9f7	865	break;
<>	144:ef7eb2e8f9f7	866	}
<>	144:ef7eb2e8f9f7	867	case RCC_DCKCFGR1_SAI1SEL_0: /* PLLI2S is the clock source for SAI1 */
<>	144:ef7eb2e8f9f7	868	{
<>	144:ef7eb2e8f9f7	869	/* Configure the PLLI2S division factor */
<>	144:ef7eb2e8f9f7	870	/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
<>	144:ef7eb2e8f9f7	871	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
<>	144:ef7eb2e8f9f7	872	{
<>	144:ef7eb2e8f9f7	873	/* In Case the PLL Source is HSI (Internal Clock) */
<>	144:ef7eb2e8f9f7	874	vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
<>	144:ef7eb2e8f9f7	875	}
<>	144:ef7eb2e8f9f7	876	else
<>	144:ef7eb2e8f9f7	877	{
<>	144:ef7eb2e8f9f7	878	/* In Case the PLL Source is HSE (External Clock) */
<>	144:ef7eb2e8f9f7	879	vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
<>	144:ef7eb2e8f9f7	880	}
<>	144:ef7eb2e8f9f7	881
<>	144:ef7eb2e8f9f7	882	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
<>	144:ef7eb2e8f9f7	883	/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
<>	144:ef7eb2e8f9f7	884	tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24;
<>	144:ef7eb2e8f9f7	885	frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);
<>	144:ef7eb2e8f9f7	886
<>	144:ef7eb2e8f9f7	887	/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
<>	144:ef7eb2e8f9f7	888	tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1);
<>	144:ef7eb2e8f9f7	889	frequency = frequency/(tmpreg);
<>	144:ef7eb2e8f9f7	890	break;
<>	144:ef7eb2e8f9f7	891	}
<>	144:ef7eb2e8f9f7	892	case RCC_DCKCFGR1_SAI1SEL_1: /* External clock is the clock source for SAI1 */
<>	144:ef7eb2e8f9f7	893	{
<>	144:ef7eb2e8f9f7	894	frequency = EXTERNAL_CLOCK_VALUE;
<>	144:ef7eb2e8f9f7	895	break;
<>	144:ef7eb2e8f9f7	896	}
<>	144:ef7eb2e8f9f7	897	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	898	case RCC_DCKCFGR1_SAI1SEL: /* HSI or HSE is the clock source for SAI*/
<>	144:ef7eb2e8f9f7	899	{
<>	144:ef7eb2e8f9f7	900	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
<>	144:ef7eb2e8f9f7	901	{
<>	144:ef7eb2e8f9f7	902	/* In Case the main PLL Source is HSI */
<>	144:ef7eb2e8f9f7	903	frequency = HSI_VALUE;
<>	144:ef7eb2e8f9f7	904	}
<>	144:ef7eb2e8f9f7	905	else
<>	144:ef7eb2e8f9f7	906	{
<>	144:ef7eb2e8f9f7	907	/* In Case the main PLL Source is HSE */
<>	144:ef7eb2e8f9f7	908	frequency = HSE_VALUE;
<>	144:ef7eb2e8f9f7	909	}
<>	144:ef7eb2e8f9f7	910	break;
<>	144:ef7eb2e8f9f7	911	}
<>	144:ef7eb2e8f9f7	912	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	913	default :
<>	144:ef7eb2e8f9f7	914	{
<>	144:ef7eb2e8f9f7	915	break;
<>	144:ef7eb2e8f9f7	916	}
<>	144:ef7eb2e8f9f7	917	}
<>	144:ef7eb2e8f9f7	918	}
<>	144:ef7eb2e8f9f7	919
<>	144:ef7eb2e8f9f7	920	if (PeriphClk == RCC_PERIPHCLK_SAI2)
<>	144:ef7eb2e8f9f7	921	{
<>	144:ef7eb2e8f9f7	922	saiclocksource = RCC->DCKCFGR1;
<>	144:ef7eb2e8f9f7	923	saiclocksource &= RCC_DCKCFGR1_SAI2SEL;
<>	144:ef7eb2e8f9f7	924	switch (saiclocksource)
<>	144:ef7eb2e8f9f7	925	{
<>	144:ef7eb2e8f9f7	926	case 0: /* PLLSAI is the clock source for SAI*/
<>	144:ef7eb2e8f9f7	927	{
<>	144:ef7eb2e8f9f7	928	/* Configure the PLLSAI division factor */
<>	144:ef7eb2e8f9f7	929	/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
<>	144:ef7eb2e8f9f7	930	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
<>	144:ef7eb2e8f9f7	931	{
<>	144:ef7eb2e8f9f7	932	/* In Case the PLL Source is HSI (Internal Clock) */
<>	144:ef7eb2e8f9f7	933	vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
<>	144:ef7eb2e8f9f7	934	}
<>	144:ef7eb2e8f9f7	935	else
<>	144:ef7eb2e8f9f7	936	{
<>	144:ef7eb2e8f9f7	937	/* In Case the PLL Source is HSE (External Clock) */
<>	144:ef7eb2e8f9f7	938	vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
<>	144:ef7eb2e8f9f7	939	}
<>	144:ef7eb2e8f9f7	940	/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
<>	144:ef7eb2e8f9f7	941	/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
<>	144:ef7eb2e8f9f7	942	tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24;
<>	144:ef7eb2e8f9f7	943	frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg);
<>	144:ef7eb2e8f9f7	944
<>	144:ef7eb2e8f9f7	945	/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
<>	144:ef7eb2e8f9f7	946	tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1);
<>	144:ef7eb2e8f9f7	947	frequency = frequency/(tmpreg);
<>	144:ef7eb2e8f9f7	948	break;
<>	144:ef7eb2e8f9f7	949	}
<>	144:ef7eb2e8f9f7	950	case RCC_DCKCFGR1_SAI2SEL_0: /* PLLI2S is the clock source for SAI2 */
<>	144:ef7eb2e8f9f7	951	{
<>	144:ef7eb2e8f9f7	952	/* Configure the PLLI2S division factor */
<>	144:ef7eb2e8f9f7	953	/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
<>	144:ef7eb2e8f9f7	954	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
<>	144:ef7eb2e8f9f7	955	{
<>	144:ef7eb2e8f9f7	956	/* In Case the PLL Source is HSI (Internal Clock) */
<>	144:ef7eb2e8f9f7	957	vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
<>	144:ef7eb2e8f9f7	958	}
<>	144:ef7eb2e8f9f7	959	else
<>	144:ef7eb2e8f9f7	960	{
<>	144:ef7eb2e8f9f7	961	/* In Case the PLL Source is HSE (External Clock) */
<>	144:ef7eb2e8f9f7	962	vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
<>	144:ef7eb2e8f9f7	963	}
<>	144:ef7eb2e8f9f7	964
<>	144:ef7eb2e8f9f7	965	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
<>	144:ef7eb2e8f9f7	966	/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
<>	144:ef7eb2e8f9f7	967	tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24;
<>	144:ef7eb2e8f9f7	968	frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);
<>	144:ef7eb2e8f9f7	969
<>	144:ef7eb2e8f9f7	970	/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
<>	144:ef7eb2e8f9f7	971	tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1);
<>	144:ef7eb2e8f9f7	972	frequency = frequency/(tmpreg);
<>	144:ef7eb2e8f9f7	973	break;
<>	144:ef7eb2e8f9f7	974	}
<>	144:ef7eb2e8f9f7	975	case RCC_DCKCFGR1_SAI2SEL_1: /* External clock is the clock source for SAI2 */
<>	144:ef7eb2e8f9f7	976	{
<>	144:ef7eb2e8f9f7	977	frequency = EXTERNAL_CLOCK_VALUE;
<>	144:ef7eb2e8f9f7	978	break;
<>	144:ef7eb2e8f9f7	979	}
<>	144:ef7eb2e8f9f7	980	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	981	case RCC_DCKCFGR1_SAI2SEL: /* HSI or HSE is the clock source for SAI2 */
<>	144:ef7eb2e8f9f7	982	{
<>	144:ef7eb2e8f9f7	983	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
<>	144:ef7eb2e8f9f7	984	{
<>	144:ef7eb2e8f9f7	985	/* In Case the main PLL Source is HSI */
<>	144:ef7eb2e8f9f7	986	frequency = HSI_VALUE;
<>	144:ef7eb2e8f9f7	987	}
<>	144:ef7eb2e8f9f7	988	else
<>	144:ef7eb2e8f9f7	989	{
<>	144:ef7eb2e8f9f7	990	/* In Case the main PLL Source is HSE */
<>	144:ef7eb2e8f9f7	991	frequency = HSE_VALUE;
<>	144:ef7eb2e8f9f7	992	}
<>	144:ef7eb2e8f9f7	993	break;
<>	144:ef7eb2e8f9f7	994	}
<>	144:ef7eb2e8f9f7	995	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	996	default :
<>	144:ef7eb2e8f9f7	997	{
<>	144:ef7eb2e8f9f7	998	break;
<>	144:ef7eb2e8f9f7	999	}
<>	144:ef7eb2e8f9f7	1000	}
<>	144:ef7eb2e8f9f7	1001	}
<>	144:ef7eb2e8f9f7	1002
<>	144:ef7eb2e8f9f7	1003	return frequency;
<>	144:ef7eb2e8f9f7	1004	}
<>	144:ef7eb2e8f9f7	1005
<>	144:ef7eb2e8f9f7	1006	#if defined (STM32F765xx) \|\| defined(STM32F767xx) \|\| defined(STM32F769xx) \|\| defined(STM32F777xx) \|\| defined(STM32F779xx)
<>	144:ef7eb2e8f9f7	1007	/**
<>	144:ef7eb2e8f9f7	1008	* @brief Initializes the RCC Oscillators according to the specified parameters in the
<>	144:ef7eb2e8f9f7	1009	* RCC_OscInitTypeDef.
<>	144:ef7eb2e8f9f7	1010	* @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
<>	144:ef7eb2e8f9f7	1011	* contains the configuration information for the RCC Oscillators.
<>	144:ef7eb2e8f9f7	1012	* @note The PLL is not disabled when used as system clock.
<>	144:ef7eb2e8f9f7	1013	* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
<>	144:ef7eb2e8f9f7	1014	* supported by this function. User should request a transition to LSE Off
<>	144:ef7eb2e8f9f7	1015	* first and then LSE On or LSE Bypass.
<>	144:ef7eb2e8f9f7	1016	* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
<>	144:ef7eb2e8f9f7	1017	* supported by this function. User should request a transition to HSE Off
<>	144:ef7eb2e8f9f7	1018	* first and then HSE On or HSE Bypass.
<>	144:ef7eb2e8f9f7	1019	* @retval HAL status
<>	144:ef7eb2e8f9f7	1020	*/
<>	144:ef7eb2e8f9f7	1021	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
<>	144:ef7eb2e8f9f7	1022	{
<>	144:ef7eb2e8f9f7	1023	uint32_t tickstart = 0;
<>	144:ef7eb2e8f9f7	1024
<>	144:ef7eb2e8f9f7	1025	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1026	assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
<>	144:ef7eb2e8f9f7	1027
<>	144:ef7eb2e8f9f7	1028	/------------------------------- HSE Configuration ------------------------/
<>	144:ef7eb2e8f9f7	1029	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
<>	144:ef7eb2e8f9f7	1030	{
<>	144:ef7eb2e8f9f7	1031	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1032	assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
<>	144:ef7eb2e8f9f7	1033	/* When the HSE is used as system clock or clock source for PLL, It can not be disabled */
<>	144:ef7eb2e8f9f7	1034	if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
<>	144:ef7eb2e8f9f7	1035	\|\| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
<>	144:ef7eb2e8f9f7	1036	{
<>	144:ef7eb2e8f9f7	1037	if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
<>	144:ef7eb2e8f9f7	1038	{
<>	144:ef7eb2e8f9f7	1039	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1040	}
<>	144:ef7eb2e8f9f7	1041	}
<>	144:ef7eb2e8f9f7	1042	else
<>	144:ef7eb2e8f9f7	1043	{
<>	144:ef7eb2e8f9f7	1044	/* Set the new HSE configuration ---------------------------------------*/
<>	144:ef7eb2e8f9f7	1045	__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
<>	144:ef7eb2e8f9f7	1046
<>	144:ef7eb2e8f9f7	1047	/* Check the HSE State */
<>	144:ef7eb2e8f9f7	1048	if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
<>	144:ef7eb2e8f9f7	1049	{
<>	144:ef7eb2e8f9f7	1050	/* Get Start Tick*/
<>	144:ef7eb2e8f9f7	1051	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	1052
<>	144:ef7eb2e8f9f7	1053	/* Wait till HSE is ready */
<>	144:ef7eb2e8f9f7	1054	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
<>	144:ef7eb2e8f9f7	1055	{
<>	144:ef7eb2e8f9f7	1056	if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
<>	144:ef7eb2e8f9f7	1057	{
<>	144:ef7eb2e8f9f7	1058	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1059	}
<>	144:ef7eb2e8f9f7	1060	}
<>	144:ef7eb2e8f9f7	1061	}
<>	144:ef7eb2e8f9f7	1062	else
<>	144:ef7eb2e8f9f7	1063	{
<>	144:ef7eb2e8f9f7	1064	/* Get Start Tick*/
<>	144:ef7eb2e8f9f7	1065	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	1066
<>	144:ef7eb2e8f9f7	1067	/* Wait till HSE is bypassed or disabled */
<>	144:ef7eb2e8f9f7	1068	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
<>	144:ef7eb2e8f9f7	1069	{
<>	144:ef7eb2e8f9f7	1070	if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
<>	144:ef7eb2e8f9f7	1071	{
<>	144:ef7eb2e8f9f7	1072	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1073	}
<>	144:ef7eb2e8f9f7	1074	}
<>	144:ef7eb2e8f9f7	1075	}
<>	144:ef7eb2e8f9f7	1076	}
<>	144:ef7eb2e8f9f7	1077	}
<>	144:ef7eb2e8f9f7	1078	/----------------------------- HSI Configuration --------------------------/
<>	144:ef7eb2e8f9f7	1079	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
<>	144:ef7eb2e8f9f7	1080	{
<>	144:ef7eb2e8f9f7	1081	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1082	assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
<>	144:ef7eb2e8f9f7	1083	assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
<>	144:ef7eb2e8f9f7	1084
<>	144:ef7eb2e8f9f7	1085	/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
<>	144:ef7eb2e8f9f7	1086	if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
<>	144:ef7eb2e8f9f7	1087	\|\| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
<>	144:ef7eb2e8f9f7	1088	{
<>	144:ef7eb2e8f9f7	1089	/* When HSI is used as system clock it will not disabled */
<>	144:ef7eb2e8f9f7	1090	if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
<>	144:ef7eb2e8f9f7	1091	{
<>	144:ef7eb2e8f9f7	1092	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1093	}
<>	144:ef7eb2e8f9f7	1094	/* Otherwise, just the calibration is allowed */
<>	144:ef7eb2e8f9f7	1095	else
<>	144:ef7eb2e8f9f7	1096	{
<>	144:ef7eb2e8f9f7	1097	/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
<>	144:ef7eb2e8f9f7	1098	__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
<>	144:ef7eb2e8f9f7	1099	}
<>	144:ef7eb2e8f9f7	1100	}
<>	144:ef7eb2e8f9f7	1101	else
<>	144:ef7eb2e8f9f7	1102	{
<>	144:ef7eb2e8f9f7	1103	/* Check the HSI State */
<>	144:ef7eb2e8f9f7	1104	if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
<>	144:ef7eb2e8f9f7	1105	{
<>	144:ef7eb2e8f9f7	1106	/* Enable the Internal High Speed oscillator (HSI). */
<>	144:ef7eb2e8f9f7	1107	__HAL_RCC_HSI_ENABLE();
<>	144:ef7eb2e8f9f7	1108
<>	144:ef7eb2e8f9f7	1109	/* Get Start Tick*/
<>	144:ef7eb2e8f9f7	1110	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	1111
<>	144:ef7eb2e8f9f7	1112	/* Wait till HSI is ready */
<>	144:ef7eb2e8f9f7	1113	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
<>	144:ef7eb2e8f9f7	1114	{
<>	144:ef7eb2e8f9f7	1115	if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
<>	144:ef7eb2e8f9f7	1116	{
<>	144:ef7eb2e8f9f7	1117	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1118	}
<>	144:ef7eb2e8f9f7	1119	}
<>	144:ef7eb2e8f9f7	1120
<>	144:ef7eb2e8f9f7	1121	/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
<>	144:ef7eb2e8f9f7	1122	__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
<>	144:ef7eb2e8f9f7	1123	}
<>	144:ef7eb2e8f9f7	1124	else
<>	144:ef7eb2e8f9f7	1125	{
<>	144:ef7eb2e8f9f7	1126	/* Disable the Internal High Speed oscillator (HSI). */
<>	144:ef7eb2e8f9f7	1127	__HAL_RCC_HSI_DISABLE();
<>	144:ef7eb2e8f9f7	1128
<>	144:ef7eb2e8f9f7	1129	/* Get Start Tick*/
<>	144:ef7eb2e8f9f7	1130	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	1131
<>	144:ef7eb2e8f9f7	1132	/* Wait till HSI is ready */
<>	144:ef7eb2e8f9f7	1133	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
<>	144:ef7eb2e8f9f7	1134	{
<>	144:ef7eb2e8f9f7	1135	if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
<>	144:ef7eb2e8f9f7	1136	{
<>	144:ef7eb2e8f9f7	1137	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1138	}
<>	144:ef7eb2e8f9f7	1139	}
<>	144:ef7eb2e8f9f7	1140	}
<>	144:ef7eb2e8f9f7	1141	}
<>	144:ef7eb2e8f9f7	1142	}
<>	144:ef7eb2e8f9f7	1143	/------------------------------ LSI Configuration -------------------------/
<>	144:ef7eb2e8f9f7	1144	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
<>	144:ef7eb2e8f9f7	1145	{
<>	144:ef7eb2e8f9f7	1146	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1147	assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
<>	144:ef7eb2e8f9f7	1148
<>	144:ef7eb2e8f9f7	1149	/* Check the LSI State */
<>	144:ef7eb2e8f9f7	1150	if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
<>	144:ef7eb2e8f9f7	1151	{
<>	144:ef7eb2e8f9f7	1152	/* Enable the Internal Low Speed oscillator (LSI). */
<>	144:ef7eb2e8f9f7	1153	__HAL_RCC_LSI_ENABLE();
<>	144:ef7eb2e8f9f7	1154
<>	144:ef7eb2e8f9f7	1155	/* Get Start Tick*/
<>	144:ef7eb2e8f9f7	1156	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	1157
<>	144:ef7eb2e8f9f7	1158	/* Wait till LSI is ready */
<>	144:ef7eb2e8f9f7	1159	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
<>	144:ef7eb2e8f9f7	1160	{
<>	144:ef7eb2e8f9f7	1161	if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
<>	144:ef7eb2e8f9f7	1162	{
<>	144:ef7eb2e8f9f7	1163	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1164	}
<>	144:ef7eb2e8f9f7	1165	}
<>	144:ef7eb2e8f9f7	1166	}
<>	144:ef7eb2e8f9f7	1167	else
<>	144:ef7eb2e8f9f7	1168	{
<>	144:ef7eb2e8f9f7	1169	/* Disable the Internal Low Speed oscillator (LSI). */
<>	144:ef7eb2e8f9f7	1170	__HAL_RCC_LSI_DISABLE();
<>	144:ef7eb2e8f9f7	1171
<>	144:ef7eb2e8f9f7	1172	/* Get Start Tick*/
<>	144:ef7eb2e8f9f7	1173	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	1174
<>	144:ef7eb2e8f9f7	1175	/* Wait till LSI is ready */
<>	144:ef7eb2e8f9f7	1176	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
<>	144:ef7eb2e8f9f7	1177	{
<>	144:ef7eb2e8f9f7	1178	if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
<>	144:ef7eb2e8f9f7	1179	{
<>	144:ef7eb2e8f9f7	1180	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1181	}
<>	144:ef7eb2e8f9f7	1182	}
<>	144:ef7eb2e8f9f7	1183	}
<>	144:ef7eb2e8f9f7	1184	}
<>	144:ef7eb2e8f9f7	1185	/------------------------------ LSE Configuration -------------------------/
<>	144:ef7eb2e8f9f7	1186	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
<>	144:ef7eb2e8f9f7	1187	{
<>	144:ef7eb2e8f9f7	1188	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1189	assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
<>	144:ef7eb2e8f9f7	1190
<>	144:ef7eb2e8f9f7	1191	/* Enable Power Clock*/
<>	144:ef7eb2e8f9f7	1192	__HAL_RCC_PWR_CLK_ENABLE();
<>	144:ef7eb2e8f9f7	1193
<>	144:ef7eb2e8f9f7	1194	/* Enable write access to Backup domain */
<>	144:ef7eb2e8f9f7	1195	PWR->CR1 \|= PWR_CR1_DBP;
<>	144:ef7eb2e8f9f7	1196
<>	144:ef7eb2e8f9f7	1197	/* Wait for Backup domain Write protection disable */
<>	144:ef7eb2e8f9f7	1198	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	1199
<>	144:ef7eb2e8f9f7	1200	while((PWR->CR1 & PWR_CR1_DBP) == RESET)
<>	144:ef7eb2e8f9f7	1201	{
<>	144:ef7eb2e8f9f7	1202	if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
<>	144:ef7eb2e8f9f7	1203	{
<>	144:ef7eb2e8f9f7	1204	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1205	}
<>	144:ef7eb2e8f9f7	1206	}
<>	144:ef7eb2e8f9f7	1207
<>	144:ef7eb2e8f9f7	1208	/* Set the new LSE configuration -----------------------------------------*/
<>	144:ef7eb2e8f9f7	1209	__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
<>	144:ef7eb2e8f9f7	1210	/* Check the LSE State */
<>	144:ef7eb2e8f9f7	1211	if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
<>	144:ef7eb2e8f9f7	1212	{
<>	144:ef7eb2e8f9f7	1213	/* Get Start Tick*/
<>	144:ef7eb2e8f9f7	1214	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	1215
<>	144:ef7eb2e8f9f7	1216	/* Wait till LSE is ready */
<>	144:ef7eb2e8f9f7	1217	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
<>	144:ef7eb2e8f9f7	1218	{
<>	144:ef7eb2e8f9f7	1219	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
<>	144:ef7eb2e8f9f7	1220	{
<>	144:ef7eb2e8f9f7	1221	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1222	}
<>	144:ef7eb2e8f9f7	1223	}
<>	144:ef7eb2e8f9f7	1224	}
<>	144:ef7eb2e8f9f7	1225	else
<>	144:ef7eb2e8f9f7	1226	{
<>	144:ef7eb2e8f9f7	1227	/* Get Start Tick*/
<>	144:ef7eb2e8f9f7	1228	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	1229
<>	144:ef7eb2e8f9f7	1230	/* Wait till LSE is ready */
<>	144:ef7eb2e8f9f7	1231	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
<>	144:ef7eb2e8f9f7	1232	{
<>	144:ef7eb2e8f9f7	1233	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
<>	144:ef7eb2e8f9f7	1234	{
<>	144:ef7eb2e8f9f7	1235	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1236	}
<>	144:ef7eb2e8f9f7	1237	}
<>	144:ef7eb2e8f9f7	1238	}
<>	144:ef7eb2e8f9f7	1239	}
<>	144:ef7eb2e8f9f7	1240	/-------------------------------- PLL Configuration -----------------------/
<>	144:ef7eb2e8f9f7	1241	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1242	assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
<>	144:ef7eb2e8f9f7	1243	if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
<>	144:ef7eb2e8f9f7	1244	{
<>	144:ef7eb2e8f9f7	1245	/* Check if the PLL is used as system clock or not */
<>	144:ef7eb2e8f9f7	1246	if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
<>	144:ef7eb2e8f9f7	1247	{
<>	144:ef7eb2e8f9f7	1248	if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
<>	144:ef7eb2e8f9f7	1249	{
<>	144:ef7eb2e8f9f7	1250	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1251	assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
<>	144:ef7eb2e8f9f7	1252	assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
<>	144:ef7eb2e8f9f7	1253	assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
<>	144:ef7eb2e8f9f7	1254	assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
<>	144:ef7eb2e8f9f7	1255	assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
<>	144:ef7eb2e8f9f7	1256	assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
<>	144:ef7eb2e8f9f7	1257
<>	144:ef7eb2e8f9f7	1258	/* Disable the main PLL. */
<>	144:ef7eb2e8f9f7	1259	__HAL_RCC_PLL_DISABLE();
<>	144:ef7eb2e8f9f7	1260
<>	144:ef7eb2e8f9f7	1261	/* Get Start Tick*/
<>	144:ef7eb2e8f9f7	1262	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	1263
<>	144:ef7eb2e8f9f7	1264	/* Wait till PLL is ready */
<>	144:ef7eb2e8f9f7	1265	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
<>	144:ef7eb2e8f9f7	1266	{
<>	144:ef7eb2e8f9f7	1267	if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
<>	144:ef7eb2e8f9f7	1268	{
<>	144:ef7eb2e8f9f7	1269	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1270	}
<>	144:ef7eb2e8f9f7	1271	}
<>	144:ef7eb2e8f9f7	1272
<>	144:ef7eb2e8f9f7	1273	/* Configure the main PLL clock source, multiplication and division factors. */
<>	144:ef7eb2e8f9f7	1274	__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
<>	144:ef7eb2e8f9f7	1275	RCC_OscInitStruct->PLL.PLLM,
<>	144:ef7eb2e8f9f7	1276	RCC_OscInitStruct->PLL.PLLN,
<>	144:ef7eb2e8f9f7	1277	RCC_OscInitStruct->PLL.PLLP,
<>	144:ef7eb2e8f9f7	1278	RCC_OscInitStruct->PLL.PLLQ,
<>	144:ef7eb2e8f9f7	1279	RCC_OscInitStruct->PLL.PLLR);
<>	144:ef7eb2e8f9f7	1280
<>	144:ef7eb2e8f9f7	1281	/* Enable the main PLL. */
<>	144:ef7eb2e8f9f7	1282	__HAL_RCC_PLL_ENABLE();
<>	144:ef7eb2e8f9f7	1283
<>	144:ef7eb2e8f9f7	1284	/* Get Start Tick*/
<>	144:ef7eb2e8f9f7	1285	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	1286
<>	144:ef7eb2e8f9f7	1287	/* Wait till PLL is ready */
<>	144:ef7eb2e8f9f7	1288	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
<>	144:ef7eb2e8f9f7	1289	{
<>	144:ef7eb2e8f9f7	1290	if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
<>	144:ef7eb2e8f9f7	1291	{
<>	144:ef7eb2e8f9f7	1292	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1293	}
<>	144:ef7eb2e8f9f7	1294	}
<>	144:ef7eb2e8f9f7	1295	}
<>	144:ef7eb2e8f9f7	1296	else
<>	144:ef7eb2e8f9f7	1297	{
<>	144:ef7eb2e8f9f7	1298	/* Disable the main PLL. */
<>	144:ef7eb2e8f9f7	1299	__HAL_RCC_PLL_DISABLE();
<>	144:ef7eb2e8f9f7	1300
<>	144:ef7eb2e8f9f7	1301	/* Get Start Tick*/
<>	144:ef7eb2e8f9f7	1302	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	1303
<>	144:ef7eb2e8f9f7	1304	/* Wait till PLL is ready */
<>	144:ef7eb2e8f9f7	1305	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
<>	144:ef7eb2e8f9f7	1306	{
<>	144:ef7eb2e8f9f7	1307	if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
<>	144:ef7eb2e8f9f7	1308	{
<>	144:ef7eb2e8f9f7	1309	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1310	}
<>	144:ef7eb2e8f9f7	1311	}
<>	144:ef7eb2e8f9f7	1312	}
<>	144:ef7eb2e8f9f7	1313	}
<>	144:ef7eb2e8f9f7	1314	else
<>	144:ef7eb2e8f9f7	1315	{
<>	144:ef7eb2e8f9f7	1316	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1317	}
<>	144:ef7eb2e8f9f7	1318	}
<>	144:ef7eb2e8f9f7	1319	return HAL_OK;
<>	144:ef7eb2e8f9f7	1320	}
<>	144:ef7eb2e8f9f7	1321	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	1322
<>	144:ef7eb2e8f9f7	1323	/**
<>	144:ef7eb2e8f9f7	1324	* @}
<>	144:ef7eb2e8f9f7	1325	*/
<>	144:ef7eb2e8f9f7	1326
<>	144:ef7eb2e8f9f7	1327	/**
<>	144:ef7eb2e8f9f7	1328	* @}
<>	144:ef7eb2e8f9f7	1329	*/
<>	144:ef7eb2e8f9f7	1330
<>	144:ef7eb2e8f9f7	1331	#endif /* HAL_RCC_MODULE_ENABLED */
<>	144:ef7eb2e8f9f7	1332	/**
<>	144:ef7eb2e8f9f7	1333	* @}
<>	144:ef7eb2e8f9f7	1334	*/
<>	144:ef7eb2e8f9f7	1335
<>	144:ef7eb2e8f9f7	1336	/**
<>	144:ef7eb2e8f9f7	1337	* @}
<>	144:ef7eb2e8f9f7	1338	*/
<>	144:ef7eb2e8f9f7	1339
<>	144:ef7eb2e8f9f7	1340	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

Repository toolbox

Export to desktop IDE

Repository details

Type:	Library
Created:	10 Sep 2016
Imports:	1
Forks:	0
Commits:	148
Dependents:	0
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc_ex.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Who changed what in which revision?

Repository toolbox

Repository details

Important Information for this Arm website

Access Warning