Johannes Stratmann
added prescaler for 16 bit pwm in LPC1347 target
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mbed official
targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc_ex.c@83:a036322b8637, 2016-03-07 (annotated)
- Committer:
- mbed_official
- Date:
- Mon Mar 07 10:00:14 2016 +0000
- Revision:
- 83:a036322b8637
- Parent:
- 0:9b334a45a8ff
- Child:
- 144:ef7eb2e8f9f7
Synchronized with git revision ee20d03969aa5c570152f88e8f3d8a4739eed40b
Full URL: https://github.com/mbedmicro/mbed/commit/ee20d03969aa5c570152f88e8f3d8a4739eed40b/
[STM32F7] Update STM32F7Cube_FW version
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| bogdanm | 0:9b334a45a8ff | 1 | /** |
| bogdanm | 0:9b334a45a8ff | 2 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 3 | * @file stm32f7xx_hal_rcc_ex.c |
| bogdanm | 0:9b334a45a8ff | 4 | * @author MCD Application Team |
| mbed_official | 83:a036322b8637 | 5 | * @version V1.0.4 |
| mbed_official | 83:a036322b8637 | 6 | * @date 09-December-2015 |
| bogdanm | 0:9b334a45a8ff | 7 | * @brief Extension RCC HAL module driver. |
| bogdanm | 0:9b334a45a8ff | 8 | * This file provides firmware functions to manage the following |
| bogdanm | 0:9b334a45a8ff | 9 | * functionalities RCC extension peripheral: |
| bogdanm | 0:9b334a45a8ff | 10 | * + Extended Peripheral Control functions |
| bogdanm | 0:9b334a45a8ff | 11 | * |
| bogdanm | 0:9b334a45a8ff | 12 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 13 | * @attention |
| bogdanm | 0:9b334a45a8ff | 14 | * |
| bogdanm | 0:9b334a45a8ff | 15 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
| bogdanm | 0:9b334a45a8ff | 16 | * |
| bogdanm | 0:9b334a45a8ff | 17 | * Redistribution and use in source and binary forms, with or without modification, |
| bogdanm | 0:9b334a45a8ff | 18 | * are permitted provided that the following conditions are met: |
| bogdanm | 0:9b334a45a8ff | 19 | * 1. Redistributions of source code must retain the above copyright notice, |
| bogdanm | 0:9b334a45a8ff | 20 | * this list of conditions and the following disclaimer. |
| bogdanm | 0:9b334a45a8ff | 21 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| bogdanm | 0:9b334a45a8ff | 22 | * this list of conditions and the following disclaimer in the documentation |
| bogdanm | 0:9b334a45a8ff | 23 | * and/or other materials provided with the distribution. |
| bogdanm | 0:9b334a45a8ff | 24 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| bogdanm | 0:9b334a45a8ff | 25 | * may be used to endorse or promote products derived from this software |
| bogdanm | 0:9b334a45a8ff | 26 | * without specific prior written permission. |
| bogdanm | 0:9b334a45a8ff | 27 | * |
| bogdanm | 0:9b334a45a8ff | 28 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| bogdanm | 0:9b334a45a8ff | 29 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| bogdanm | 0:9b334a45a8ff | 30 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| bogdanm | 0:9b334a45a8ff | 31 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| bogdanm | 0:9b334a45a8ff | 32 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| bogdanm | 0:9b334a45a8ff | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| bogdanm | 0:9b334a45a8ff | 34 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| bogdanm | 0:9b334a45a8ff | 35 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| bogdanm | 0:9b334a45a8ff | 36 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| bogdanm | 0:9b334a45a8ff | 37 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| bogdanm | 0:9b334a45a8ff | 38 | * |
| bogdanm | 0:9b334a45a8ff | 39 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 40 | */ |
| bogdanm | 0:9b334a45a8ff | 41 | |
| bogdanm | 0:9b334a45a8ff | 42 | /* Includes ------------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 43 | #include "stm32f7xx_hal.h" |
| bogdanm | 0:9b334a45a8ff | 44 | |
| bogdanm | 0:9b334a45a8ff | 45 | /** @addtogroup STM32F7xx_HAL_Driver |
| bogdanm | 0:9b334a45a8ff | 46 | * @{ |
| bogdanm | 0:9b334a45a8ff | 47 | */ |
| bogdanm | 0:9b334a45a8ff | 48 | |
| bogdanm | 0:9b334a45a8ff | 49 | /** @defgroup RCCEx RCCEx |
| bogdanm | 0:9b334a45a8ff | 50 | * @brief RCCEx HAL module driver |
| bogdanm | 0:9b334a45a8ff | 51 | * @{ |
| bogdanm | 0:9b334a45a8ff | 52 | */ |
| bogdanm | 0:9b334a45a8ff | 53 | |
| bogdanm | 0:9b334a45a8ff | 54 | #ifdef HAL_RCC_MODULE_ENABLED |
| bogdanm | 0:9b334a45a8ff | 55 | |
| bogdanm | 0:9b334a45a8ff | 56 | /* Private typedef -----------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 57 | /* Private define ------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 58 | /** @defgroup RCCEx_Private_Defines RCCEx Private Defines |
| bogdanm | 0:9b334a45a8ff | 59 | * @{ |
| bogdanm | 0:9b334a45a8ff | 60 | */ |
| bogdanm | 0:9b334a45a8ff | 61 | |
| bogdanm | 0:9b334a45a8ff | 62 | #define PLLI2S_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */ |
| bogdanm | 0:9b334a45a8ff | 63 | #define PLLSAI_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */ |
| bogdanm | 0:9b334a45a8ff | 64 | |
| bogdanm | 0:9b334a45a8ff | 65 | /** |
| bogdanm | 0:9b334a45a8ff | 66 | * @} |
| bogdanm | 0:9b334a45a8ff | 67 | */ |
| bogdanm | 0:9b334a45a8ff | 68 | /* Private macro -------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 69 | /** @defgroup RCCEx_Private_Macros RCCEx Private Macros |
| bogdanm | 0:9b334a45a8ff | 70 | * @{ |
| bogdanm | 0:9b334a45a8ff | 71 | */ |
| bogdanm | 0:9b334a45a8ff | 72 | /** |
| bogdanm | 0:9b334a45a8ff | 73 | * @} |
| bogdanm | 0:9b334a45a8ff | 74 | */ |
| bogdanm | 0:9b334a45a8ff | 75 | |
| bogdanm | 0:9b334a45a8ff | 76 | /** @defgroup RCCEx_Private_Macros RCCEx Private Macros |
| bogdanm | 0:9b334a45a8ff | 77 | * @{ |
| bogdanm | 0:9b334a45a8ff | 78 | */ |
| bogdanm | 0:9b334a45a8ff | 79 | |
| bogdanm | 0:9b334a45a8ff | 80 | /** |
| bogdanm | 0:9b334a45a8ff | 81 | * @} |
| bogdanm | 0:9b334a45a8ff | 82 | */ |
| bogdanm | 0:9b334a45a8ff | 83 | |
| bogdanm | 0:9b334a45a8ff | 84 | |
| bogdanm | 0:9b334a45a8ff | 85 | /* Private variables ---------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 86 | /* Private function prototypes -----------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 87 | /* Private functions ---------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 88 | |
| bogdanm | 0:9b334a45a8ff | 89 | /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions |
| bogdanm | 0:9b334a45a8ff | 90 | * @{ |
| bogdanm | 0:9b334a45a8ff | 91 | */ |
| bogdanm | 0:9b334a45a8ff | 92 | |
| bogdanm | 0:9b334a45a8ff | 93 | /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions |
| bogdanm | 0:9b334a45a8ff | 94 | * @brief Extended Peripheral Control functions |
| bogdanm | 0:9b334a45a8ff | 95 | * |
| bogdanm | 0:9b334a45a8ff | 96 | @verbatim |
| bogdanm | 0:9b334a45a8ff | 97 | =============================================================================== |
| bogdanm | 0:9b334a45a8ff | 98 | ##### Extended Peripheral Control functions ##### |
| bogdanm | 0:9b334a45a8ff | 99 | =============================================================================== |
| bogdanm | 0:9b334a45a8ff | 100 | [..] |
| bogdanm | 0:9b334a45a8ff | 101 | This subsection provides a set of functions allowing to control the RCC Clocks |
| bogdanm | 0:9b334a45a8ff | 102 | frequencies. |
| bogdanm | 0:9b334a45a8ff | 103 | [..] |
| bogdanm | 0:9b334a45a8ff | 104 | (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to |
| bogdanm | 0:9b334a45a8ff | 105 | select the RTC clock source; in this case the Backup domain will be reset in |
| bogdanm | 0:9b334a45a8ff | 106 | order to modify the RTC Clock source, as consequence RTC registers (including |
| bogdanm | 0:9b334a45a8ff | 107 | the backup registers) and RCC_BDCR register will be set to their reset values. |
| bogdanm | 0:9b334a45a8ff | 108 | |
| bogdanm | 0:9b334a45a8ff | 109 | @endverbatim |
| bogdanm | 0:9b334a45a8ff | 110 | * @{ |
| bogdanm | 0:9b334a45a8ff | 111 | */ |
| bogdanm | 0:9b334a45a8ff | 112 | /** |
| bogdanm | 0:9b334a45a8ff | 113 | * @brief Initializes the RCC extended peripherals clocks according to the specified |
| bogdanm | 0:9b334a45a8ff | 114 | * parameters in the RCC_PeriphCLKInitTypeDef. |
| bogdanm | 0:9b334a45a8ff | 115 | * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that |
| bogdanm | 0:9b334a45a8ff | 116 | * contains the configuration information for the Extended Peripherals |
| bogdanm | 0:9b334a45a8ff | 117 | * clocks(I2S, SAI, LTDC RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...). |
| bogdanm | 0:9b334a45a8ff | 118 | * |
| bogdanm | 0:9b334a45a8ff | 119 | * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select |
| bogdanm | 0:9b334a45a8ff | 120 | * the RTC clock source; in this case the Backup domain will be reset in |
| bogdanm | 0:9b334a45a8ff | 121 | * order to modify the RTC Clock source, as consequence RTC registers (including |
| bogdanm | 0:9b334a45a8ff | 122 | * the backup registers) and RCC_BDCR register are set to their reset values. |
| bogdanm | 0:9b334a45a8ff | 123 | * |
| bogdanm | 0:9b334a45a8ff | 124 | * @retval HAL status |
| bogdanm | 0:9b334a45a8ff | 125 | */ |
| bogdanm | 0:9b334a45a8ff | 126 | HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) |
| bogdanm | 0:9b334a45a8ff | 127 | { |
| bogdanm | 0:9b334a45a8ff | 128 | uint32_t tickstart = 0; |
| bogdanm | 0:9b334a45a8ff | 129 | uint32_t tmpreg0 = 0; |
| bogdanm | 0:9b334a45a8ff | 130 | uint32_t tmpreg1 = 0; |
| bogdanm | 0:9b334a45a8ff | 131 | uint32_t plli2sused = 0; |
| bogdanm | 0:9b334a45a8ff | 132 | uint32_t pllsaiused = 0; |
| bogdanm | 0:9b334a45a8ff | 133 | |
| bogdanm | 0:9b334a45a8ff | 134 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 135 | assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); |
| bogdanm | 0:9b334a45a8ff | 136 | |
| bogdanm | 0:9b334a45a8ff | 137 | /*----------------------------------- I2S configuration ----------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 138 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) |
| bogdanm | 0:9b334a45a8ff | 139 | { |
| bogdanm | 0:9b334a45a8ff | 140 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 141 | assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); |
| bogdanm | 0:9b334a45a8ff | 142 | |
| bogdanm | 0:9b334a45a8ff | 143 | /* Configure I2S Clock source */ |
| bogdanm | 0:9b334a45a8ff | 144 | __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); |
| bogdanm | 0:9b334a45a8ff | 145 | |
| bogdanm | 0:9b334a45a8ff | 146 | /* Enable the PLLI2S when it's used as clock source for I2S */ |
| bogdanm | 0:9b334a45a8ff | 147 | if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S) |
| bogdanm | 0:9b334a45a8ff | 148 | { |
| bogdanm | 0:9b334a45a8ff | 149 | plli2sused = 1; |
| bogdanm | 0:9b334a45a8ff | 150 | } |
| bogdanm | 0:9b334a45a8ff | 151 | } |
| bogdanm | 0:9b334a45a8ff | 152 | |
| bogdanm | 0:9b334a45a8ff | 153 | /*------------------------------------ SAI1 configuration --------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 154 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1)) |
| bogdanm | 0:9b334a45a8ff | 155 | { |
| bogdanm | 0:9b334a45a8ff | 156 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 157 | assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); |
| bogdanm | 0:9b334a45a8ff | 158 | |
| bogdanm | 0:9b334a45a8ff | 159 | /* Configure SAI1 Clock source */ |
| bogdanm | 0:9b334a45a8ff | 160 | __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); |
| bogdanm | 0:9b334a45a8ff | 161 | /* Enable the PLLI2S when it's used as clock source for SAI */ |
| bogdanm | 0:9b334a45a8ff | 162 | if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S) |
| bogdanm | 0:9b334a45a8ff | 163 | { |
| bogdanm | 0:9b334a45a8ff | 164 | plli2sused = 1; |
| bogdanm | 0:9b334a45a8ff | 165 | } |
| bogdanm | 0:9b334a45a8ff | 166 | /* Enable the PLLSAI when it's used as clock source for SAI */ |
| bogdanm | 0:9b334a45a8ff | 167 | if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI) |
| bogdanm | 0:9b334a45a8ff | 168 | { |
| bogdanm | 0:9b334a45a8ff | 169 | pllsaiused = 1; |
| bogdanm | 0:9b334a45a8ff | 170 | } |
| bogdanm | 0:9b334a45a8ff | 171 | } |
| bogdanm | 0:9b334a45a8ff | 172 | |
| bogdanm | 0:9b334a45a8ff | 173 | /*------------------------------------ SAI2 configuration --------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 174 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2)) |
| bogdanm | 0:9b334a45a8ff | 175 | { |
| bogdanm | 0:9b334a45a8ff | 176 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 177 | assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection)); |
| bogdanm | 0:9b334a45a8ff | 178 | |
| bogdanm | 0:9b334a45a8ff | 179 | /* Configure SAI2 Clock source */ |
| bogdanm | 0:9b334a45a8ff | 180 | __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); |
| bogdanm | 0:9b334a45a8ff | 181 | |
| bogdanm | 0:9b334a45a8ff | 182 | /* Enable the PLLI2S when it's used as clock source for SAI */ |
| bogdanm | 0:9b334a45a8ff | 183 | if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S) |
| bogdanm | 0:9b334a45a8ff | 184 | { |
| bogdanm | 0:9b334a45a8ff | 185 | plli2sused = 1; |
| bogdanm | 0:9b334a45a8ff | 186 | } |
| bogdanm | 0:9b334a45a8ff | 187 | /* Enable the PLLSAI when it's used as clock source for SAI */ |
| bogdanm | 0:9b334a45a8ff | 188 | if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI) |
| bogdanm | 0:9b334a45a8ff | 189 | { |
| bogdanm | 0:9b334a45a8ff | 190 | pllsaiused = 1; |
| bogdanm | 0:9b334a45a8ff | 191 | } |
| bogdanm | 0:9b334a45a8ff | 192 | } |
| bogdanm | 0:9b334a45a8ff | 193 | |
| bogdanm | 0:9b334a45a8ff | 194 | /*-------------------------------------- SPDIF-RX Configuration -----------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 195 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) |
| bogdanm | 0:9b334a45a8ff | 196 | { |
| bogdanm | 0:9b334a45a8ff | 197 | plli2sused = 1; |
| bogdanm | 0:9b334a45a8ff | 198 | } |
| bogdanm | 0:9b334a45a8ff | 199 | |
| bogdanm | 0:9b334a45a8ff | 200 | /*------------------------------------ RTC configuration --------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 201 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) |
| bogdanm | 0:9b334a45a8ff | 202 | { |
| mbed_official | 83:a036322b8637 | 203 | /* Enable Power Clock*/ |
| mbed_official | 83:a036322b8637 | 204 | __HAL_RCC_PWR_CLK_ENABLE(); |
| mbed_official | 83:a036322b8637 | 205 | |
| mbed_official | 83:a036322b8637 | 206 | /* Enable write access to Backup domain */ |
| mbed_official | 83:a036322b8637 | 207 | PWR->CR1 |= PWR_CR1_DBP; |
| mbed_official | 83:a036322b8637 | 208 | |
| mbed_official | 83:a036322b8637 | 209 | /* Get Start Tick*/ |
| mbed_official | 83:a036322b8637 | 210 | tickstart = HAL_GetTick(); |
| mbed_official | 83:a036322b8637 | 211 | |
| mbed_official | 83:a036322b8637 | 212 | /* Wait for Backup domain Write protection disable */ |
| mbed_official | 83:a036322b8637 | 213 | while((PWR->CR1 & PWR_CR1_DBP) == RESET) |
| mbed_official | 83:a036322b8637 | 214 | { |
| mbed_official | 83:a036322b8637 | 215 | if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) |
| mbed_official | 83:a036322b8637 | 216 | { |
| mbed_official | 83:a036322b8637 | 217 | return HAL_TIMEOUT; |
| mbed_official | 83:a036322b8637 | 218 | } |
| mbed_official | 83:a036322b8637 | 219 | } |
| bogdanm | 0:9b334a45a8ff | 220 | /* Reset the Backup domain only if the RTC Clock source selection is modified */ |
| bogdanm | 0:9b334a45a8ff | 221 | if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)) |
| bogdanm | 0:9b334a45a8ff | 222 | { |
| bogdanm | 0:9b334a45a8ff | 223 | /* Store the content of BDCR register before the reset of Backup Domain */ |
| bogdanm | 0:9b334a45a8ff | 224 | tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); |
| bogdanm | 0:9b334a45a8ff | 225 | |
| bogdanm | 0:9b334a45a8ff | 226 | /* RTC Clock selection can be changed only if the Backup Domain is reset */ |
| bogdanm | 0:9b334a45a8ff | 227 | __HAL_RCC_BACKUPRESET_FORCE(); |
| bogdanm | 0:9b334a45a8ff | 228 | __HAL_RCC_BACKUPRESET_RELEASE(); |
| bogdanm | 0:9b334a45a8ff | 229 | |
| bogdanm | 0:9b334a45a8ff | 230 | /* Restore the Content of BDCR register */ |
| bogdanm | 0:9b334a45a8ff | 231 | RCC->BDCR = tmpreg0; |
| bogdanm | 0:9b334a45a8ff | 232 | |
| bogdanm | 0:9b334a45a8ff | 233 | /* If LSE is selected as RTC clock source, wait for LSE reactivation */ |
| bogdanm | 0:9b334a45a8ff | 234 | if (HAL_IS_BIT_SET(tmpreg0, RCC_BDCR_LSERDY)) |
| bogdanm | 0:9b334a45a8ff | 235 | { |
| bogdanm | 0:9b334a45a8ff | 236 | /* Get Start Tick*/ |
| bogdanm | 0:9b334a45a8ff | 237 | tickstart = HAL_GetTick(); |
| bogdanm | 0:9b334a45a8ff | 238 | |
| bogdanm | 0:9b334a45a8ff | 239 | /* Wait till LSE is ready */ |
| bogdanm | 0:9b334a45a8ff | 240 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) |
| bogdanm | 0:9b334a45a8ff | 241 | { |
| bogdanm | 0:9b334a45a8ff | 242 | if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) |
| bogdanm | 0:9b334a45a8ff | 243 | { |
| bogdanm | 0:9b334a45a8ff | 244 | return HAL_TIMEOUT; |
| bogdanm | 0:9b334a45a8ff | 245 | } |
| bogdanm | 0:9b334a45a8ff | 246 | } |
| bogdanm | 0:9b334a45a8ff | 247 | } |
| bogdanm | 0:9b334a45a8ff | 248 | __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); |
| bogdanm | 0:9b334a45a8ff | 249 | } |
| bogdanm | 0:9b334a45a8ff | 250 | } |
| bogdanm | 0:9b334a45a8ff | 251 | |
| bogdanm | 0:9b334a45a8ff | 252 | /*------------------------------------ TIM configuration --------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 253 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) |
| bogdanm | 0:9b334a45a8ff | 254 | { |
| bogdanm | 0:9b334a45a8ff | 255 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 256 | assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); |
| bogdanm | 0:9b334a45a8ff | 257 | |
| bogdanm | 0:9b334a45a8ff | 258 | /* Configure Timer Prescaler */ |
| bogdanm | 0:9b334a45a8ff | 259 | __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); |
| bogdanm | 0:9b334a45a8ff | 260 | } |
| bogdanm | 0:9b334a45a8ff | 261 | |
| bogdanm | 0:9b334a45a8ff | 262 | /*-------------------------------------- I2C1 Configuration -----------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 263 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) |
| bogdanm | 0:9b334a45a8ff | 264 | { |
| bogdanm | 0:9b334a45a8ff | 265 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 266 | assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); |
| bogdanm | 0:9b334a45a8ff | 267 | |
| bogdanm | 0:9b334a45a8ff | 268 | /* Configure the I2C1 clock source */ |
| bogdanm | 0:9b334a45a8ff | 269 | __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); |
| bogdanm | 0:9b334a45a8ff | 270 | } |
| bogdanm | 0:9b334a45a8ff | 271 | |
| bogdanm | 0:9b334a45a8ff | 272 | /*-------------------------------------- I2C2 Configuration -----------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 273 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) |
| bogdanm | 0:9b334a45a8ff | 274 | { |
| bogdanm | 0:9b334a45a8ff | 275 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 276 | assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); |
| bogdanm | 0:9b334a45a8ff | 277 | |
| bogdanm | 0:9b334a45a8ff | 278 | /* Configure the I2C2 clock source */ |
| bogdanm | 0:9b334a45a8ff | 279 | __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); |
| bogdanm | 0:9b334a45a8ff | 280 | } |
| bogdanm | 0:9b334a45a8ff | 281 | |
| bogdanm | 0:9b334a45a8ff | 282 | /*-------------------------------------- I2C3 Configuration -----------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 283 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) |
| bogdanm | 0:9b334a45a8ff | 284 | { |
| bogdanm | 0:9b334a45a8ff | 285 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 286 | assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); |
| bogdanm | 0:9b334a45a8ff | 287 | |
| bogdanm | 0:9b334a45a8ff | 288 | /* Configure the I2C3 clock source */ |
| bogdanm | 0:9b334a45a8ff | 289 | __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); |
| bogdanm | 0:9b334a45a8ff | 290 | } |
| bogdanm | 0:9b334a45a8ff | 291 | |
| bogdanm | 0:9b334a45a8ff | 292 | /*-------------------------------------- I2C4 Configuration -----------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 293 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) |
| bogdanm | 0:9b334a45a8ff | 294 | { |
| bogdanm | 0:9b334a45a8ff | 295 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 296 | assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); |
| bogdanm | 0:9b334a45a8ff | 297 | |
| bogdanm | 0:9b334a45a8ff | 298 | /* Configure the I2C4 clock source */ |
| bogdanm | 0:9b334a45a8ff | 299 | __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); |
| bogdanm | 0:9b334a45a8ff | 300 | } |
| bogdanm | 0:9b334a45a8ff | 301 | |
| bogdanm | 0:9b334a45a8ff | 302 | /*-------------------------------------- USART1 Configuration -----------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 303 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) |
| bogdanm | 0:9b334a45a8ff | 304 | { |
| bogdanm | 0:9b334a45a8ff | 305 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 306 | assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); |
| bogdanm | 0:9b334a45a8ff | 307 | |
| bogdanm | 0:9b334a45a8ff | 308 | /* Configure the USART1 clock source */ |
| bogdanm | 0:9b334a45a8ff | 309 | __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); |
| bogdanm | 0:9b334a45a8ff | 310 | } |
| bogdanm | 0:9b334a45a8ff | 311 | |
| bogdanm | 0:9b334a45a8ff | 312 | /*-------------------------------------- USART2 Configuration -----------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 313 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) |
| bogdanm | 0:9b334a45a8ff | 314 | { |
| bogdanm | 0:9b334a45a8ff | 315 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 316 | assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); |
| bogdanm | 0:9b334a45a8ff | 317 | |
| bogdanm | 0:9b334a45a8ff | 318 | /* Configure the USART2 clock source */ |
| bogdanm | 0:9b334a45a8ff | 319 | __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); |
| bogdanm | 0:9b334a45a8ff | 320 | } |
| bogdanm | 0:9b334a45a8ff | 321 | |
| bogdanm | 0:9b334a45a8ff | 322 | /*-------------------------------------- USART3 Configuration -----------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 323 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) |
| bogdanm | 0:9b334a45a8ff | 324 | { |
| bogdanm | 0:9b334a45a8ff | 325 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 326 | assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); |
| bogdanm | 0:9b334a45a8ff | 327 | |
| bogdanm | 0:9b334a45a8ff | 328 | /* Configure the USART3 clock source */ |
| bogdanm | 0:9b334a45a8ff | 329 | __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); |
| bogdanm | 0:9b334a45a8ff | 330 | } |
| bogdanm | 0:9b334a45a8ff | 331 | |
| bogdanm | 0:9b334a45a8ff | 332 | /*-------------------------------------- UART4 Configuration -----------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 333 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) |
| bogdanm | 0:9b334a45a8ff | 334 | { |
| bogdanm | 0:9b334a45a8ff | 335 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 336 | assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); |
| bogdanm | 0:9b334a45a8ff | 337 | |
| bogdanm | 0:9b334a45a8ff | 338 | /* Configure the UART4 clock source */ |
| bogdanm | 0:9b334a45a8ff | 339 | __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); |
| bogdanm | 0:9b334a45a8ff | 340 | } |
| bogdanm | 0:9b334a45a8ff | 341 | |
| bogdanm | 0:9b334a45a8ff | 342 | /*-------------------------------------- UART5 Configuration -----------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 343 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) |
| bogdanm | 0:9b334a45a8ff | 344 | { |
| bogdanm | 0:9b334a45a8ff | 345 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 346 | assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection)); |
| bogdanm | 0:9b334a45a8ff | 347 | |
| bogdanm | 0:9b334a45a8ff | 348 | /* Configure the UART5 clock source */ |
| bogdanm | 0:9b334a45a8ff | 349 | __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection); |
| bogdanm | 0:9b334a45a8ff | 350 | } |
| bogdanm | 0:9b334a45a8ff | 351 | |
| bogdanm | 0:9b334a45a8ff | 352 | /*-------------------------------------- USART6 Configuration -----------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 353 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) |
| bogdanm | 0:9b334a45a8ff | 354 | { |
| bogdanm | 0:9b334a45a8ff | 355 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 356 | assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection)); |
| bogdanm | 0:9b334a45a8ff | 357 | |
| bogdanm | 0:9b334a45a8ff | 358 | /* Configure the USART6 clock source */ |
| bogdanm | 0:9b334a45a8ff | 359 | __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection); |
| bogdanm | 0:9b334a45a8ff | 360 | } |
| bogdanm | 0:9b334a45a8ff | 361 | |
| bogdanm | 0:9b334a45a8ff | 362 | /*-------------------------------------- UART7 Configuration -----------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 363 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) |
| bogdanm | 0:9b334a45a8ff | 364 | { |
| bogdanm | 0:9b334a45a8ff | 365 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 366 | assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection)); |
| bogdanm | 0:9b334a45a8ff | 367 | |
| bogdanm | 0:9b334a45a8ff | 368 | /* Configure the UART7 clock source */ |
| bogdanm | 0:9b334a45a8ff | 369 | __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection); |
| bogdanm | 0:9b334a45a8ff | 370 | } |
| bogdanm | 0:9b334a45a8ff | 371 | |
| bogdanm | 0:9b334a45a8ff | 372 | /*-------------------------------------- UART8 Configuration -----------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 373 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) |
| bogdanm | 0:9b334a45a8ff | 374 | { |
| bogdanm | 0:9b334a45a8ff | 375 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 376 | assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection)); |
| bogdanm | 0:9b334a45a8ff | 377 | |
| bogdanm | 0:9b334a45a8ff | 378 | /* Configure the UART8 clock source */ |
| bogdanm | 0:9b334a45a8ff | 379 | __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection); |
| bogdanm | 0:9b334a45a8ff | 380 | } |
| bogdanm | 0:9b334a45a8ff | 381 | |
| bogdanm | 0:9b334a45a8ff | 382 | /*--------------------------------------- CEC Configuration -----------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 383 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) |
| bogdanm | 0:9b334a45a8ff | 384 | { |
| bogdanm | 0:9b334a45a8ff | 385 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 386 | assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); |
| bogdanm | 0:9b334a45a8ff | 387 | |
| bogdanm | 0:9b334a45a8ff | 388 | /* Configure the CEC clock source */ |
| bogdanm | 0:9b334a45a8ff | 389 | __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); |
| bogdanm | 0:9b334a45a8ff | 390 | } |
| bogdanm | 0:9b334a45a8ff | 391 | |
| bogdanm | 0:9b334a45a8ff | 392 | /*-------------------------------------- CK48 Configuration -----------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 393 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) |
| bogdanm | 0:9b334a45a8ff | 394 | { |
| bogdanm | 0:9b334a45a8ff | 395 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 396 | assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection)); |
| bogdanm | 0:9b334a45a8ff | 397 | |
| bogdanm | 0:9b334a45a8ff | 398 | /* Configure the CLK48 source */ |
| bogdanm | 0:9b334a45a8ff | 399 | __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); |
| bogdanm | 0:9b334a45a8ff | 400 | |
| bogdanm | 0:9b334a45a8ff | 401 | /* Enable the PLLSAI when it's used as clock source for CK48 */ |
| bogdanm | 0:9b334a45a8ff | 402 | if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP) |
| bogdanm | 0:9b334a45a8ff | 403 | { |
| bogdanm | 0:9b334a45a8ff | 404 | pllsaiused = 1; |
| bogdanm | 0:9b334a45a8ff | 405 | } |
| bogdanm | 0:9b334a45a8ff | 406 | } |
| bogdanm | 0:9b334a45a8ff | 407 | |
| bogdanm | 0:9b334a45a8ff | 408 | /*-------------------------------------- LTDC Configuration -----------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 409 | #if defined(STM32F756xx) || defined(STM32F746xx) |
| bogdanm | 0:9b334a45a8ff | 410 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) |
| bogdanm | 0:9b334a45a8ff | 411 | { |
| bogdanm | 0:9b334a45a8ff | 412 | pllsaiused = 1; |
| bogdanm | 0:9b334a45a8ff | 413 | } |
| bogdanm | 0:9b334a45a8ff | 414 | #endif /* STM32F756xx || STM32F746xx */ |
| bogdanm | 0:9b334a45a8ff | 415 | /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 416 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) |
| bogdanm | 0:9b334a45a8ff | 417 | { |
| bogdanm | 0:9b334a45a8ff | 418 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 419 | assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection)); |
| bogdanm | 0:9b334a45a8ff | 420 | |
| bogdanm | 0:9b334a45a8ff | 421 | /* Configure the LTPIM1 clock source */ |
| bogdanm | 0:9b334a45a8ff | 422 | __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); |
| bogdanm | 0:9b334a45a8ff | 423 | } |
| bogdanm | 0:9b334a45a8ff | 424 | |
| mbed_official | 83:a036322b8637 | 425 | /*------------------------------------- SDMMC1 Configuration ------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 426 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) |
| bogdanm | 0:9b334a45a8ff | 427 | { |
| bogdanm | 0:9b334a45a8ff | 428 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 429 | assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection)); |
| bogdanm | 0:9b334a45a8ff | 430 | |
| bogdanm | 0:9b334a45a8ff | 431 | /* Configure the SDMMC1 clock source */ |
| bogdanm | 0:9b334a45a8ff | 432 | __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection); |
| bogdanm | 0:9b334a45a8ff | 433 | } |
| bogdanm | 0:9b334a45a8ff | 434 | |
| bogdanm | 0:9b334a45a8ff | 435 | /*-------------------------------------- PLLI2S Configuration ---------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 436 | /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */ |
| bogdanm | 0:9b334a45a8ff | 437 | if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S)) |
| bogdanm | 0:9b334a45a8ff | 438 | { |
| bogdanm | 0:9b334a45a8ff | 439 | /* Disable the PLLI2S */ |
| bogdanm | 0:9b334a45a8ff | 440 | __HAL_RCC_PLLI2S_DISABLE(); |
| bogdanm | 0:9b334a45a8ff | 441 | |
| bogdanm | 0:9b334a45a8ff | 442 | /* Get Start Tick*/ |
| bogdanm | 0:9b334a45a8ff | 443 | tickstart = HAL_GetTick(); |
| bogdanm | 0:9b334a45a8ff | 444 | |
| bogdanm | 0:9b334a45a8ff | 445 | /* Wait till PLLI2S is disabled */ |
| bogdanm | 0:9b334a45a8ff | 446 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) |
| bogdanm | 0:9b334a45a8ff | 447 | { |
| bogdanm | 0:9b334a45a8ff | 448 | if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) |
| bogdanm | 0:9b334a45a8ff | 449 | { |
| bogdanm | 0:9b334a45a8ff | 450 | /* return in case of Timeout detected */ |
| bogdanm | 0:9b334a45a8ff | 451 | return HAL_TIMEOUT; |
| bogdanm | 0:9b334a45a8ff | 452 | } |
| bogdanm | 0:9b334a45a8ff | 453 | } |
| bogdanm | 0:9b334a45a8ff | 454 | |
| bogdanm | 0:9b334a45a8ff | 455 | /* check for common PLLI2S Parameters */ |
| bogdanm | 0:9b334a45a8ff | 456 | assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); |
| bogdanm | 0:9b334a45a8ff | 457 | |
| bogdanm | 0:9b334a45a8ff | 458 | /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/ |
| bogdanm | 0:9b334a45a8ff | 459 | if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S))) |
| bogdanm | 0:9b334a45a8ff | 460 | { |
| bogdanm | 0:9b334a45a8ff | 461 | /* check for Parameters */ |
| bogdanm | 0:9b334a45a8ff | 462 | assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); |
| bogdanm | 0:9b334a45a8ff | 463 | |
| bogdanm | 0:9b334a45a8ff | 464 | /* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */ |
| bogdanm | 0:9b334a45a8ff | 465 | tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)); |
| bogdanm | 0:9b334a45a8ff | 466 | tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)); |
| bogdanm | 0:9b334a45a8ff | 467 | /* Configure the PLLI2S division factors */ |
| bogdanm | 0:9b334a45a8ff | 468 | /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */ |
| bogdanm | 0:9b334a45a8ff | 469 | /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ |
| bogdanm | 0:9b334a45a8ff | 470 | __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR); |
| bogdanm | 0:9b334a45a8ff | 471 | } |
| bogdanm | 0:9b334a45a8ff | 472 | |
| bogdanm | 0:9b334a45a8ff | 473 | /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/ |
| bogdanm | 0:9b334a45a8ff | 474 | if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || |
| bogdanm | 0:9b334a45a8ff | 475 | ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) |
| bogdanm | 0:9b334a45a8ff | 476 | { |
| bogdanm | 0:9b334a45a8ff | 477 | /* Check for PLLI2S Parameters */ |
| bogdanm | 0:9b334a45a8ff | 478 | assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); |
| bogdanm | 0:9b334a45a8ff | 479 | /* Check for PLLI2S/DIVQ parameters */ |
| bogdanm | 0:9b334a45a8ff | 480 | assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); |
| bogdanm | 0:9b334a45a8ff | 481 | |
| bogdanm | 0:9b334a45a8ff | 482 | /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */ |
| bogdanm | 0:9b334a45a8ff | 483 | tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)); |
| bogdanm | 0:9b334a45a8ff | 484 | tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)); |
| bogdanm | 0:9b334a45a8ff | 485 | /* Configure the PLLI2S division factors */ |
| bogdanm | 0:9b334a45a8ff | 486 | /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ |
| bogdanm | 0:9b334a45a8ff | 487 | /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ |
| bogdanm | 0:9b334a45a8ff | 488 | /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ |
| bogdanm | 0:9b334a45a8ff | 489 | __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1); |
| bogdanm | 0:9b334a45a8ff | 490 | |
| bogdanm | 0:9b334a45a8ff | 491 | /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ |
| bogdanm | 0:9b334a45a8ff | 492 | __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); |
| bogdanm | 0:9b334a45a8ff | 493 | } |
| bogdanm | 0:9b334a45a8ff | 494 | |
| bogdanm | 0:9b334a45a8ff | 495 | /*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/ |
| bogdanm | 0:9b334a45a8ff | 496 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) |
| bogdanm | 0:9b334a45a8ff | 497 | { |
| bogdanm | 0:9b334a45a8ff | 498 | /* check for Parameters */ |
| bogdanm | 0:9b334a45a8ff | 499 | assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); |
| bogdanm | 0:9b334a45a8ff | 500 | |
| bogdanm | 0:9b334a45a8ff | 501 | /* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */ |
| bogdanm | 0:9b334a45a8ff | 502 | tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)); |
| bogdanm | 0:9b334a45a8ff | 503 | tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)); |
| bogdanm | 0:9b334a45a8ff | 504 | /* Configure the PLLI2S division factors */ |
| bogdanm | 0:9b334a45a8ff | 505 | /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */ |
| bogdanm | 0:9b334a45a8ff | 506 | /* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ |
| bogdanm | 0:9b334a45a8ff | 507 | __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1); |
| bogdanm | 0:9b334a45a8ff | 508 | } |
| bogdanm | 0:9b334a45a8ff | 509 | |
| bogdanm | 0:9b334a45a8ff | 510 | /*----------------- In Case of PLLI2S is just selected -----------------*/ |
| bogdanm | 0:9b334a45a8ff | 511 | if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) |
| bogdanm | 0:9b334a45a8ff | 512 | { |
| bogdanm | 0:9b334a45a8ff | 513 | /* Check for Parameters */ |
| bogdanm | 0:9b334a45a8ff | 514 | assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); |
| bogdanm | 0:9b334a45a8ff | 515 | assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); |
| bogdanm | 0:9b334a45a8ff | 516 | assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); |
| bogdanm | 0:9b334a45a8ff | 517 | |
| bogdanm | 0:9b334a45a8ff | 518 | /* Configure the PLLI2S division factors */ |
| bogdanm | 0:9b334a45a8ff | 519 | /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */ |
| bogdanm | 0:9b334a45a8ff | 520 | /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ |
| bogdanm | 0:9b334a45a8ff | 521 | __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); |
| bogdanm | 0:9b334a45a8ff | 522 | } |
| bogdanm | 0:9b334a45a8ff | 523 | |
| bogdanm | 0:9b334a45a8ff | 524 | /* Enable the PLLI2S */ |
| bogdanm | 0:9b334a45a8ff | 525 | __HAL_RCC_PLLI2S_ENABLE(); |
| bogdanm | 0:9b334a45a8ff | 526 | |
| bogdanm | 0:9b334a45a8ff | 527 | /* Get Start Tick*/ |
| bogdanm | 0:9b334a45a8ff | 528 | tickstart = HAL_GetTick(); |
| bogdanm | 0:9b334a45a8ff | 529 | |
| bogdanm | 0:9b334a45a8ff | 530 | /* Wait till PLLI2S is ready */ |
| bogdanm | 0:9b334a45a8ff | 531 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) |
| bogdanm | 0:9b334a45a8ff | 532 | { |
| bogdanm | 0:9b334a45a8ff | 533 | if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) |
| bogdanm | 0:9b334a45a8ff | 534 | { |
| bogdanm | 0:9b334a45a8ff | 535 | /* return in case of Timeout detected */ |
| bogdanm | 0:9b334a45a8ff | 536 | return HAL_TIMEOUT; |
| bogdanm | 0:9b334a45a8ff | 537 | } |
| bogdanm | 0:9b334a45a8ff | 538 | } |
| bogdanm | 0:9b334a45a8ff | 539 | } |
| bogdanm | 0:9b334a45a8ff | 540 | |
| bogdanm | 0:9b334a45a8ff | 541 | /*-------------------------------------- PLLSAI Configuration ---------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 542 | /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */ |
| bogdanm | 0:9b334a45a8ff | 543 | if(pllsaiused == 1) |
| bogdanm | 0:9b334a45a8ff | 544 | { |
| bogdanm | 0:9b334a45a8ff | 545 | /* Disable PLLSAI Clock */ |
| bogdanm | 0:9b334a45a8ff | 546 | __HAL_RCC_PLLSAI_DISABLE(); |
| bogdanm | 0:9b334a45a8ff | 547 | |
| bogdanm | 0:9b334a45a8ff | 548 | /* Get Start Tick*/ |
| bogdanm | 0:9b334a45a8ff | 549 | tickstart = HAL_GetTick(); |
| bogdanm | 0:9b334a45a8ff | 550 | |
| bogdanm | 0:9b334a45a8ff | 551 | /* Wait till PLLSAI is disabled */ |
| bogdanm | 0:9b334a45a8ff | 552 | while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) |
| bogdanm | 0:9b334a45a8ff | 553 | { |
| bogdanm | 0:9b334a45a8ff | 554 | if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) |
| bogdanm | 0:9b334a45a8ff | 555 | { |
| bogdanm | 0:9b334a45a8ff | 556 | /* return in case of Timeout detected */ |
| bogdanm | 0:9b334a45a8ff | 557 | return HAL_TIMEOUT; |
| bogdanm | 0:9b334a45a8ff | 558 | } |
| bogdanm | 0:9b334a45a8ff | 559 | } |
| bogdanm | 0:9b334a45a8ff | 560 | |
| bogdanm | 0:9b334a45a8ff | 561 | /* Check the PLLSAI division factors */ |
| bogdanm | 0:9b334a45a8ff | 562 | assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); |
| bogdanm | 0:9b334a45a8ff | 563 | |
| bogdanm | 0:9b334a45a8ff | 564 | /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/ |
| mbed_official | 83:a036322b8637 | 565 | if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\ |
| bogdanm | 0:9b334a45a8ff | 566 | ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) |
| bogdanm | 0:9b334a45a8ff | 567 | { |
| bogdanm | 0:9b334a45a8ff | 568 | /* check for PLLSAIQ Parameter */ |
| bogdanm | 0:9b334a45a8ff | 569 | assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); |
| bogdanm | 0:9b334a45a8ff | 570 | /* check for PLLSAI/DIVQ Parameter */ |
| bogdanm | 0:9b334a45a8ff | 571 | assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); |
| bogdanm | 0:9b334a45a8ff | 572 | |
| bogdanm | 0:9b334a45a8ff | 573 | /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ |
| bogdanm | 0:9b334a45a8ff | 574 | tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)); |
| bogdanm | 0:9b334a45a8ff | 575 | tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)); |
| bogdanm | 0:9b334a45a8ff | 576 | /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ |
| bogdanm | 0:9b334a45a8ff | 577 | /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ |
| bogdanm | 0:9b334a45a8ff | 578 | /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ |
| bogdanm | 0:9b334a45a8ff | 579 | __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1); |
| bogdanm | 0:9b334a45a8ff | 580 | |
| bogdanm | 0:9b334a45a8ff | 581 | /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ |
| bogdanm | 0:9b334a45a8ff | 582 | __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); |
| bogdanm | 0:9b334a45a8ff | 583 | } |
| bogdanm | 0:9b334a45a8ff | 584 | |
| bogdanm | 0:9b334a45a8ff | 585 | /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/ |
| bogdanm | 0:9b334a45a8ff | 586 | /* In Case of PLLI2S is selected as source clock for CK48 */ |
| bogdanm | 0:9b334a45a8ff | 587 | if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)) |
| bogdanm | 0:9b334a45a8ff | 588 | { |
| bogdanm | 0:9b334a45a8ff | 589 | /* check for Parameters */ |
| bogdanm | 0:9b334a45a8ff | 590 | assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); |
| bogdanm | 0:9b334a45a8ff | 591 | /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */ |
| bogdanm | 0:9b334a45a8ff | 592 | tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)); |
| bogdanm | 0:9b334a45a8ff | 593 | tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)); |
| bogdanm | 0:9b334a45a8ff | 594 | |
| bogdanm | 0:9b334a45a8ff | 595 | /* Configure the PLLSAI division factors */ |
| bogdanm | 0:9b334a45a8ff | 596 | /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */ |
| bogdanm | 0:9b334a45a8ff | 597 | /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */ |
| bogdanm | 0:9b334a45a8ff | 598 | __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1); |
| bogdanm | 0:9b334a45a8ff | 599 | } |
| bogdanm | 0:9b334a45a8ff | 600 | |
| bogdanm | 0:9b334a45a8ff | 601 | #if defined(STM32F756xx) || defined(STM32F746xx) |
| bogdanm | 0:9b334a45a8ff | 602 | /*---------------------------- LTDC configuration -------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 603 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC)) |
| bogdanm | 0:9b334a45a8ff | 604 | { |
| bogdanm | 0:9b334a45a8ff | 605 | assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR)); |
| bogdanm | 0:9b334a45a8ff | 606 | assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR)); |
| bogdanm | 0:9b334a45a8ff | 607 | |
| bogdanm | 0:9b334a45a8ff | 608 | /* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */ |
| bogdanm | 0:9b334a45a8ff | 609 | tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)); |
| bogdanm | 0:9b334a45a8ff | 610 | tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)); |
| bogdanm | 0:9b334a45a8ff | 611 | |
| bogdanm | 0:9b334a45a8ff | 612 | /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ |
| bogdanm | 0:9b334a45a8ff | 613 | /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ |
| bogdanm | 0:9b334a45a8ff | 614 | /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */ |
| bogdanm | 0:9b334a45a8ff | 615 | __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR); |
| bogdanm | 0:9b334a45a8ff | 616 | |
| bogdanm | 0:9b334a45a8ff | 617 | /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ |
| bogdanm | 0:9b334a45a8ff | 618 | __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR); |
| bogdanm | 0:9b334a45a8ff | 619 | } |
| bogdanm | 0:9b334a45a8ff | 620 | #endif /* STM32F756xx || STM32F746xx */ |
| bogdanm | 0:9b334a45a8ff | 621 | |
| bogdanm | 0:9b334a45a8ff | 622 | /* Enable PLLSAI Clock */ |
| bogdanm | 0:9b334a45a8ff | 623 | __HAL_RCC_PLLSAI_ENABLE(); |
| bogdanm | 0:9b334a45a8ff | 624 | |
| bogdanm | 0:9b334a45a8ff | 625 | /* Get Start Tick*/ |
| bogdanm | 0:9b334a45a8ff | 626 | tickstart = HAL_GetTick(); |
| bogdanm | 0:9b334a45a8ff | 627 | |
| bogdanm | 0:9b334a45a8ff | 628 | /* Wait till PLLSAI is ready */ |
| bogdanm | 0:9b334a45a8ff | 629 | while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) |
| bogdanm | 0:9b334a45a8ff | 630 | { |
| bogdanm | 0:9b334a45a8ff | 631 | if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) |
| bogdanm | 0:9b334a45a8ff | 632 | { |
| bogdanm | 0:9b334a45a8ff | 633 | /* return in case of Timeout detected */ |
| bogdanm | 0:9b334a45a8ff | 634 | return HAL_TIMEOUT; |
| bogdanm | 0:9b334a45a8ff | 635 | } |
| bogdanm | 0:9b334a45a8ff | 636 | } |
| bogdanm | 0:9b334a45a8ff | 637 | } |
| bogdanm | 0:9b334a45a8ff | 638 | return HAL_OK; |
| bogdanm | 0:9b334a45a8ff | 639 | } |
| bogdanm | 0:9b334a45a8ff | 640 | |
| bogdanm | 0:9b334a45a8ff | 641 | /** |
| bogdanm | 0:9b334a45a8ff | 642 | * @brief Get the RCC_PeriphCLKInitTypeDef according to the internal |
| bogdanm | 0:9b334a45a8ff | 643 | * RCC configuration registers. |
| bogdanm | 0:9b334a45a8ff | 644 | * @param PeriphClkInit: pointer to the configured RCC_PeriphCLKInitTypeDef structure |
| bogdanm | 0:9b334a45a8ff | 645 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 646 | */ |
| bogdanm | 0:9b334a45a8ff | 647 | void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) |
| bogdanm | 0:9b334a45a8ff | 648 | { |
| bogdanm | 0:9b334a45a8ff | 649 | uint32_t tempreg = 0; |
| bogdanm | 0:9b334a45a8ff | 650 | |
| mbed_official | 83:a036322b8637 | 651 | /* Set all possible values for the extended clock type parameter------------*/ |
| mbed_official | 83:a036322b8637 | 652 | PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\ |
| bogdanm | 0:9b334a45a8ff | 653 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\ |
| bogdanm | 0:9b334a45a8ff | 654 | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\ |
| bogdanm | 0:9b334a45a8ff | 655 | RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_I2C4 |\ |
| bogdanm | 0:9b334a45a8ff | 656 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 |\ |
| bogdanm | 0:9b334a45a8ff | 657 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_USART1 |\ |
| bogdanm | 0:9b334a45a8ff | 658 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\ |
| bogdanm | 0:9b334a45a8ff | 659 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 |\ |
| bogdanm | 0:9b334a45a8ff | 660 | RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 |\ |
| mbed_official | 83:a036322b8637 | 661 | RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\ |
| mbed_official | 83:a036322b8637 | 662 | RCC_PERIPHCLK_CLK48; |
| mbed_official | 83:a036322b8637 | 663 | |
| bogdanm | 0:9b334a45a8ff | 664 | |
| bogdanm | 0:9b334a45a8ff | 665 | /* Get the PLLI2S Clock configuration -----------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 666 | PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)); |
| bogdanm | 0:9b334a45a8ff | 667 | PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)); |
| bogdanm | 0:9b334a45a8ff | 668 | PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)); |
| bogdanm | 0:9b334a45a8ff | 669 | PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)); |
| bogdanm | 0:9b334a45a8ff | 670 | |
| bogdanm | 0:9b334a45a8ff | 671 | /* Get the PLLSAI Clock configuration -----------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 672 | PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)); |
| bogdanm | 0:9b334a45a8ff | 673 | PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)); |
| bogdanm | 0:9b334a45a8ff | 674 | PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)); |
| bogdanm | 0:9b334a45a8ff | 675 | PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)); |
| bogdanm | 0:9b334a45a8ff | 676 | |
| bogdanm | 0:9b334a45a8ff | 677 | /* Get the PLLSAI/PLLI2S division factors -------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 678 | PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR1_PLLI2SDIVQ)); |
| bogdanm | 0:9b334a45a8ff | 679 | PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR1_PLLSAIDIVQ)); |
| bogdanm | 0:9b334a45a8ff | 680 | PeriphClkInit->PLLSAIDivR = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVR) >> POSITION_VAL(RCC_DCKCFGR1_PLLSAIDIVR)); |
| bogdanm | 0:9b334a45a8ff | 681 | |
| bogdanm | 0:9b334a45a8ff | 682 | /* Get the SAI1 clock configuration ----------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 683 | PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); |
| bogdanm | 0:9b334a45a8ff | 684 | |
| bogdanm | 0:9b334a45a8ff | 685 | /* Get the SAI2 clock configuration ----------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 686 | PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE(); |
| bogdanm | 0:9b334a45a8ff | 687 | |
| bogdanm | 0:9b334a45a8ff | 688 | /* Get the I2S clock configuration ------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 689 | PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2SCLKSOURCE(); |
| bogdanm | 0:9b334a45a8ff | 690 | |
| bogdanm | 0:9b334a45a8ff | 691 | /* Get the I2C1 clock configuration ------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 692 | PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); |
| bogdanm | 0:9b334a45a8ff | 693 | |
| bogdanm | 0:9b334a45a8ff | 694 | /* Get the I2C2 clock configuration ------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 695 | PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE(); |
| bogdanm | 0:9b334a45a8ff | 696 | |
| bogdanm | 0:9b334a45a8ff | 697 | /* Get the I2C3 clock configuration ------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 698 | PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE(); |
| bogdanm | 0:9b334a45a8ff | 699 | |
| bogdanm | 0:9b334a45a8ff | 700 | /* Get the I2C4 clock configuration ------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 701 | PeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE(); |
| bogdanm | 0:9b334a45a8ff | 702 | |
| bogdanm | 0:9b334a45a8ff | 703 | /* Get the USART1 clock configuration ------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 704 | PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); |
| bogdanm | 0:9b334a45a8ff | 705 | |
| bogdanm | 0:9b334a45a8ff | 706 | /* Get the USART2 clock configuration ------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 707 | PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); |
| bogdanm | 0:9b334a45a8ff | 708 | |
| bogdanm | 0:9b334a45a8ff | 709 | /* Get the USART3 clock configuration ------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 710 | PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE(); |
| bogdanm | 0:9b334a45a8ff | 711 | |
| bogdanm | 0:9b334a45a8ff | 712 | /* Get the UART4 clock configuration ------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 713 | PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE(); |
| bogdanm | 0:9b334a45a8ff | 714 | |
| bogdanm | 0:9b334a45a8ff | 715 | /* Get the UART5 clock configuration ------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 716 | PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE(); |
| bogdanm | 0:9b334a45a8ff | 717 | |
| bogdanm | 0:9b334a45a8ff | 718 | /* Get the USART6 clock configuration ------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 719 | PeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE(); |
| bogdanm | 0:9b334a45a8ff | 720 | |
| bogdanm | 0:9b334a45a8ff | 721 | /* Get the UART7 clock configuration ------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 722 | PeriphClkInit->Uart7ClockSelection = __HAL_RCC_GET_UART7_SOURCE(); |
| bogdanm | 0:9b334a45a8ff | 723 | |
| bogdanm | 0:9b334a45a8ff | 724 | /* Get the UART8 clock configuration ------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 725 | PeriphClkInit->Uart8ClockSelection = __HAL_RCC_GET_UART8_SOURCE(); |
| bogdanm | 0:9b334a45a8ff | 726 | |
| bogdanm | 0:9b334a45a8ff | 727 | /* Get the LPTIM1 clock configuration ------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 728 | PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); |
| bogdanm | 0:9b334a45a8ff | 729 | |
| bogdanm | 0:9b334a45a8ff | 730 | /* Get the CEC clock configuration -----------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 731 | PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE(); |
| bogdanm | 0:9b334a45a8ff | 732 | |
| bogdanm | 0:9b334a45a8ff | 733 | /* Get the CK48 clock configuration -----------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 734 | PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE(); |
| bogdanm | 0:9b334a45a8ff | 735 | |
| bogdanm | 0:9b334a45a8ff | 736 | /* Get the SDMMC clock configuration -----------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 737 | PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE(); |
| bogdanm | 0:9b334a45a8ff | 738 | |
| bogdanm | 0:9b334a45a8ff | 739 | /* Get the RTC Clock configuration -----------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 740 | tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); |
| bogdanm | 0:9b334a45a8ff | 741 | PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); |
| bogdanm | 0:9b334a45a8ff | 742 | |
| bogdanm | 0:9b334a45a8ff | 743 | /* Get the TIM Prescaler configuration --------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 744 | if ((RCC->DCKCFGR1 & RCC_DCKCFGR1_TIMPRE) == RESET) |
| bogdanm | 0:9b334a45a8ff | 745 | { |
| bogdanm | 0:9b334a45a8ff | 746 | PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; |
| bogdanm | 0:9b334a45a8ff | 747 | } |
| bogdanm | 0:9b334a45a8ff | 748 | else |
| bogdanm | 0:9b334a45a8ff | 749 | { |
| bogdanm | 0:9b334a45a8ff | 750 | PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; |
| bogdanm | 0:9b334a45a8ff | 751 | } |
| bogdanm | 0:9b334a45a8ff | 752 | } |
| bogdanm | 0:9b334a45a8ff | 753 | |
| bogdanm | 0:9b334a45a8ff | 754 | /** |
| bogdanm | 0:9b334a45a8ff | 755 | * @brief Return the peripheral clock frequency for a given peripheral(SAI..) |
| bogdanm | 0:9b334a45a8ff | 756 | * @note Return 0 if peripheral clock identifier not managed by this API |
| bogdanm | 0:9b334a45a8ff | 757 | * @param PeriphClk: Peripheral clock identifier |
| bogdanm | 0:9b334a45a8ff | 758 | * This parameter can be one of the following values: |
| bogdanm | 0:9b334a45a8ff | 759 | * @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock |
| bogdanm | 0:9b334a45a8ff | 760 | * @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock |
| bogdanm | 0:9b334a45a8ff | 761 | * @retval Frequency in KHz |
| bogdanm | 0:9b334a45a8ff | 762 | */ |
| bogdanm | 0:9b334a45a8ff | 763 | uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) |
| bogdanm | 0:9b334a45a8ff | 764 | { |
| bogdanm | 0:9b334a45a8ff | 765 | uint32_t tmpreg = 0; |
| mbed_official | 83:a036322b8637 | 766 | /* This variable is used to store the SAI clock frequency (value in Hz) */ |
| bogdanm | 0:9b334a45a8ff | 767 | uint32_t frequency = 0; |
| mbed_official | 83:a036322b8637 | 768 | /* This variable is used to store the VCO Input (value in Hz) */ |
| bogdanm | 0:9b334a45a8ff | 769 | uint32_t vcoinput = 0; |
| mbed_official | 83:a036322b8637 | 770 | /* This variable is used to store the SAI clock source */ |
| bogdanm | 0:9b334a45a8ff | 771 | uint32_t saiclocksource = 0; |
| mbed_official | 83:a036322b8637 | 772 | |
| mbed_official | 83:a036322b8637 | 773 | if (PeriphClk == RCC_PERIPHCLK_SAI1) |
| bogdanm | 0:9b334a45a8ff | 774 | { |
| bogdanm | 0:9b334a45a8ff | 775 | saiclocksource = RCC->DCKCFGR1; |
| mbed_official | 83:a036322b8637 | 776 | saiclocksource &= RCC_DCKCFGR1_SAI1SEL; |
| mbed_official | 83:a036322b8637 | 777 | switch (saiclocksource) |
| mbed_official | 83:a036322b8637 | 778 | { |
| mbed_official | 83:a036322b8637 | 779 | case 0: /* PLLSAI is the clock source for SAI1 */ |
| mbed_official | 83:a036322b8637 | 780 | { |
| mbed_official | 83:a036322b8637 | 781 | /* Configure the PLLSAI division factor */ |
| mbed_official | 83:a036322b8637 | 782 | /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ |
| mbed_official | 83:a036322b8637 | 783 | if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) |
| mbed_official | 83:a036322b8637 | 784 | { |
| mbed_official | 83:a036322b8637 | 785 | /* In Case the PLL Source is HSI (Internal Clock) */ |
| mbed_official | 83:a036322b8637 | 786 | vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); |
| mbed_official | 83:a036322b8637 | 787 | } |
| mbed_official | 83:a036322b8637 | 788 | else |
| mbed_official | 83:a036322b8637 | 789 | { |
| mbed_official | 83:a036322b8637 | 790 | /* In Case the PLL Source is HSE (External Clock) */ |
| mbed_official | 83:a036322b8637 | 791 | vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); |
| mbed_official | 83:a036322b8637 | 792 | } |
| mbed_official | 83:a036322b8637 | 793 | /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ |
| mbed_official | 83:a036322b8637 | 794 | /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ |
| mbed_official | 83:a036322b8637 | 795 | tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24; |
| mbed_official | 83:a036322b8637 | 796 | frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg); |
| mbed_official | 83:a036322b8637 | 797 | |
| mbed_official | 83:a036322b8637 | 798 | /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ |
| mbed_official | 83:a036322b8637 | 799 | tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1); |
| mbed_official | 83:a036322b8637 | 800 | frequency = frequency/(tmpreg); |
| mbed_official | 83:a036322b8637 | 801 | break; |
| mbed_official | 83:a036322b8637 | 802 | } |
| mbed_official | 83:a036322b8637 | 803 | case RCC_DCKCFGR1_SAI1SEL_0: /* PLLI2S is the clock source for SAI1 */ |
| mbed_official | 83:a036322b8637 | 804 | { |
| mbed_official | 83:a036322b8637 | 805 | /* Configure the PLLI2S division factor */ |
| mbed_official | 83:a036322b8637 | 806 | /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ |
| mbed_official | 83:a036322b8637 | 807 | if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) |
| mbed_official | 83:a036322b8637 | 808 | { |
| mbed_official | 83:a036322b8637 | 809 | /* In Case the PLL Source is HSI (Internal Clock) */ |
| mbed_official | 83:a036322b8637 | 810 | vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); |
| mbed_official | 83:a036322b8637 | 811 | } |
| mbed_official | 83:a036322b8637 | 812 | else |
| mbed_official | 83:a036322b8637 | 813 | { |
| mbed_official | 83:a036322b8637 | 814 | /* In Case the PLL Source is HSE (External Clock) */ |
| mbed_official | 83:a036322b8637 | 815 | vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); |
| mbed_official | 83:a036322b8637 | 816 | } |
| mbed_official | 83:a036322b8637 | 817 | |
| mbed_official | 83:a036322b8637 | 818 | /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ |
| mbed_official | 83:a036322b8637 | 819 | /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ |
| mbed_official | 83:a036322b8637 | 820 | tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24; |
| mbed_official | 83:a036322b8637 | 821 | frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg); |
| mbed_official | 83:a036322b8637 | 822 | |
| mbed_official | 83:a036322b8637 | 823 | /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ |
| mbed_official | 83:a036322b8637 | 824 | tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1); |
| mbed_official | 83:a036322b8637 | 825 | frequency = frequency/(tmpreg); |
| mbed_official | 83:a036322b8637 | 826 | break; |
| mbed_official | 83:a036322b8637 | 827 | } |
| mbed_official | 83:a036322b8637 | 828 | case RCC_DCKCFGR1_SAI1SEL_1: /* External clock is the clock source for SAI1 */ |
| mbed_official | 83:a036322b8637 | 829 | { |
| mbed_official | 83:a036322b8637 | 830 | frequency = EXTERNAL_CLOCK_VALUE; |
| mbed_official | 83:a036322b8637 | 831 | break; |
| mbed_official | 83:a036322b8637 | 832 | } |
| mbed_official | 83:a036322b8637 | 833 | default : |
| mbed_official | 83:a036322b8637 | 834 | { |
| mbed_official | 83:a036322b8637 | 835 | break; |
| mbed_official | 83:a036322b8637 | 836 | } |
| mbed_official | 83:a036322b8637 | 837 | } |
| mbed_official | 83:a036322b8637 | 838 | } |
| mbed_official | 83:a036322b8637 | 839 | |
| mbed_official | 83:a036322b8637 | 840 | if (PeriphClk == RCC_PERIPHCLK_SAI2) |
| mbed_official | 83:a036322b8637 | 841 | { |
| mbed_official | 83:a036322b8637 | 842 | saiclocksource = RCC->DCKCFGR1; |
| mbed_official | 83:a036322b8637 | 843 | saiclocksource &= RCC_DCKCFGR1_SAI2SEL; |
| bogdanm | 0:9b334a45a8ff | 844 | switch (saiclocksource) |
| bogdanm | 0:9b334a45a8ff | 845 | { |
| bogdanm | 0:9b334a45a8ff | 846 | case 0: /* PLLSAI is the clock source for SAI*/ |
| bogdanm | 0:9b334a45a8ff | 847 | { |
| bogdanm | 0:9b334a45a8ff | 848 | /* Configure the PLLSAI division factor */ |
| bogdanm | 0:9b334a45a8ff | 849 | /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ |
| bogdanm | 0:9b334a45a8ff | 850 | if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) |
| bogdanm | 0:9b334a45a8ff | 851 | { |
| bogdanm | 0:9b334a45a8ff | 852 | /* In Case the PLL Source is HSI (Internal Clock) */ |
| bogdanm | 0:9b334a45a8ff | 853 | vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); |
| bogdanm | 0:9b334a45a8ff | 854 | } |
| bogdanm | 0:9b334a45a8ff | 855 | else |
| bogdanm | 0:9b334a45a8ff | 856 | { |
| bogdanm | 0:9b334a45a8ff | 857 | /* In Case the PLL Source is HSE (External Clock) */ |
| bogdanm | 0:9b334a45a8ff | 858 | vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); |
| bogdanm | 0:9b334a45a8ff | 859 | } |
| bogdanm | 0:9b334a45a8ff | 860 | /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ |
| bogdanm | 0:9b334a45a8ff | 861 | /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ |
| bogdanm | 0:9b334a45a8ff | 862 | tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24; |
| bogdanm | 0:9b334a45a8ff | 863 | frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg); |
| bogdanm | 0:9b334a45a8ff | 864 | |
| bogdanm | 0:9b334a45a8ff | 865 | /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ |
| bogdanm | 0:9b334a45a8ff | 866 | tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1); |
| bogdanm | 0:9b334a45a8ff | 867 | frequency = frequency/(tmpreg); |
| bogdanm | 0:9b334a45a8ff | 868 | break; |
| bogdanm | 0:9b334a45a8ff | 869 | } |
| mbed_official | 83:a036322b8637 | 870 | case RCC_DCKCFGR1_SAI2SEL_0: /* PLLI2S is the clock source for SAI2 */ |
| bogdanm | 0:9b334a45a8ff | 871 | { |
| bogdanm | 0:9b334a45a8ff | 872 | /* Configure the PLLI2S division factor */ |
| bogdanm | 0:9b334a45a8ff | 873 | /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ |
| bogdanm | 0:9b334a45a8ff | 874 | if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) |
| bogdanm | 0:9b334a45a8ff | 875 | { |
| bogdanm | 0:9b334a45a8ff | 876 | /* In Case the PLL Source is HSI (Internal Clock) */ |
| bogdanm | 0:9b334a45a8ff | 877 | vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); |
| bogdanm | 0:9b334a45a8ff | 878 | } |
| bogdanm | 0:9b334a45a8ff | 879 | else |
| bogdanm | 0:9b334a45a8ff | 880 | { |
| bogdanm | 0:9b334a45a8ff | 881 | /* In Case the PLL Source is HSE (External Clock) */ |
| bogdanm | 0:9b334a45a8ff | 882 | vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); |
| bogdanm | 0:9b334a45a8ff | 883 | } |
| bogdanm | 0:9b334a45a8ff | 884 | |
| bogdanm | 0:9b334a45a8ff | 885 | /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ |
| bogdanm | 0:9b334a45a8ff | 886 | /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ |
| bogdanm | 0:9b334a45a8ff | 887 | tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24; |
| bogdanm | 0:9b334a45a8ff | 888 | frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg); |
| bogdanm | 0:9b334a45a8ff | 889 | |
| bogdanm | 0:9b334a45a8ff | 890 | /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ |
| bogdanm | 0:9b334a45a8ff | 891 | tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1); |
| bogdanm | 0:9b334a45a8ff | 892 | frequency = frequency/(tmpreg); |
| bogdanm | 0:9b334a45a8ff | 893 | break; |
| bogdanm | 0:9b334a45a8ff | 894 | } |
| mbed_official | 83:a036322b8637 | 895 | case RCC_DCKCFGR1_SAI2SEL_1: /* External clock is the clock source for SAI2 */ |
| bogdanm | 0:9b334a45a8ff | 896 | { |
| bogdanm | 0:9b334a45a8ff | 897 | frequency = EXTERNAL_CLOCK_VALUE; |
| bogdanm | 0:9b334a45a8ff | 898 | break; |
| bogdanm | 0:9b334a45a8ff | 899 | } |
| bogdanm | 0:9b334a45a8ff | 900 | default : |
| bogdanm | 0:9b334a45a8ff | 901 | { |
| bogdanm | 0:9b334a45a8ff | 902 | break; |
| bogdanm | 0:9b334a45a8ff | 903 | } |
| bogdanm | 0:9b334a45a8ff | 904 | } |
| bogdanm | 0:9b334a45a8ff | 905 | } |
| mbed_official | 83:a036322b8637 | 906 | |
| bogdanm | 0:9b334a45a8ff | 907 | return frequency; |
| bogdanm | 0:9b334a45a8ff | 908 | } |
| bogdanm | 0:9b334a45a8ff | 909 | /** |
| bogdanm | 0:9b334a45a8ff | 910 | * @} |
| bogdanm | 0:9b334a45a8ff | 911 | */ |
| bogdanm | 0:9b334a45a8ff | 912 | |
| bogdanm | 0:9b334a45a8ff | 913 | /** |
| bogdanm | 0:9b334a45a8ff | 914 | * @} |
| bogdanm | 0:9b334a45a8ff | 915 | */ |
| bogdanm | 0:9b334a45a8ff | 916 | |
| bogdanm | 0:9b334a45a8ff | 917 | #endif /* HAL_RCC_MODULE_ENABLED */ |
| bogdanm | 0:9b334a45a8ff | 918 | /** |
| bogdanm | 0:9b334a45a8ff | 919 | * @} |
| bogdanm | 0:9b334a45a8ff | 920 | */ |
| bogdanm | 0:9b334a45a8ff | 921 | |
| bogdanm | 0:9b334a45a8ff | 922 | /** |
| bogdanm | 0:9b334a45a8ff | 923 | * @} |
| bogdanm | 0:9b334a45a8ff | 924 | */ |
| bogdanm | 0:9b334a45a8ff | 925 | |
| bogdanm | 0:9b334a45a8ff | 926 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |