Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash_ex.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
83:a036322b8637 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f7xx_hal_flash_ex.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.0
<> 144:ef7eb2e8f9f7 6 * @date 22-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of FLASH HAL Extension module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F7xx_HAL_FLASH_EX_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F7xx_HAL_FLASH_EX_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f7xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F7xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup FLASHEx
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /** @defgroup FLASHEx_Exported_Types FLASH Exported Types
<> 144:ef7eb2e8f9f7 59 * @{
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /**
<> 144:ef7eb2e8f9f7 63 * @brief FLASH Erase structure definition
<> 144:ef7eb2e8f9f7 64 */
<> 144:ef7eb2e8f9f7 65 typedef struct
<> 144:ef7eb2e8f9f7 66 {
<> 144:ef7eb2e8f9f7 67 uint32_t TypeErase; /*!< Mass erase or sector Erase.
<> 144:ef7eb2e8f9f7 68 This parameter can be a value of @ref FLASHEx_Type_Erase */
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 #if defined (FLASH_OPTCR_nDBANK)
<> 144:ef7eb2e8f9f7 71 uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled.
<> 144:ef7eb2e8f9f7 72 This parameter must be a value of @ref FLASHEx_Banks */
<> 144:ef7eb2e8f9f7 73 #endif /* FLASH_OPTCR_nDBANK */
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled
<> 144:ef7eb2e8f9f7 76 This parameter must be a value of @ref FLASHEx_Sectors */
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 uint32_t NbSectors; /*!< Number of sectors to be erased.
<> 144:ef7eb2e8f9f7 79 This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism
<> 144:ef7eb2e8f9f7 82 This parameter must be a value of @ref FLASHEx_Voltage_Range */
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 } FLASH_EraseInitTypeDef;
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 /**
<> 144:ef7eb2e8f9f7 87 * @brief FLASH Option Bytes Program structure definition
<> 144:ef7eb2e8f9f7 88 */
<> 144:ef7eb2e8f9f7 89 typedef struct
<> 144:ef7eb2e8f9f7 90 {
<> 144:ef7eb2e8f9f7 91 uint32_t OptionType; /*!< Option byte to be configured.
<> 144:ef7eb2e8f9f7 92 This parameter can be a value of @ref FLASHEx_Option_Type */
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 uint32_t WRPState; /*!< Write protection activation or deactivation.
<> 144:ef7eb2e8f9f7 95 This parameter can be a value of @ref FLASHEx_WRP_State */
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected.
<> 144:ef7eb2e8f9f7 98 The value of this parameter depend on device used within the same series */
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 uint32_t RDPLevel; /*!< Set the read protection level.
<> 144:ef7eb2e8f9f7 101 This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 uint32_t BORLevel; /*!< Set the BOR Level.
<> 144:ef7eb2e8f9f7 104 This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 uint32_t USERConfig; /*!< Program the FLASH User Option Byte: WWDG_SW / IWDG_SW / RST_STOP / RST_STDBY /
<> 144:ef7eb2e8f9f7 107 IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / nDBANK / nDBOOT.
<> 144:ef7eb2e8f9f7 108 nDBANK / nDBOOT are only available for STM32F76xxx/STM32F77xxx devices */
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 uint32_t BootAddr0; /*!< Boot base address when Boot pin = 0.
<> 144:ef7eb2e8f9f7 111 This parameter can be a value of @ref FLASHEx_Boot_Address */
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 uint32_t BootAddr1; /*!< Boot base address when Boot pin = 1.
<> 144:ef7eb2e8f9f7 114 This parameter can be a value of @ref FLASHEx_Boot_Address */
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 } FLASH_OBProgramInitTypeDef;
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 /**
<> 144:ef7eb2e8f9f7 119 * @}
<> 144:ef7eb2e8f9f7 120 */
<> 144:ef7eb2e8f9f7 121 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 /** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants
<> 144:ef7eb2e8f9f7 124 * @{
<> 144:ef7eb2e8f9f7 125 */
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 /** @defgroup FLASHEx_Type_Erase FLASH Type Erase
<> 144:ef7eb2e8f9f7 128 * @{
<> 144:ef7eb2e8f9f7 129 */
<> 144:ef7eb2e8f9f7 130 #define FLASH_TYPEERASE_SECTORS ((uint32_t)0x00U) /*!< Sectors erase only */
<> 144:ef7eb2e8f9f7 131 #define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01U) /*!< Flash Mass erase activation */
<> 144:ef7eb2e8f9f7 132 /**
<> 144:ef7eb2e8f9f7 133 * @}
<> 144:ef7eb2e8f9f7 134 */
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 /** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range
<> 144:ef7eb2e8f9f7 137 * @{
<> 144:ef7eb2e8f9f7 138 */
<> 144:ef7eb2e8f9f7 139 #define FLASH_VOLTAGE_RANGE_1 ((uint32_t)0x00U) /*!< Device operating range: 1.8V to 2.1V */
<> 144:ef7eb2e8f9f7 140 #define FLASH_VOLTAGE_RANGE_2 ((uint32_t)0x01U) /*!< Device operating range: 2.1V to 2.7V */
<> 144:ef7eb2e8f9f7 141 #define FLASH_VOLTAGE_RANGE_3 ((uint32_t)0x02U) /*!< Device operating range: 2.7V to 3.6V */
<> 144:ef7eb2e8f9f7 142 #define FLASH_VOLTAGE_RANGE_4 ((uint32_t)0x03U) /*!< Device operating range: 2.7V to 3.6V + External Vpp */
<> 144:ef7eb2e8f9f7 143 /**
<> 144:ef7eb2e8f9f7 144 * @}
<> 144:ef7eb2e8f9f7 145 */
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 /** @defgroup FLASHEx_WRP_State FLASH WRP State
<> 144:ef7eb2e8f9f7 148 * @{
<> 144:ef7eb2e8f9f7 149 */
<> 144:ef7eb2e8f9f7 150 #define OB_WRPSTATE_DISABLE ((uint32_t)0x00U) /*!< Disable the write protection of the desired bank 1 sectors */
<> 144:ef7eb2e8f9f7 151 #define OB_WRPSTATE_ENABLE ((uint32_t)0x01U) /*!< Enable the write protection of the desired bank 1 sectors */
<> 144:ef7eb2e8f9f7 152 /**
<> 144:ef7eb2e8f9f7 153 * @}
<> 144:ef7eb2e8f9f7 154 */
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 /** @defgroup FLASHEx_Option_Type FLASH Option Type
<> 144:ef7eb2e8f9f7 157 * @{
<> 144:ef7eb2e8f9f7 158 */
<> 144:ef7eb2e8f9f7 159 #define OPTIONBYTE_WRP ((uint32_t)0x01U) /*!< WRP option byte configuration */
<> 144:ef7eb2e8f9f7 160 #define OPTIONBYTE_RDP ((uint32_t)0x02U) /*!< RDP option byte configuration */
<> 144:ef7eb2e8f9f7 161 #define OPTIONBYTE_USER ((uint32_t)0x04U) /*!< USER option byte configuration */
<> 144:ef7eb2e8f9f7 162 #define OPTIONBYTE_BOR ((uint32_t)0x08U) /*!< BOR option byte configuration */
<> 144:ef7eb2e8f9f7 163 #define OPTIONBYTE_BOOTADDR_0 ((uint32_t)0x10U) /*!< Boot 0 Address configuration */
<> 144:ef7eb2e8f9f7 164 #define OPTIONBYTE_BOOTADDR_1 ((uint32_t)0x20U) /*!< Boot 1 Address configuration */
<> 144:ef7eb2e8f9f7 165 /**
<> 144:ef7eb2e8f9f7 166 * @}
<> 144:ef7eb2e8f9f7 167 */
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 /** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection
<> 144:ef7eb2e8f9f7 170 * @{
<> 144:ef7eb2e8f9f7 171 */
<> 144:ef7eb2e8f9f7 172 #define OB_RDP_LEVEL_0 ((uint8_t)0xAAU)
<> 144:ef7eb2e8f9f7 173 #define OB_RDP_LEVEL_1 ((uint8_t)0x55U)
<> 144:ef7eb2e8f9f7 174 #define OB_RDP_LEVEL_2 ((uint8_t)0xCCU) /*!< Warning: When enabling read protection level 2
<> 144:ef7eb2e8f9f7 175 it s no more possible to go back to level 1 or 0 */
<> 144:ef7eb2e8f9f7 176 /**
<> 144:ef7eb2e8f9f7 177 * @}
<> 144:ef7eb2e8f9f7 178 */
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 /** @defgroup FLASHEx_Option_Bytes_WWatchdog FLASH Option Bytes WWatchdog
<> 144:ef7eb2e8f9f7 181 * @{
<> 144:ef7eb2e8f9f7 182 */
<> 144:ef7eb2e8f9f7 183 #define OB_WWDG_SW ((uint32_t)0x10U) /*!< Software WWDG selected */
<> 144:ef7eb2e8f9f7 184 #define OB_WWDG_HW ((uint32_t)0x00U) /*!< Hardware WWDG selected */
<> 144:ef7eb2e8f9f7 185 /**
<> 144:ef7eb2e8f9f7 186 * @}
<> 144:ef7eb2e8f9f7 187 */
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 /** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog
<> 144:ef7eb2e8f9f7 191 * @{
<> 144:ef7eb2e8f9f7 192 */
<> 144:ef7eb2e8f9f7 193 #define OB_IWDG_SW ((uint32_t)0x20U) /*!< Software IWDG selected */
<> 144:ef7eb2e8f9f7 194 #define OB_IWDG_HW ((uint32_t)0x00U) /*!< Hardware IWDG selected */
<> 144:ef7eb2e8f9f7 195 /**
<> 144:ef7eb2e8f9f7 196 * @}
<> 144:ef7eb2e8f9f7 197 */
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 /** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP
<> 144:ef7eb2e8f9f7 200 * @{
<> 144:ef7eb2e8f9f7 201 */
<> 144:ef7eb2e8f9f7 202 #define OB_STOP_NO_RST ((uint32_t)0x40U) /*!< No reset generated when entering in STOP */
<> 144:ef7eb2e8f9f7 203 #define OB_STOP_RST ((uint32_t)0x00U) /*!< Reset generated when entering in STOP */
<> 144:ef7eb2e8f9f7 204 /**
<> 144:ef7eb2e8f9f7 205 * @}
<> 144:ef7eb2e8f9f7 206 */
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 /** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY
<> 144:ef7eb2e8f9f7 209 * @{
<> 144:ef7eb2e8f9f7 210 */
<> 144:ef7eb2e8f9f7 211 #define OB_STDBY_NO_RST ((uint32_t)0x80U) /*!< No reset generated when entering in STANDBY */
<> 144:ef7eb2e8f9f7 212 #define OB_STDBY_RST ((uint32_t)0x00U) /*!< Reset generated when entering in STANDBY */
<> 144:ef7eb2e8f9f7 213 /**
<> 144:ef7eb2e8f9f7 214 * @}
<> 144:ef7eb2e8f9f7 215 */
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 /** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP
<> 144:ef7eb2e8f9f7 218 * @{
<> 144:ef7eb2e8f9f7 219 */
<> 144:ef7eb2e8f9f7 220 #define OB_IWDG_STOP_FREEZE ((uint32_t)0x00000000U) /*!< Freeze IWDG counter in STOP mode */
<> 144:ef7eb2e8f9f7 221 #define OB_IWDG_STOP_ACTIVE ((uint32_t)0x80000000U) /*!< IWDG counter active in STOP mode */
<> 144:ef7eb2e8f9f7 222 /**
<> 144:ef7eb2e8f9f7 223 * @}
<> 144:ef7eb2e8f9f7 224 */
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 /** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY
<> 144:ef7eb2e8f9f7 227 * @{
<> 144:ef7eb2e8f9f7 228 */
<> 144:ef7eb2e8f9f7 229 #define OB_IWDG_STDBY_FREEZE ((uint32_t)0x00000000U) /*!< Freeze IWDG counter in STANDBY mode */
<> 144:ef7eb2e8f9f7 230 #define OB_IWDG_STDBY_ACTIVE ((uint32_t)0x40000000U) /*!< IWDG counter active in STANDBY mode */
<> 144:ef7eb2e8f9f7 231 /**
<> 144:ef7eb2e8f9f7 232 * @}
<> 144:ef7eb2e8f9f7 233 */
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 /** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level
<> 144:ef7eb2e8f9f7 236 * @{
<> 144:ef7eb2e8f9f7 237 */
<> 144:ef7eb2e8f9f7 238 #define OB_BOR_LEVEL3 ((uint32_t)0x00U) /*!< Supply voltage ranges from 2.70 to 3.60 V */
<> 144:ef7eb2e8f9f7 239 #define OB_BOR_LEVEL2 ((uint32_t)0x04U) /*!< Supply voltage ranges from 2.40 to 2.70 V */
<> 144:ef7eb2e8f9f7 240 #define OB_BOR_LEVEL1 ((uint32_t)0x08U) /*!< Supply voltage ranges from 2.10 to 2.40 V */
<> 144:ef7eb2e8f9f7 241 #define OB_BOR_OFF ((uint32_t)0x0CU) /*!< Supply voltage ranges from 1.62 to 2.10 V */
<> 144:ef7eb2e8f9f7 242 /**
<> 144:ef7eb2e8f9f7 243 * @}
<> 144:ef7eb2e8f9f7 244 */
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 #if defined (FLASH_OPTCR_nDBOOT)
<> 144:ef7eb2e8f9f7 247 /** @defgroup FLASHEx_Option_Bytes_nDBOOT FLASH Option Bytes nDBOOT
<> 144:ef7eb2e8f9f7 248 * @{
<> 144:ef7eb2e8f9f7 249 */
<> 144:ef7eb2e8f9f7 250 #define OB_DUAL_BOOT_DISABLE ((uint32_t)0x10000000U) /* !< Dual Boot disable. Boot according to boot address option */
<> 144:ef7eb2e8f9f7 251 #define OB_DUAL_BOOT_ENABLE ((uint32_t)0x00000000U) /* !< Dual Boot enable. Boot always from system memory if boot address in flash
<> 144:ef7eb2e8f9f7 252 (Dual bank Boot mode), or RAM if Boot address option in RAM */
<> 144:ef7eb2e8f9f7 253 /**
<> 144:ef7eb2e8f9f7 254 * @}
<> 144:ef7eb2e8f9f7 255 */
<> 144:ef7eb2e8f9f7 256 #endif /* FLASH_OPTCR_nDBOOT */
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 #if defined (FLASH_OPTCR_nDBANK)
<> 144:ef7eb2e8f9f7 259 /** @defgroup FLASHEx_Option_Bytes_nDBank FLASH Single Bank or Dual Bank
<> 144:ef7eb2e8f9f7 260 * @{
<> 144:ef7eb2e8f9f7 261 */
<> 144:ef7eb2e8f9f7 262 #define OB_NDBANK_SINGLE_BANK ((uint32_t)0x20000000U) /*!< NDBANK bit is set : Single Bank mode */
<> 144:ef7eb2e8f9f7 263 #define OB_NDBANK_DUAL_BANK ((uint32_t)0x00000000U) /*!< NDBANK bit is reset : Dual Bank mode */
<> 144:ef7eb2e8f9f7 264 /**
<> 144:ef7eb2e8f9f7 265 * @}
<> 144:ef7eb2e8f9f7 266 */
<> 144:ef7eb2e8f9f7 267 #endif /* FLASH_OPTCR_nDBANK */
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269 /** @defgroup FLASHEx_Boot_Address FLASH Boot Address
<> 144:ef7eb2e8f9f7 270 * @{
<> 144:ef7eb2e8f9f7 271 */
<> 144:ef7eb2e8f9f7 272 #define OB_BOOTADDR_ITCM_RAM ((uint32_t)0x0000U) /*!< Boot from ITCM RAM (0x00000000) */
<> 144:ef7eb2e8f9f7 273 #define OB_BOOTADDR_SYSTEM ((uint32_t)0x0040U) /*!< Boot from System memory bootloader (0x00100000) */
<> 144:ef7eb2e8f9f7 274 #define OB_BOOTADDR_ITCM_FLASH ((uint32_t)0x0080U) /*!< Boot from Flash on ITCM interface (0x00200000) */
<> 144:ef7eb2e8f9f7 275 #define OB_BOOTADDR_AXIM_FLASH ((uint32_t)0x2000U) /*!< Boot from Flash on AXIM interface (0x08000000) */
<> 144:ef7eb2e8f9f7 276 #define OB_BOOTADDR_DTCM_RAM ((uint32_t)0x8000U) /*!< Boot from DTCM RAM (0x20000000) */
<> 144:ef7eb2e8f9f7 277 #define OB_BOOTADDR_SRAM1 ((uint32_t)0x8004U) /*!< Boot from SRAM1 (0x20010000) */
<> 144:ef7eb2e8f9f7 278 #define OB_BOOTADDR_SRAM2 ((uint32_t)0x8013U) /*!< Boot from SRAM2 (0x2004C000) */
<> 144:ef7eb2e8f9f7 279 /**
<> 144:ef7eb2e8f9f7 280 * @}
<> 144:ef7eb2e8f9f7 281 */
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 /** @defgroup FLASH_Latency FLASH Latency
<> 144:ef7eb2e8f9f7 284 * @{
<> 144:ef7eb2e8f9f7 285 */
<> 144:ef7eb2e8f9f7 286 #define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */
<> 144:ef7eb2e8f9f7 287 #define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One Latency cycle */
<> 144:ef7eb2e8f9f7 288 #define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two Latency cycles */
<> 144:ef7eb2e8f9f7 289 #define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycles */
<> 144:ef7eb2e8f9f7 290 #define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four Latency cycles */
<> 144:ef7eb2e8f9f7 291 #define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five Latency cycles */
<> 144:ef7eb2e8f9f7 292 #define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */
<> 144:ef7eb2e8f9f7 293 #define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */
<> 144:ef7eb2e8f9f7 294 #define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight Latency cycles */
<> 144:ef7eb2e8f9f7 295 #define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine Latency cycles */
<> 144:ef7eb2e8f9f7 296 #define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten Latency cycles */
<> 144:ef7eb2e8f9f7 297 #define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven Latency cycles */
<> 144:ef7eb2e8f9f7 298 #define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve Latency cycles */
<> 144:ef7eb2e8f9f7 299 #define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen Latency cycles */
<> 144:ef7eb2e8f9f7 300 #define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen Latency cycles */
<> 144:ef7eb2e8f9f7 301 #define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen Latency cycles */
<> 144:ef7eb2e8f9f7 302 /**
<> 144:ef7eb2e8f9f7 303 * @}
<> 144:ef7eb2e8f9f7 304 */
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306 #if defined (FLASH_OPTCR_nDBANK)
<> 144:ef7eb2e8f9f7 307 /** @defgroup FLASHEx_Banks FLASH Banks
<> 144:ef7eb2e8f9f7 308 * @{
<> 144:ef7eb2e8f9f7 309 */
<> 144:ef7eb2e8f9f7 310 #define FLASH_BANK_1 ((uint32_t)0x01U) /*!< Bank 1 */
<> 144:ef7eb2e8f9f7 311 #define FLASH_BANK_2 ((uint32_t)0x02U) /*!< Bank 2 */
<> 144:ef7eb2e8f9f7 312 #define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2)) /*!< Bank1 and Bank2 */
<> 144:ef7eb2e8f9f7 313 /**
<> 144:ef7eb2e8f9f7 314 * @}
<> 144:ef7eb2e8f9f7 315 */
<> 144:ef7eb2e8f9f7 316 #endif /* FLASH_OPTCR_nDBANK */
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 /** @defgroup FLASHEx_MassErase_bit FLASH Mass Erase bit
<> 144:ef7eb2e8f9f7 319 * @{
<> 144:ef7eb2e8f9f7 320 */
<> 144:ef7eb2e8f9f7 321 #if defined (FLASH_OPTCR_nDBANK)
<> 144:ef7eb2e8f9f7 322 #define FLASH_MER_BIT (FLASH_CR_MER1 | FLASH_CR_MER2) /*!< 2 MER bits */
<> 144:ef7eb2e8f9f7 323 #else
<> 144:ef7eb2e8f9f7 324 #define FLASH_MER_BIT (FLASH_CR_MER) /*!< only 1 MER bit */
<> 144:ef7eb2e8f9f7 325 #endif /* FLASH_OPTCR_nDBANK */
<> 144:ef7eb2e8f9f7 326 /**
<> 144:ef7eb2e8f9f7 327 * @}
<> 144:ef7eb2e8f9f7 328 */
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 /** @defgroup FLASHEx_Sectors FLASH Sectors
<> 144:ef7eb2e8f9f7 331 * @{
<> 144:ef7eb2e8f9f7 332 */
<> 144:ef7eb2e8f9f7 333 #if (FLASH_SECTOR_TOTAL == 24)
<> 144:ef7eb2e8f9f7 334 #define FLASH_SECTOR_8 ((uint32_t)8U) /*!< Sector Number 8 */
<> 144:ef7eb2e8f9f7 335 #define FLASH_SECTOR_9 ((uint32_t)9U) /*!< Sector Number 9 */
<> 144:ef7eb2e8f9f7 336 #define FLASH_SECTOR_10 ((uint32_t)10U) /*!< Sector Number 10 */
<> 144:ef7eb2e8f9f7 337 #define FLASH_SECTOR_11 ((uint32_t)11U) /*!< Sector Number 11 */
<> 144:ef7eb2e8f9f7 338 #define FLASH_SECTOR_12 ((uint32_t)12U) /*!< Sector Number 12 */
<> 144:ef7eb2e8f9f7 339 #define FLASH_SECTOR_13 ((uint32_t)13U) /*!< Sector Number 13 */
<> 144:ef7eb2e8f9f7 340 #define FLASH_SECTOR_14 ((uint32_t)14U) /*!< Sector Number 14 */
<> 144:ef7eb2e8f9f7 341 #define FLASH_SECTOR_15 ((uint32_t)15U) /*!< Sector Number 15 */
<> 144:ef7eb2e8f9f7 342 #define FLASH_SECTOR_16 ((uint32_t)16U) /*!< Sector Number 16 */
<> 144:ef7eb2e8f9f7 343 #define FLASH_SECTOR_17 ((uint32_t)17U) /*!< Sector Number 17 */
<> 144:ef7eb2e8f9f7 344 #define FLASH_SECTOR_18 ((uint32_t)18U) /*!< Sector Number 18 */
<> 144:ef7eb2e8f9f7 345 #define FLASH_SECTOR_19 ((uint32_t)19U) /*!< Sector Number 19 */
<> 144:ef7eb2e8f9f7 346 #define FLASH_SECTOR_20 ((uint32_t)20U) /*!< Sector Number 20 */
<> 144:ef7eb2e8f9f7 347 #define FLASH_SECTOR_21 ((uint32_t)21U) /*!< Sector Number 21 */
<> 144:ef7eb2e8f9f7 348 #define FLASH_SECTOR_22 ((uint32_t)22U) /*!< Sector Number 22 */
<> 144:ef7eb2e8f9f7 349 #define FLASH_SECTOR_23 ((uint32_t)23U) /*!< Sector Number 23 */
<> 144:ef7eb2e8f9f7 350 #endif /* FLASH_SECTOR_TOTAL == 24 */
<> 144:ef7eb2e8f9f7 351 /**
<> 144:ef7eb2e8f9f7 352 * @}
<> 144:ef7eb2e8f9f7 353 */
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 #if (FLASH_SECTOR_TOTAL == 24)
<> 144:ef7eb2e8f9f7 356 /** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
<> 144:ef7eb2e8f9f7 357 * @note For Single Bank mode, use OB_WRP_SECTOR_x defines: In fact, in FLASH_OPTCR register,
<> 144:ef7eb2e8f9f7 358 * nWRP[11:0] bits contain the value of the write-protection option bytes for sectors 0 to 11.
<> 144:ef7eb2e8f9f7 359 * For Dual Bank mode, use OB_WRP_DB_SECTOR_x defines: In fact, in FLASH_OPTCR register,
<> 144:ef7eb2e8f9f7 360 * nWRP[11:0] bits are divided on two groups, one group dedicated for bank 1 and
<> 144:ef7eb2e8f9f7 361 * a second one dedicated for bank 2 (nWRP[i] activates Write protection on sector 2*i and 2*i+1).
<> 144:ef7eb2e8f9f7 362 * This behavior is applicable only for STM32F76xxx / STM32F77xxx devices.
<> 144:ef7eb2e8f9f7 363 * @{
<> 144:ef7eb2e8f9f7 364 */
<> 144:ef7eb2e8f9f7 365 /* Single Bank Sectors */
<> 144:ef7eb2e8f9f7 366 #define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Single Bank Sector0 */
<> 144:ef7eb2e8f9f7 367 #define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Single Bank Sector1 */
<> 144:ef7eb2e8f9f7 368 #define OB_WRP_SECTOR_2 ((uint32_t)0x00040000U) /*!< Write protection of Single Bank Sector2 */
<> 144:ef7eb2e8f9f7 369 #define OB_WRP_SECTOR_3 ((uint32_t)0x00080000U) /*!< Write protection of Single Bank Sector3 */
<> 144:ef7eb2e8f9f7 370 #define OB_WRP_SECTOR_4 ((uint32_t)0x00100000U) /*!< Write protection of Single Bank Sector4 */
<> 144:ef7eb2e8f9f7 371 #define OB_WRP_SECTOR_5 ((uint32_t)0x00200000U) /*!< Write protection of Single Bank Sector5 */
<> 144:ef7eb2e8f9f7 372 #define OB_WRP_SECTOR_6 ((uint32_t)0x00400000U) /*!< Write protection of Single Bank Sector6 */
<> 144:ef7eb2e8f9f7 373 #define OB_WRP_SECTOR_7 ((uint32_t)0x00800000U) /*!< Write protection of Single Bank Sector7 */
<> 144:ef7eb2e8f9f7 374 #define OB_WRP_SECTOR_8 ((uint32_t)0x01000000U) /*!< Write protection of Single Bank Sector8 */
<> 144:ef7eb2e8f9f7 375 #define OB_WRP_SECTOR_9 ((uint32_t)0x02000000U) /*!< Write protection of Single Bank Sector9 */
<> 144:ef7eb2e8f9f7 376 #define OB_WRP_SECTOR_10 ((uint32_t)0x04000000U) /*!< Write protection of Single Bank Sector10 */
<> 144:ef7eb2e8f9f7 377 #define OB_WRP_SECTOR_11 ((uint32_t)0x08000000U) /*!< Write protection of Single Bank Sector11 */
<> 144:ef7eb2e8f9f7 378 #define OB_WRP_SECTOR_All ((uint32_t)0x0FFF0000U) /*!< Write protection of all Sectors for Single Bank Flash */
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 /* Dual Bank Sectors */
<> 144:ef7eb2e8f9f7 381 #define OB_WRP_DB_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Dual Bank Sector0 */
<> 144:ef7eb2e8f9f7 382 #define OB_WRP_DB_SECTOR_1 ((uint32_t)0x00010000U) /*!< Write protection of Dual Bank Sector1 */
<> 144:ef7eb2e8f9f7 383 #define OB_WRP_DB_SECTOR_2 ((uint32_t)0x00020000U) /*!< Write protection of Dual Bank Sector2 */
<> 144:ef7eb2e8f9f7 384 #define OB_WRP_DB_SECTOR_3 ((uint32_t)0x00020000U) /*!< Write protection of Dual Bank Sector3 */
<> 144:ef7eb2e8f9f7 385 #define OB_WRP_DB_SECTOR_4 ((uint32_t)0x00040000U) /*!< Write protection of Dual Bank Sector4 */
<> 144:ef7eb2e8f9f7 386 #define OB_WRP_DB_SECTOR_5 ((uint32_t)0x00040000U) /*!< Write protection of Dual Bank Sector5 */
<> 144:ef7eb2e8f9f7 387 #define OB_WRP_DB_SECTOR_6 ((uint32_t)0x00080000U) /*!< Write protection of Dual Bank Sector6 */
<> 144:ef7eb2e8f9f7 388 #define OB_WRP_DB_SECTOR_7 ((uint32_t)0x00080000U) /*!< Write protection of Dual Bank Sector7 */
<> 144:ef7eb2e8f9f7 389 #define OB_WRP_DB_SECTOR_8 ((uint32_t)0x00100000U) /*!< Write protection of Dual Bank Sector8 */
<> 144:ef7eb2e8f9f7 390 #define OB_WRP_DB_SECTOR_9 ((uint32_t)0x00100000U) /*!< Write protection of Dual Bank Sector9 */
<> 144:ef7eb2e8f9f7 391 #define OB_WRP_DB_SECTOR_10 ((uint32_t)0x00200000U) /*!< Write protection of Dual Bank Sector10 */
<> 144:ef7eb2e8f9f7 392 #define OB_WRP_DB_SECTOR_11 ((uint32_t)0x00200000U) /*!< Write protection of Dual Bank Sector11 */
<> 144:ef7eb2e8f9f7 393 #define OB_WRP_DB_SECTOR_12 ((uint32_t)0x00400000U) /*!< Write protection of Dual Bank Sector12 */
<> 144:ef7eb2e8f9f7 394 #define OB_WRP_DB_SECTOR_13 ((uint32_t)0x00400000U) /*!< Write protection of Dual Bank Sector13 */
<> 144:ef7eb2e8f9f7 395 #define OB_WRP_DB_SECTOR_14 ((uint32_t)0x00800000U) /*!< Write protection of Dual Bank Sector14 */
<> 144:ef7eb2e8f9f7 396 #define OB_WRP_DB_SECTOR_15 ((uint32_t)0x00800000U) /*!< Write protection of Dual Bank Sector15 */
<> 144:ef7eb2e8f9f7 397 #define OB_WRP_DB_SECTOR_16 ((uint32_t)0x01000000U) /*!< Write protection of Dual Bank Sector16 */
<> 144:ef7eb2e8f9f7 398 #define OB_WRP_DB_SECTOR_17 ((uint32_t)0x01000000U) /*!< Write protection of Dual Bank Sector17 */
<> 144:ef7eb2e8f9f7 399 #define OB_WRP_DB_SECTOR_18 ((uint32_t)0x02000000U) /*!< Write protection of Dual Bank Sector18 */
<> 144:ef7eb2e8f9f7 400 #define OB_WRP_DB_SECTOR_19 ((uint32_t)0x02000000U) /*!< Write protection of Dual Bank Sector19 */
<> 144:ef7eb2e8f9f7 401 #define OB_WRP_DB_SECTOR_20 ((uint32_t)0x04000000U) /*!< Write protection of Dual Bank Sector20 */
<> 144:ef7eb2e8f9f7 402 #define OB_WRP_DB_SECTOR_21 ((uint32_t)0x04000000U) /*!< Write protection of Dual Bank Sector21 */
<> 144:ef7eb2e8f9f7 403 #define OB_WRP_DB_SECTOR_22 ((uint32_t)0x08000000U) /*!< Write protection of Dual Bank Sector22 */
<> 144:ef7eb2e8f9f7 404 #define OB_WRP_DB_SECTOR_23 ((uint32_t)0x08000000U) /*!< Write protection of Dual Bank Sector23 */
<> 144:ef7eb2e8f9f7 405 #define OB_WRP_DB_SECTOR_All ((uint32_t)0x0FFF0000U) /*!< Write protection of all Sectors for Dual Bank Flash */
<> 144:ef7eb2e8f9f7 406 /**
<> 144:ef7eb2e8f9f7 407 * @}
<> 144:ef7eb2e8f9f7 408 */
<> 144:ef7eb2e8f9f7 409 #endif /* FLASH_SECTOR_TOTAL == 24 */
<> 144:ef7eb2e8f9f7 410
<> 144:ef7eb2e8f9f7 411 #if (FLASH_SECTOR_TOTAL == 8)
<> 144:ef7eb2e8f9f7 412 /** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
<> 144:ef7eb2e8f9f7 413 * @{
<> 144:ef7eb2e8f9f7 414 */
<> 144:ef7eb2e8f9f7 415 #define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Sector0 */
<> 144:ef7eb2e8f9f7 416 #define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Sector1 */
<> 144:ef7eb2e8f9f7 417 #define OB_WRP_SECTOR_2 ((uint32_t)0x00040000U) /*!< Write protection of Sector2 */
<> 144:ef7eb2e8f9f7 418 #define OB_WRP_SECTOR_3 ((uint32_t)0x00080000U) /*!< Write protection of Sector3 */
<> 144:ef7eb2e8f9f7 419 #define OB_WRP_SECTOR_4 ((uint32_t)0x00100000U) /*!< Write protection of Sector4 */
<> 144:ef7eb2e8f9f7 420 #define OB_WRP_SECTOR_5 ((uint32_t)0x00200000U) /*!< Write protection of Sector5 */
<> 144:ef7eb2e8f9f7 421 #define OB_WRP_SECTOR_6 ((uint32_t)0x00400000U) /*!< Write protection of Sector6 */
<> 144:ef7eb2e8f9f7 422 #define OB_WRP_SECTOR_7 ((uint32_t)0x00800000U) /*!< Write protection of Sector7 */
<> 144:ef7eb2e8f9f7 423 #define OB_WRP_SECTOR_All ((uint32_t)0x00FF0000U) /*!< Write protection of all Sectors */
<> 144:ef7eb2e8f9f7 424 /**
<> 144:ef7eb2e8f9f7 425 * @}
<> 144:ef7eb2e8f9f7 426 */
<> 144:ef7eb2e8f9f7 427 #endif /* FLASH_SECTOR_TOTAL == 8 */
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 /**
<> 144:ef7eb2e8f9f7 430 * @}
<> 144:ef7eb2e8f9f7 431 */
<> 144:ef7eb2e8f9f7 432
<> 144:ef7eb2e8f9f7 433 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 434 /** @defgroup FLASH_Exported_Macros FLASH Exported Macros
<> 144:ef7eb2e8f9f7 435 * @{
<> 144:ef7eb2e8f9f7 436 */
<> 144:ef7eb2e8f9f7 437 /**
<> 144:ef7eb2e8f9f7 438 * @brief Calculate the FLASH Boot Base Adress (BOOT_ADD0 or BOOT_ADD1)
<> 144:ef7eb2e8f9f7 439 * @note Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14].
<> 144:ef7eb2e8f9f7 440 * @param __ADDRESS__: FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB)
<> 144:ef7eb2e8f9f7 441 * @retval The FLASH Boot Base Adress
<> 144:ef7eb2e8f9f7 442 */
<> 144:ef7eb2e8f9f7 443 #define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14)
<> 144:ef7eb2e8f9f7 444 /**
<> 144:ef7eb2e8f9f7 445 * @}
<> 144:ef7eb2e8f9f7 446 */
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 449 /** @addtogroup FLASHEx_Exported_Functions
<> 144:ef7eb2e8f9f7 450 * @{
<> 144:ef7eb2e8f9f7 451 */
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 /** @addtogroup FLASHEx_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 454 * @{
<> 144:ef7eb2e8f9f7 455 */
<> 144:ef7eb2e8f9f7 456 /* Extension Program operation functions *************************************/
<> 144:ef7eb2e8f9f7 457 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError);
<> 144:ef7eb2e8f9f7 458 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
<> 144:ef7eb2e8f9f7 459 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
<> 144:ef7eb2e8f9f7 460 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462 /**
<> 144:ef7eb2e8f9f7 463 * @}
<> 144:ef7eb2e8f9f7 464 */
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 /**
<> 144:ef7eb2e8f9f7 467 * @}
<> 144:ef7eb2e8f9f7 468 */
<> 144:ef7eb2e8f9f7 469 /* Private types -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 470 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 471 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 472 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 473 /** @defgroup FLASHEx_Private_Macros FLASH Private Macros
<> 144:ef7eb2e8f9f7 474 * @{
<> 144:ef7eb2e8f9f7 475 */
<> 144:ef7eb2e8f9f7 476
<> 144:ef7eb2e8f9f7 477 /** @defgroup FLASHEx_IS_FLASH_Definitions FLASH Private macros to check input parameters
<> 144:ef7eb2e8f9f7 478 * @{
<> 144:ef7eb2e8f9f7 479 */
<> 144:ef7eb2e8f9f7 480
<> 144:ef7eb2e8f9f7 481 #define IS_FLASH_TYPEERASE(VALUE)(((VALUE) == FLASH_TYPEERASE_SECTORS) || \
<> 144:ef7eb2e8f9f7 482 ((VALUE) == FLASH_TYPEERASE_MASSERASE))
<> 144:ef7eb2e8f9f7 483
<> 144:ef7eb2e8f9f7 484 #define IS_VOLTAGERANGE(RANGE)(((RANGE) == FLASH_VOLTAGE_RANGE_1) || \
<> 144:ef7eb2e8f9f7 485 ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \
<> 144:ef7eb2e8f9f7 486 ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \
<> 144:ef7eb2e8f9f7 487 ((RANGE) == FLASH_VOLTAGE_RANGE_4))
<> 144:ef7eb2e8f9f7 488
<> 144:ef7eb2e8f9f7 489 #define IS_WRPSTATE(VALUE)(((VALUE) == OB_WRPSTATE_DISABLE) || \
<> 144:ef7eb2e8f9f7 490 ((VALUE) == OB_WRPSTATE_ENABLE))
<> 144:ef7eb2e8f9f7 491
<> 144:ef7eb2e8f9f7 492 #define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
<> 144:ef7eb2e8f9f7 493 OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1)))
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495 #define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013)
<> 144:ef7eb2e8f9f7 496
<> 144:ef7eb2e8f9f7 497 #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
<> 144:ef7eb2e8f9f7 498 ((LEVEL) == OB_RDP_LEVEL_1) ||\
<> 144:ef7eb2e8f9f7 499 ((LEVEL) == OB_RDP_LEVEL_2))
<> 144:ef7eb2e8f9f7 500
<> 144:ef7eb2e8f9f7 501 #define IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW))
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
<> 144:ef7eb2e8f9f7 504
<> 144:ef7eb2e8f9f7 505 #define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
<> 144:ef7eb2e8f9f7 506
<> 144:ef7eb2e8f9f7 507 #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
<> 144:ef7eb2e8f9f7 508
<> 144:ef7eb2e8f9f7 509 #define IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE))
<> 144:ef7eb2e8f9f7 510
<> 144:ef7eb2e8f9f7 511 #define IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE))
<> 144:ef7eb2e8f9f7 512
<> 144:ef7eb2e8f9f7 513 #define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\
<> 144:ef7eb2e8f9f7 514 ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))
<> 144:ef7eb2e8f9f7 515
<> 144:ef7eb2e8f9f7 516 #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
<> 144:ef7eb2e8f9f7 517 ((LATENCY) == FLASH_LATENCY_1) || \
<> 144:ef7eb2e8f9f7 518 ((LATENCY) == FLASH_LATENCY_2) || \
<> 144:ef7eb2e8f9f7 519 ((LATENCY) == FLASH_LATENCY_3) || \
<> 144:ef7eb2e8f9f7 520 ((LATENCY) == FLASH_LATENCY_4) || \
<> 144:ef7eb2e8f9f7 521 ((LATENCY) == FLASH_LATENCY_5) || \
<> 144:ef7eb2e8f9f7 522 ((LATENCY) == FLASH_LATENCY_6) || \
<> 144:ef7eb2e8f9f7 523 ((LATENCY) == FLASH_LATENCY_7) || \
<> 144:ef7eb2e8f9f7 524 ((LATENCY) == FLASH_LATENCY_8) || \
<> 144:ef7eb2e8f9f7 525 ((LATENCY) == FLASH_LATENCY_9) || \
<> 144:ef7eb2e8f9f7 526 ((LATENCY) == FLASH_LATENCY_10) || \
<> 144:ef7eb2e8f9f7 527 ((LATENCY) == FLASH_LATENCY_11) || \
<> 144:ef7eb2e8f9f7 528 ((LATENCY) == FLASH_LATENCY_12) || \
<> 144:ef7eb2e8f9f7 529 ((LATENCY) == FLASH_LATENCY_13) || \
<> 144:ef7eb2e8f9f7 530 ((LATENCY) == FLASH_LATENCY_14) || \
<> 144:ef7eb2e8f9f7 531 ((LATENCY) == FLASH_LATENCY_15))
<> 144:ef7eb2e8f9f7 532
<> 144:ef7eb2e8f9f7 533 #define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END))
<> 144:ef7eb2e8f9f7 534
<> 144:ef7eb2e8f9f7 535 #define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0U) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
<> 144:ef7eb2e8f9f7 536
<> 144:ef7eb2e8f9f7 537 #if (FLASH_SECTOR_TOTAL == 8)
<> 144:ef7eb2e8f9f7 538 #define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
<> 144:ef7eb2e8f9f7 539 ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
<> 144:ef7eb2e8f9f7 540 ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\
<> 144:ef7eb2e8f9f7 541 ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7))
<> 144:ef7eb2e8f9f7 542
<> 144:ef7eb2e8f9f7 543 #define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & (uint32_t)0xFF00FFFF) == 0x00000000U) && ((SECTOR) != 0x00000000U))
<> 144:ef7eb2e8f9f7 544 #endif /* FLASH_SECTOR_TOTAL == 8 */
<> 144:ef7eb2e8f9f7 545
<> 144:ef7eb2e8f9f7 546 #if (FLASH_SECTOR_TOTAL == 24)
<> 144:ef7eb2e8f9f7 547 #define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
<> 144:ef7eb2e8f9f7 548 ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
<> 144:ef7eb2e8f9f7 549 ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\
<> 144:ef7eb2e8f9f7 550 ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7) ||\
<> 144:ef7eb2e8f9f7 551 ((SECTOR) == FLASH_SECTOR_8) || ((SECTOR) == FLASH_SECTOR_9) ||\
<> 144:ef7eb2e8f9f7 552 ((SECTOR) == FLASH_SECTOR_10) || ((SECTOR) == FLASH_SECTOR_11) ||\
<> 144:ef7eb2e8f9f7 553 ((SECTOR) == FLASH_SECTOR_12) || ((SECTOR) == FLASH_SECTOR_13) ||\
<> 144:ef7eb2e8f9f7 554 ((SECTOR) == FLASH_SECTOR_14) || ((SECTOR) == FLASH_SECTOR_15) ||\
<> 144:ef7eb2e8f9f7 555 ((SECTOR) == FLASH_SECTOR_16) || ((SECTOR) == FLASH_SECTOR_17) ||\
<> 144:ef7eb2e8f9f7 556 ((SECTOR) == FLASH_SECTOR_18) || ((SECTOR) == FLASH_SECTOR_19) ||\
<> 144:ef7eb2e8f9f7 557 ((SECTOR) == FLASH_SECTOR_20) || ((SECTOR) == FLASH_SECTOR_21) ||\
<> 144:ef7eb2e8f9f7 558 ((SECTOR) == FLASH_SECTOR_22) || ((SECTOR) == FLASH_SECTOR_23))
<> 144:ef7eb2e8f9f7 559
<> 144:ef7eb2e8f9f7 560 #define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & (uint32_t)0xF000FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U))
<> 144:ef7eb2e8f9f7 561 #endif /* FLASH_SECTOR_TOTAL == 24 */
<> 144:ef7eb2e8f9f7 562
<> 144:ef7eb2e8f9f7 563 #if defined (FLASH_OPTCR_nDBANK)
<> 144:ef7eb2e8f9f7 564 #define IS_OB_NDBANK(VALUE) (((VALUE) == OB_NDBANK_SINGLE_BANK) || \
<> 144:ef7eb2e8f9f7 565 ((VALUE) == OB_NDBANK_DUAL_BANK))
<> 144:ef7eb2e8f9f7 566
<> 144:ef7eb2e8f9f7 567 #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \
<> 144:ef7eb2e8f9f7 568 ((BANK) == FLASH_BANK_2) || \
<> 144:ef7eb2e8f9f7 569 ((BANK) == FLASH_BANK_BOTH))
<> 144:ef7eb2e8f9f7 570 #endif /* FLASH_OPTCR_nDBANK */
<> 144:ef7eb2e8f9f7 571
<> 144:ef7eb2e8f9f7 572 #if defined (FLASH_OPTCR_nDBOOT)
<> 144:ef7eb2e8f9f7 573 #define IS_OB_NDBOOT(VALUE) (((VALUE) == OB_DUAL_BOOT_DISABLE) || \
<> 144:ef7eb2e8f9f7 574 ((VALUE) == OB_DUAL_BOOT_ENABLE))
<> 144:ef7eb2e8f9f7 575 #endif /* FLASH_OPTCR_nDBOOT */
<> 144:ef7eb2e8f9f7 576
<> 144:ef7eb2e8f9f7 577 /**
<> 144:ef7eb2e8f9f7 578 * @}
<> 144:ef7eb2e8f9f7 579 */
<> 144:ef7eb2e8f9f7 580
<> 144:ef7eb2e8f9f7 581 /**
<> 144:ef7eb2e8f9f7 582 * @}
<> 144:ef7eb2e8f9f7 583 */
<> 144:ef7eb2e8f9f7 584
<> 144:ef7eb2e8f9f7 585 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 586 /** @defgroup FLASHEx_Private_Functions FLASH Private Functions
<> 144:ef7eb2e8f9f7 587 * @{
<> 144:ef7eb2e8f9f7 588 */
<> 144:ef7eb2e8f9f7 589 void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange);
<> 144:ef7eb2e8f9f7 590 /**
<> 144:ef7eb2e8f9f7 591 * @}
<> 144:ef7eb2e8f9f7 592 */
<> 144:ef7eb2e8f9f7 593
<> 144:ef7eb2e8f9f7 594 /**
<> 144:ef7eb2e8f9f7 595 * @}
<> 144:ef7eb2e8f9f7 596 */
<> 144:ef7eb2e8f9f7 597
<> 144:ef7eb2e8f9f7 598 /**
<> 144:ef7eb2e8f9f7 599 * @}
<> 144:ef7eb2e8f9f7 600 */
<> 144:ef7eb2e8f9f7 601
<> 144:ef7eb2e8f9f7 602 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 603 }
<> 144:ef7eb2e8f9f7 604 #endif
<> 144:ef7eb2e8f9f7 605
<> 144:ef7eb2e8f9f7 606 #endif /* __STM32F7xx_HAL_FLASH_EX_H */
<> 144:ef7eb2e8f9f7 607
<> 144:ef7eb2e8f9f7 608 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/