Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

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targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma2d.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
83:a036322b8637 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f7xx_hal_dma2d.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.0
<> 144:ef7eb2e8f9f7 6 * @date 22-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of DMA2D HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F7xx_HAL_DMA2D_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F7xx_HAL_DMA2D_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f7xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F7xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup DMA2D DMA2D
<> 144:ef7eb2e8f9f7 54 * @brief DMA2D HAL module driver
<> 144:ef7eb2e8f9f7 55 * @{
<> 144:ef7eb2e8f9f7 56 */
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 59 /** @defgroup DMA2D_Exported_Types DMA2D Exported Types
<> 144:ef7eb2e8f9f7 60 * @{
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62 #define MAX_DMA2D_LAYER 2
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 /**
<> 144:ef7eb2e8f9f7 65 * @brief DMA2D color Structure definition
<> 144:ef7eb2e8f9f7 66 */
<> 144:ef7eb2e8f9f7 67 typedef struct
<> 144:ef7eb2e8f9f7 68 {
<> 144:ef7eb2e8f9f7 69 uint32_t Blue; /*!< Configures the blue value.
<> 144:ef7eb2e8f9f7 70 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 uint32_t Green; /*!< Configures the green value.
<> 144:ef7eb2e8f9f7 73 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 uint32_t Red; /*!< Configures the red value.
<> 144:ef7eb2e8f9f7 76 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
<> 144:ef7eb2e8f9f7 77 } DMA2D_ColorTypeDef;
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 /**
<> 144:ef7eb2e8f9f7 80 * @brief DMA2D CLUT Structure definition
<> 144:ef7eb2e8f9f7 81 */
<> 144:ef7eb2e8f9f7 82 typedef struct
<> 144:ef7eb2e8f9f7 83 {
<> 144:ef7eb2e8f9f7 84 uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 uint32_t CLUTColorMode; /*!< Configures the DMA2D CLUT color mode.
<> 144:ef7eb2e8f9f7 87 This parameter can be one value of @ref DMA2D_CLUT_CM. */
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 uint32_t Size; /*!< Configures the DMA2D CLUT size.
<> 144:ef7eb2e8f9f7 90 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/
<> 144:ef7eb2e8f9f7 91 } DMA2D_CLUTCfgTypeDef;
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 /**
<> 144:ef7eb2e8f9f7 94 * @brief DMA2D Init structure definition
<> 144:ef7eb2e8f9f7 95 */
<> 144:ef7eb2e8f9f7 96 typedef struct
<> 144:ef7eb2e8f9f7 97 {
<> 144:ef7eb2e8f9f7 98 uint32_t Mode; /*!< Configures the DMA2D transfer mode.
<> 144:ef7eb2e8f9f7 99 This parameter can be one value of @ref DMA2D_Mode. */
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 uint32_t ColorMode; /*!< Configures the color format of the output image.
<> 144:ef7eb2e8f9f7 102 This parameter can be one value of @ref DMA2D_Output_Color_Mode. */
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 uint32_t OutputOffset; /*!< Specifies the Offset value.
<> 144:ef7eb2e8f9f7 105 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
<> 144:ef7eb2e8f9f7 106 #if defined (DMA2D_OPFCCR_AI)
<> 144:ef7eb2e8f9f7 107 uint32_t AlphaInverted; /*!< Select regular or inverted alpha value for the output pixel format converter.
<> 144:ef7eb2e8f9f7 108 This parameter can be one value of @ref DMA2D_Alpha_Inverted. */
<> 144:ef7eb2e8f9f7 109 #endif /* DMA2D_OPFCCR_AI */
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 #if defined (DMA2D_OPFCCR_RBS)
<> 144:ef7eb2e8f9f7 112 uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR)
<> 144:ef7eb2e8f9f7 113 for the output pixel format converter.
<> 144:ef7eb2e8f9f7 114 This parameter can be one value of @ref DMA2D_RB_Swap. */
<> 144:ef7eb2e8f9f7 115 #endif /* DMA2D_OPFCCR_RBS */
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 } DMA2D_InitTypeDef;
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 /**
<> 144:ef7eb2e8f9f7 121 * @brief DMA2D Layer structure definition
<> 144:ef7eb2e8f9f7 122 */
<> 144:ef7eb2e8f9f7 123 typedef struct
<> 144:ef7eb2e8f9f7 124 {
<> 144:ef7eb2e8f9f7 125 uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset.
<> 144:ef7eb2e8f9f7 126 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode.
<> 144:ef7eb2e8f9f7 129 This parameter can be one value of @ref DMA2D_Input_Color_Mode. */
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode.
<> 144:ef7eb2e8f9f7 132 This parameter can be one value of @ref DMA2D_Alpha_Mode. */
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value in case of A8 or A4 color mode.
<> 144:ef7eb2e8f9f7 135 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF except for the color modes detailed below.
<> 144:ef7eb2e8f9f7 136 @note In case of A8 or A4 color mode (ARGB), this parameter must be a number between
<> 144:ef7eb2e8f9f7 137 Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where
<> 144:ef7eb2e8f9f7 138 - InputAlpha[24:31] is the alpha value ALPHA[0:7]
<> 144:ef7eb2e8f9f7 139 - InputAlpha[16:23] is the red value RED[0:7]
<> 144:ef7eb2e8f9f7 140 - InputAlpha[8:15] is the green value GREEN[0:7]
<> 144:ef7eb2e8f9f7 141 - InputAlpha[0:7] is the blue value BLUE[0:7]. */
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 #if defined (DMA2D_FGPFCCR_AI) && defined (DMA2D_BGPFCCR_AI)
<> 144:ef7eb2e8f9f7 144 uint32_t AlphaInverted; /*!< Select regular or inverted alpha value.
<> 144:ef7eb2e8f9f7 145 This parameter can be one value of @ref DMA2D_Alpha_Inverted.
<> 144:ef7eb2e8f9f7 146 This feature is only available on devices :
<> 144:ef7eb2e8f9f7 147 STM32F756xx, STM32F767xx, STM32F769xx, STM32F777xx and STM32F779xx.*/
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 #endif /* (DMA2D_FGPFCCR_AI) && (DMA2D_BGPFCCR_AI) */
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 #if defined (DMA2D_FGPFCCR_RBS) && defined (DMA2D_BGPFCCR_RBS)
<> 144:ef7eb2e8f9f7 152 uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR).
<> 144:ef7eb2e8f9f7 153 This parameter can be one value of @ref DMA2D_RB_Swap
<> 144:ef7eb2e8f9f7 154 This feature is only available on devices :
<> 144:ef7eb2e8f9f7 155 STM32F756xx, STM32F767xx, STM32F769xx, STM32F777xx and STM32F779xx.*/
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 #endif /* (DMA2D_FGPFCCR_RBS) && (DMA2D_BGPFCCR_RBS) */
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 } DMA2D_LayerCfgTypeDef;
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 /**
<> 144:ef7eb2e8f9f7 162 * @brief HAL DMA2D State structures definition
<> 144:ef7eb2e8f9f7 163 */
<> 144:ef7eb2e8f9f7 164 typedef enum
<> 144:ef7eb2e8f9f7 165 {
<> 144:ef7eb2e8f9f7 166 HAL_DMA2D_STATE_RESET = 0x00U, /*!< DMA2D not yet initialized or disabled */
<> 144:ef7eb2e8f9f7 167 HAL_DMA2D_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
<> 144:ef7eb2e8f9f7 168 HAL_DMA2D_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
<> 144:ef7eb2e8f9f7 169 HAL_DMA2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
<> 144:ef7eb2e8f9f7 170 HAL_DMA2D_STATE_ERROR = 0x04U, /*!< DMA2D state error */
<> 144:ef7eb2e8f9f7 171 HAL_DMA2D_STATE_SUSPEND = 0x05U /*!< DMA2D process is suspended */
<> 144:ef7eb2e8f9f7 172 }HAL_DMA2D_StateTypeDef;
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 /**
<> 144:ef7eb2e8f9f7 175 * @brief DMA2D handle Structure definition
<> 144:ef7eb2e8f9f7 176 */
<> 144:ef7eb2e8f9f7 177 typedef struct __DMA2D_HandleTypeDef
<> 144:ef7eb2e8f9f7 178 {
<> 144:ef7eb2e8f9f7 179 DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer complete callback. */
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback. */
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 HAL_LockTypeDef Lock; /*!< DMA2D lock. */
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 __IO uint32_t ErrorCode; /*!< DMA2D error code. */
<> 144:ef7eb2e8f9f7 194 } DMA2D_HandleTypeDef;
<> 144:ef7eb2e8f9f7 195 /**
<> 144:ef7eb2e8f9f7 196 * @}
<> 144:ef7eb2e8f9f7 197 */
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 200 /** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants
<> 144:ef7eb2e8f9f7 201 * @{
<> 144:ef7eb2e8f9f7 202 */
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 /** @defgroup DMA2D_Error_Code DMA2D Error Code
<> 144:ef7eb2e8f9f7 205 * @{
<> 144:ef7eb2e8f9f7 206 */
<> 144:ef7eb2e8f9f7 207 #define HAL_DMA2D_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
<> 144:ef7eb2e8f9f7 208 #define HAL_DMA2D_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */
<> 144:ef7eb2e8f9f7 209 #define HAL_DMA2D_ERROR_CE ((uint32_t)0x00000002U) /*!< Configuration error */
<> 144:ef7eb2e8f9f7 210 #define HAL_DMA2D_ERROR_CAE ((uint32_t)0x00000004U) /*!< CLUT access error */
<> 144:ef7eb2e8f9f7 211 #define HAL_DMA2D_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */
<> 144:ef7eb2e8f9f7 212 /**
<> 144:ef7eb2e8f9f7 213 * @}
<> 144:ef7eb2e8f9f7 214 */
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 /** @defgroup DMA2D_Mode DMA2D Mode
<> 144:ef7eb2e8f9f7 217 * @{
<> 144:ef7eb2e8f9f7 218 */
<> 144:ef7eb2e8f9f7 219 #define DMA2D_M2M ((uint32_t)0x00000000U) /*!< DMA2D memory to memory transfer mode */
<> 144:ef7eb2e8f9f7 220 #define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */
<> 144:ef7eb2e8f9f7 221 #define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */
<> 144:ef7eb2e8f9f7 222 #define DMA2D_R2M DMA2D_CR_MODE /*!< DMA2D register to memory transfer mode */
<> 144:ef7eb2e8f9f7 223 /**
<> 144:ef7eb2e8f9f7 224 * @}
<> 144:ef7eb2e8f9f7 225 */
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 /** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode
<> 144:ef7eb2e8f9f7 228 * @{
<> 144:ef7eb2e8f9f7 229 */
<> 144:ef7eb2e8f9f7 230 #define DMA2D_OUTPUT_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 DMA2D color mode */
<> 144:ef7eb2e8f9f7 231 #define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 DMA2D color mode */
<> 144:ef7eb2e8f9f7 232 #define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 DMA2D color mode */
<> 144:ef7eb2e8f9f7 233 #define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */
<> 144:ef7eb2e8f9f7 234 #define DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 DMA2D color mode */
<> 144:ef7eb2e8f9f7 235 /**
<> 144:ef7eb2e8f9f7 236 * @}
<> 144:ef7eb2e8f9f7 237 */
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 /** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode
<> 144:ef7eb2e8f9f7 240 * @{
<> 144:ef7eb2e8f9f7 241 */
<> 144:ef7eb2e8f9f7 242 #define DMA2D_INPUT_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 color mode */
<> 144:ef7eb2e8f9f7 243 #define DMA2D_INPUT_RGB888 ((uint32_t)0x00000001U) /*!< RGB888 color mode */
<> 144:ef7eb2e8f9f7 244 #define DMA2D_INPUT_RGB565 ((uint32_t)0x00000002U) /*!< RGB565 color mode */
<> 144:ef7eb2e8f9f7 245 #define DMA2D_INPUT_ARGB1555 ((uint32_t)0x00000003U) /*!< ARGB1555 color mode */
<> 144:ef7eb2e8f9f7 246 #define DMA2D_INPUT_ARGB4444 ((uint32_t)0x00000004U) /*!< ARGB4444 color mode */
<> 144:ef7eb2e8f9f7 247 #define DMA2D_INPUT_L8 ((uint32_t)0x00000005U) /*!< L8 color mode */
<> 144:ef7eb2e8f9f7 248 #define DMA2D_INPUT_AL44 ((uint32_t)0x00000006U) /*!< AL44 color mode */
<> 144:ef7eb2e8f9f7 249 #define DMA2D_INPUT_AL88 ((uint32_t)0x00000007U) /*!< AL88 color mode */
<> 144:ef7eb2e8f9f7 250 #define DMA2D_INPUT_L4 ((uint32_t)0x00000008U) /*!< L4 color mode */
<> 144:ef7eb2e8f9f7 251 #define DMA2D_INPUT_A8 ((uint32_t)0x00000009U) /*!< A8 color mode */
<> 144:ef7eb2e8f9f7 252 #define DMA2D_INPUT_A4 ((uint32_t)0x0000000AU) /*!< A4 color mode */
<> 144:ef7eb2e8f9f7 253 /**
<> 144:ef7eb2e8f9f7 254 * @}
<> 144:ef7eb2e8f9f7 255 */
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 /** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode
<> 144:ef7eb2e8f9f7 258 * @{
<> 144:ef7eb2e8f9f7 259 */
<> 144:ef7eb2e8f9f7 260 #define DMA2D_NO_MODIF_ALPHA ((uint32_t)0x00000000U) /*!< No modification of the alpha channel value */
<> 144:ef7eb2e8f9f7 261 #define DMA2D_REPLACE_ALPHA ((uint32_t)0x00000001U) /*!< Replace original alpha channel value by programmed alpha value */
<> 144:ef7eb2e8f9f7 262 #define DMA2D_COMBINE_ALPHA ((uint32_t)0x00000002U) /*!< Replace original alpha channel value by programmed alpha value
<> 144:ef7eb2e8f9f7 263 with original alpha channel value */
<> 144:ef7eb2e8f9f7 264 /**
<> 144:ef7eb2e8f9f7 265 * @}
<> 144:ef7eb2e8f9f7 266 */
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 #if defined (DMA2D_FGPFCCR_AI) && defined (DMA2D_BGPFCCR_AI)
<> 144:ef7eb2e8f9f7 269 /** @defgroup DMA2D_Alpha_Inverted DMA2D ALPHA Inversion
<> 144:ef7eb2e8f9f7 270 * @{
<> 144:ef7eb2e8f9f7 271 */
<> 144:ef7eb2e8f9f7 272 #define DMA2D_REGULAR_ALPHA ((uint32_t)0x00000000U) /*!< No modification of the alpha channel value */
<> 144:ef7eb2e8f9f7 273 #define DMA2D_INVERTED_ALPHA ((uint32_t)0x00000001U) /*!< Invert the alpha channel value */
<> 144:ef7eb2e8f9f7 274 /**
<> 144:ef7eb2e8f9f7 275 * @}
<> 144:ef7eb2e8f9f7 276 */
<> 144:ef7eb2e8f9f7 277 #endif /* (DMA2D_FGPFCCR_AI) && (DMA2D_BGPFCCR_AI) */
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 #if defined (DMA2D_FGPFCCR_RBS) && defined (DMA2D_BGPFCCR_RBS)
<> 144:ef7eb2e8f9f7 280 /** @defgroup DMA2D_RB_Swap DMA2D Red and Blue Swap
<> 144:ef7eb2e8f9f7 281 * @{
<> 144:ef7eb2e8f9f7 282 */
<> 144:ef7eb2e8f9f7 283 #define DMA2D_RB_REGULAR ((uint32_t)0x00000000U) /*!< Select regular mode (RGB or ARGB) */
<> 144:ef7eb2e8f9f7 284 #define DMA2D_RB_SWAP ((uint32_t)0x00000001U) /*!< Select swap mode (BGR or ABGR) */
<> 144:ef7eb2e8f9f7 285 /**
<> 144:ef7eb2e8f9f7 286 * @}
<> 144:ef7eb2e8f9f7 287 */
<> 144:ef7eb2e8f9f7 288 #endif /* (DMA2D_FGPFCCR_RBS) && (DMA2D_BGPFCCR_RBS) */
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 /** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode
<> 144:ef7eb2e8f9f7 291 * @{
<> 144:ef7eb2e8f9f7 292 */
<> 144:ef7eb2e8f9f7 293 #define DMA2D_CCM_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 DMA2D CLUT color mode */
<> 144:ef7eb2e8f9f7 294 #define DMA2D_CCM_RGB888 ((uint32_t)0x00000001U) /*!< RGB888 DMA2D CLUT color mode */
<> 144:ef7eb2e8f9f7 295 /**
<> 144:ef7eb2e8f9f7 296 * @}
<> 144:ef7eb2e8f9f7 297 */
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 /** @defgroup DMA2D_Interrupts DMA2D Interrupts
<> 144:ef7eb2e8f9f7 301 * @{
<> 144:ef7eb2e8f9f7 302 */
<> 144:ef7eb2e8f9f7 303 #define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */
<> 144:ef7eb2e8f9f7 304 #define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */
<> 144:ef7eb2e8f9f7 305 #define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */
<> 144:ef7eb2e8f9f7 306 #define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */
<> 144:ef7eb2e8f9f7 307 #define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */
<> 144:ef7eb2e8f9f7 308 #define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */
<> 144:ef7eb2e8f9f7 309 /**
<> 144:ef7eb2e8f9f7 310 * @}
<> 144:ef7eb2e8f9f7 311 */
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 /** @defgroup DMA2D_Flags DMA2D Flags
<> 144:ef7eb2e8f9f7 314 * @{
<> 144:ef7eb2e8f9f7 315 */
<> 144:ef7eb2e8f9f7 316 #define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */
<> 144:ef7eb2e8f9f7 317 #define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */
<> 144:ef7eb2e8f9f7 318 #define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */
<> 144:ef7eb2e8f9f7 319 #define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */
<> 144:ef7eb2e8f9f7 320 #define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */
<> 144:ef7eb2e8f9f7 321 #define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */
<> 144:ef7eb2e8f9f7 322 /**
<> 144:ef7eb2e8f9f7 323 * @}
<> 144:ef7eb2e8f9f7 324 */
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 /** @defgroup DMA2D_Aliases DMA2D API Aliases
<> 144:ef7eb2e8f9f7 327 * @{
<> 144:ef7eb2e8f9f7 328 */
<> 144:ef7eb2e8f9f7 329 #define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort for compatibility with legacy code */
<> 144:ef7eb2e8f9f7 330 /**
<> 144:ef7eb2e8f9f7 331 * @}
<> 144:ef7eb2e8f9f7 332 */
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 /**
<> 144:ef7eb2e8f9f7 336 * @}
<> 144:ef7eb2e8f9f7 337 */
<> 144:ef7eb2e8f9f7 338 /* Exported macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 339 /** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros
<> 144:ef7eb2e8f9f7 340 * @{
<> 144:ef7eb2e8f9f7 341 */
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 /** @brief Reset DMA2D handle state
<> 144:ef7eb2e8f9f7 344 * @param __HANDLE__: specifies the DMA2D handle.
<> 144:ef7eb2e8f9f7 345 * @retval None
<> 144:ef7eb2e8f9f7 346 */
<> 144:ef7eb2e8f9f7 347 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 /**
<> 144:ef7eb2e8f9f7 350 * @brief Enable the DMA2D.
<> 144:ef7eb2e8f9f7 351 * @param __HANDLE__: DMA2D handle
<> 144:ef7eb2e8f9f7 352 * @retval None.
<> 144:ef7eb2e8f9f7 353 */
<> 144:ef7eb2e8f9f7 354 #define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 /* Interrupt & Flag management */
<> 144:ef7eb2e8f9f7 358 /**
<> 144:ef7eb2e8f9f7 359 * @brief Get the DMA2D pending flags.
<> 144:ef7eb2e8f9f7 360 * @param __HANDLE__: DMA2D handle
<> 144:ef7eb2e8f9f7 361 * @param __FLAG__: flag to check.
<> 144:ef7eb2e8f9f7 362 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 363 * @arg DMA2D_FLAG_CE: Configuration error flag
<> 144:ef7eb2e8f9f7 364 * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
<> 144:ef7eb2e8f9f7 365 * @arg DMA2D_FLAG_CAE: CLUT access error flag
<> 144:ef7eb2e8f9f7 366 * @arg DMA2D_FLAG_TW: Transfer Watermark flag
<> 144:ef7eb2e8f9f7 367 * @arg DMA2D_FLAG_TC: Transfer complete flag
<> 144:ef7eb2e8f9f7 368 * @arg DMA2D_FLAG_TE: Transfer error flag
<> 144:ef7eb2e8f9f7 369 * @retval The state of FLAG.
<> 144:ef7eb2e8f9f7 370 */
<> 144:ef7eb2e8f9f7 371 #define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 /**
<> 144:ef7eb2e8f9f7 374 * @brief Clear the DMA2D pending flags.
<> 144:ef7eb2e8f9f7 375 * @param __HANDLE__: DMA2D handle
<> 144:ef7eb2e8f9f7 376 * @param __FLAG__: specifies the flag to clear.
<> 144:ef7eb2e8f9f7 377 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 378 * @arg DMA2D_FLAG_CE: Configuration error flag
<> 144:ef7eb2e8f9f7 379 * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
<> 144:ef7eb2e8f9f7 380 * @arg DMA2D_FLAG_CAE: CLUT access error flag
<> 144:ef7eb2e8f9f7 381 * @arg DMA2D_FLAG_TW: Transfer Watermark flag
<> 144:ef7eb2e8f9f7 382 * @arg DMA2D_FLAG_TC: Transfer complete flag
<> 144:ef7eb2e8f9f7 383 * @arg DMA2D_FLAG_TE: Transfer error flag
<> 144:ef7eb2e8f9f7 384 * @retval None
<> 144:ef7eb2e8f9f7 385 */
<> 144:ef7eb2e8f9f7 386 #define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 /**
<> 144:ef7eb2e8f9f7 389 * @brief Enable the specified DMA2D interrupts.
<> 144:ef7eb2e8f9f7 390 * @param __HANDLE__: DMA2D handle
<> 144:ef7eb2e8f9f7 391 * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be enabled.
<> 144:ef7eb2e8f9f7 392 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 393 * @arg DMA2D_IT_CE: Configuration error interrupt mask
<> 144:ef7eb2e8f9f7 394 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
<> 144:ef7eb2e8f9f7 395 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask
<> 144:ef7eb2e8f9f7 396 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
<> 144:ef7eb2e8f9f7 397 * @arg DMA2D_IT_TC: Transfer complete interrupt mask
<> 144:ef7eb2e8f9f7 398 * @arg DMA2D_IT_TE: Transfer error interrupt mask
<> 144:ef7eb2e8f9f7 399 * @retval None
<> 144:ef7eb2e8f9f7 400 */
<> 144:ef7eb2e8f9f7 401 #define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 /**
<> 144:ef7eb2e8f9f7 404 * @brief Disable the specified DMA2D interrupts.
<> 144:ef7eb2e8f9f7 405 * @param __HANDLE__: DMA2D handle
<> 144:ef7eb2e8f9f7 406 * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be disabled.
<> 144:ef7eb2e8f9f7 407 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 408 * @arg DMA2D_IT_CE: Configuration error interrupt mask
<> 144:ef7eb2e8f9f7 409 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
<> 144:ef7eb2e8f9f7 410 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask
<> 144:ef7eb2e8f9f7 411 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
<> 144:ef7eb2e8f9f7 412 * @arg DMA2D_IT_TC: Transfer complete interrupt mask
<> 144:ef7eb2e8f9f7 413 * @arg DMA2D_IT_TE: Transfer error interrupt mask
<> 144:ef7eb2e8f9f7 414 * @retval None
<> 144:ef7eb2e8f9f7 415 */
<> 144:ef7eb2e8f9f7 416 #define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
<> 144:ef7eb2e8f9f7 417
<> 144:ef7eb2e8f9f7 418 /**
<> 144:ef7eb2e8f9f7 419 * @brief Check whether the specified DMA2D interrupt source is enabled or not.
<> 144:ef7eb2e8f9f7 420 * @param __HANDLE__: DMA2D handle
<> 144:ef7eb2e8f9f7 421 * @param __INTERRUPT__: specifies the DMA2D interrupt source to check.
<> 144:ef7eb2e8f9f7 422 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 423 * @arg DMA2D_IT_CE: Configuration error interrupt mask
<> 144:ef7eb2e8f9f7 424 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
<> 144:ef7eb2e8f9f7 425 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask
<> 144:ef7eb2e8f9f7 426 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
<> 144:ef7eb2e8f9f7 427 * @arg DMA2D_IT_TC: Transfer complete interrupt mask
<> 144:ef7eb2e8f9f7 428 * @arg DMA2D_IT_TE: Transfer error interrupt mask
<> 144:ef7eb2e8f9f7 429 * @retval The state of INTERRUPT source.
<> 144:ef7eb2e8f9f7 430 */
<> 144:ef7eb2e8f9f7 431 #define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 432
<> 144:ef7eb2e8f9f7 433 /**
<> 144:ef7eb2e8f9f7 434 * @}
<> 144:ef7eb2e8f9f7 435 */
<> 144:ef7eb2e8f9f7 436
<> 144:ef7eb2e8f9f7 437 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 438 /** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions
<> 144:ef7eb2e8f9f7 439 * @{
<> 144:ef7eb2e8f9f7 440 */
<> 144:ef7eb2e8f9f7 441
<> 144:ef7eb2e8f9f7 442 /** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 443 * @{
<> 144:ef7eb2e8f9f7 444 */
<> 144:ef7eb2e8f9f7 445
<> 144:ef7eb2e8f9f7 446 /* Initialization and de-initialization functions *******************************/
<> 144:ef7eb2e8f9f7 447 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
<> 144:ef7eb2e8f9f7 448 HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d);
<> 144:ef7eb2e8f9f7 449 void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);
<> 144:ef7eb2e8f9f7 450 void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);
<> 144:ef7eb2e8f9f7 451
<> 144:ef7eb2e8f9f7 452 /**
<> 144:ef7eb2e8f9f7 453 * @}
<> 144:ef7eb2e8f9f7 454 */
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456
<> 144:ef7eb2e8f9f7 457 /** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 458 * @{
<> 144:ef7eb2e8f9f7 459 */
<> 144:ef7eb2e8f9f7 460
<> 144:ef7eb2e8f9f7 461 /* IO operation functions *******************************************************/
<> 144:ef7eb2e8f9f7 462 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
<> 144:ef7eb2e8f9f7 463 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
<> 144:ef7eb2e8f9f7 464 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
<> 144:ef7eb2e8f9f7 465 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
<> 144:ef7eb2e8f9f7 466 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
<> 144:ef7eb2e8f9f7 467 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
<> 144:ef7eb2e8f9f7 468 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
<> 144:ef7eb2e8f9f7 469 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
<> 144:ef7eb2e8f9f7 470 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
<> 144:ef7eb2e8f9f7 471 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
<> 144:ef7eb2e8f9f7 472 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
<> 144:ef7eb2e8f9f7 473 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
<> 144:ef7eb2e8f9f7 474 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
<> 144:ef7eb2e8f9f7 475 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 476 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);
<> 144:ef7eb2e8f9f7 477 void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d);
<> 144:ef7eb2e8f9f7 478 void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d);
<> 144:ef7eb2e8f9f7 479
<> 144:ef7eb2e8f9f7 480 /**
<> 144:ef7eb2e8f9f7 481 * @}
<> 144:ef7eb2e8f9f7 482 */
<> 144:ef7eb2e8f9f7 483
<> 144:ef7eb2e8f9f7 484 /** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
<> 144:ef7eb2e8f9f7 485 * @{
<> 144:ef7eb2e8f9f7 486 */
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488 /* Peripheral Control functions *************************************************/
<> 144:ef7eb2e8f9f7 489 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
<> 144:ef7eb2e8f9f7 490 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
<> 144:ef7eb2e8f9f7 491 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);
<> 144:ef7eb2e8f9f7 492 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d);
<> 144:ef7eb2e8f9f7 493 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d);
<> 144:ef7eb2e8f9f7 494 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime);
<> 144:ef7eb2e8f9f7 495
<> 144:ef7eb2e8f9f7 496 /**
<> 144:ef7eb2e8f9f7 497 * @}
<> 144:ef7eb2e8f9f7 498 */
<> 144:ef7eb2e8f9f7 499
<> 144:ef7eb2e8f9f7 500 /** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
<> 144:ef7eb2e8f9f7 501 * @{
<> 144:ef7eb2e8f9f7 502 */
<> 144:ef7eb2e8f9f7 503
<> 144:ef7eb2e8f9f7 504 /* Peripheral State functions ***************************************************/
<> 144:ef7eb2e8f9f7 505 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);
<> 144:ef7eb2e8f9f7 506 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 /**
<> 144:ef7eb2e8f9f7 509 * @}
<> 144:ef7eb2e8f9f7 510 */
<> 144:ef7eb2e8f9f7 511
<> 144:ef7eb2e8f9f7 512 /**
<> 144:ef7eb2e8f9f7 513 * @}
<> 144:ef7eb2e8f9f7 514 */
<> 144:ef7eb2e8f9f7 515
<> 144:ef7eb2e8f9f7 516 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 517
<> 144:ef7eb2e8f9f7 518 /** @addtogroup DMA2D_Private_Constants DMA2D Private Constants
<> 144:ef7eb2e8f9f7 519 * @{
<> 144:ef7eb2e8f9f7 520 */
<> 144:ef7eb2e8f9f7 521
<> 144:ef7eb2e8f9f7 522 /** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark
<> 144:ef7eb2e8f9f7 523 * @{
<> 144:ef7eb2e8f9f7 524 */
<> 144:ef7eb2e8f9f7 525 #define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW /*!< DMA2D maximum line watermark */
<> 144:ef7eb2e8f9f7 526 /**
<> 144:ef7eb2e8f9f7 527 * @}
<> 144:ef7eb2e8f9f7 528 */
<> 144:ef7eb2e8f9f7 529
<> 144:ef7eb2e8f9f7 530 /** @defgroup DMA2D_Color_Value DMA2D Color Value
<> 144:ef7eb2e8f9f7 531 * @{
<> 144:ef7eb2e8f9f7 532 */
<> 144:ef7eb2e8f9f7 533 #define DMA2D_COLOR_VALUE ((uint32_t)0x000000FFU) /*!< Color value mask */
<> 144:ef7eb2e8f9f7 534 /**
<> 144:ef7eb2e8f9f7 535 * @}
<> 144:ef7eb2e8f9f7 536 */
<> 144:ef7eb2e8f9f7 537
<> 144:ef7eb2e8f9f7 538 /** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers
<> 144:ef7eb2e8f9f7 539 * @{
<> 144:ef7eb2e8f9f7 540 */
<> 144:ef7eb2e8f9f7 541 #define DMA2D_MAX_LAYER 2 /*!< DMA2D maximum number of layers */
<> 144:ef7eb2e8f9f7 542 /**
<> 144:ef7eb2e8f9f7 543 * @}
<> 144:ef7eb2e8f9f7 544 */
<> 144:ef7eb2e8f9f7 545
<> 144:ef7eb2e8f9f7 546 /** @defgroup DMA2D_Offset DMA2D Offset
<> 144:ef7eb2e8f9f7 547 * @{
<> 144:ef7eb2e8f9f7 548 */
<> 144:ef7eb2e8f9f7 549 #define DMA2D_OFFSET DMA2D_FGOR_LO /*!< Line Offset */
<> 144:ef7eb2e8f9f7 550 /**
<> 144:ef7eb2e8f9f7 551 * @}
<> 144:ef7eb2e8f9f7 552 */
<> 144:ef7eb2e8f9f7 553
<> 144:ef7eb2e8f9f7 554 /** @defgroup DMA2D_Size DMA2D Size
<> 144:ef7eb2e8f9f7 555 * @{
<> 144:ef7eb2e8f9f7 556 */
<> 144:ef7eb2e8f9f7 557 #define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /*!< DMA2D number of pixels per line */
<> 144:ef7eb2e8f9f7 558 #define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D number of lines */
<> 144:ef7eb2e8f9f7 559 /**
<> 144:ef7eb2e8f9f7 560 * @}
<> 144:ef7eb2e8f9f7 561 */
<> 144:ef7eb2e8f9f7 562
<> 144:ef7eb2e8f9f7 563 /** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size
<> 144:ef7eb2e8f9f7 564 * @{
<> 144:ef7eb2e8f9f7 565 */
<> 144:ef7eb2e8f9f7 566 #define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8) /*!< DMA2D CLUT size */
<> 144:ef7eb2e8f9f7 567 /**
<> 144:ef7eb2e8f9f7 568 * @}
<> 144:ef7eb2e8f9f7 569 */
<> 144:ef7eb2e8f9f7 570
<> 144:ef7eb2e8f9f7 571 /**
<> 144:ef7eb2e8f9f7 572 * @}
<> 144:ef7eb2e8f9f7 573 */
<> 144:ef7eb2e8f9f7 574
<> 144:ef7eb2e8f9f7 575
<> 144:ef7eb2e8f9f7 576 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 577 /** @defgroup DMA2D_Private_Macros DMA2D Private Macros
<> 144:ef7eb2e8f9f7 578 * @{
<> 144:ef7eb2e8f9f7 579 */
<> 144:ef7eb2e8f9f7 580 #define IS_DMA2D_LAYER(LAYER) ((LAYER) <= DMA2D_MAX_LAYER)
<> 144:ef7eb2e8f9f7 581 #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
<> 144:ef7eb2e8f9f7 582 ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
<> 144:ef7eb2e8f9f7 583 #define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \
<> 144:ef7eb2e8f9f7 584 ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
<> 144:ef7eb2e8f9f7 585 ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444))
<> 144:ef7eb2e8f9f7 586 #define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE)
<> 144:ef7eb2e8f9f7 587 #define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE)
<> 144:ef7eb2e8f9f7 588 #define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)
<> 144:ef7eb2e8f9f7 589 #define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)
<> 144:ef7eb2e8f9f7 590 #define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888) || \
<> 144:ef7eb2e8f9f7 591 ((INPUT_CM) == DMA2D_INPUT_RGB565) || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
<> 144:ef7eb2e8f9f7 592 ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8) || \
<> 144:ef7eb2e8f9f7 593 ((INPUT_CM) == DMA2D_INPUT_AL44) || ((INPUT_CM) == DMA2D_INPUT_AL88) || \
<> 144:ef7eb2e8f9f7 594 ((INPUT_CM) == DMA2D_INPUT_L4) || ((INPUT_CM) == DMA2D_INPUT_A8) || \
<> 144:ef7eb2e8f9f7 595 ((INPUT_CM) == DMA2D_INPUT_A4))
<> 144:ef7eb2e8f9f7 596 #define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
<> 144:ef7eb2e8f9f7 597 ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \
<> 144:ef7eb2e8f9f7 598 ((AlphaMode) == DMA2D_COMBINE_ALPHA))
<> 144:ef7eb2e8f9f7 599
<> 144:ef7eb2e8f9f7 600 #define IS_DMA2D_ALPHA_INVERTED(Alpha_Inverted) (((Alpha_Inverted) == DMA2D_REGULAR_ALPHA) || \
<> 144:ef7eb2e8f9f7 601 ((Alpha_Inverted) == DMA2D_INVERTED_ALPHA))
<> 144:ef7eb2e8f9f7 602
<> 144:ef7eb2e8f9f7 603 #define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \
<> 144:ef7eb2e8f9f7 604 ((RB_Swap) == DMA2D_RB_SWAP))
<> 144:ef7eb2e8f9f7 605
<> 144:ef7eb2e8f9f7 606 #define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
<> 144:ef7eb2e8f9f7 607 #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
<> 144:ef7eb2e8f9f7 608 #define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX)
<> 144:ef7eb2e8f9f7 609 #define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
<> 144:ef7eb2e8f9f7 610 ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
<> 144:ef7eb2e8f9f7 611 ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
<> 144:ef7eb2e8f9f7 612 #define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
<> 144:ef7eb2e8f9f7 613 ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \
<> 144:ef7eb2e8f9f7 614 ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE))
<> 144:ef7eb2e8f9f7 615 /**
<> 144:ef7eb2e8f9f7 616 * @}
<> 144:ef7eb2e8f9f7 617 */
<> 144:ef7eb2e8f9f7 618
<> 144:ef7eb2e8f9f7 619 /**
<> 144:ef7eb2e8f9f7 620 * @}
<> 144:ef7eb2e8f9f7 621 */
<> 144:ef7eb2e8f9f7 622
<> 144:ef7eb2e8f9f7 623 /**
<> 144:ef7eb2e8f9f7 624 * @}
<> 144:ef7eb2e8f9f7 625 */
<> 144:ef7eb2e8f9f7 626
<> 144:ef7eb2e8f9f7 627
<> 144:ef7eb2e8f9f7 628 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 629 }
<> 144:ef7eb2e8f9f7 630 #endif
<> 144:ef7eb2e8f9f7 631
<> 144:ef7eb2e8f9f7 632 #endif /* __STM32F7xx_HAL_DMA2D_H */
<> 144:ef7eb2e8f9f7 633
<> 144:ef7eb2e8f9f7 634
<> 144:ef7eb2e8f9f7 635 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/