added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

Committer:
mbed_official
Date:
Mon Mar 07 10:00:14 2016 +0000
Revision:
83:a036322b8637
Parent:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Synchronized with git revision ee20d03969aa5c570152f88e8f3d8a4739eed40b

Full URL: https://github.com/mbedmicro/mbed/commit/ee20d03969aa5c570152f88e8f3d8a4739eed40b/

[STM32F7] Update STM32F7Cube_FW version

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f7xx_hal_dma2d.h
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
mbed_official 83:a036322b8637 5 * @version V1.0.4
mbed_official 83:a036322b8637 6 * @date 09-December-2015
bogdanm 0:9b334a45a8ff 7 * @brief Header file of DMA2D HAL module.
bogdanm 0:9b334a45a8ff 8 ******************************************************************************
bogdanm 0:9b334a45a8ff 9 * @attention
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 12 *
bogdanm 0:9b334a45a8ff 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 14 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 16 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 19 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 21 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 22 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 23 *
bogdanm 0:9b334a45a8ff 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 34 *
bogdanm 0:9b334a45a8ff 35 ******************************************************************************
bogdanm 0:9b334a45a8ff 36 */
bogdanm 0:9b334a45a8ff 37
bogdanm 0:9b334a45a8ff 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 0:9b334a45a8ff 39 #ifndef __STM32F7xx_HAL_DMA2D_H
bogdanm 0:9b334a45a8ff 40 #define __STM32F7xx_HAL_DMA2D_H
bogdanm 0:9b334a45a8ff 41
bogdanm 0:9b334a45a8ff 42 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 43 extern "C" {
bogdanm 0:9b334a45a8ff 44 #endif
bogdanm 0:9b334a45a8ff 45
bogdanm 0:9b334a45a8ff 46 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 47 #include "stm32f7xx_hal_def.h"
bogdanm 0:9b334a45a8ff 48
bogdanm 0:9b334a45a8ff 49 /** @addtogroup STM32F7xx_HAL_Driver
bogdanm 0:9b334a45a8ff 50 * @{
bogdanm 0:9b334a45a8ff 51 */
bogdanm 0:9b334a45a8ff 52
bogdanm 0:9b334a45a8ff 53 /** @defgroup DMA2D DMA2D
bogdanm 0:9b334a45a8ff 54 * @brief DMA2D HAL module driver
bogdanm 0:9b334a45a8ff 55 * @{
bogdanm 0:9b334a45a8ff 56 */
bogdanm 0:9b334a45a8ff 57
bogdanm 0:9b334a45a8ff 58 /* Exported types ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 59 /** @defgroup DMA2D_Exported_Types DMA2D Exported Types
bogdanm 0:9b334a45a8ff 60 * @{
bogdanm 0:9b334a45a8ff 61 */
bogdanm 0:9b334a45a8ff 62 #define MAX_DMA2D_LAYER 2
bogdanm 0:9b334a45a8ff 63
bogdanm 0:9b334a45a8ff 64 /**
bogdanm 0:9b334a45a8ff 65 * @brief DMA2D color Structure definition
bogdanm 0:9b334a45a8ff 66 */
bogdanm 0:9b334a45a8ff 67 typedef struct
bogdanm 0:9b334a45a8ff 68 {
bogdanm 0:9b334a45a8ff 69 uint32_t Blue; /*!< Configures the blue value.
bogdanm 0:9b334a45a8ff 70 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
bogdanm 0:9b334a45a8ff 71
bogdanm 0:9b334a45a8ff 72 uint32_t Green; /*!< Configures the green value.
bogdanm 0:9b334a45a8ff 73 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
bogdanm 0:9b334a45a8ff 74
bogdanm 0:9b334a45a8ff 75 uint32_t Red; /*!< Configures the red value.
bogdanm 0:9b334a45a8ff 76 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
bogdanm 0:9b334a45a8ff 77 } DMA2D_ColorTypeDef;
bogdanm 0:9b334a45a8ff 78
bogdanm 0:9b334a45a8ff 79 /**
bogdanm 0:9b334a45a8ff 80 * @brief DMA2D CLUT Structure definition
bogdanm 0:9b334a45a8ff 81 */
bogdanm 0:9b334a45a8ff 82 typedef struct
bogdanm 0:9b334a45a8ff 83 {
bogdanm 0:9b334a45a8ff 84 uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/
bogdanm 0:9b334a45a8ff 85
bogdanm 0:9b334a45a8ff 86 uint32_t CLUTColorMode; /*!< configures the DMA2D CLUT color mode.
bogdanm 0:9b334a45a8ff 87 This parameter can be one value of @ref DMA2D_CLUT_CM */
bogdanm 0:9b334a45a8ff 88
bogdanm 0:9b334a45a8ff 89 uint32_t Size; /*!< configures the DMA2D CLUT size.
bogdanm 0:9b334a45a8ff 90 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/
bogdanm 0:9b334a45a8ff 91 } DMA2D_CLUTCfgTypeDef;
bogdanm 0:9b334a45a8ff 92
bogdanm 0:9b334a45a8ff 93 /**
bogdanm 0:9b334a45a8ff 94 * @brief DMA2D Init structure definition
bogdanm 0:9b334a45a8ff 95 */
bogdanm 0:9b334a45a8ff 96 typedef struct
bogdanm 0:9b334a45a8ff 97 {
bogdanm 0:9b334a45a8ff 98 uint32_t Mode; /*!< configures the DMA2D transfer mode.
bogdanm 0:9b334a45a8ff 99 This parameter can be one value of @ref DMA2D_Mode */
bogdanm 0:9b334a45a8ff 100
bogdanm 0:9b334a45a8ff 101 uint32_t ColorMode; /*!< configures the color format of the output image.
bogdanm 0:9b334a45a8ff 102 This parameter can be one value of @ref DMA2D_Color_Mode */
bogdanm 0:9b334a45a8ff 103
bogdanm 0:9b334a45a8ff 104 uint32_t OutputOffset; /*!< Specifies the Offset value.
bogdanm 0:9b334a45a8ff 105 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
bogdanm 0:9b334a45a8ff 106 } DMA2D_InitTypeDef;
bogdanm 0:9b334a45a8ff 107
bogdanm 0:9b334a45a8ff 108 /**
bogdanm 0:9b334a45a8ff 109 * @brief DMA2D Layer structure definition
bogdanm 0:9b334a45a8ff 110 */
bogdanm 0:9b334a45a8ff 111 typedef struct
bogdanm 0:9b334a45a8ff 112 {
bogdanm 0:9b334a45a8ff 113 uint32_t InputOffset; /*!< configures the DMA2D foreground offset.
bogdanm 0:9b334a45a8ff 114 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
bogdanm 0:9b334a45a8ff 115
bogdanm 0:9b334a45a8ff 116 uint32_t InputColorMode; /*!< configures the DMA2D foreground color mode .
bogdanm 0:9b334a45a8ff 117 This parameter can be one value of @ref DMA2D_Input_Color_Mode */
bogdanm 0:9b334a45a8ff 118
bogdanm 0:9b334a45a8ff 119 uint32_t AlphaMode; /*!< configures the DMA2D foreground alpha mode.
bogdanm 0:9b334a45a8ff 120 This parameter can be one value of @ref DMA2D_ALPHA_MODE */
bogdanm 0:9b334a45a8ff 121
bogdanm 0:9b334a45a8ff 122 uint32_t InputAlpha; /*!< Specifies the DMA2D foreground alpha value and color value in case of A8 or A4 color mode.
bogdanm 0:9b334a45a8ff 123 This parameter must be a number between Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF
bogdanm 0:9b334a45a8ff 124 in case of A8 or A4 color mode (ARGB).
bogdanm 0:9b334a45a8ff 125 Otherwise, This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/
bogdanm 0:9b334a45a8ff 126
bogdanm 0:9b334a45a8ff 127 } DMA2D_LayerCfgTypeDef;
bogdanm 0:9b334a45a8ff 128
bogdanm 0:9b334a45a8ff 129 /**
bogdanm 0:9b334a45a8ff 130 * @brief HAL DMA2D State structures definition
bogdanm 0:9b334a45a8ff 131 */
bogdanm 0:9b334a45a8ff 132 typedef enum
bogdanm 0:9b334a45a8ff 133 {
bogdanm 0:9b334a45a8ff 134 HAL_DMA2D_STATE_RESET = 0x00, /*!< DMA2D not yet initialized or disabled */
bogdanm 0:9b334a45a8ff 135 HAL_DMA2D_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
bogdanm 0:9b334a45a8ff 136 HAL_DMA2D_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
bogdanm 0:9b334a45a8ff 137 HAL_DMA2D_STATE_TIMEOUT = 0x03, /*!< Timeout state */
bogdanm 0:9b334a45a8ff 138 HAL_DMA2D_STATE_ERROR = 0x04, /*!< DMA2D state error */
bogdanm 0:9b334a45a8ff 139 HAL_DMA2D_STATE_SUSPEND = 0x05 /*!< DMA2D process is suspended */
bogdanm 0:9b334a45a8ff 140 }HAL_DMA2D_StateTypeDef;
bogdanm 0:9b334a45a8ff 141
bogdanm 0:9b334a45a8ff 142 /**
bogdanm 0:9b334a45a8ff 143 * @brief DMA2D handle Structure definition
bogdanm 0:9b334a45a8ff 144 */
bogdanm 0:9b334a45a8ff 145 typedef struct __DMA2D_HandleTypeDef
bogdanm 0:9b334a45a8ff 146 {
bogdanm 0:9b334a45a8ff 147 DMA2D_TypeDef *Instance; /*!< DMA2D Register base address */
bogdanm 0:9b334a45a8ff 148
bogdanm 0:9b334a45a8ff 149 DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters */
bogdanm 0:9b334a45a8ff 150
bogdanm 0:9b334a45a8ff 151 void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer complete callback */
bogdanm 0:9b334a45a8ff 152
bogdanm 0:9b334a45a8ff 153 void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback */
bogdanm 0:9b334a45a8ff 154
bogdanm 0:9b334a45a8ff 155 DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */
bogdanm 0:9b334a45a8ff 156
bogdanm 0:9b334a45a8ff 157 HAL_LockTypeDef Lock; /*!< DMA2D Lock */
bogdanm 0:9b334a45a8ff 158
bogdanm 0:9b334a45a8ff 159 __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state */
bogdanm 0:9b334a45a8ff 160
bogdanm 0:9b334a45a8ff 161 __IO uint32_t ErrorCode; /*!< DMA2D Error code */
bogdanm 0:9b334a45a8ff 162 } DMA2D_HandleTypeDef;
bogdanm 0:9b334a45a8ff 163 /**
bogdanm 0:9b334a45a8ff 164 * @}
bogdanm 0:9b334a45a8ff 165 */
bogdanm 0:9b334a45a8ff 166
bogdanm 0:9b334a45a8ff 167 /* Exported constants --------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 168 /** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants
bogdanm 0:9b334a45a8ff 169 * @{
bogdanm 0:9b334a45a8ff 170 */
bogdanm 0:9b334a45a8ff 171
bogdanm 0:9b334a45a8ff 172 /** @defgroup DMA2D_Error_Code DMA2D Error Code
bogdanm 0:9b334a45a8ff 173 * @{
bogdanm 0:9b334a45a8ff 174 */
bogdanm 0:9b334a45a8ff 175 #define HAL_DMA2D_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
bogdanm 0:9b334a45a8ff 176 #define HAL_DMA2D_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
bogdanm 0:9b334a45a8ff 177 #define HAL_DMA2D_ERROR_CE ((uint32_t)0x00000002) /*!< Configuration error */
bogdanm 0:9b334a45a8ff 178 #define HAL_DMA2D_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
bogdanm 0:9b334a45a8ff 179 /**
bogdanm 0:9b334a45a8ff 180 * @}
bogdanm 0:9b334a45a8ff 181 */
bogdanm 0:9b334a45a8ff 182
bogdanm 0:9b334a45a8ff 183 /** @defgroup DMA2D_Mode DMA2D Mode
bogdanm 0:9b334a45a8ff 184 * @{
bogdanm 0:9b334a45a8ff 185 */
bogdanm 0:9b334a45a8ff 186 #define DMA2D_M2M ((uint32_t)0x00000000) /*!< DMA2D memory to memory transfer mode */
bogdanm 0:9b334a45a8ff 187 #define DMA2D_M2M_PFC ((uint32_t)0x00010000) /*!< DMA2D memory to memory with pixel format conversion transfer mode */
bogdanm 0:9b334a45a8ff 188 #define DMA2D_M2M_BLEND ((uint32_t)0x00020000) /*!< DMA2D memory to memory with blending transfer mode */
bogdanm 0:9b334a45a8ff 189 #define DMA2D_R2M ((uint32_t)0x00030000) /*!< DMA2D register to memory transfer mode */
bogdanm 0:9b334a45a8ff 190 /**
bogdanm 0:9b334a45a8ff 191 * @}
bogdanm 0:9b334a45a8ff 192 */
bogdanm 0:9b334a45a8ff 193
bogdanm 0:9b334a45a8ff 194 /** @defgroup DMA2D_Color_Mode DMA2D Color Mode
bogdanm 0:9b334a45a8ff 195 * @{
bogdanm 0:9b334a45a8ff 196 */
bogdanm 0:9b334a45a8ff 197 #define DMA2D_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 DMA2D color mode */
bogdanm 0:9b334a45a8ff 198 #define DMA2D_RGB888 ((uint32_t)0x00000001) /*!< RGB888 DMA2D color mode */
bogdanm 0:9b334a45a8ff 199 #define DMA2D_RGB565 ((uint32_t)0x00000002) /*!< RGB565 DMA2D color mode */
bogdanm 0:9b334a45a8ff 200 #define DMA2D_ARGB1555 ((uint32_t)0x00000003) /*!< ARGB1555 DMA2D color mode */
bogdanm 0:9b334a45a8ff 201 #define DMA2D_ARGB4444 ((uint32_t)0x00000004) /*!< ARGB4444 DMA2D color mode */
bogdanm 0:9b334a45a8ff 202 /**
bogdanm 0:9b334a45a8ff 203 * @}
bogdanm 0:9b334a45a8ff 204 */
bogdanm 0:9b334a45a8ff 205
bogdanm 0:9b334a45a8ff 206 /** @defgroup DMA2D_COLOR_VALUE DMA2D COLOR VALUE
bogdanm 0:9b334a45a8ff 207 * @{
bogdanm 0:9b334a45a8ff 208 */
bogdanm 0:9b334a45a8ff 209 #define COLOR_VALUE ((uint32_t)0x000000FF) /*!< color value mask */
bogdanm 0:9b334a45a8ff 210 /**
bogdanm 0:9b334a45a8ff 211 * @}
bogdanm 0:9b334a45a8ff 212 */
bogdanm 0:9b334a45a8ff 213
bogdanm 0:9b334a45a8ff 214 /** @defgroup DMA2D_SIZE DMA2D SIZE
bogdanm 0:9b334a45a8ff 215 * @{
bogdanm 0:9b334a45a8ff 216 */
bogdanm 0:9b334a45a8ff 217 #define DMA2D_PIXEL (DMA2D_NLR_PL >> 16) /*!< DMA2D pixel per line */
bogdanm 0:9b334a45a8ff 218 #define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D number of line */
bogdanm 0:9b334a45a8ff 219 /**
bogdanm 0:9b334a45a8ff 220 * @}
bogdanm 0:9b334a45a8ff 221 */
bogdanm 0:9b334a45a8ff 222
bogdanm 0:9b334a45a8ff 223 /** @defgroup DMA2D_Offset DMA2D Offset
bogdanm 0:9b334a45a8ff 224 * @{
bogdanm 0:9b334a45a8ff 225 */
bogdanm 0:9b334a45a8ff 226 #define DMA2D_OFFSET DMA2D_FGOR_LO /*!< Line Offset */
bogdanm 0:9b334a45a8ff 227 /**
bogdanm 0:9b334a45a8ff 228 * @}
bogdanm 0:9b334a45a8ff 229 */
bogdanm 0:9b334a45a8ff 230
bogdanm 0:9b334a45a8ff 231 /** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode
bogdanm 0:9b334a45a8ff 232 * @{
bogdanm 0:9b334a45a8ff 233 */
bogdanm 0:9b334a45a8ff 234 #define CM_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 color mode */
bogdanm 0:9b334a45a8ff 235 #define CM_RGB888 ((uint32_t)0x00000001) /*!< RGB888 color mode */
bogdanm 0:9b334a45a8ff 236 #define CM_RGB565 ((uint32_t)0x00000002) /*!< RGB565 color mode */
bogdanm 0:9b334a45a8ff 237 #define CM_ARGB1555 ((uint32_t)0x00000003) /*!< ARGB1555 color mode */
bogdanm 0:9b334a45a8ff 238 #define CM_ARGB4444 ((uint32_t)0x00000004) /*!< ARGB4444 color mode */
bogdanm 0:9b334a45a8ff 239 #define CM_L8 ((uint32_t)0x00000005) /*!< L8 color mode */
bogdanm 0:9b334a45a8ff 240 #define CM_AL44 ((uint32_t)0x00000006) /*!< AL44 color mode */
bogdanm 0:9b334a45a8ff 241 #define CM_AL88 ((uint32_t)0x00000007) /*!< AL88 color mode */
bogdanm 0:9b334a45a8ff 242 #define CM_L4 ((uint32_t)0x00000008) /*!< L4 color mode */
bogdanm 0:9b334a45a8ff 243 #define CM_A8 ((uint32_t)0x00000009) /*!< A8 color mode */
bogdanm 0:9b334a45a8ff 244 #define CM_A4 ((uint32_t)0x0000000A) /*!< A4 color mode */
bogdanm 0:9b334a45a8ff 245 /**
bogdanm 0:9b334a45a8ff 246 * @}
bogdanm 0:9b334a45a8ff 247 */
bogdanm 0:9b334a45a8ff 248
bogdanm 0:9b334a45a8ff 249 /** @defgroup DMA2D_ALPHA_MODE DMA2D ALPHA MODE
bogdanm 0:9b334a45a8ff 250 * @{
bogdanm 0:9b334a45a8ff 251 */
bogdanm 0:9b334a45a8ff 252 #define DMA2D_NO_MODIF_ALPHA ((uint32_t)0x00000000) /*!< No modification of the alpha channel value */
bogdanm 0:9b334a45a8ff 253 #define DMA2D_REPLACE_ALPHA ((uint32_t)0x00000001) /*!< Replace original alpha channel value by programmed alpha value */
bogdanm 0:9b334a45a8ff 254 #define DMA2D_COMBINE_ALPHA ((uint32_t)0x00000002) /*!< Replace original alpha channel value by programmed alpha value
bogdanm 0:9b334a45a8ff 255 with original alpha channel value */
bogdanm 0:9b334a45a8ff 256 /**
bogdanm 0:9b334a45a8ff 257 * @}
bogdanm 0:9b334a45a8ff 258 */
bogdanm 0:9b334a45a8ff 259
bogdanm 0:9b334a45a8ff 260 /** @defgroup DMA2D_CLUT_CM DMA2D CLUT CM
bogdanm 0:9b334a45a8ff 261 * @{
bogdanm 0:9b334a45a8ff 262 */
bogdanm 0:9b334a45a8ff 263 #define DMA2D_CCM_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 DMA2D C-LUT color mode */
bogdanm 0:9b334a45a8ff 264 #define DMA2D_CCM_RGB888 ((uint32_t)0x00000001) /*!< RGB888 DMA2D C-LUT color mode */
bogdanm 0:9b334a45a8ff 265 /**
bogdanm 0:9b334a45a8ff 266 * @}
bogdanm 0:9b334a45a8ff 267 */
bogdanm 0:9b334a45a8ff 268
bogdanm 0:9b334a45a8ff 269 /** @defgroup DMA2D_Size_Clut DMA2D Size Clut
bogdanm 0:9b334a45a8ff 270 * @{
bogdanm 0:9b334a45a8ff 271 */
bogdanm 0:9b334a45a8ff 272 #define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8) /*!< DMA2D C-LUT size */
bogdanm 0:9b334a45a8ff 273 /**
bogdanm 0:9b334a45a8ff 274 * @}
bogdanm 0:9b334a45a8ff 275 */
bogdanm 0:9b334a45a8ff 276
bogdanm 0:9b334a45a8ff 277 /** @defgroup DMA2D_DeadTime DMA2D DeadTime
bogdanm 0:9b334a45a8ff 278 * @{
bogdanm 0:9b334a45a8ff 279 */
bogdanm 0:9b334a45a8ff 280 #define LINE_WATERMARK DMA2D_LWR_LW
bogdanm 0:9b334a45a8ff 281 /**
bogdanm 0:9b334a45a8ff 282 * @}
bogdanm 0:9b334a45a8ff 283 */
bogdanm 0:9b334a45a8ff 284
bogdanm 0:9b334a45a8ff 285 /** @defgroup DMA2D_Interrupts DMA2D Interrupts
bogdanm 0:9b334a45a8ff 286 * @{
bogdanm 0:9b334a45a8ff 287 */
bogdanm 0:9b334a45a8ff 288 #define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */
bogdanm 0:9b334a45a8ff 289 #define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< C-LUT Transfer Complete Interrupt */
bogdanm 0:9b334a45a8ff 290 #define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< C-LUT Access Error Interrupt */
bogdanm 0:9b334a45a8ff 291 #define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */
bogdanm 0:9b334a45a8ff 292 #define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */
bogdanm 0:9b334a45a8ff 293 #define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */
bogdanm 0:9b334a45a8ff 294 /**
bogdanm 0:9b334a45a8ff 295 * @}
bogdanm 0:9b334a45a8ff 296 */
bogdanm 0:9b334a45a8ff 297
bogdanm 0:9b334a45a8ff 298 /** @defgroup DMA2D_Flag DMA2D Flag
bogdanm 0:9b334a45a8ff 299 * @{
bogdanm 0:9b334a45a8ff 300 */
bogdanm 0:9b334a45a8ff 301 #define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */
bogdanm 0:9b334a45a8ff 302 #define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< C-LUT Transfer Complete Interrupt Flag */
bogdanm 0:9b334a45a8ff 303 #define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< C-LUT Access Error Interrupt Flag */
bogdanm 0:9b334a45a8ff 304 #define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */
bogdanm 0:9b334a45a8ff 305 #define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */
bogdanm 0:9b334a45a8ff 306 #define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */
bogdanm 0:9b334a45a8ff 307 /**
bogdanm 0:9b334a45a8ff 308 * @}
bogdanm 0:9b334a45a8ff 309 */
bogdanm 0:9b334a45a8ff 310
bogdanm 0:9b334a45a8ff 311 /**
bogdanm 0:9b334a45a8ff 312 * @}
bogdanm 0:9b334a45a8ff 313 */
bogdanm 0:9b334a45a8ff 314 /* Exported macro ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 315 /** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros
bogdanm 0:9b334a45a8ff 316 * @{
bogdanm 0:9b334a45a8ff 317 */
bogdanm 0:9b334a45a8ff 318
bogdanm 0:9b334a45a8ff 319 /** @brief Reset DMA2D handle state
bogdanm 0:9b334a45a8ff 320 * @param __HANDLE__: specifies the DMA2D handle.
bogdanm 0:9b334a45a8ff 321 * @retval None
bogdanm 0:9b334a45a8ff 322 */
bogdanm 0:9b334a45a8ff 323 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
bogdanm 0:9b334a45a8ff 324
bogdanm 0:9b334a45a8ff 325 /**
bogdanm 0:9b334a45a8ff 326 * @brief Enable the DMA2D.
bogdanm 0:9b334a45a8ff 327 * @param __HANDLE__: DMA2D handle
bogdanm 0:9b334a45a8ff 328 * @retval None.
bogdanm 0:9b334a45a8ff 329 */
bogdanm 0:9b334a45a8ff 330 #define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
bogdanm 0:9b334a45a8ff 331
bogdanm 0:9b334a45a8ff 332 /**
bogdanm 0:9b334a45a8ff 333 * @brief Disable the DMA2D.
bogdanm 0:9b334a45a8ff 334 * @param __HANDLE__: DMA2D handle
bogdanm 0:9b334a45a8ff 335 * @retval None.
bogdanm 0:9b334a45a8ff 336 */
bogdanm 0:9b334a45a8ff 337 #define __HAL_DMA2D_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA2D_CR_START)
bogdanm 0:9b334a45a8ff 338
bogdanm 0:9b334a45a8ff 339 /* Interrupt & Flag management */
bogdanm 0:9b334a45a8ff 340 /**
bogdanm 0:9b334a45a8ff 341 * @brief Get the DMA2D pending flags.
bogdanm 0:9b334a45a8ff 342 * @param __HANDLE__: DMA2D handle
bogdanm 0:9b334a45a8ff 343 * @param __FLAG__: Get the specified flag.
bogdanm 0:9b334a45a8ff 344 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 345 * @arg DMA2D_FLAG_CE: Configuration error flag
bogdanm 0:9b334a45a8ff 346 * @arg DMA2D_FLAG_CTC: C-LUT transfer complete flag
bogdanm 0:9b334a45a8ff 347 * @arg DMA2D_FLAG_CAE: C-LUT access error flag
bogdanm 0:9b334a45a8ff 348 * @arg DMA2D_FLAG_TW: Transfer Watermark flag
bogdanm 0:9b334a45a8ff 349 * @arg DMA2D_FLAG_TC: Transfer complete flag
bogdanm 0:9b334a45a8ff 350 * @arg DMA2D_FLAG_TE: Transfer error flag
bogdanm 0:9b334a45a8ff 351 * @retval The state of FLAG.
bogdanm 0:9b334a45a8ff 352 */
bogdanm 0:9b334a45a8ff 353 #define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
bogdanm 0:9b334a45a8ff 354
bogdanm 0:9b334a45a8ff 355 /**
bogdanm 0:9b334a45a8ff 356 * @brief Clears the DMA2D pending flags.
bogdanm 0:9b334a45a8ff 357 * @param __HANDLE__: DMA2D handle
bogdanm 0:9b334a45a8ff 358 * @param __FLAG__: specifies the flag to clear.
bogdanm 0:9b334a45a8ff 359 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 360 * @arg DMA2D_FLAG_CE: Configuration error flag
bogdanm 0:9b334a45a8ff 361 * @arg DMA2D_FLAG_CTC: C-LUT transfer complete flag
bogdanm 0:9b334a45a8ff 362 * @arg DMA2D_FLAG_CAE: C-LUT access error flag
bogdanm 0:9b334a45a8ff 363 * @arg DMA2D_FLAG_TW: Transfer Watermark flag
bogdanm 0:9b334a45a8ff 364 * @arg DMA2D_FLAG_TC: Transfer complete flag
bogdanm 0:9b334a45a8ff 365 * @arg DMA2D_FLAG_TE: Transfer error flag
bogdanm 0:9b334a45a8ff 366 * @retval None
bogdanm 0:9b334a45a8ff 367 */
bogdanm 0:9b334a45a8ff 368 #define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))
bogdanm 0:9b334a45a8ff 369
bogdanm 0:9b334a45a8ff 370 /**
bogdanm 0:9b334a45a8ff 371 * @brief Enables the specified DMA2D interrupts.
bogdanm 0:9b334a45a8ff 372 * @param __HANDLE__: DMA2D handle
bogdanm 0:9b334a45a8ff 373 * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be enabled.
bogdanm 0:9b334a45a8ff 374 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 375 * @arg DMA2D_IT_CE: Configuration error interrupt mask
bogdanm 0:9b334a45a8ff 376 * @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask
bogdanm 0:9b334a45a8ff 377 * @arg DMA2D_IT_CAE: C-LUT access error interrupt mask
bogdanm 0:9b334a45a8ff 378 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
bogdanm 0:9b334a45a8ff 379 * @arg DMA2D_IT_TC: Transfer complete interrupt mask
bogdanm 0:9b334a45a8ff 380 * @arg DMA2D_IT_TE: Transfer error interrupt mask
bogdanm 0:9b334a45a8ff 381 * @retval None
bogdanm 0:9b334a45a8ff 382 */
bogdanm 0:9b334a45a8ff 383 #define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
bogdanm 0:9b334a45a8ff 384
bogdanm 0:9b334a45a8ff 385 /**
bogdanm 0:9b334a45a8ff 386 * @brief Disables the specified DMA2D interrupts.
bogdanm 0:9b334a45a8ff 387 * @param __HANDLE__: DMA2D handle
bogdanm 0:9b334a45a8ff 388 * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be disabled.
bogdanm 0:9b334a45a8ff 389 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 390 * @arg DMA2D_IT_CE: Configuration error interrupt mask
bogdanm 0:9b334a45a8ff 391 * @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask
bogdanm 0:9b334a45a8ff 392 * @arg DMA2D_IT_CAE: C-LUT access error interrupt mask
bogdanm 0:9b334a45a8ff 393 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
bogdanm 0:9b334a45a8ff 394 * @arg DMA2D_IT_TC: Transfer complete interrupt mask
bogdanm 0:9b334a45a8ff 395 * @arg DMA2D_IT_TE: Transfer error interrupt mask
bogdanm 0:9b334a45a8ff 396 * @retval None
bogdanm 0:9b334a45a8ff 397 */
bogdanm 0:9b334a45a8ff 398 #define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
bogdanm 0:9b334a45a8ff 399
bogdanm 0:9b334a45a8ff 400 /**
bogdanm 0:9b334a45a8ff 401 * @brief Checks whether the specified DMA2D interrupt has occurred or not.
bogdanm 0:9b334a45a8ff 402 * @param __HANDLE__: DMA2D handle
bogdanm 0:9b334a45a8ff 403 * @param __INTERRUPT__: specifies the DMA2D interrupt source to check.
bogdanm 0:9b334a45a8ff 404 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 405 * @arg DMA2D_IT_CE: Configuration error interrupt mask
bogdanm 0:9b334a45a8ff 406 * @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask
bogdanm 0:9b334a45a8ff 407 * @arg DMA2D_IT_CAE: C-LUT access error interrupt mask
bogdanm 0:9b334a45a8ff 408 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
bogdanm 0:9b334a45a8ff 409 * @arg DMA2D_IT_TC: Transfer complete interrupt mask
bogdanm 0:9b334a45a8ff 410 * @arg DMA2D_IT_TE: Transfer error interrupt mask
bogdanm 0:9b334a45a8ff 411 * @retval The state of INTERRUPT.
bogdanm 0:9b334a45a8ff 412 */
bogdanm 0:9b334a45a8ff 413 #define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
bogdanm 0:9b334a45a8ff 414 /**
bogdanm 0:9b334a45a8ff 415 * @}
bogdanm 0:9b334a45a8ff 416 */
bogdanm 0:9b334a45a8ff 417
bogdanm 0:9b334a45a8ff 418 /* Exported functions --------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 419 /** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions
bogdanm 0:9b334a45a8ff 420 * @{
bogdanm 0:9b334a45a8ff 421 */
bogdanm 0:9b334a45a8ff 422 /* Initialization and de-initialization functions *******************************/
bogdanm 0:9b334a45a8ff 423 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
bogdanm 0:9b334a45a8ff 424 HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d);
bogdanm 0:9b334a45a8ff 425 void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);
bogdanm 0:9b334a45a8ff 426 void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);
bogdanm 0:9b334a45a8ff 427
bogdanm 0:9b334a45a8ff 428 /* IO operation functions *******************************************************/
bogdanm 0:9b334a45a8ff 429 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
bogdanm 0:9b334a45a8ff 430 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
bogdanm 0:9b334a45a8ff 431 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
bogdanm 0:9b334a45a8ff 432 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
bogdanm 0:9b334a45a8ff 433 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
bogdanm 0:9b334a45a8ff 434 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
bogdanm 0:9b334a45a8ff 435 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
bogdanm 0:9b334a45a8ff 436 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);
bogdanm 0:9b334a45a8ff 437 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);
bogdanm 0:9b334a45a8ff 438
bogdanm 0:9b334a45a8ff 439 /* Peripheral Control functions *************************************************/
bogdanm 0:9b334a45a8ff 440 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
bogdanm 0:9b334a45a8ff 441 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
bogdanm 0:9b334a45a8ff 442 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
bogdanm 0:9b334a45a8ff 443 HAL_StatusTypeDef HAL_DMA2D_DisableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
bogdanm 0:9b334a45a8ff 444 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);
bogdanm 0:9b334a45a8ff 445
bogdanm 0:9b334a45a8ff 446 /* Peripheral State functions ***************************************************/
bogdanm 0:9b334a45a8ff 447 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);
bogdanm 0:9b334a45a8ff 448 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
bogdanm 0:9b334a45a8ff 449 /**
bogdanm 0:9b334a45a8ff 450 * @}
bogdanm 0:9b334a45a8ff 451 */
bogdanm 0:9b334a45a8ff 452
bogdanm 0:9b334a45a8ff 453 /* Private types -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 454 /** @defgroup DMA2D_Private_Types DMA2D Private Types
bogdanm 0:9b334a45a8ff 455 * @{
bogdanm 0:9b334a45a8ff 456 */
bogdanm 0:9b334a45a8ff 457
bogdanm 0:9b334a45a8ff 458 /**
bogdanm 0:9b334a45a8ff 459 * @}
bogdanm 0:9b334a45a8ff 460 */
bogdanm 0:9b334a45a8ff 461
bogdanm 0:9b334a45a8ff 462 /* Private defines -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 463 /** @defgroup DMA2D_Private_Defines DMA2D Private Defines
bogdanm 0:9b334a45a8ff 464 * @{
bogdanm 0:9b334a45a8ff 465 */
bogdanm 0:9b334a45a8ff 466
bogdanm 0:9b334a45a8ff 467 /**
bogdanm 0:9b334a45a8ff 468 * @}
bogdanm 0:9b334a45a8ff 469 */
bogdanm 0:9b334a45a8ff 470
bogdanm 0:9b334a45a8ff 471 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 472 /** @defgroup DMA2D_Private_Variables DMA2D Private Variables
bogdanm 0:9b334a45a8ff 473 * @{
bogdanm 0:9b334a45a8ff 474 */
bogdanm 0:9b334a45a8ff 475
bogdanm 0:9b334a45a8ff 476 /**
bogdanm 0:9b334a45a8ff 477 * @}
bogdanm 0:9b334a45a8ff 478 */
bogdanm 0:9b334a45a8ff 479
bogdanm 0:9b334a45a8ff 480 /* Private constants ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 481 /** @defgroup DMA2D_Private_Constants DMA2D Private Constants
bogdanm 0:9b334a45a8ff 482 * @{
bogdanm 0:9b334a45a8ff 483 */
bogdanm 0:9b334a45a8ff 484
bogdanm 0:9b334a45a8ff 485 /**
bogdanm 0:9b334a45a8ff 486 * @}
bogdanm 0:9b334a45a8ff 487 */
bogdanm 0:9b334a45a8ff 488
bogdanm 0:9b334a45a8ff 489 /* Private macros ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 490 /** @defgroup DMA2D_Private_Macros DMA2D Private Macros
bogdanm 0:9b334a45a8ff 491 * @{
bogdanm 0:9b334a45a8ff 492 */
bogdanm 0:9b334a45a8ff 493 #define IS_DMA2D_LAYER(LAYER) ((LAYER) <= MAX_DMA2D_LAYER)
bogdanm 0:9b334a45a8ff 494 #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
bogdanm 0:9b334a45a8ff 495 ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
bogdanm 0:9b334a45a8ff 496 #define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_ARGB8888) || ((MODE_ARGB) == DMA2D_RGB888) || \
bogdanm 0:9b334a45a8ff 497 ((MODE_ARGB) == DMA2D_RGB565) || ((MODE_ARGB) == DMA2D_ARGB1555) || \
bogdanm 0:9b334a45a8ff 498 ((MODE_ARGB) == DMA2D_ARGB4444))
bogdanm 0:9b334a45a8ff 499 #define IS_DMA2D_COLOR(COLOR) ((COLOR) <= COLOR_VALUE)
bogdanm 0:9b334a45a8ff 500 #define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE)
bogdanm 0:9b334a45a8ff 501 #define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)
bogdanm 0:9b334a45a8ff 502 #define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)
bogdanm 0:9b334a45a8ff 503 #define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == CM_ARGB8888) || ((INPUT_CM) == CM_RGB888) || \
bogdanm 0:9b334a45a8ff 504 ((INPUT_CM) == CM_RGB565) || ((INPUT_CM) == CM_ARGB1555) || \
bogdanm 0:9b334a45a8ff 505 ((INPUT_CM) == CM_ARGB4444) || ((INPUT_CM) == CM_L8) || \
bogdanm 0:9b334a45a8ff 506 ((INPUT_CM) == CM_AL44) || ((INPUT_CM) == CM_AL88) || \
bogdanm 0:9b334a45a8ff 507 ((INPUT_CM) == CM_L4) || ((INPUT_CM) == CM_A8) || \
bogdanm 0:9b334a45a8ff 508 ((INPUT_CM) == CM_A4))
bogdanm 0:9b334a45a8ff 509 #define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
bogdanm 0:9b334a45a8ff 510 ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \
bogdanm 0:9b334a45a8ff 511 ((AlphaMode) == DMA2D_COMBINE_ALPHA))
bogdanm 0:9b334a45a8ff 512 #define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
bogdanm 0:9b334a45a8ff 513 #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
bogdanm 0:9b334a45a8ff 514 #define IS_DMA2D_LineWatermark(LineWatermark) ((LineWatermark) <= LINE_WATERMARK)
bogdanm 0:9b334a45a8ff 515 #define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
bogdanm 0:9b334a45a8ff 516 ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
bogdanm 0:9b334a45a8ff 517 ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
bogdanm 0:9b334a45a8ff 518 #define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
bogdanm 0:9b334a45a8ff 519 ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \
bogdanm 0:9b334a45a8ff 520 ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE))
bogdanm 0:9b334a45a8ff 521 /**
bogdanm 0:9b334a45a8ff 522 * @}
bogdanm 0:9b334a45a8ff 523 */
bogdanm 0:9b334a45a8ff 524
bogdanm 0:9b334a45a8ff 525 /* Private functions prototypes ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 526 /** @defgroup DMA2D_Private_Functions_Prototypes DMA2D Private Functions Prototypes
bogdanm 0:9b334a45a8ff 527 * @{
bogdanm 0:9b334a45a8ff 528 */
bogdanm 0:9b334a45a8ff 529
bogdanm 0:9b334a45a8ff 530 /**
bogdanm 0:9b334a45a8ff 531 * @}
bogdanm 0:9b334a45a8ff 532 */
bogdanm 0:9b334a45a8ff 533
bogdanm 0:9b334a45a8ff 534 /* Private functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 535 /** @defgroup DMA2D_Private_Functions DMA2D Private Functions
bogdanm 0:9b334a45a8ff 536 * @{
bogdanm 0:9b334a45a8ff 537 */
bogdanm 0:9b334a45a8ff 538
bogdanm 0:9b334a45a8ff 539 /**
bogdanm 0:9b334a45a8ff 540 * @}
bogdanm 0:9b334a45a8ff 541 */
bogdanm 0:9b334a45a8ff 542
bogdanm 0:9b334a45a8ff 543 /**
bogdanm 0:9b334a45a8ff 544 * @}
bogdanm 0:9b334a45a8ff 545 */
bogdanm 0:9b334a45a8ff 546
bogdanm 0:9b334a45a8ff 547 /**
bogdanm 0:9b334a45a8ff 548 * @}
bogdanm 0:9b334a45a8ff 549 */
bogdanm 0:9b334a45a8ff 550
bogdanm 0:9b334a45a8ff 551
bogdanm 0:9b334a45a8ff 552 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 553 }
bogdanm 0:9b334a45a8ff 554 #endif
bogdanm 0:9b334a45a8ff 555
bogdanm 0:9b334a45a8ff 556 #endif /* __STM32F7xx_HAL_DMA2D_H */
bogdanm 0:9b334a45a8ff 557
bogdanm 0:9b334a45a8ff 558
bogdanm 0:9b334a45a8ff 559 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/