added prescaler for 16 bit pwm in LPC1347 target
Fork of mbed-dev by
targets/cmsis/TARGET_NXP/TARGET_LPC43XX/system_LPC43xx.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)
- Committer:
- <>
- Date:
- Fri Sep 02 15:07:44 2016 +0100
- Revision:
- 144:ef7eb2e8f9f7
- Parent:
- 0:9b334a45a8ff
This updates the lib to the mbed lib v125
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /* |
<> | 144:ef7eb2e8f9f7 | 2 | * @brief LPC43xx/LPC18xx mcu header |
<> | 144:ef7eb2e8f9f7 | 3 | * |
<> | 144:ef7eb2e8f9f7 | 4 | * Copyright(C) NXP Semiconductors, 2012 |
<> | 144:ef7eb2e8f9f7 | 5 | * All rights reserved. |
<> | 144:ef7eb2e8f9f7 | 6 | * |
<> | 144:ef7eb2e8f9f7 | 7 | * Software that is described herein is for illustrative purposes only |
<> | 144:ef7eb2e8f9f7 | 8 | * which provides customers with programming information regarding the |
<> | 144:ef7eb2e8f9f7 | 9 | * LPC products. This software is supplied "AS IS" without any warranties of |
<> | 144:ef7eb2e8f9f7 | 10 | * any kind, and NXP Semiconductors and its licensor disclaim any and |
<> | 144:ef7eb2e8f9f7 | 11 | * all warranties, express or implied, including all implied warranties of |
<> | 144:ef7eb2e8f9f7 | 12 | * merchantability, fitness for a particular purpose and non-infringement of |
<> | 144:ef7eb2e8f9f7 | 13 | * intellectual property rights. NXP Semiconductors assumes no responsibility |
<> | 144:ef7eb2e8f9f7 | 14 | * or liability for the use of the software, conveys no license or rights under any |
<> | 144:ef7eb2e8f9f7 | 15 | * patent, copyright, mask work right, or any other intellectual property rights in |
<> | 144:ef7eb2e8f9f7 | 16 | * or to any products. NXP Semiconductors reserves the right to make changes |
<> | 144:ef7eb2e8f9f7 | 17 | * in the software without notification. NXP Semiconductors also makes no |
<> | 144:ef7eb2e8f9f7 | 18 | * representation or warranty that such application will be suitable for the |
<> | 144:ef7eb2e8f9f7 | 19 | * specified use without further testing or modification. |
<> | 144:ef7eb2e8f9f7 | 20 | * |
<> | 144:ef7eb2e8f9f7 | 21 | * Permission to use, copy, modify, and distribute this software and its |
<> | 144:ef7eb2e8f9f7 | 22 | * documentation is hereby granted, under NXP Semiconductors' and its |
<> | 144:ef7eb2e8f9f7 | 23 | * licensor's relevant copyrights in the software, without fee, provided that it |
<> | 144:ef7eb2e8f9f7 | 24 | * is used in conjunction with NXP Semiconductors microcontrollers. This |
<> | 144:ef7eb2e8f9f7 | 25 | * copyright, permission, and disclaimer notice must appear in all copies of |
<> | 144:ef7eb2e8f9f7 | 26 | * this code. |
<> | 144:ef7eb2e8f9f7 | 27 | */ |
<> | 144:ef7eb2e8f9f7 | 28 | |
<> | 144:ef7eb2e8f9f7 | 29 | #ifndef __SYSTEM_LPC43XX_H |
<> | 144:ef7eb2e8f9f7 | 30 | #define __SYSTEM_LPC43XX_H |
<> | 144:ef7eb2e8f9f7 | 31 | |
<> | 144:ef7eb2e8f9f7 | 32 | #ifdef __cplusplus |
<> | 144:ef7eb2e8f9f7 | 33 | extern "C" { |
<> | 144:ef7eb2e8f9f7 | 34 | #endif |
<> | 144:ef7eb2e8f9f7 | 35 | |
<> | 144:ef7eb2e8f9f7 | 36 | /* System initialization options */ |
<> | 144:ef7eb2e8f9f7 | 37 | #define PIN_SETUP 1 /* Configure pins during initialization */ |
<> | 144:ef7eb2e8f9f7 | 38 | #define CLOCK_SETUP 1 /* Configure clocks during initialization */ |
<> | 144:ef7eb2e8f9f7 | 39 | #define MEMORY_SETUP 0 /* Configure external memory during init */ |
<> | 144:ef7eb2e8f9f7 | 40 | #define SPIFI_INIT 1 /* Initialize SPIFI */ |
<> | 144:ef7eb2e8f9f7 | 41 | |
<> | 144:ef7eb2e8f9f7 | 42 | /* Crystal frequency into device */ |
<> | 144:ef7eb2e8f9f7 | 43 | #define CRYSTAL_MAIN_FREQ_IN 12000000 |
<> | 144:ef7eb2e8f9f7 | 44 | |
<> | 144:ef7eb2e8f9f7 | 45 | /* Crystal frequency into device for RTC/32K input */ |
<> | 144:ef7eb2e8f9f7 | 46 | #define CRYSTAL_32K_FREQ_IN 32768 |
<> | 144:ef7eb2e8f9f7 | 47 | |
<> | 144:ef7eb2e8f9f7 | 48 | /* Default CPU clock frequency */ |
<> | 144:ef7eb2e8f9f7 | 49 | #if defined(CHIP_LPC43XX) |
<> | 144:ef7eb2e8f9f7 | 50 | #define MAX_CLOCK_FREQ (204000000) |
<> | 144:ef7eb2e8f9f7 | 51 | #else |
<> | 144:ef7eb2e8f9f7 | 52 | #define MAX_CLOCK_FREQ (180000000) |
<> | 144:ef7eb2e8f9f7 | 53 | #endif |
<> | 144:ef7eb2e8f9f7 | 54 | |
<> | 144:ef7eb2e8f9f7 | 55 | #if defined(__FPU_PRESENT) && __FPU_PRESENT == 1 |
<> | 144:ef7eb2e8f9f7 | 56 | /* FPU declarations */ |
<> | 144:ef7eb2e8f9f7 | 57 | #define LPC_CPACR 0xE000ED88 |
<> | 144:ef7eb2e8f9f7 | 58 | |
<> | 144:ef7eb2e8f9f7 | 59 | #define SCB_MVFR0 0xE000EF40 |
<> | 144:ef7eb2e8f9f7 | 60 | #define SCB_MVFR0_RESET 0x10110021 |
<> | 144:ef7eb2e8f9f7 | 61 | |
<> | 144:ef7eb2e8f9f7 | 62 | #define SCB_MVFR1 0xE000EF44 |
<> | 144:ef7eb2e8f9f7 | 63 | #define SCB_MVFR1_RESET 0x11000011 |
<> | 144:ef7eb2e8f9f7 | 64 | |
<> | 144:ef7eb2e8f9f7 | 65 | #if defined(__ARMCC_VERSION) |
<> | 144:ef7eb2e8f9f7 | 66 | void fpuInit(void) __attribute__ ((section("BOOTSTRAP_CODE"))); |
<> | 144:ef7eb2e8f9f7 | 67 | #else |
<> | 144:ef7eb2e8f9f7 | 68 | extern void fpuInit(void); |
<> | 144:ef7eb2e8f9f7 | 69 | #endif |
<> | 144:ef7eb2e8f9f7 | 70 | #endif |
<> | 144:ef7eb2e8f9f7 | 71 | |
<> | 144:ef7eb2e8f9f7 | 72 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ |
<> | 144:ef7eb2e8f9f7 | 73 | |
<> | 144:ef7eb2e8f9f7 | 74 | /** |
<> | 144:ef7eb2e8f9f7 | 75 | * Initialize the system |
<> | 144:ef7eb2e8f9f7 | 76 | * |
<> | 144:ef7eb2e8f9f7 | 77 | * @param none |
<> | 144:ef7eb2e8f9f7 | 78 | * @return none |
<> | 144:ef7eb2e8f9f7 | 79 | * |
<> | 144:ef7eb2e8f9f7 | 80 | * @brief Setup the microcontroller system. |
<> | 144:ef7eb2e8f9f7 | 81 | * Initialize the System and update the SystemCoreClock variable. |
<> | 144:ef7eb2e8f9f7 | 82 | */ |
<> | 144:ef7eb2e8f9f7 | 83 | extern void SystemInit (void); |
<> | 144:ef7eb2e8f9f7 | 84 | extern void SystemCoreClockUpdate(void); |
<> | 144:ef7eb2e8f9f7 | 85 | |
<> | 144:ef7eb2e8f9f7 | 86 | #ifdef __cplusplus |
<> | 144:ef7eb2e8f9f7 | 87 | } |
<> | 144:ef7eb2e8f9f7 | 88 | #endif |
<> | 144:ef7eb2e8f9f7 | 89 | |
<> | 144:ef7eb2e8f9f7 | 90 | #endif /* __SYSTEM_LPC43XX_H */ |