Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_NXP/TARGET_LPC43XX/system_LPC43xx.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
0:9b334a45a8ff 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 * @brief LPC43xx System Initialization
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * @note
<> 144:ef7eb2e8f9f7 5 * Copyright(C) NXP Semiconductors, 2012
<> 144:ef7eb2e8f9f7 6 * All rights reserved.
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * @par
<> 144:ef7eb2e8f9f7 9 * Software that is described herein is for illustrative purposes only
<> 144:ef7eb2e8f9f7 10 * which provides customers with programming information regarding the
<> 144:ef7eb2e8f9f7 11 * LPC products. This software is supplied "AS IS" without any warranties of
<> 144:ef7eb2e8f9f7 12 * any kind, and NXP Semiconductors and its licensor disclaim any and
<> 144:ef7eb2e8f9f7 13 * all warranties, express or implied, including all implied warranties of
<> 144:ef7eb2e8f9f7 14 * merchantability, fitness for a particular purpose and non-infringement of
<> 144:ef7eb2e8f9f7 15 * intellectual property rights. NXP Semiconductors assumes no responsibility
<> 144:ef7eb2e8f9f7 16 * or liability for the use of the software, conveys no license or rights under any
<> 144:ef7eb2e8f9f7 17 * patent, copyright, mask work right, or any other intellectual property rights in
<> 144:ef7eb2e8f9f7 18 * or to any products. NXP Semiconductors reserves the right to make changes
<> 144:ef7eb2e8f9f7 19 * in the software without notification. NXP Semiconductors also makes no
<> 144:ef7eb2e8f9f7 20 * representation or warranty that such application will be suitable for the
<> 144:ef7eb2e8f9f7 21 * specified use without further testing or modification.
<> 144:ef7eb2e8f9f7 22 *
<> 144:ef7eb2e8f9f7 23 * @par
<> 144:ef7eb2e8f9f7 24 * Permission to use, copy, modify, and distribute this software and its
<> 144:ef7eb2e8f9f7 25 * documentation is hereby granted, under NXP Semiconductors' and its
<> 144:ef7eb2e8f9f7 26 * licensor's relevant copyrights in the software, without fee, provided that it
<> 144:ef7eb2e8f9f7 27 * is used in conjunction with NXP Semiconductors microcontrollers. This
<> 144:ef7eb2e8f9f7 28 * copyright, permission, and disclaimer notice must appear in all copies of
<> 144:ef7eb2e8f9f7 29 * this code.
<> 144:ef7eb2e8f9f7 30 *
<> 144:ef7eb2e8f9f7 31 * Modified by Micromint USA <support@micromint.com>
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33 #include "LPC43xx.h"
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 #define COUNT_OF(a) (sizeof(a)/sizeof(a[0]))
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 /* Clock variables */
<> 144:ef7eb2e8f9f7 38 #if (CLOCK_SETUP)
<> 144:ef7eb2e8f9f7 39 uint32_t SystemCoreClock = MAX_CLOCK_FREQ;
<> 144:ef7eb2e8f9f7 40 #else
<> 144:ef7eb2e8f9f7 41 uint32_t SystemCoreClock = CRYSTAL_MAIN_FREQ_IN;
<> 144:ef7eb2e8f9f7 42 #endif
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 #if !defined(CORE_M0)
<> 144:ef7eb2e8f9f7 45 /* SCU pin definitions for pin muxing */
<> 144:ef7eb2e8f9f7 46 typedef struct {
<> 144:ef7eb2e8f9f7 47 __IO uint32_t *reg; /* SCU register address */
<> 144:ef7eb2e8f9f7 48 uint16_t mode; /* SCU pin mode and function */
<> 144:ef7eb2e8f9f7 49 } PINMUX_GRP_T;
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 /* Pins to initialize before clocks are configured */
<> 144:ef7eb2e8f9f7 52 static const PINMUX_GRP_T pre_clock_mux[] = {
<> 144:ef7eb2e8f9f7 53 /* SPIFI pins */
<> 144:ef7eb2e8f9f7 54 {SCU_REG(0x3, 3), (SCU_PINIO_FAST | 0x3)}, /* P3_3 SPIFI CLK */
<> 144:ef7eb2e8f9f7 55 {SCU_REG(0x3, 4), (SCU_PINIO_FAST | 0x3)}, /* P3_4 SPIFI D3 */
<> 144:ef7eb2e8f9f7 56 {SCU_REG(0x3, 5), (SCU_PINIO_FAST | 0x3)}, /* P3_5 SPIFI D2 */
<> 144:ef7eb2e8f9f7 57 {SCU_REG(0x3, 6), (SCU_PINIO_FAST | 0x3)}, /* P3_6 SPIFI D1 */
<> 144:ef7eb2e8f9f7 58 {SCU_REG(0x3, 7), (SCU_PINIO_FAST | 0x3)}, /* P3_7 SPIFI D0 */
<> 144:ef7eb2e8f9f7 59 {SCU_REG(0x3, 8), (SCU_PINIO_FAST | 0x3)} /* P3_8 SPIFI CS/SSEL */
<> 144:ef7eb2e8f9f7 60 };
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /* Pins to initialize after clocks are configured */
<> 144:ef7eb2e8f9f7 63 static const PINMUX_GRP_T post_clock_mux[] = {
<> 144:ef7eb2e8f9f7 64 /* Boot pins */
<> 144:ef7eb2e8f9f7 65 {SCU_REG(0x1, 1), (SCU_PINIO_FAST | 0x0)}, /* P1_1 BOOT0 */
<> 144:ef7eb2e8f9f7 66 {SCU_REG(0x1, 2), (SCU_PINIO_FAST | 0x0)}, /* P1_2 BOOT1 */
<> 144:ef7eb2e8f9f7 67 {SCU_REG(0x2, 8), (SCU_PINIO_FAST | 0x0)}, /* P2_8 BOOT2 */
<> 144:ef7eb2e8f9f7 68 {SCU_REG(0x2, 9), (SCU_PINIO_FAST | 0x0)}, /* P2_9 BOOT3 */
<> 144:ef7eb2e8f9f7 69 /* Micromint Bambino 200/210 */
<> 144:ef7eb2e8f9f7 70 {SCU_REG(0x6, 11), (SCU_PINIO_FAST | 0x0)}, /* P6_11 LED1 */
<> 144:ef7eb2e8f9f7 71 {SCU_REG(0x2, 5), (SCU_PINIO_FAST | 0x0)}, /* P2_5 LED2 */
<> 144:ef7eb2e8f9f7 72 {SCU_REG(0x2, 7), (SCU_PINIO_FAST | 0x0)}, /* P2_7 BTN1 */
<> 144:ef7eb2e8f9f7 73 /* Micromint Bambino 210 */
<> 144:ef7eb2e8f9f7 74 {SCU_REG(0x6, 1), (SCU_PINIO_FAST | 0x0)}, /* P6_1 LED3 */
<> 144:ef7eb2e8f9f7 75 {SCU_REG(0x6, 2), (SCU_PINIO_FAST | 0x0)}, /* P6_2 LED4 */
<> 144:ef7eb2e8f9f7 76 };
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 #if (CLOCK_SETUP)
<> 144:ef7eb2e8f9f7 79 /* Structure for initial base clock states */
<> 144:ef7eb2e8f9f7 80 struct CLK_BASE_STATES {
<> 144:ef7eb2e8f9f7 81 CGU_BASE_CLK_T clk; /* Base clock */
<> 144:ef7eb2e8f9f7 82 CGU_CLKIN_T clkin; /* Base clock source */
<> 144:ef7eb2e8f9f7 83 uint8_t powerdn; /* Set to 1 if base clock is initially powered down */
<> 144:ef7eb2e8f9f7 84 };
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 /* Initial base clock states are mostly on */
<> 144:ef7eb2e8f9f7 87 static const struct CLK_BASE_STATES clock_states[] = {
<> 144:ef7eb2e8f9f7 88 {CLK_BASE_SAFE, CLKIN_IRC, 0},
<> 144:ef7eb2e8f9f7 89 {CLK_BASE_APB1, CLKIN_MAINPLL, 0},
<> 144:ef7eb2e8f9f7 90 {CLK_BASE_APB3, CLKIN_MAINPLL, 0},
<> 144:ef7eb2e8f9f7 91 {CLK_BASE_USB0, CLKIN_USBPLL, 1},
<> 144:ef7eb2e8f9f7 92 {CLK_BASE_PERIPH, CLKIN_MAINPLL, 0},
<> 144:ef7eb2e8f9f7 93 {CLK_BASE_SPI, CLKIN_MAINPLL, 0},
<> 144:ef7eb2e8f9f7 94 {CLK_BASE_PHY_TX, CLKIN_ENET_TX, 0},
<> 144:ef7eb2e8f9f7 95 #if defined(USE_RMII)
<> 144:ef7eb2e8f9f7 96 {CLK_BASE_PHY_RX, CLKIN_ENET_TX, 0},
<> 144:ef7eb2e8f9f7 97 #else
<> 144:ef7eb2e8f9f7 98 {CLK_BASE_PHY_RX, CLKIN_ENET_RX, 0},
<> 144:ef7eb2e8f9f7 99 #endif
<> 144:ef7eb2e8f9f7 100 {CLK_BASE_SDIO, CLKIN_MAINPLL, 0},
<> 144:ef7eb2e8f9f7 101 {CLK_BASE_SSP0, CLKIN_IDIVC, 0},
<> 144:ef7eb2e8f9f7 102 {CLK_BASE_SSP1, CLKIN_IDIVC, 0},
<> 144:ef7eb2e8f9f7 103 {CLK_BASE_UART0, CLKIN_MAINPLL, 0},
<> 144:ef7eb2e8f9f7 104 {CLK_BASE_UART1, CLKIN_MAINPLL, 0},
<> 144:ef7eb2e8f9f7 105 {CLK_BASE_UART2, CLKIN_MAINPLL, 0},
<> 144:ef7eb2e8f9f7 106 {CLK_BASE_UART3, CLKIN_MAINPLL, 0},
<> 144:ef7eb2e8f9f7 107 {CLK_BASE_OUT, CLKINPUT_PD, 0},
<> 144:ef7eb2e8f9f7 108 {CLK_BASE_APLL, CLKINPUT_PD, 0},
<> 144:ef7eb2e8f9f7 109 {CLK_BASE_CGU_OUT0, CLKINPUT_PD, 0},
<> 144:ef7eb2e8f9f7 110 {CLK_BASE_CGU_OUT1, CLKINPUT_PD, 0},
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 /* Clocks derived from dividers */
<> 144:ef7eb2e8f9f7 113 {CLK_BASE_LCD, CLKIN_IDIVC, 0},
<> 144:ef7eb2e8f9f7 114 {CLK_BASE_USB1, CLKIN_IDIVD, 1}
<> 144:ef7eb2e8f9f7 115 };
<> 144:ef7eb2e8f9f7 116 #endif /* defined(CLOCK_SETUP) */
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 /* Local functions */
<> 144:ef7eb2e8f9f7 119 static uint32_t SystemGetMainPLLHz(void);
<> 144:ef7eb2e8f9f7 120 static void SystemSetupClock(void);
<> 144:ef7eb2e8f9f7 121 static void SystemSetupPins(const PINMUX_GRP_T *mux, uint32_t n);
<> 144:ef7eb2e8f9f7 122 static void SystemSetupMemory(void);
<> 144:ef7eb2e8f9f7 123 static void WaitUs(uint32_t us);
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 #endif /* !defined(CORE_M0) */
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 /*
<> 144:ef7eb2e8f9f7 128 * SystemInit() - Initialize the system
<> 144:ef7eb2e8f9f7 129 */
<> 144:ef7eb2e8f9f7 130 void SystemInit(void)
<> 144:ef7eb2e8f9f7 131 {
<> 144:ef7eb2e8f9f7 132 #if !defined(CORE_M0)
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 /* Initialize vector table in flash */
<> 144:ef7eb2e8f9f7 135 #if defined(__ARMCC_VERSION)
<> 144:ef7eb2e8f9f7 136 extern void *__Vectors;
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 SCB->VTOR = (unsigned int) &__Vectors;
<> 144:ef7eb2e8f9f7 139 #elif defined(__IAR_SYSTEMS_ICC__)
<> 144:ef7eb2e8f9f7 140 extern void *__vector_table;
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 SCB->VTOR = (unsigned int) &__vector_table;
<> 144:ef7eb2e8f9f7 143 #elif defined(TOOLCHAIN_GCC_ARM)
<> 144:ef7eb2e8f9f7 144 extern void *__isr_vector;
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 SCB->VTOR = (unsigned int) &__isr_vector;
<> 144:ef7eb2e8f9f7 147 #else /* defined(__GNUC__) and others */
<> 144:ef7eb2e8f9f7 148 extern void *g_pfnVectors;
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 SCB->VTOR = (unsigned int) &g_pfnVectors;
<> 144:ef7eb2e8f9f7 151 #endif
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 #if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
<> 144:ef7eb2e8f9f7 154 /* Initialize floating point */
<> 144:ef7eb2e8f9f7 155 fpuInit();
<> 144:ef7eb2e8f9f7 156 #endif
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 SystemSetupPins(pre_clock_mux, COUNT_OF(pre_clock_mux)); /* Configure pins */
<> 144:ef7eb2e8f9f7 159 SystemSetupClock(); /* Configure processor and peripheral clocks */
<> 144:ef7eb2e8f9f7 160 SystemSetupPins(post_clock_mux, COUNT_OF(post_clock_mux)); /* Configure pins */
<> 144:ef7eb2e8f9f7 161 SystemSetupMemory(); /* Configure external memory */
<> 144:ef7eb2e8f9f7 162 #endif /* !defined(CORE_M0) */
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 SystemCoreClockUpdate(); /* Update SystemCoreClock variable */
<> 144:ef7eb2e8f9f7 165 }
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 /*
<> 144:ef7eb2e8f9f7 168 * SystemCoreClockUpdate() - Update SystemCoreClock variable
<> 144:ef7eb2e8f9f7 169 */
<> 144:ef7eb2e8f9f7 170 void SystemCoreClockUpdate(void)
<> 144:ef7eb2e8f9f7 171 {
<> 144:ef7eb2e8f9f7 172 uint32_t reg, div, rate;
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 /* Get main PLL rate */
<> 144:ef7eb2e8f9f7 175 rate = SystemGetMainPLLHz();
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 /* Get clock divider */
<> 144:ef7eb2e8f9f7 178 reg = LPC_CCU1->CLKCCU[CLK_MX_MXCORE].CFG;
<> 144:ef7eb2e8f9f7 179 if (((reg >> 5) & 0x7) == 0) {
<> 144:ef7eb2e8f9f7 180 div = 1;
<> 144:ef7eb2e8f9f7 181 }
<> 144:ef7eb2e8f9f7 182 else {
<> 144:ef7eb2e8f9f7 183 div = 2;
<> 144:ef7eb2e8f9f7 184 }
<> 144:ef7eb2e8f9f7 185 rate = rate / div;
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 SystemCoreClock = rate;
<> 144:ef7eb2e8f9f7 188 }
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 /* Returns the frequency of the main PLL */
<> 144:ef7eb2e8f9f7 191 uint32_t SystemGetMainPLLHz(void)
<> 144:ef7eb2e8f9f7 192 {
<> 144:ef7eb2e8f9f7 193 uint32_t PLLReg = LPC_CGU->PLL1_CTRL;
<> 144:ef7eb2e8f9f7 194 uint32_t freq = CRYSTAL_MAIN_FREQ_IN;
<> 144:ef7eb2e8f9f7 195 uint32_t msel, nsel, psel, direct, fbsel;
<> 144:ef7eb2e8f9f7 196 uint32_t m, n, p;
<> 144:ef7eb2e8f9f7 197 const uint8_t ptab[] = {1, 2, 4, 8};
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 msel = (PLLReg >> 16) & 0xFF;
<> 144:ef7eb2e8f9f7 200 nsel = (PLLReg >> 12) & 0x3;
<> 144:ef7eb2e8f9f7 201 psel = (PLLReg >> 8) & 0x3;
<> 144:ef7eb2e8f9f7 202 direct = (PLLReg >> 7) & 0x1;
<> 144:ef7eb2e8f9f7 203 fbsel = (PLLReg >> 6) & 0x1;
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 m = msel + 1;
<> 144:ef7eb2e8f9f7 206 n = nsel + 1;
<> 144:ef7eb2e8f9f7 207 p = ptab[psel];
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 if (direct || fbsel) {
<> 144:ef7eb2e8f9f7 210 return m * (freq / n);
<> 144:ef7eb2e8f9f7 211 }
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 return (m / (2 * p)) * (freq / n);
<> 144:ef7eb2e8f9f7 214 }
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 #if !defined(CORE_M0)
<> 144:ef7eb2e8f9f7 217 /*
<> 144:ef7eb2e8f9f7 218 * SystemSetupClock() - Set processor and peripheral clocks
<> 144:ef7eb2e8f9f7 219 *
<> 144:ef7eb2e8f9f7 220 * Clock Frequency Source
<> 144:ef7eb2e8f9f7 221 * CLK_BASE_MX 204 MHz CLKIN_MAINPLL (CLKIN_PLL1)
<> 144:ef7eb2e8f9f7 222 * CLK_BASE_SPIFI 102 MHz CLKIN_IDIVE
<> 144:ef7eb2e8f9f7 223 * CLK_BASE_USB0 480 MHz CLKIN_USBPLL (Disabled) (CLKIN_PLL0USB)
<> 144:ef7eb2e8f9f7 224 * CLK_BASE_USB1 60 MHz CLKIN_IDIVE (Disabled)
<> 144:ef7eb2e8f9f7 225 * 120 MHz CLKIN_IDIVD (Disabled)
<> 144:ef7eb2e8f9f7 226 *
<> 144:ef7eb2e8f9f7 227 * 12 MHz CLKIN_IDIVB
<> 144:ef7eb2e8f9f7 228 * 12 MHz CLKIN_IDIVC
<> 144:ef7eb2e8f9f7 229 *
<> 144:ef7eb2e8f9f7 230 */
<> 144:ef7eb2e8f9f7 231 void SystemSetupClock(void)
<> 144:ef7eb2e8f9f7 232 {
<> 144:ef7eb2e8f9f7 233 #if (CLOCK_SETUP)
<> 144:ef7eb2e8f9f7 234 uint32_t i;
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236 /* Switch main clock to Internal RC (IRC) while setting up PLL1 */
<> 144:ef7eb2e8f9f7 237 LPC_CGU->BASE_CLK[CLK_BASE_MX] = (1 << 11) | (CLKIN_IRC << 24);
<> 144:ef7eb2e8f9f7 238 /* Set prescaler/divider on SSP1 assuming 204 MHz clock */
<> 144:ef7eb2e8f9f7 239 LPC_SSP1->CR1 &= ~(1 << 1);
<> 144:ef7eb2e8f9f7 240 LPC_SSP1->CPSR = 0x0002;
<> 144:ef7eb2e8f9f7 241 LPC_SSP1->CR0 = 0x00006507;
<> 144:ef7eb2e8f9f7 242 LPC_SSP1->CR1 |= (1 << 1);
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 /* Enable the oscillator and wait 100 us */
<> 144:ef7eb2e8f9f7 245 LPC_CGU->XTAL_OSC_CTRL = 0;
<> 144:ef7eb2e8f9f7 246 WaitUs(100);
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 #if (SPIFI_INIT)
<> 144:ef7eb2e8f9f7 249 /* Setup SPIFI control register and no-opcode mode */
<> 144:ef7eb2e8f9f7 250 LPC_SPIFI->CTRL = (0x100 << 0) | (1 << 16) | (1 << 29) | (1 << 30);
<> 144:ef7eb2e8f9f7 251 LPC_SPIFI->IDATA = 0xA5;
<> 144:ef7eb2e8f9f7 252 /* Switch IDIVE clock to IRC and connect to SPIFI clock */
<> 144:ef7eb2e8f9f7 253 LPC_CGU->IDIV_CTRL[CLK_IDIV_E] = ((1 << 11) | (CLKIN_IRC << 24));
<> 144:ef7eb2e8f9f7 254 LPC_CGU->BASE_CLK[CLK_BASE_SPIFI] = ((1 << 11) | (CLKIN_IDIVE << 24));
<> 144:ef7eb2e8f9f7 255 #endif /* SPIFI_INIT */
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 /* Configure PLL1 (MAINPLL) for main clock */
<> 144:ef7eb2e8f9f7 258 LPC_CGU->PLL1_CTRL |= 1; /* Power down PLL1 */
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 /* Change PLL1 to 108 Mhz (msel=9, 12 MHz*9=108 MHz) */
<> 144:ef7eb2e8f9f7 261 LPC_CGU->PLL1_CTRL = (1 << 7) | (0 << 8) | (1 << 11) | (0 << 12) | (8 << 16)
<> 144:ef7eb2e8f9f7 262 | (CLKIN_MAINPLL << 24);
<> 144:ef7eb2e8f9f7 263 while (!(LPC_CGU->PLL1_STAT & 1)); /* Wait for PLL1 to lock */
<> 144:ef7eb2e8f9f7 264 WaitUs(100);
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 /* Change PLL1 to 204 Mhz (msel=17, 12 MHz*17=204 MHz) */
<> 144:ef7eb2e8f9f7 267 LPC_CGU->PLL1_CTRL = (1 << 7) | (0 << 8) | (1 << 11) | (0 << 12) | (16 << 16)
<> 144:ef7eb2e8f9f7 268 | (CLKIN_MAINPLL << 24);
<> 144:ef7eb2e8f9f7 269 while (!(LPC_CGU->PLL1_STAT & 1)); /* Wait for PLL1 to lock */
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 /* Connect main clock to PLL1 */
<> 144:ef7eb2e8f9f7 272 LPC_CGU->BASE_CLK[CLK_BASE_MX] = (1 << 11) | (CLKIN_MAINPLL << 24);
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 /* Set USB PLL dividers for 480 MHz (for USB0) */
<> 144:ef7eb2e8f9f7 275 LPC_CGU->PLL[CGU_USB_PLL].PLL_MDIV = 0x06167FFA;
<> 144:ef7eb2e8f9f7 276 LPC_CGU->PLL[CGU_USB_PLL].PLL_NP_DIV = 0x00302062;
<> 144:ef7eb2e8f9f7 277 LPC_CGU->PLL[CGU_USB_PLL].PLL_CTRL = 0x0000081D | (CLKIN_CRYSTAL << 24);
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 /* Set IDIVE clock to PLL1/2 = 102 MHz */
<> 144:ef7eb2e8f9f7 280 LPC_CGU->IDIV_CTRL[CLK_IDIV_E] = (1 << 2) | (1 << 11) | (CLKIN_MAINPLL << 24); /* PLL1/2 */
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 /* Set IDIVD clock to ((USBPLL/4) / 2) = 60 MHz (for USB1) */
<> 144:ef7eb2e8f9f7 283 LPC_CGU->IDIV_CTRL[CLK_IDIV_A] = (3 << 2) | (1 << 11) | (CLKIN_USBPLL << 24); /* USBPLL/4 */
<> 144:ef7eb2e8f9f7 284 LPC_CGU->IDIV_CTRL[CLK_IDIV_D] = (1 << 2) | (1 << 11) | (CLKIN_IDIVA << 24); /* IDIVA/2 */
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 /* Configure remaining integer dividers */
<> 144:ef7eb2e8f9f7 287 LPC_CGU->IDIV_CTRL[CLK_IDIV_B] = (0 << 2) | (1 << 11) | (CLKIN_IRC << 24); /* IRC */
<> 144:ef7eb2e8f9f7 288 LPC_CGU->IDIV_CTRL[CLK_IDIV_C] = (1 << 2) | (1 << 11) | (CLKIN_MAINPLL << 24); /* PLL1/2 */
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 /* Connect base clocks */
<> 144:ef7eb2e8f9f7 291 for (i = 0; i < COUNT_OF(clock_states); i++) {
<> 144:ef7eb2e8f9f7 292 LPC_CGU->BASE_CLK[clock_states[i].clk] =
<> 144:ef7eb2e8f9f7 293 ( clock_states[i].powerdn << 0)
<> 144:ef7eb2e8f9f7 294 | (1 << 11) | (clock_states[i].clkin << 24);
<> 144:ef7eb2e8f9f7 295 }
<> 144:ef7eb2e8f9f7 296 #endif /* CLOCK_SETUP */
<> 144:ef7eb2e8f9f7 297 /* Reset peripherals */
<> 144:ef7eb2e8f9f7 298 LPC_RGU->RESET_CTRL0 = 0x105F0000;
<> 144:ef7eb2e8f9f7 299 LPC_RGU->RESET_CTRL1 = 0x01DFF7FF;
<> 144:ef7eb2e8f9f7 300 }
<> 144:ef7eb2e8f9f7 301
<> 144:ef7eb2e8f9f7 302 /*
<> 144:ef7eb2e8f9f7 303 * SystemSetupPins() - Configure MCU pins
<> 144:ef7eb2e8f9f7 304 */
<> 144:ef7eb2e8f9f7 305 void SystemSetupPins(const PINMUX_GRP_T *mux, uint32_t n)
<> 144:ef7eb2e8f9f7 306 {
<> 144:ef7eb2e8f9f7 307 uint32_t i;
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 for (i = 0; i < n; i++) {
<> 144:ef7eb2e8f9f7 310 *(mux[i].reg) = mux[i].mode;
<> 144:ef7eb2e8f9f7 311 }
<> 144:ef7eb2e8f9f7 312 }
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 /*
<> 144:ef7eb2e8f9f7 315 * SystemSetupMemory() - Configure external memory
<> 144:ef7eb2e8f9f7 316 */
<> 144:ef7eb2e8f9f7 317 void SystemSetupMemory(void)
<> 144:ef7eb2e8f9f7 318 {
<> 144:ef7eb2e8f9f7 319 #if (MEMORY_SETUP)
<> 144:ef7eb2e8f9f7 320 /* None required for boards without external memory */
<> 144:ef7eb2e8f9f7 321 #endif /* MEMORY_SETUP */
<> 144:ef7eb2e8f9f7 322 }
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 #if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
<> 144:ef7eb2e8f9f7 325 /*
<> 144:ef7eb2e8f9f7 326 * fpuInit() - Early initialization of the FPU
<> 144:ef7eb2e8f9f7 327 */
<> 144:ef7eb2e8f9f7 328 void fpuInit(void)
<> 144:ef7eb2e8f9f7 329 {
<> 144:ef7eb2e8f9f7 330 /*
<> 144:ef7eb2e8f9f7 331 * from ARM TRM manual:
<> 144:ef7eb2e8f9f7 332 * ; CPACR is located at address 0xE000ED88
<> 144:ef7eb2e8f9f7 333 * LDR.W R0, =0xE000ED88
<> 144:ef7eb2e8f9f7 334 * ; Read CPACR
<> 144:ef7eb2e8f9f7 335 * LDR R1, [R0]
<> 144:ef7eb2e8f9f7 336 * ; Set bits 20-23 to enable CP10 and CP11 coprocessors
<> 144:ef7eb2e8f9f7 337 * ORR R1, R1, #(0xF << 20)
<> 144:ef7eb2e8f9f7 338 * ; Write back the modified value to the CPACR
<> 144:ef7eb2e8f9f7 339 * STR R1, [R0]
<> 144:ef7eb2e8f9f7 340 */
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342 volatile uint32_t *regCpacr = (uint32_t *) LPC_CPACR;
<> 144:ef7eb2e8f9f7 343 volatile uint32_t *regMvfr0 = (uint32_t *) SCB_MVFR0;
<> 144:ef7eb2e8f9f7 344 volatile uint32_t *regMvfr1 = (uint32_t *) SCB_MVFR1;
<> 144:ef7eb2e8f9f7 345 volatile uint32_t Cpacr;
<> 144:ef7eb2e8f9f7 346 volatile uint32_t Mvfr0;
<> 144:ef7eb2e8f9f7 347 volatile uint32_t Mvfr1;
<> 144:ef7eb2e8f9f7 348 char vfpPresent = 0;
<> 144:ef7eb2e8f9f7 349
<> 144:ef7eb2e8f9f7 350 Mvfr0 = *regMvfr0;
<> 144:ef7eb2e8f9f7 351 Mvfr1 = *regMvfr1;
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 vfpPresent = ((SCB_MVFR0_RESET == Mvfr0) && (SCB_MVFR1_RESET == Mvfr1));
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 if (vfpPresent) {
<> 144:ef7eb2e8f9f7 356 Cpacr = *regCpacr;
<> 144:ef7eb2e8f9f7 357 Cpacr |= (0xF << 20);
<> 144:ef7eb2e8f9f7 358 *regCpacr = Cpacr; /* enable CP10 and CP11 for full access */
<> 144:ef7eb2e8f9f7 359 }
<> 144:ef7eb2e8f9f7 360 }
<> 144:ef7eb2e8f9f7 361 #endif /* defined(__FPU_PRESENT) && __FPU_PRESENT == 1 */
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 /* Approximate delay function */
<> 144:ef7eb2e8f9f7 364 #define CPU_NANOSEC(x) (((uint64_t) (x) * SystemCoreClock) / 1000000000)
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366 static void WaitUs(uint32_t us)
<> 144:ef7eb2e8f9f7 367 {
<> 144:ef7eb2e8f9f7 368 volatile uint32_t cyc = us * CPU_NANOSEC(1000) / 4;
<> 144:ef7eb2e8f9f7 369 while (cyc--)
<> 144:ef7eb2e8f9f7 370 ;
<> 144:ef7eb2e8f9f7 371 }
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 #endif /* !defined(CORE_M0) */