Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_NXP/TARGET_LPC23XX/vector_defns.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
0:9b334a45a8ff 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library - Vectors
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2009 ARM Limited. All rights reserved.
<> 144:ef7eb2e8f9f7 3 */
<> 144:ef7eb2e8f9f7 4
<> 144:ef7eb2e8f9f7 5 #ifndef MBED_VECTOR_DEFNS_H
<> 144:ef7eb2e8f9f7 6 #define MBED_VECTOR_DEFNS_H
<> 144:ef7eb2e8f9f7 7
<> 144:ef7eb2e8f9f7 8 // Assember Macros
<> 144:ef7eb2e8f9f7 9 #ifdef __ARMCC_VERSION
<> 144:ef7eb2e8f9f7 10 #define EXPORT(x) EXPORT x
<> 144:ef7eb2e8f9f7 11 #define WEAK_EXPORT(x) EXPORT x [WEAK]
<> 144:ef7eb2e8f9f7 12 #define IMPORT(x) IMPORT x
<> 144:ef7eb2e8f9f7 13 #define LABEL(x) x
<> 144:ef7eb2e8f9f7 14 #else
<> 144:ef7eb2e8f9f7 15 #define EXPORT(x) .global x
<> 144:ef7eb2e8f9f7 16 #define WEAK_EXPORT(x) .weak x
<> 144:ef7eb2e8f9f7 17 #define IMPORT(x) .global x
<> 144:ef7eb2e8f9f7 18 #define LABEL(x) x:
<> 144:ef7eb2e8f9f7 19 #endif
<> 144:ef7eb2e8f9f7 20
<> 144:ef7eb2e8f9f7 21 // RealMonitor
<> 144:ef7eb2e8f9f7 22 // Requires RAM (0x40000040-0x4000011F) to be allocated by the linker
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 // RealMonitor entry points
<> 144:ef7eb2e8f9f7 25 #define rm_init_entry 0x7fffff91
<> 144:ef7eb2e8f9f7 26 #define rm_undef_handler 0x7fffffa0
<> 144:ef7eb2e8f9f7 27 #define rm_prefetchabort_handler 0x7fffffb0
<> 144:ef7eb2e8f9f7 28 #define rm_dataabort_handler 0x7fffffc0
<> 144:ef7eb2e8f9f7 29 #define rm_irqhandler2 0x7fffffe0
<> 144:ef7eb2e8f9f7 30 //#define rm_RunningToStopped 0x7ffff808 // ARM - MBED64
<> 144:ef7eb2e8f9f7 31 #define rm_RunningToStopped 0x7ffff820 // ARM - PHAT40
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 // Unofficial RealMonitor entry points and variables
<> 144:ef7eb2e8f9f7 34 #define RM_MSG_SWI 0x00940000
<> 144:ef7eb2e8f9f7 35 #define StateP 0x40000040
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 // VIC register addresses
<> 144:ef7eb2e8f9f7 38 #define VIC_Base 0xfffff000
<> 144:ef7eb2e8f9f7 39 #define VICAddress_Offset 0xf00
<> 144:ef7eb2e8f9f7 40 #define VICVectAddr0_Offset 0x100
<> 144:ef7eb2e8f9f7 41 #define VICVectAddr2_Offset 0x108
<> 144:ef7eb2e8f9f7 42 #define VICVectAddr3_Offset 0x10c
<> 144:ef7eb2e8f9f7 43 #define VICVectAddr31_Offset 0x17c
<> 144:ef7eb2e8f9f7 44 #define VICIntEnClr_Offset 0x014
<> 144:ef7eb2e8f9f7 45 #define VICIntEnClr (*(volatile unsigned long *)(VIC_Base + 0x014))
<> 144:ef7eb2e8f9f7 46 #define VICVectAddr2 (*(volatile unsigned long *)(VIC_Base + 0x108))
<> 144:ef7eb2e8f9f7 47 #define VICVectAddr3 (*(volatile unsigned long *)(VIC_Base + 0x10C))
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 // ARM Mode bits and Interrupt flags in PSRs
<> 144:ef7eb2e8f9f7 50 #define Mode_USR 0x10
<> 144:ef7eb2e8f9f7 51 #define Mode_FIQ 0x11
<> 144:ef7eb2e8f9f7 52 #define Mode_IRQ 0x12
<> 144:ef7eb2e8f9f7 53 #define Mode_SVC 0x13
<> 144:ef7eb2e8f9f7 54 #define Mode_ABT 0x17
<> 144:ef7eb2e8f9f7 55 #define Mode_UND 0x1B
<> 144:ef7eb2e8f9f7 56 #define Mode_SYS 0x1F
<> 144:ef7eb2e8f9f7 57 #define I_Bit 0x80 // when I bit is set, IRQ is disabled
<> 144:ef7eb2e8f9f7 58 #define F_Bit 0x40 // when F bit is set, FIQ is disabled
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 // MCU RAM
<> 144:ef7eb2e8f9f7 61 #define LPC2368_RAM_ADDRESS 0x40000000 // RAM Base
<> 144:ef7eb2e8f9f7 62 #define LPC2368_RAM_SIZE 0x8000 // 32KB
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 // ISR Stack Allocation
<> 144:ef7eb2e8f9f7 65 #define UND_stack_size 0x00000040
<> 144:ef7eb2e8f9f7 66 #define SVC_stack_size 0x00000040
<> 144:ef7eb2e8f9f7 67 #define ABT_stack_size 0x00000040
<> 144:ef7eb2e8f9f7 68 #define FIQ_stack_size 0x00000000
<> 144:ef7eb2e8f9f7 69 #define IRQ_stack_size 0x00000040
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 #define ISR_stack_size (UND_stack_size + SVC_stack_size + ABT_stack_size + FIQ_stack_size + IRQ_stack_size)
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 // Full Descending Stack, so top-most stack points to just above the top of RAM
<> 144:ef7eb2e8f9f7 74 #define LPC2368_STACK_TOP (LPC2368_RAM_ADDRESS + LPC2368_RAM_SIZE)
<> 144:ef7eb2e8f9f7 75 #define USR_STACK_TOP (LPC2368_STACK_TOP - ISR_stack_size)
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 #endif