Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pwrman_regs.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
0:9b334a45a8ff 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*******************************************************************************
<> 144:ef7eb2e8f9f7 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 144:ef7eb2e8f9f7 5 * copy of this software and associated documentation files (the "Software"),
<> 144:ef7eb2e8f9f7 6 * to deal in the Software without restriction, including without limitation
<> 144:ef7eb2e8f9f7 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 144:ef7eb2e8f9f7 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 144:ef7eb2e8f9f7 9 * Software is furnished to do so, subject to the following conditions:
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * The above copyright notice and this permission notice shall be included
<> 144:ef7eb2e8f9f7 12 * in all copies or substantial portions of the Software.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 144:ef7eb2e8f9f7 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 144:ef7eb2e8f9f7 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 144:ef7eb2e8f9f7 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 144:ef7eb2e8f9f7 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 144:ef7eb2e8f9f7 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * Except as contained in this notice, the name of Maxim Integrated
<> 144:ef7eb2e8f9f7 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 144:ef7eb2e8f9f7 24 * Products, Inc. Branding Policy.
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * The mere transfer of this software does not imply any licenses
<> 144:ef7eb2e8f9f7 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 144:ef7eb2e8f9f7 28 * trademarks, maskwork rights, or any other form of intellectual
<> 144:ef7eb2e8f9f7 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 144:ef7eb2e8f9f7 30 * ownership rights.
<> 144:ef7eb2e8f9f7 31 *******************************************************************************
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #ifndef _MXC_PWRMAN_REGS_H_
<> 144:ef7eb2e8f9f7 35 #define _MXC_PWRMAN_REGS_H_
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 38 extern "C" {
<> 144:ef7eb2e8f9f7 39 #endif
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 #include <stdint.h>
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /**
<> 144:ef7eb2e8f9f7 44 * @file pwrman_regs.h
<> 144:ef7eb2e8f9f7 45 * @addtogroup pwrman PWRMAN
<> 144:ef7eb2e8f9f7 46 * @{
<> 144:ef7eb2e8f9f7 47 */
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /**
<> 144:ef7eb2e8f9f7 50 * @brief Defines PAD Modes for Wake Up Detection.
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52 typedef enum {
<> 144:ef7eb2e8f9f7 53 /** WUD Mode for Selected PAD = Clear/Activate */
<> 144:ef7eb2e8f9f7 54 MXC_E_PWRMAN_PAD_MODE_CLEAR_SET,
<> 144:ef7eb2e8f9f7 55 /** WUD Mode for Selected PAD = Set WUD Act Hi/Set WUD Act Lo */
<> 144:ef7eb2e8f9f7 56 MXC_E_PWRMAN_PAD_MODE_ACT_HI_LO,
<> 144:ef7eb2e8f9f7 57 /** WUD Mode for Selected PAD = Set Weak Hi/ Set Weak Lo */
<> 144:ef7eb2e8f9f7 58 MXC_E_PWRMAN_PAD_MODE_WEAK_HI_LO,
<> 144:ef7eb2e8f9f7 59 /** WUD Mode for Selected PAD = No pad state change */
<> 144:ef7eb2e8f9f7 60 MXC_E_PWRMAN_PAD_MODE_NONE
<> 144:ef7eb2e8f9f7 61 } mxc_pwrman_pad_mode_t;
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /* Offset Register Description
<> 144:ef7eb2e8f9f7 64 ====== =========================================== */
<> 144:ef7eb2e8f9f7 65 typedef struct {
<> 144:ef7eb2e8f9f7 66 __IO uint32_t pwr_rst_ctrl; /* 0x0000 Power Reset Control and Status */
<> 144:ef7eb2e8f9f7 67 __IO uint32_t intfl; /* 0x0004 Interrupt Flags */
<> 144:ef7eb2e8f9f7 68 __IO uint32_t inten; /* 0x0008 Interrupt Enable/Disable Controls */
<> 144:ef7eb2e8f9f7 69 __IO uint32_t svm_events; /* 0x000C SVM Event Status Flags (read-only) */
<> 144:ef7eb2e8f9f7 70 __IO uint32_t wud_ctrl; /* 0x0010 Wake-Up Detect Control */
<> 144:ef7eb2e8f9f7 71 __IO uint32_t wud_pulse0; /* 0x0014 WUD Pulse To Mode Bit 0 */
<> 144:ef7eb2e8f9f7 72 __IO uint32_t wud_pulse1; /* 0x0018 WUD Pulse To Mode Bit 1 */
<> 144:ef7eb2e8f9f7 73 __I uint32_t rsv001C[5]; /* 0x001C */
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 __IO uint32_t wud_seen0; /* 0x0030 Wake-up Detect Status for P0/P1/P2/P3 */
<> 144:ef7eb2e8f9f7 76 __IO uint32_t wud_seen1; /* 0x0034 Wake-up Detect Status for P4/P5/P6/P7 */
<> 144:ef7eb2e8f9f7 77 __IO uint32_t die_type; /* 0x0038 Die ID Register (Device Type) */
<> 144:ef7eb2e8f9f7 78 __IO uint32_t base_part_num; /* 0x003C Base Part Number */
<> 144:ef7eb2e8f9f7 79 __IO uint32_t mask_id0; /* 0x0040 Mask ID Register 0 */
<> 144:ef7eb2e8f9f7 80 __IO uint32_t mask_id1; /* 0x0044 Mask ID Register 1 */
<> 144:ef7eb2e8f9f7 81 __IO uint32_t peripheral_reset; /* 0x0048 Peripheral Reset Control Register */
<> 144:ef7eb2e8f9f7 82 } mxc_pwrman_regs_t;
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 /*
<> 144:ef7eb2e8f9f7 85 Register offsets for module PWRMAN.
<> 144:ef7eb2e8f9f7 86 */
<> 144:ef7eb2e8f9f7 87 #define MXC_R_PWRMAN_OFFS_PWR_RST_CTRL ((uint32_t)0x00000000UL)
<> 144:ef7eb2e8f9f7 88 #define MXC_R_PWRMAN_OFFS_INTFL ((uint32_t)0x00000004UL)
<> 144:ef7eb2e8f9f7 89 #define MXC_R_PWRMAN_OFFS_INTEN ((uint32_t)0x00000008UL)
<> 144:ef7eb2e8f9f7 90 #define MXC_R_PWRMAN_OFFS_SVM_EVENTS ((uint32_t)0x0000000CUL)
<> 144:ef7eb2e8f9f7 91 #define MXC_R_PWRMAN_OFFS_WUD_CTRL ((uint32_t)0x00000010UL)
<> 144:ef7eb2e8f9f7 92 #define MXC_R_PWRMAN_OFFS_WUD_PULSE0 ((uint32_t)0x00000014UL)
<> 144:ef7eb2e8f9f7 93 #define MXC_R_PWRMAN_OFFS_WUD_PULSE1 ((uint32_t)0x00000018UL)
<> 144:ef7eb2e8f9f7 94 #define MXC_R_PWRMAN_OFFS_WUD_SEEN0 ((uint32_t)0x00000030UL)
<> 144:ef7eb2e8f9f7 95 #define MXC_R_PWRMAN_OFFS_WUD_SEEN1 ((uint32_t)0x00000034UL)
<> 144:ef7eb2e8f9f7 96 #define MXC_R_PWRMAN_OFFS_DIE_TYPE ((uint32_t)0x00000038UL)
<> 144:ef7eb2e8f9f7 97 #define MXC_R_PWRMAN_OFFS_BASE_PART_NUM ((uint32_t)0x0000003CUL)
<> 144:ef7eb2e8f9f7 98 #define MXC_R_PWRMAN_OFFS_MASK_ID0 ((uint32_t)0x00000040UL)
<> 144:ef7eb2e8f9f7 99 #define MXC_R_PWRMAN_OFFS_MASK_ID1 ((uint32_t)0x00000044UL)
<> 144:ef7eb2e8f9f7 100 #define MXC_R_PWRMAN_OFFS_PERIPHERAL_RESET ((uint32_t)0x00000048UL)
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 /*
<> 144:ef7eb2e8f9f7 103 Field positions and masks for module PWRMAN.
<> 144:ef7eb2e8f9f7 104 */
<> 144:ef7eb2e8f9f7 105 #define MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE_POS 0
<> 144:ef7eb2e8f9f7 106 #define MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE_POS))
<> 144:ef7eb2e8f9f7 107 #define MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE_POS 1
<> 144:ef7eb2e8f9f7 108 #define MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE_POS))
<> 144:ef7eb2e8f9f7 109 #define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS 2
<> 144:ef7eb2e8f9f7 110 #define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS))
<> 144:ef7eb2e8f9f7 111 #define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS 3
<> 144:ef7eb2e8f9f7 112 #define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS))
<> 144:ef7eb2e8f9f7 113 #define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS 4
<> 144:ef7eb2e8f9f7 114 #define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS))
<> 144:ef7eb2e8f9f7 115 #define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS 5
<> 144:ef7eb2e8f9f7 116 #define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS))
<> 144:ef7eb2e8f9f7 117 #define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS 8
<> 144:ef7eb2e8f9f7 118 #define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS))
<> 144:ef7eb2e8f9f7 119 #define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS 9
<> 144:ef7eb2e8f9f7 120 #define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS))
<> 144:ef7eb2e8f9f7 121 #define MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR_POS 12
<> 144:ef7eb2e8f9f7 122 #define MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR_POS))
<> 144:ef7eb2e8f9f7 123 #define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS 16
<> 144:ef7eb2e8f9f7 124 #define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS))
<> 144:ef7eb2e8f9f7 125 #define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS 17
<> 144:ef7eb2e8f9f7 126 #define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS))
<> 144:ef7eb2e8f9f7 127 #define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS 18
<> 144:ef7eb2e8f9f7 128 #define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS))
<> 144:ef7eb2e8f9f7 129 #define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS 19
<> 144:ef7eb2e8f9f7 130 #define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS))
<> 144:ef7eb2e8f9f7 131 #define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS 20
<> 144:ef7eb2e8f9f7 132 #define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS))
<> 144:ef7eb2e8f9f7 133 #define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS 21
<> 144:ef7eb2e8f9f7 134 #define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS))
<> 144:ef7eb2e8f9f7 135 #define MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS 22
<> 144:ef7eb2e8f9f7 136 #define MXC_F_PWRMAN_PWR_RST_CTRL_POR ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS))
<> 144:ef7eb2e8f9f7 137 #define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS 31
<> 144:ef7eb2e8f9f7 138 #define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS))
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 #define MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS 0
<> 144:ef7eb2e8f9f7 141 #define MXC_F_PWRMAN_INTFL_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS))
<> 144:ef7eb2e8f9f7 142 #define MXC_F_PWRMAN_INTFL_V3_3_WARNING_POS 1
<> 144:ef7eb2e8f9f7 143 #define MXC_F_PWRMAN_INTFL_V3_3_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V3_3_WARNING_POS))
<> 144:ef7eb2e8f9f7 144 #define MXC_F_PWRMAN_INTFL_RTC_WARNING_POS 2
<> 144:ef7eb2e8f9f7 145 #define MXC_F_PWRMAN_INTFL_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_RTC_WARNING_POS))
<> 144:ef7eb2e8f9f7 146 #define MXC_F_PWRMAN_INTFL_V3_3_RESET_POS 3
<> 144:ef7eb2e8f9f7 147 #define MXC_F_PWRMAN_INTFL_V3_3_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V3_3_RESET_POS))
<> 144:ef7eb2e8f9f7 148 #define MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS 4
<> 144:ef7eb2e8f9f7 149 #define MXC_F_PWRMAN_INTFL_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS))
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 #define MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS 0
<> 144:ef7eb2e8f9f7 152 #define MXC_F_PWRMAN_INTEN_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS))
<> 144:ef7eb2e8f9f7 153 #define MXC_F_PWRMAN_INTEN_V3_3_WARNING_POS 1
<> 144:ef7eb2e8f9f7 154 #define MXC_F_PWRMAN_INTEN_V3_3_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V3_3_WARNING_POS))
<> 144:ef7eb2e8f9f7 155 #define MXC_F_PWRMAN_INTEN_RTC_WARNING_POS 2
<> 144:ef7eb2e8f9f7 156 #define MXC_F_PWRMAN_INTEN_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_RTC_WARNING_POS))
<> 144:ef7eb2e8f9f7 157 #define MXC_F_PWRMAN_INTEN_V3_3_RESET_POS 3
<> 144:ef7eb2e8f9f7 158 #define MXC_F_PWRMAN_INTEN_V3_3_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V3_3_RESET_POS))
<> 144:ef7eb2e8f9f7 159 #define MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS 4
<> 144:ef7eb2e8f9f7 160 #define MXC_F_PWRMAN_INTEN_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS))
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 #define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS 0
<> 144:ef7eb2e8f9f7 163 #define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS))
<> 144:ef7eb2e8f9f7 164 #define MXC_F_PWRMAN_SVM_EVENTS_V3_3_WARNING_POS 1
<> 144:ef7eb2e8f9f7 165 #define MXC_F_PWRMAN_SVM_EVENTS_V3_3_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V3_3_WARNING_POS))
<> 144:ef7eb2e8f9f7 166 #define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS 2
<> 144:ef7eb2e8f9f7 167 #define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS))
<> 144:ef7eb2e8f9f7 168 #define MXC_F_PWRMAN_SVM_EVENTS_V3_3_RESET_POS 3
<> 144:ef7eb2e8f9f7 169 #define MXC_F_PWRMAN_SVM_EVENTS_V3_3_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V3_3_RESET_POS))
<> 144:ef7eb2e8f9f7 170 #define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS 4
<> 144:ef7eb2e8f9f7 171 #define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS))
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 #define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS 0
<> 144:ef7eb2e8f9f7 174 #define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT ((uint32_t)(0x0000003FUL << MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS))
<> 144:ef7eb2e8f9f7 175 #define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS 8
<> 144:ef7eb2e8f9f7 176 #define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE ((uint32_t)(0x00000003UL << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS))
<> 144:ef7eb2e8f9f7 177 #define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS 12
<> 144:ef7eb2e8f9f7 178 #define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS))
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS 0
<> 144:ef7eb2e8f9f7 181 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS))
<> 144:ef7eb2e8f9f7 182 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS 1
<> 144:ef7eb2e8f9f7 183 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS))
<> 144:ef7eb2e8f9f7 184 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS 2
<> 144:ef7eb2e8f9f7 185 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS))
<> 144:ef7eb2e8f9f7 186 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS 3
<> 144:ef7eb2e8f9f7 187 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS))
<> 144:ef7eb2e8f9f7 188 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS 4
<> 144:ef7eb2e8f9f7 189 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO4 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS))
<> 144:ef7eb2e8f9f7 190 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS 5
<> 144:ef7eb2e8f9f7 191 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO5 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS))
<> 144:ef7eb2e8f9f7 192 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS 6
<> 144:ef7eb2e8f9f7 193 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO6 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS))
<> 144:ef7eb2e8f9f7 194 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS 7
<> 144:ef7eb2e8f9f7 195 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO7 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS))
<> 144:ef7eb2e8f9f7 196 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS 8
<> 144:ef7eb2e8f9f7 197 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO8 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS))
<> 144:ef7eb2e8f9f7 198 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS 9
<> 144:ef7eb2e8f9f7 199 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO9 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS))
<> 144:ef7eb2e8f9f7 200 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS 10
<> 144:ef7eb2e8f9f7 201 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO10 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS))
<> 144:ef7eb2e8f9f7 202 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS 11
<> 144:ef7eb2e8f9f7 203 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO11 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS))
<> 144:ef7eb2e8f9f7 204 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS 12
<> 144:ef7eb2e8f9f7 205 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO12 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS))
<> 144:ef7eb2e8f9f7 206 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS 13
<> 144:ef7eb2e8f9f7 207 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO13 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS))
<> 144:ef7eb2e8f9f7 208 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS 14
<> 144:ef7eb2e8f9f7 209 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO14 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS))
<> 144:ef7eb2e8f9f7 210 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS 15
<> 144:ef7eb2e8f9f7 211 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO15 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS))
<> 144:ef7eb2e8f9f7 212 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS 16
<> 144:ef7eb2e8f9f7 213 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO16 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS))
<> 144:ef7eb2e8f9f7 214 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS 17
<> 144:ef7eb2e8f9f7 215 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO17 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS))
<> 144:ef7eb2e8f9f7 216 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS 18
<> 144:ef7eb2e8f9f7 217 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO18 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS))
<> 144:ef7eb2e8f9f7 218 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS 19
<> 144:ef7eb2e8f9f7 219 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO19 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS))
<> 144:ef7eb2e8f9f7 220 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS 20
<> 144:ef7eb2e8f9f7 221 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO20 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS))
<> 144:ef7eb2e8f9f7 222 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS 21
<> 144:ef7eb2e8f9f7 223 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO21 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS))
<> 144:ef7eb2e8f9f7 224 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS 22
<> 144:ef7eb2e8f9f7 225 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO22 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS))
<> 144:ef7eb2e8f9f7 226 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS 23
<> 144:ef7eb2e8f9f7 227 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO23 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS))
<> 144:ef7eb2e8f9f7 228 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS 24
<> 144:ef7eb2e8f9f7 229 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO24 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS))
<> 144:ef7eb2e8f9f7 230 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS 25
<> 144:ef7eb2e8f9f7 231 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO25 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS))
<> 144:ef7eb2e8f9f7 232 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS 26
<> 144:ef7eb2e8f9f7 233 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO26 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS))
<> 144:ef7eb2e8f9f7 234 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS 27
<> 144:ef7eb2e8f9f7 235 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO27 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS))
<> 144:ef7eb2e8f9f7 236 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS 28
<> 144:ef7eb2e8f9f7 237 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO28 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS))
<> 144:ef7eb2e8f9f7 238 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS 29
<> 144:ef7eb2e8f9f7 239 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO29 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS))
<> 144:ef7eb2e8f9f7 240 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS 30
<> 144:ef7eb2e8f9f7 241 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO30 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS))
<> 144:ef7eb2e8f9f7 242 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS 31
<> 144:ef7eb2e8f9f7 243 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO31 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS))
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS 0
<> 144:ef7eb2e8f9f7 246 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO32 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS))
<> 144:ef7eb2e8f9f7 247 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS 1
<> 144:ef7eb2e8f9f7 248 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO33 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS))
<> 144:ef7eb2e8f9f7 249 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS 2
<> 144:ef7eb2e8f9f7 250 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO34 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS))
<> 144:ef7eb2e8f9f7 251 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS 3
<> 144:ef7eb2e8f9f7 252 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO35 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS))
<> 144:ef7eb2e8f9f7 253 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS 4
<> 144:ef7eb2e8f9f7 254 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO36 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS))
<> 144:ef7eb2e8f9f7 255 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS 5
<> 144:ef7eb2e8f9f7 256 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO37 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS))
<> 144:ef7eb2e8f9f7 257 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS 6
<> 144:ef7eb2e8f9f7 258 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO38 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS))
<> 144:ef7eb2e8f9f7 259 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS 7
<> 144:ef7eb2e8f9f7 260 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO39 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS))
<> 144:ef7eb2e8f9f7 261 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO40_POS 8
<> 144:ef7eb2e8f9f7 262 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO40 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO40_POS))
<> 144:ef7eb2e8f9f7 263 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO41_POS 9
<> 144:ef7eb2e8f9f7 264 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO41 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO41_POS))
<> 144:ef7eb2e8f9f7 265 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO42_POS 10
<> 144:ef7eb2e8f9f7 266 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO42 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO42_POS))
<> 144:ef7eb2e8f9f7 267 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO43_POS 11
<> 144:ef7eb2e8f9f7 268 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO43 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO43_POS))
<> 144:ef7eb2e8f9f7 269 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO44_POS 12
<> 144:ef7eb2e8f9f7 270 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO44 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO44_POS))
<> 144:ef7eb2e8f9f7 271 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO45_POS 13
<> 144:ef7eb2e8f9f7 272 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO45 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO45_POS))
<> 144:ef7eb2e8f9f7 273 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO46_POS 14
<> 144:ef7eb2e8f9f7 274 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO46 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO46_POS))
<> 144:ef7eb2e8f9f7 275 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO47_POS 15
<> 144:ef7eb2e8f9f7 276 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO47 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO47_POS))
<> 144:ef7eb2e8f9f7 277 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO48_POS 16
<> 144:ef7eb2e8f9f7 278 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO48 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO48_POS))
<> 144:ef7eb2e8f9f7 279 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO49_POS 17
<> 144:ef7eb2e8f9f7 280 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO49 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO49_POS))
<> 144:ef7eb2e8f9f7 281 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO50_POS 18
<> 144:ef7eb2e8f9f7 282 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO50 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO50_POS))
<> 144:ef7eb2e8f9f7 283 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO51_POS 19
<> 144:ef7eb2e8f9f7 284 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO51 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO51_POS))
<> 144:ef7eb2e8f9f7 285 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO52_POS 20
<> 144:ef7eb2e8f9f7 286 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO52 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO52_POS))
<> 144:ef7eb2e8f9f7 287 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO53_POS 21
<> 144:ef7eb2e8f9f7 288 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO53 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO53_POS))
<> 144:ef7eb2e8f9f7 289 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO54_POS 22
<> 144:ef7eb2e8f9f7 290 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO54 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO54_POS))
<> 144:ef7eb2e8f9f7 291 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO55_POS 23
<> 144:ef7eb2e8f9f7 292 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO55 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO55_POS))
<> 144:ef7eb2e8f9f7 293 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO56_POS 24
<> 144:ef7eb2e8f9f7 294 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO56 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO56_POS))
<> 144:ef7eb2e8f9f7 295 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO57_POS 25
<> 144:ef7eb2e8f9f7 296 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO57 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO57_POS))
<> 144:ef7eb2e8f9f7 297 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO58_POS 26
<> 144:ef7eb2e8f9f7 298 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO58 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO58_POS))
<> 144:ef7eb2e8f9f7 299 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO59_POS 27
<> 144:ef7eb2e8f9f7 300 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO59 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO59_POS))
<> 144:ef7eb2e8f9f7 301 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO60_POS 28
<> 144:ef7eb2e8f9f7 302 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO60 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO60_POS))
<> 144:ef7eb2e8f9f7 303 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO61_POS 29
<> 144:ef7eb2e8f9f7 304 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO61 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO61_POS))
<> 144:ef7eb2e8f9f7 305 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO62_POS 30
<> 144:ef7eb2e8f9f7 306 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO62 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO62_POS))
<> 144:ef7eb2e8f9f7 307 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO63_POS 31
<> 144:ef7eb2e8f9f7 308 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO63 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO63_POS))
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 #define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS 0
<> 144:ef7eb2e8f9f7 311 #define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER ((uint32_t)(0x0000FFFFUL << MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS))
<> 144:ef7eb2e8f9f7 312 #define MXC_F_PWRMAN_BASE_PART_NUM_PACKAGE_SELECT_POS 28
<> 144:ef7eb2e8f9f7 313 #define MXC_F_PWRMAN_BASE_PART_NUM_PACKAGE_SELECT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_BASE_PART_NUM_PACKAGE_SELECT_POS))
<> 144:ef7eb2e8f9f7 314
<> 144:ef7eb2e8f9f7 315 #define MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS 0
<> 144:ef7eb2e8f9f7 316 #define MXC_F_PWRMAN_MASK_ID0_REVISION_ID ((uint32_t)(0x0000000FUL << MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS))
<> 144:ef7eb2e8f9f7 317 #define MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS 4
<> 144:ef7eb2e8f9f7 318 #define MXC_F_PWRMAN_MASK_ID0_MASK_ID ((uint32_t)(0x0FFFFFFFUL << MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS))
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320 #define MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS 0
<> 144:ef7eb2e8f9f7 321 #define MXC_F_PWRMAN_MASK_ID1_MASK_ID ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS))
<> 144:ef7eb2e8f9f7 322 #define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS 31
<> 144:ef7eb2e8f9f7 323 #define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS))
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS 0
<> 144:ef7eb2e8f9f7 326 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS))
<> 144:ef7eb2e8f9f7 327 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS 1
<> 144:ef7eb2e8f9f7 328 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS))
<> 144:ef7eb2e8f9f7 329 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS 2
<> 144:ef7eb2e8f9f7 330 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS))
<> 144:ef7eb2e8f9f7 331 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS 3
<> 144:ef7eb2e8f9f7 332 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS))
<> 144:ef7eb2e8f9f7 333 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS 4
<> 144:ef7eb2e8f9f7 334 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS))
<> 144:ef7eb2e8f9f7 335 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS 5
<> 144:ef7eb2e8f9f7 336 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS))
<> 144:ef7eb2e8f9f7 337 #define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS 6
<> 144:ef7eb2e8f9f7 338 #define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS))
<> 144:ef7eb2e8f9f7 339 #define MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS 7
<> 144:ef7eb2e8f9f7 340 #define MXC_F_PWRMAN_PERIPHERAL_RESET_USB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS))
<> 144:ef7eb2e8f9f7 341 #define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS 8
<> 144:ef7eb2e8f9f7 342 #define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS))
<> 144:ef7eb2e8f9f7 343 #define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC0_POS 9
<> 144:ef7eb2e8f9f7 344 #define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC0_POS))
<> 144:ef7eb2e8f9f7 345 #define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC1_POS 10
<> 144:ef7eb2e8f9f7 346 #define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC1_POS))
<> 144:ef7eb2e8f9f7 347 #define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC2_POS 11
<> 144:ef7eb2e8f9f7 348 #define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC2_POS))
<> 144:ef7eb2e8f9f7 349 #define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC3_POS 12
<> 144:ef7eb2e8f9f7 350 #define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC3_POS))
<> 144:ef7eb2e8f9f7 351 #define MXC_F_PWRMAN_PERIPHERAL_RESET_DMA_POS 13
<> 144:ef7eb2e8f9f7 352 #define MXC_F_PWRMAN_PERIPHERAL_RESET_DMA ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DMA_POS))
<> 144:ef7eb2e8f9f7 353 #define MXC_F_PWRMAN_PERIPHERAL_RESET_LCD_POS 14
<> 144:ef7eb2e8f9f7 354 #define MXC_F_PWRMAN_PERIPHERAL_RESET_LCD ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_LCD_POS))
<> 144:ef7eb2e8f9f7 355 #define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS 15
<> 144:ef7eb2e8f9f7 356 #define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS))
<> 144:ef7eb2e8f9f7 357 #define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS 16
<> 144:ef7eb2e8f9f7 358 #define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS))
<> 144:ef7eb2e8f9f7 359 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI0_POS 17
<> 144:ef7eb2e8f9f7 360 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPI0_POS))
<> 144:ef7eb2e8f9f7 361 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI1_POS 18
<> 144:ef7eb2e8f9f7 362 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPI1_POS))
<> 144:ef7eb2e8f9f7 363 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI2_POS 19
<> 144:ef7eb2e8f9f7 364 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPI2_POS))
<> 144:ef7eb2e8f9f7 365 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS 20
<> 144:ef7eb2e8f9f7 366 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS))
<> 144:ef7eb2e8f9f7 367 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS 21
<> 144:ef7eb2e8f9f7 368 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS))
<> 144:ef7eb2e8f9f7 369 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS 22
<> 144:ef7eb2e8f9f7 370 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS))
<> 144:ef7eb2e8f9f7 371 #define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS 23
<> 144:ef7eb2e8f9f7 372 #define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS))
<> 144:ef7eb2e8f9f7 373 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS 24
<> 144:ef7eb2e8f9f7 374 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS))
<> 144:ef7eb2e8f9f7 375 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS 25
<> 144:ef7eb2e8f9f7 376 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS))
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 379 }
<> 144:ef7eb2e8f9f7 380 #endif
<> 144:ef7eb2e8f9f7 381
<> 144:ef7eb2e8f9f7 382 /**
<> 144:ef7eb2e8f9f7 383 * @}
<> 144:ef7eb2e8f9f7 384 */
<> 144:ef7eb2e8f9f7 385
<> 144:ef7eb2e8f9f7 386 #endif /* _MXC_PWRMAN_REGS_H_ */