Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pwrman_regs.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /*******************************************************************************
bogdanm 0:9b334a45a8ff 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
bogdanm 0:9b334a45a8ff 3 *
bogdanm 0:9b334a45a8ff 4 * Permission is hereby granted, free of charge, to any person obtaining a
bogdanm 0:9b334a45a8ff 5 * copy of this software and associated documentation files (the "Software"),
bogdanm 0:9b334a45a8ff 6 * to deal in the Software without restriction, including without limitation
bogdanm 0:9b334a45a8ff 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
bogdanm 0:9b334a45a8ff 8 * and/or sell copies of the Software, and to permit persons to whom the
bogdanm 0:9b334a45a8ff 9 * Software is furnished to do so, subject to the following conditions:
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 * The above copyright notice and this permission notice shall be included
bogdanm 0:9b334a45a8ff 12 * in all copies or substantial portions of the Software.
bogdanm 0:9b334a45a8ff 13 *
bogdanm 0:9b334a45a8ff 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
bogdanm 0:9b334a45a8ff 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
bogdanm 0:9b334a45a8ff 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
bogdanm 0:9b334a45a8ff 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
bogdanm 0:9b334a45a8ff 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
bogdanm 0:9b334a45a8ff 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
bogdanm 0:9b334a45a8ff 20 * OTHER DEALINGS IN THE SOFTWARE.
bogdanm 0:9b334a45a8ff 21 *
bogdanm 0:9b334a45a8ff 22 * Except as contained in this notice, the name of Maxim Integrated
bogdanm 0:9b334a45a8ff 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
bogdanm 0:9b334a45a8ff 24 * Products, Inc. Branding Policy.
bogdanm 0:9b334a45a8ff 25 *
bogdanm 0:9b334a45a8ff 26 * The mere transfer of this software does not imply any licenses
bogdanm 0:9b334a45a8ff 27 * of trade secrets, proprietary technology, copyrights, patents,
bogdanm 0:9b334a45a8ff 28 * trademarks, maskwork rights, or any other form of intellectual
bogdanm 0:9b334a45a8ff 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
bogdanm 0:9b334a45a8ff 30 * ownership rights.
bogdanm 0:9b334a45a8ff 31 *******************************************************************************
bogdanm 0:9b334a45a8ff 32 */
bogdanm 0:9b334a45a8ff 33
bogdanm 0:9b334a45a8ff 34 #ifndef _MXC_PWRMAN_REGS_H_
bogdanm 0:9b334a45a8ff 35 #define _MXC_PWRMAN_REGS_H_
bogdanm 0:9b334a45a8ff 36
bogdanm 0:9b334a45a8ff 37 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 38 extern "C" {
bogdanm 0:9b334a45a8ff 39 #endif
bogdanm 0:9b334a45a8ff 40
bogdanm 0:9b334a45a8ff 41 #include <stdint.h>
bogdanm 0:9b334a45a8ff 42
bogdanm 0:9b334a45a8ff 43 /**
bogdanm 0:9b334a45a8ff 44 * @file pwrman_regs.h
bogdanm 0:9b334a45a8ff 45 * @addtogroup pwrman PWRMAN
bogdanm 0:9b334a45a8ff 46 * @{
bogdanm 0:9b334a45a8ff 47 */
bogdanm 0:9b334a45a8ff 48
bogdanm 0:9b334a45a8ff 49 /**
bogdanm 0:9b334a45a8ff 50 * @brief Defines PAD Modes for Wake Up Detection.
bogdanm 0:9b334a45a8ff 51 */
bogdanm 0:9b334a45a8ff 52 typedef enum {
bogdanm 0:9b334a45a8ff 53 /** WUD Mode for Selected PAD = Clear/Activate */
bogdanm 0:9b334a45a8ff 54 MXC_E_PWRMAN_PAD_MODE_CLEAR_SET,
bogdanm 0:9b334a45a8ff 55 /** WUD Mode for Selected PAD = Set WUD Act Hi/Set WUD Act Lo */
bogdanm 0:9b334a45a8ff 56 MXC_E_PWRMAN_PAD_MODE_ACT_HI_LO,
bogdanm 0:9b334a45a8ff 57 /** WUD Mode for Selected PAD = Set Weak Hi/ Set Weak Lo */
bogdanm 0:9b334a45a8ff 58 MXC_E_PWRMAN_PAD_MODE_WEAK_HI_LO,
bogdanm 0:9b334a45a8ff 59 /** WUD Mode for Selected PAD = No pad state change */
bogdanm 0:9b334a45a8ff 60 MXC_E_PWRMAN_PAD_MODE_NONE
bogdanm 0:9b334a45a8ff 61 } mxc_pwrman_pad_mode_t;
bogdanm 0:9b334a45a8ff 62
bogdanm 0:9b334a45a8ff 63 /* Offset Register Description
bogdanm 0:9b334a45a8ff 64 ====== =========================================== */
bogdanm 0:9b334a45a8ff 65 typedef struct {
bogdanm 0:9b334a45a8ff 66 __IO uint32_t pwr_rst_ctrl; /* 0x0000 Power Reset Control and Status */
bogdanm 0:9b334a45a8ff 67 __IO uint32_t intfl; /* 0x0004 Interrupt Flags */
bogdanm 0:9b334a45a8ff 68 __IO uint32_t inten; /* 0x0008 Interrupt Enable/Disable Controls */
bogdanm 0:9b334a45a8ff 69 __IO uint32_t svm_events; /* 0x000C SVM Event Status Flags (read-only) */
bogdanm 0:9b334a45a8ff 70 __IO uint32_t wud_ctrl; /* 0x0010 Wake-Up Detect Control */
bogdanm 0:9b334a45a8ff 71 __IO uint32_t wud_pulse0; /* 0x0014 WUD Pulse To Mode Bit 0 */
bogdanm 0:9b334a45a8ff 72 __IO uint32_t wud_pulse1; /* 0x0018 WUD Pulse To Mode Bit 1 */
bogdanm 0:9b334a45a8ff 73 __I uint32_t rsv001C[5]; /* 0x001C */
bogdanm 0:9b334a45a8ff 74
bogdanm 0:9b334a45a8ff 75 __IO uint32_t wud_seen0; /* 0x0030 Wake-up Detect Status for P0/P1/P2/P3 */
bogdanm 0:9b334a45a8ff 76 __IO uint32_t wud_seen1; /* 0x0034 Wake-up Detect Status for P4/P5/P6/P7 */
bogdanm 0:9b334a45a8ff 77 __IO uint32_t die_type; /* 0x0038 Die ID Register (Device Type) */
bogdanm 0:9b334a45a8ff 78 __IO uint32_t base_part_num; /* 0x003C Base Part Number */
bogdanm 0:9b334a45a8ff 79 __IO uint32_t mask_id0; /* 0x0040 Mask ID Register 0 */
bogdanm 0:9b334a45a8ff 80 __IO uint32_t mask_id1; /* 0x0044 Mask ID Register 1 */
bogdanm 0:9b334a45a8ff 81 __IO uint32_t peripheral_reset; /* 0x0048 Peripheral Reset Control Register */
bogdanm 0:9b334a45a8ff 82 } mxc_pwrman_regs_t;
bogdanm 0:9b334a45a8ff 83
bogdanm 0:9b334a45a8ff 84 /*
bogdanm 0:9b334a45a8ff 85 Register offsets for module PWRMAN.
bogdanm 0:9b334a45a8ff 86 */
bogdanm 0:9b334a45a8ff 87 #define MXC_R_PWRMAN_OFFS_PWR_RST_CTRL ((uint32_t)0x00000000UL)
bogdanm 0:9b334a45a8ff 88 #define MXC_R_PWRMAN_OFFS_INTFL ((uint32_t)0x00000004UL)
bogdanm 0:9b334a45a8ff 89 #define MXC_R_PWRMAN_OFFS_INTEN ((uint32_t)0x00000008UL)
bogdanm 0:9b334a45a8ff 90 #define MXC_R_PWRMAN_OFFS_SVM_EVENTS ((uint32_t)0x0000000CUL)
bogdanm 0:9b334a45a8ff 91 #define MXC_R_PWRMAN_OFFS_WUD_CTRL ((uint32_t)0x00000010UL)
bogdanm 0:9b334a45a8ff 92 #define MXC_R_PWRMAN_OFFS_WUD_PULSE0 ((uint32_t)0x00000014UL)
bogdanm 0:9b334a45a8ff 93 #define MXC_R_PWRMAN_OFFS_WUD_PULSE1 ((uint32_t)0x00000018UL)
bogdanm 0:9b334a45a8ff 94 #define MXC_R_PWRMAN_OFFS_WUD_SEEN0 ((uint32_t)0x00000030UL)
bogdanm 0:9b334a45a8ff 95 #define MXC_R_PWRMAN_OFFS_WUD_SEEN1 ((uint32_t)0x00000034UL)
bogdanm 0:9b334a45a8ff 96 #define MXC_R_PWRMAN_OFFS_DIE_TYPE ((uint32_t)0x00000038UL)
bogdanm 0:9b334a45a8ff 97 #define MXC_R_PWRMAN_OFFS_BASE_PART_NUM ((uint32_t)0x0000003CUL)
bogdanm 0:9b334a45a8ff 98 #define MXC_R_PWRMAN_OFFS_MASK_ID0 ((uint32_t)0x00000040UL)
bogdanm 0:9b334a45a8ff 99 #define MXC_R_PWRMAN_OFFS_MASK_ID1 ((uint32_t)0x00000044UL)
bogdanm 0:9b334a45a8ff 100 #define MXC_R_PWRMAN_OFFS_PERIPHERAL_RESET ((uint32_t)0x00000048UL)
bogdanm 0:9b334a45a8ff 101
bogdanm 0:9b334a45a8ff 102 /*
bogdanm 0:9b334a45a8ff 103 Field positions and masks for module PWRMAN.
bogdanm 0:9b334a45a8ff 104 */
bogdanm 0:9b334a45a8ff 105 #define MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE_POS 0
bogdanm 0:9b334a45a8ff 106 #define MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE_POS))
bogdanm 0:9b334a45a8ff 107 #define MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE_POS 1
bogdanm 0:9b334a45a8ff 108 #define MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE_POS))
bogdanm 0:9b334a45a8ff 109 #define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS 2
bogdanm 0:9b334a45a8ff 110 #define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS))
bogdanm 0:9b334a45a8ff 111 #define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS 3
bogdanm 0:9b334a45a8ff 112 #define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS))
bogdanm 0:9b334a45a8ff 113 #define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS 4
bogdanm 0:9b334a45a8ff 114 #define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS))
bogdanm 0:9b334a45a8ff 115 #define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS 5
bogdanm 0:9b334a45a8ff 116 #define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS))
bogdanm 0:9b334a45a8ff 117 #define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS 8
bogdanm 0:9b334a45a8ff 118 #define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS))
bogdanm 0:9b334a45a8ff 119 #define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS 9
bogdanm 0:9b334a45a8ff 120 #define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS))
bogdanm 0:9b334a45a8ff 121 #define MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR_POS 12
bogdanm 0:9b334a45a8ff 122 #define MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR_POS))
bogdanm 0:9b334a45a8ff 123 #define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS 16
bogdanm 0:9b334a45a8ff 124 #define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS))
bogdanm 0:9b334a45a8ff 125 #define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS 17
bogdanm 0:9b334a45a8ff 126 #define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS))
bogdanm 0:9b334a45a8ff 127 #define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS 18
bogdanm 0:9b334a45a8ff 128 #define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS))
bogdanm 0:9b334a45a8ff 129 #define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS 19
bogdanm 0:9b334a45a8ff 130 #define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS))
bogdanm 0:9b334a45a8ff 131 #define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS 20
bogdanm 0:9b334a45a8ff 132 #define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS))
bogdanm 0:9b334a45a8ff 133 #define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS 21
bogdanm 0:9b334a45a8ff 134 #define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS))
bogdanm 0:9b334a45a8ff 135 #define MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS 22
bogdanm 0:9b334a45a8ff 136 #define MXC_F_PWRMAN_PWR_RST_CTRL_POR ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS))
bogdanm 0:9b334a45a8ff 137 #define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS 31
bogdanm 0:9b334a45a8ff 138 #define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS))
bogdanm 0:9b334a45a8ff 139
bogdanm 0:9b334a45a8ff 140 #define MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS 0
bogdanm 0:9b334a45a8ff 141 #define MXC_F_PWRMAN_INTFL_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS))
bogdanm 0:9b334a45a8ff 142 #define MXC_F_PWRMAN_INTFL_V3_3_WARNING_POS 1
bogdanm 0:9b334a45a8ff 143 #define MXC_F_PWRMAN_INTFL_V3_3_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V3_3_WARNING_POS))
bogdanm 0:9b334a45a8ff 144 #define MXC_F_PWRMAN_INTFL_RTC_WARNING_POS 2
bogdanm 0:9b334a45a8ff 145 #define MXC_F_PWRMAN_INTFL_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_RTC_WARNING_POS))
bogdanm 0:9b334a45a8ff 146 #define MXC_F_PWRMAN_INTFL_V3_3_RESET_POS 3
bogdanm 0:9b334a45a8ff 147 #define MXC_F_PWRMAN_INTFL_V3_3_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V3_3_RESET_POS))
bogdanm 0:9b334a45a8ff 148 #define MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS 4
bogdanm 0:9b334a45a8ff 149 #define MXC_F_PWRMAN_INTFL_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS))
bogdanm 0:9b334a45a8ff 150
bogdanm 0:9b334a45a8ff 151 #define MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS 0
bogdanm 0:9b334a45a8ff 152 #define MXC_F_PWRMAN_INTEN_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS))
bogdanm 0:9b334a45a8ff 153 #define MXC_F_PWRMAN_INTEN_V3_3_WARNING_POS 1
bogdanm 0:9b334a45a8ff 154 #define MXC_F_PWRMAN_INTEN_V3_3_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V3_3_WARNING_POS))
bogdanm 0:9b334a45a8ff 155 #define MXC_F_PWRMAN_INTEN_RTC_WARNING_POS 2
bogdanm 0:9b334a45a8ff 156 #define MXC_F_PWRMAN_INTEN_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_RTC_WARNING_POS))
bogdanm 0:9b334a45a8ff 157 #define MXC_F_PWRMAN_INTEN_V3_3_RESET_POS 3
bogdanm 0:9b334a45a8ff 158 #define MXC_F_PWRMAN_INTEN_V3_3_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V3_3_RESET_POS))
bogdanm 0:9b334a45a8ff 159 #define MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS 4
bogdanm 0:9b334a45a8ff 160 #define MXC_F_PWRMAN_INTEN_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS))
bogdanm 0:9b334a45a8ff 161
bogdanm 0:9b334a45a8ff 162 #define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS 0
bogdanm 0:9b334a45a8ff 163 #define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS))
bogdanm 0:9b334a45a8ff 164 #define MXC_F_PWRMAN_SVM_EVENTS_V3_3_WARNING_POS 1
bogdanm 0:9b334a45a8ff 165 #define MXC_F_PWRMAN_SVM_EVENTS_V3_3_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V3_3_WARNING_POS))
bogdanm 0:9b334a45a8ff 166 #define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS 2
bogdanm 0:9b334a45a8ff 167 #define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS))
bogdanm 0:9b334a45a8ff 168 #define MXC_F_PWRMAN_SVM_EVENTS_V3_3_RESET_POS 3
bogdanm 0:9b334a45a8ff 169 #define MXC_F_PWRMAN_SVM_EVENTS_V3_3_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V3_3_RESET_POS))
bogdanm 0:9b334a45a8ff 170 #define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS 4
bogdanm 0:9b334a45a8ff 171 #define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS))
bogdanm 0:9b334a45a8ff 172
bogdanm 0:9b334a45a8ff 173 #define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS 0
bogdanm 0:9b334a45a8ff 174 #define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT ((uint32_t)(0x0000003FUL << MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS))
bogdanm 0:9b334a45a8ff 175 #define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS 8
bogdanm 0:9b334a45a8ff 176 #define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE ((uint32_t)(0x00000003UL << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS))
bogdanm 0:9b334a45a8ff 177 #define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS 12
bogdanm 0:9b334a45a8ff 178 #define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS))
bogdanm 0:9b334a45a8ff 179
bogdanm 0:9b334a45a8ff 180 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS 0
bogdanm 0:9b334a45a8ff 181 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS))
bogdanm 0:9b334a45a8ff 182 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS 1
bogdanm 0:9b334a45a8ff 183 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS))
bogdanm 0:9b334a45a8ff 184 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS 2
bogdanm 0:9b334a45a8ff 185 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS))
bogdanm 0:9b334a45a8ff 186 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS 3
bogdanm 0:9b334a45a8ff 187 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS))
bogdanm 0:9b334a45a8ff 188 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS 4
bogdanm 0:9b334a45a8ff 189 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO4 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS))
bogdanm 0:9b334a45a8ff 190 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS 5
bogdanm 0:9b334a45a8ff 191 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO5 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS))
bogdanm 0:9b334a45a8ff 192 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS 6
bogdanm 0:9b334a45a8ff 193 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO6 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS))
bogdanm 0:9b334a45a8ff 194 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS 7
bogdanm 0:9b334a45a8ff 195 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO7 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS))
bogdanm 0:9b334a45a8ff 196 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS 8
bogdanm 0:9b334a45a8ff 197 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO8 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS))
bogdanm 0:9b334a45a8ff 198 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS 9
bogdanm 0:9b334a45a8ff 199 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO9 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS))
bogdanm 0:9b334a45a8ff 200 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS 10
bogdanm 0:9b334a45a8ff 201 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO10 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS))
bogdanm 0:9b334a45a8ff 202 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS 11
bogdanm 0:9b334a45a8ff 203 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO11 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS))
bogdanm 0:9b334a45a8ff 204 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS 12
bogdanm 0:9b334a45a8ff 205 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO12 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS))
bogdanm 0:9b334a45a8ff 206 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS 13
bogdanm 0:9b334a45a8ff 207 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO13 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS))
bogdanm 0:9b334a45a8ff 208 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS 14
bogdanm 0:9b334a45a8ff 209 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO14 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS))
bogdanm 0:9b334a45a8ff 210 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS 15
bogdanm 0:9b334a45a8ff 211 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO15 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS))
bogdanm 0:9b334a45a8ff 212 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS 16
bogdanm 0:9b334a45a8ff 213 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO16 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS))
bogdanm 0:9b334a45a8ff 214 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS 17
bogdanm 0:9b334a45a8ff 215 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO17 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS))
bogdanm 0:9b334a45a8ff 216 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS 18
bogdanm 0:9b334a45a8ff 217 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO18 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS))
bogdanm 0:9b334a45a8ff 218 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS 19
bogdanm 0:9b334a45a8ff 219 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO19 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS))
bogdanm 0:9b334a45a8ff 220 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS 20
bogdanm 0:9b334a45a8ff 221 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO20 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS))
bogdanm 0:9b334a45a8ff 222 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS 21
bogdanm 0:9b334a45a8ff 223 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO21 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS))
bogdanm 0:9b334a45a8ff 224 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS 22
bogdanm 0:9b334a45a8ff 225 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO22 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS))
bogdanm 0:9b334a45a8ff 226 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS 23
bogdanm 0:9b334a45a8ff 227 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO23 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS))
bogdanm 0:9b334a45a8ff 228 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS 24
bogdanm 0:9b334a45a8ff 229 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO24 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS))
bogdanm 0:9b334a45a8ff 230 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS 25
bogdanm 0:9b334a45a8ff 231 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO25 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS))
bogdanm 0:9b334a45a8ff 232 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS 26
bogdanm 0:9b334a45a8ff 233 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO26 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS))
bogdanm 0:9b334a45a8ff 234 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS 27
bogdanm 0:9b334a45a8ff 235 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO27 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS))
bogdanm 0:9b334a45a8ff 236 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS 28
bogdanm 0:9b334a45a8ff 237 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO28 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS))
bogdanm 0:9b334a45a8ff 238 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS 29
bogdanm 0:9b334a45a8ff 239 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO29 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS))
bogdanm 0:9b334a45a8ff 240 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS 30
bogdanm 0:9b334a45a8ff 241 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO30 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS))
bogdanm 0:9b334a45a8ff 242 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS 31
bogdanm 0:9b334a45a8ff 243 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO31 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS))
bogdanm 0:9b334a45a8ff 244
bogdanm 0:9b334a45a8ff 245 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS 0
bogdanm 0:9b334a45a8ff 246 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO32 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS))
bogdanm 0:9b334a45a8ff 247 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS 1
bogdanm 0:9b334a45a8ff 248 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO33 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS))
bogdanm 0:9b334a45a8ff 249 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS 2
bogdanm 0:9b334a45a8ff 250 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO34 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS))
bogdanm 0:9b334a45a8ff 251 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS 3
bogdanm 0:9b334a45a8ff 252 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO35 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS))
bogdanm 0:9b334a45a8ff 253 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS 4
bogdanm 0:9b334a45a8ff 254 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO36 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS))
bogdanm 0:9b334a45a8ff 255 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS 5
bogdanm 0:9b334a45a8ff 256 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO37 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS))
bogdanm 0:9b334a45a8ff 257 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS 6
bogdanm 0:9b334a45a8ff 258 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO38 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS))
bogdanm 0:9b334a45a8ff 259 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS 7
bogdanm 0:9b334a45a8ff 260 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO39 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS))
bogdanm 0:9b334a45a8ff 261 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO40_POS 8
bogdanm 0:9b334a45a8ff 262 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO40 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO40_POS))
bogdanm 0:9b334a45a8ff 263 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO41_POS 9
bogdanm 0:9b334a45a8ff 264 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO41 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO41_POS))
bogdanm 0:9b334a45a8ff 265 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO42_POS 10
bogdanm 0:9b334a45a8ff 266 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO42 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO42_POS))
bogdanm 0:9b334a45a8ff 267 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO43_POS 11
bogdanm 0:9b334a45a8ff 268 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO43 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO43_POS))
bogdanm 0:9b334a45a8ff 269 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO44_POS 12
bogdanm 0:9b334a45a8ff 270 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO44 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO44_POS))
bogdanm 0:9b334a45a8ff 271 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO45_POS 13
bogdanm 0:9b334a45a8ff 272 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO45 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO45_POS))
bogdanm 0:9b334a45a8ff 273 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO46_POS 14
bogdanm 0:9b334a45a8ff 274 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO46 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO46_POS))
bogdanm 0:9b334a45a8ff 275 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO47_POS 15
bogdanm 0:9b334a45a8ff 276 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO47 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO47_POS))
bogdanm 0:9b334a45a8ff 277 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO48_POS 16
bogdanm 0:9b334a45a8ff 278 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO48 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO48_POS))
bogdanm 0:9b334a45a8ff 279 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO49_POS 17
bogdanm 0:9b334a45a8ff 280 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO49 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO49_POS))
bogdanm 0:9b334a45a8ff 281 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO50_POS 18
bogdanm 0:9b334a45a8ff 282 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO50 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO50_POS))
bogdanm 0:9b334a45a8ff 283 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO51_POS 19
bogdanm 0:9b334a45a8ff 284 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO51 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO51_POS))
bogdanm 0:9b334a45a8ff 285 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO52_POS 20
bogdanm 0:9b334a45a8ff 286 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO52 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO52_POS))
bogdanm 0:9b334a45a8ff 287 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO53_POS 21
bogdanm 0:9b334a45a8ff 288 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO53 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO53_POS))
bogdanm 0:9b334a45a8ff 289 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO54_POS 22
bogdanm 0:9b334a45a8ff 290 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO54 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO54_POS))
bogdanm 0:9b334a45a8ff 291 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO55_POS 23
bogdanm 0:9b334a45a8ff 292 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO55 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO55_POS))
bogdanm 0:9b334a45a8ff 293 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO56_POS 24
bogdanm 0:9b334a45a8ff 294 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO56 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO56_POS))
bogdanm 0:9b334a45a8ff 295 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO57_POS 25
bogdanm 0:9b334a45a8ff 296 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO57 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO57_POS))
bogdanm 0:9b334a45a8ff 297 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO58_POS 26
bogdanm 0:9b334a45a8ff 298 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO58 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO58_POS))
bogdanm 0:9b334a45a8ff 299 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO59_POS 27
bogdanm 0:9b334a45a8ff 300 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO59 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO59_POS))
bogdanm 0:9b334a45a8ff 301 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO60_POS 28
bogdanm 0:9b334a45a8ff 302 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO60 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO60_POS))
bogdanm 0:9b334a45a8ff 303 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO61_POS 29
bogdanm 0:9b334a45a8ff 304 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO61 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO61_POS))
bogdanm 0:9b334a45a8ff 305 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO62_POS 30
bogdanm 0:9b334a45a8ff 306 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO62 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO62_POS))
bogdanm 0:9b334a45a8ff 307 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO63_POS 31
bogdanm 0:9b334a45a8ff 308 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO63 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO63_POS))
bogdanm 0:9b334a45a8ff 309
bogdanm 0:9b334a45a8ff 310 #define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS 0
bogdanm 0:9b334a45a8ff 311 #define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER ((uint32_t)(0x0000FFFFUL << MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS))
bogdanm 0:9b334a45a8ff 312 #define MXC_F_PWRMAN_BASE_PART_NUM_PACKAGE_SELECT_POS 28
bogdanm 0:9b334a45a8ff 313 #define MXC_F_PWRMAN_BASE_PART_NUM_PACKAGE_SELECT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_BASE_PART_NUM_PACKAGE_SELECT_POS))
bogdanm 0:9b334a45a8ff 314
bogdanm 0:9b334a45a8ff 315 #define MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS 0
bogdanm 0:9b334a45a8ff 316 #define MXC_F_PWRMAN_MASK_ID0_REVISION_ID ((uint32_t)(0x0000000FUL << MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS))
bogdanm 0:9b334a45a8ff 317 #define MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS 4
bogdanm 0:9b334a45a8ff 318 #define MXC_F_PWRMAN_MASK_ID0_MASK_ID ((uint32_t)(0x0FFFFFFFUL << MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS))
bogdanm 0:9b334a45a8ff 319
bogdanm 0:9b334a45a8ff 320 #define MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS 0
bogdanm 0:9b334a45a8ff 321 #define MXC_F_PWRMAN_MASK_ID1_MASK_ID ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS))
bogdanm 0:9b334a45a8ff 322 #define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS 31
bogdanm 0:9b334a45a8ff 323 #define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS))
bogdanm 0:9b334a45a8ff 324
bogdanm 0:9b334a45a8ff 325 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS 0
bogdanm 0:9b334a45a8ff 326 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS))
bogdanm 0:9b334a45a8ff 327 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS 1
bogdanm 0:9b334a45a8ff 328 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS))
bogdanm 0:9b334a45a8ff 329 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS 2
bogdanm 0:9b334a45a8ff 330 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS))
bogdanm 0:9b334a45a8ff 331 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS 3
bogdanm 0:9b334a45a8ff 332 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS))
bogdanm 0:9b334a45a8ff 333 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS 4
bogdanm 0:9b334a45a8ff 334 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS))
bogdanm 0:9b334a45a8ff 335 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS 5
bogdanm 0:9b334a45a8ff 336 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS))
bogdanm 0:9b334a45a8ff 337 #define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS 6
bogdanm 0:9b334a45a8ff 338 #define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS))
bogdanm 0:9b334a45a8ff 339 #define MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS 7
bogdanm 0:9b334a45a8ff 340 #define MXC_F_PWRMAN_PERIPHERAL_RESET_USB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS))
bogdanm 0:9b334a45a8ff 341 #define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS 8
bogdanm 0:9b334a45a8ff 342 #define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS))
bogdanm 0:9b334a45a8ff 343 #define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC0_POS 9
bogdanm 0:9b334a45a8ff 344 #define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC0_POS))
bogdanm 0:9b334a45a8ff 345 #define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC1_POS 10
bogdanm 0:9b334a45a8ff 346 #define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC1_POS))
bogdanm 0:9b334a45a8ff 347 #define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC2_POS 11
bogdanm 0:9b334a45a8ff 348 #define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC2_POS))
bogdanm 0:9b334a45a8ff 349 #define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC3_POS 12
bogdanm 0:9b334a45a8ff 350 #define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC3_POS))
bogdanm 0:9b334a45a8ff 351 #define MXC_F_PWRMAN_PERIPHERAL_RESET_DMA_POS 13
bogdanm 0:9b334a45a8ff 352 #define MXC_F_PWRMAN_PERIPHERAL_RESET_DMA ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DMA_POS))
bogdanm 0:9b334a45a8ff 353 #define MXC_F_PWRMAN_PERIPHERAL_RESET_LCD_POS 14
bogdanm 0:9b334a45a8ff 354 #define MXC_F_PWRMAN_PERIPHERAL_RESET_LCD ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_LCD_POS))
bogdanm 0:9b334a45a8ff 355 #define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS 15
bogdanm 0:9b334a45a8ff 356 #define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS))
bogdanm 0:9b334a45a8ff 357 #define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS 16
bogdanm 0:9b334a45a8ff 358 #define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS))
bogdanm 0:9b334a45a8ff 359 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI0_POS 17
bogdanm 0:9b334a45a8ff 360 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPI0_POS))
bogdanm 0:9b334a45a8ff 361 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI1_POS 18
bogdanm 0:9b334a45a8ff 362 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPI1_POS))
bogdanm 0:9b334a45a8ff 363 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI2_POS 19
bogdanm 0:9b334a45a8ff 364 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPI2_POS))
bogdanm 0:9b334a45a8ff 365 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS 20
bogdanm 0:9b334a45a8ff 366 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS))
bogdanm 0:9b334a45a8ff 367 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS 21
bogdanm 0:9b334a45a8ff 368 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS))
bogdanm 0:9b334a45a8ff 369 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS 22
bogdanm 0:9b334a45a8ff 370 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS))
bogdanm 0:9b334a45a8ff 371 #define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS 23
bogdanm 0:9b334a45a8ff 372 #define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS))
bogdanm 0:9b334a45a8ff 373 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS 24
bogdanm 0:9b334a45a8ff 374 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS))
bogdanm 0:9b334a45a8ff 375 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS 25
bogdanm 0:9b334a45a8ff 376 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS))
bogdanm 0:9b334a45a8ff 377
bogdanm 0:9b334a45a8ff 378 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 379 }
bogdanm 0:9b334a45a8ff 380 #endif
bogdanm 0:9b334a45a8ff 381
bogdanm 0:9b334a45a8ff 382 /**
bogdanm 0:9b334a45a8ff 383 * @}
bogdanm 0:9b334a45a8ff 384 */
bogdanm 0:9b334a45a8ff 385
bogdanm 0:9b334a45a8ff 386 #endif /* _MXC_PWRMAN_REGS_H_ */