Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Maxim/TARGET_MAX32610/clkman_regs.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
0:9b334a45a8ff 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*******************************************************************************
<> 144:ef7eb2e8f9f7 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 144:ef7eb2e8f9f7 5 * copy of this software and associated documentation files (the "Software"),
<> 144:ef7eb2e8f9f7 6 * to deal in the Software without restriction, including without limitation
<> 144:ef7eb2e8f9f7 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 144:ef7eb2e8f9f7 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 144:ef7eb2e8f9f7 9 * Software is furnished to do so, subject to the following conditions:
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * The above copyright notice and this permission notice shall be included
<> 144:ef7eb2e8f9f7 12 * in all copies or substantial portions of the Software.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 144:ef7eb2e8f9f7 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 144:ef7eb2e8f9f7 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 144:ef7eb2e8f9f7 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 144:ef7eb2e8f9f7 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 144:ef7eb2e8f9f7 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * Except as contained in this notice, the name of Maxim Integrated
<> 144:ef7eb2e8f9f7 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 144:ef7eb2e8f9f7 24 * Products, Inc. Branding Policy.
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * The mere transfer of this software does not imply any licenses
<> 144:ef7eb2e8f9f7 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 144:ef7eb2e8f9f7 28 * trademarks, maskwork rights, or any other form of intellectual
<> 144:ef7eb2e8f9f7 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 144:ef7eb2e8f9f7 30 * ownership rights.
<> 144:ef7eb2e8f9f7 31 *******************************************************************************
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #ifndef _MXC_CLKMAN_REGS_H_
<> 144:ef7eb2e8f9f7 35 #define _MXC_CLKMAN_REGS_H_
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 38 extern "C" {
<> 144:ef7eb2e8f9f7 39 #endif
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 #include <stdint.h>
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /**
<> 144:ef7eb2e8f9f7 44 * @file clkman_regs.h
<> 144:ef7eb2e8f9f7 45 * @addtogroup clkman CLKMAN
<> 144:ef7eb2e8f9f7 46 * @{
<> 144:ef7eb2e8f9f7 47 */
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /**
<> 144:ef7eb2e8f9f7 50 * @brief Defines clock input selections for the phase locked loop.
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52 typedef enum {
<> 144:ef7eb2e8f9f7 53 /** Input select for high frequency crystal oscillator */
<> 144:ef7eb2e8f9f7 54 MXC_E_CLKMAN_PLL_INPUT_SELECT_HFX = 0,
<> 144:ef7eb2e8f9f7 55 /** Input select for 24MHz ring oscillator */
<> 144:ef7eb2e8f9f7 56 MXC_E_CLKMAN_PLL_INPUT_SELECT_24MHZ_RO,
<> 144:ef7eb2e8f9f7 57 } mxc_clkman_pll_input_select_t;
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /**
<> 144:ef7eb2e8f9f7 60 * @brief Defines clock input frequency for the phase locked loop.
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62 typedef enum {
<> 144:ef7eb2e8f9f7 63 /** Input frequency of 24MHz */
<> 144:ef7eb2e8f9f7 64 MXC_E_CLKMAN_PLL_DIVISOR_SELECT_24MHZ = 0,
<> 144:ef7eb2e8f9f7 65 /** Input frequency of 12MHz */
<> 144:ef7eb2e8f9f7 66 MXC_E_CLKMAN_PLL_DIVISOR_SELECT_12MHZ,
<> 144:ef7eb2e8f9f7 67 /** Input frequency of 8MHz */
<> 144:ef7eb2e8f9f7 68 MXC_E_CLKMAN_PLL_DIVISOR_SELECT_8MHZ,
<> 144:ef7eb2e8f9f7 69 } mxc_clkman_pll_divisor_select_t;
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 /**
<> 144:ef7eb2e8f9f7 72 * @brief Defines terminal count for PLL stable.
<> 144:ef7eb2e8f9f7 73 */
<> 144:ef7eb2e8f9f7 74 typedef enum {
<> 144:ef7eb2e8f9f7 75 /** Clock stable after 2^8 = 256 clock cycles */
<> 144:ef7eb2e8f9f7 76 MXC_E_CLKMAN_STABILITY_COUNT_2_8_CLKS = 0,
<> 144:ef7eb2e8f9f7 77 /** Clock stable after 2^9 = 512 clock cycles */
<> 144:ef7eb2e8f9f7 78 MXC_E_CLKMAN_STABILITY_COUNT_2_9_CLKS,
<> 144:ef7eb2e8f9f7 79 /** Clock stable after 2^10 = 1024 clock cycles */
<> 144:ef7eb2e8f9f7 80 MXC_E_CLKMAN_STABILITY_COUNT_2_10_CLKS,
<> 144:ef7eb2e8f9f7 81 /** Clock stable after 2^11 = 2048 clock cycles */
<> 144:ef7eb2e8f9f7 82 MXC_E_CLKMAN_STABILITY_COUNT_2_11_CLKS,
<> 144:ef7eb2e8f9f7 83 /** Clock stable after 2^12 = 4096 clock cycles */
<> 144:ef7eb2e8f9f7 84 MXC_E_CLKMAN_STABILITY_COUNT_2_12_CLKS,
<> 144:ef7eb2e8f9f7 85 /** Clock stable after 2^13 = 8192 clock cycles */
<> 144:ef7eb2e8f9f7 86 MXC_E_CLKMAN_STABILITY_COUNT_2_13_CLKS,
<> 144:ef7eb2e8f9f7 87 /** Clock stable after 2^14 = 16384 clock cycles */
<> 144:ef7eb2e8f9f7 88 MXC_E_CLKMAN_STABILITY_COUNT_2_14_CLKS,
<> 144:ef7eb2e8f9f7 89 /** Clock stable after 2^15 = 32768 clock cycles */
<> 144:ef7eb2e8f9f7 90 MXC_E_CLKMAN_STABILITY_COUNT_2_15_CLKS,
<> 144:ef7eb2e8f9f7 91 /** Clock stable after 2^16 = 65536 clock cycles */
<> 144:ef7eb2e8f9f7 92 MXC_E_CLKMAN_STABILITY_COUNT_2_16_CLKS,
<> 144:ef7eb2e8f9f7 93 /** Clock stable after 2^17 = 131072 clock cycles */
<> 144:ef7eb2e8f9f7 94 MXC_E_CLKMAN_STABILITY_COUNT_2_17_CLKS,
<> 144:ef7eb2e8f9f7 95 /** Clock stable after 2^18 = 262144 clock cycles */
<> 144:ef7eb2e8f9f7 96 MXC_E_CLKMAN_STABILITY_COUNT_2_18_CLKS,
<> 144:ef7eb2e8f9f7 97 /** Clock stable after 2^19 = 524288 clock cycles */
<> 144:ef7eb2e8f9f7 98 MXC_E_CLKMAN_STABILITY_COUNT_2_19_CLKS,
<> 144:ef7eb2e8f9f7 99 /** Clock stable after 2^20 = 1048576 clock cycles */
<> 144:ef7eb2e8f9f7 100 MXC_E_CLKMAN_STABILITY_COUNT_2_20_CLKS,
<> 144:ef7eb2e8f9f7 101 /** Clock stable after 2^21 = 2097152 clock cycles */
<> 144:ef7eb2e8f9f7 102 MXC_E_CLKMAN_STABILITY_COUNT_2_21_CLKS,
<> 144:ef7eb2e8f9f7 103 /** Clock stable after 2^22 = 4194304 clock cycles */
<> 144:ef7eb2e8f9f7 104 MXC_E_CLKMAN_STABILITY_COUNT_2_22_CLKS,
<> 144:ef7eb2e8f9f7 105 /** Clock stable after 2^23 = 8388608 clock cycles */
<> 144:ef7eb2e8f9f7 106 MXC_E_CLKMAN_STABILITY_COUNT_2_23_CLKS
<> 144:ef7eb2e8f9f7 107 } mxc_clkman_stability_count_t;
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 /**
<> 144:ef7eb2e8f9f7 110 * @brief Defines clock source selections for system clock.
<> 144:ef7eb2e8f9f7 111 */
<> 144:ef7eb2e8f9f7 112 typedef enum {
<> 144:ef7eb2e8f9f7 113 /** Clock select for 24MHz ring oscillator divided by 8 (3MHz) */
<> 144:ef7eb2e8f9f7 114 MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO_DIV_8 = 0,
<> 144:ef7eb2e8f9f7 115 /** Clock select for 24MHz ring oscillator */
<> 144:ef7eb2e8f9f7 116 MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO,
<> 144:ef7eb2e8f9f7 117 /** Clock select for high frequency crystal oscillator */
<> 144:ef7eb2e8f9f7 118 MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_HFX,
<> 144:ef7eb2e8f9f7 119 /** Clock select for 48MHz phase locked loop output divided by 2 (24MHz) */
<> 144:ef7eb2e8f9f7 120 MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_PLL_48MHZ_DIV_2
<> 144:ef7eb2e8f9f7 121 } mxc_clkman_system_source_select_t;
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 /**
<> 144:ef7eb2e8f9f7 124 * @brief Defines clock source selections for analog to digital converter clock.
<> 144:ef7eb2e8f9f7 125 */
<> 144:ef7eb2e8f9f7 126 typedef enum {
<> 144:ef7eb2e8f9f7 127 /** Clock select for system clock frequency */
<> 144:ef7eb2e8f9f7 128 MXC_E_CLKMAN_ADC_SOURCE_SELECT_SYSTEM = 0,
<> 144:ef7eb2e8f9f7 129 /** Clock select for 8MHz phase locked loop output */
<> 144:ef7eb2e8f9f7 130 MXC_E_CLKMAN_ADC_SOURCE_SELECT_PLL_8MHZ,
<> 144:ef7eb2e8f9f7 131 /** Clock select for high frequency crystal oscillator */
<> 144:ef7eb2e8f9f7 132 MXC_E_CLKMAN_ADC_SOURCE_SELECT_HFX,
<> 144:ef7eb2e8f9f7 133 /** Clock select for 24MHz ring oscillator */
<> 144:ef7eb2e8f9f7 134 MXC_E_CLKMAN_ADC_SOURCE_SELECT_24MHZ_RO,
<> 144:ef7eb2e8f9f7 135 } mxc_clkman_adc_source_select_t;
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 /**
<> 144:ef7eb2e8f9f7 138 * @brief Defines clock source selections for watchdog timer clock.
<> 144:ef7eb2e8f9f7 139 */
<> 144:ef7eb2e8f9f7 140 typedef enum {
<> 144:ef7eb2e8f9f7 141 /** Clock select for system clock frequency */
<> 144:ef7eb2e8f9f7 142 MXC_E_CLKMAN_WDT_SOURCE_SELECT_SYSTEM = 0,
<> 144:ef7eb2e8f9f7 143 /** Clock select for 8MHz phase locked loop output */
<> 144:ef7eb2e8f9f7 144 MXC_E_CLKMAN_WDT_SOURCE_SELECT_RTC,
<> 144:ef7eb2e8f9f7 145 /** Clock select for high frequency crystal oscillator */
<> 144:ef7eb2e8f9f7 146 MXC_E_CLKMAN_WDT_SOURCE_SELECT_24MHZ_RO,
<> 144:ef7eb2e8f9f7 147 /** Clock select for 24MHz ring oscillator */
<> 144:ef7eb2e8f9f7 148 MXC_E_CLKMAN_WDT_SOURCE_SELECT_NANO,
<> 144:ef7eb2e8f9f7 149 } mxc_clkman_wdt_source_select_t;
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 /**
<> 144:ef7eb2e8f9f7 152 * @brief Defines clock scales for various clocks.
<> 144:ef7eb2e8f9f7 153 */
<> 144:ef7eb2e8f9f7 154 typedef enum {
<> 144:ef7eb2e8f9f7 155 /** Clock disabled */
<> 144:ef7eb2e8f9f7 156 MXC_E_CLKMAN_CLK_SCALE_DISABLED = 0,
<> 144:ef7eb2e8f9f7 157 /** Clock enabled */
<> 144:ef7eb2e8f9f7 158 MXC_E_CLKMAN_CLK_SCALE_ENABLED,
<> 144:ef7eb2e8f9f7 159 /** Clock scale for dividing by 2 */
<> 144:ef7eb2e8f9f7 160 MXC_E_CLKMAN_CLK_SCALE_DIV_2,
<> 144:ef7eb2e8f9f7 161 /** Clock scale for dividing by 4 */
<> 144:ef7eb2e8f9f7 162 MXC_E_CLKMAN_CLK_SCALE_DIV_4,
<> 144:ef7eb2e8f9f7 163 /** Clock scale for dividing by 8 */
<> 144:ef7eb2e8f9f7 164 MXC_E_CLKMAN_CLK_SCALE_DIV_8,
<> 144:ef7eb2e8f9f7 165 /** Clock scale for dividing by 16 */
<> 144:ef7eb2e8f9f7 166 MXC_E_CLKMAN_CLK_SCALE_DIV_16,
<> 144:ef7eb2e8f9f7 167 /** Clock scale for dividing by 32 */
<> 144:ef7eb2e8f9f7 168 MXC_E_CLKMAN_CLK_SCALE_DIV_32,
<> 144:ef7eb2e8f9f7 169 /** Clock scale for dividing by 64 */
<> 144:ef7eb2e8f9f7 170 MXC_E_CLKMAN_CLK_SCALE_DIV_64,
<> 144:ef7eb2e8f9f7 171 /** Clock scale for dividing by 128 */
<> 144:ef7eb2e8f9f7 172 MXC_E_CLKMAN_CLK_SCALE_DIV_128,
<> 144:ef7eb2e8f9f7 173 /** Clock scale for dividing by 256 */
<> 144:ef7eb2e8f9f7 174 MXC_E_CLKMAN_CLK_SCALE_DIV_256
<> 144:ef7eb2e8f9f7 175 } mxc_clkman_clk_scale_t;
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 /**
<> 144:ef7eb2e8f9f7 178 * @brief Defines Setting of the Clock Gates .
<> 144:ef7eb2e8f9f7 179 */
<> 144:ef7eb2e8f9f7 180 typedef enum {
<> 144:ef7eb2e8f9f7 181 /** Clock Gater is Off */
<> 144:ef7eb2e8f9f7 182 MXC_E_CLKMAN_CLK_GATE_OFF = 0,
<> 144:ef7eb2e8f9f7 183 /** Clock Gater is Dynamic */
<> 144:ef7eb2e8f9f7 184 MXC_E_CLKMAN_CLK_GATE_DYNAMIC,
<> 144:ef7eb2e8f9f7 185 /** Clock Gater is On */
<> 144:ef7eb2e8f9f7 186 MXC_E_CLKMAN_CLK_GATE_ON
<> 144:ef7eb2e8f9f7 187 } mxc_clkman_clk_gate_t;
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 /* Offset Register Description
<> 144:ef7eb2e8f9f7 190 ====== ===================================================================== */
<> 144:ef7eb2e8f9f7 191 typedef struct {
<> 144:ef7eb2e8f9f7 192 __IO uint32_t clk_config; /* 0x0000 System Clock Configuration */
<> 144:ef7eb2e8f9f7 193 __IO uint32_t clk_ctrl; /* 0x0004 System Clock Controls */
<> 144:ef7eb2e8f9f7 194 __IO uint32_t intfl; /* 0x0008 Interrupt Flags */
<> 144:ef7eb2e8f9f7 195 __IO uint32_t inten; /* 0x000C Interrupt Enable/Disable Controls */
<> 144:ef7eb2e8f9f7 196 __IO uint32_t trim_calc; /* 0x0010 Trim Calculation Controls */
<> 144:ef7eb2e8f9f7 197 __I uint32_t rsv0014[4]; /* 0x0014 */
<> 144:ef7eb2e8f9f7 198 __IO uint32_t i2c_timer_ctrl; /* 0x0024 I2C Timer Control */
<> 144:ef7eb2e8f9f7 199 __I uint32_t rsv0028[6]; /* 0x0028 */
<> 144:ef7eb2e8f9f7 200 __IO uint32_t clk_ctrl_0_system; /* 0x0040 Control Settings for CLK0 - System Clock */
<> 144:ef7eb2e8f9f7 201 __IO uint32_t clk_ctrl_1_gpio; /* 0x0044 Control Settings for CLK1 - GPIO Module Clock */
<> 144:ef7eb2e8f9f7 202 __IO uint32_t clk_ctrl_2_pt; /* 0x0048 Control Settings for CLK2 - Pulse Train Module Clock */
<> 144:ef7eb2e8f9f7 203 __IO uint32_t clk_ctrl_3_spi0; /* 0x004C Control Settings for CLK3 - SPI0 Master Clock */
<> 144:ef7eb2e8f9f7 204 __IO uint32_t clk_ctrl_4_spi1; /* 0x0050 Control Settings for CLK4 - SPI1 Master Clock */
<> 144:ef7eb2e8f9f7 205 __IO uint32_t clk_ctrl_5_spi2; /* 0x0054 Control Settings for CLK5 - SPI2 Master Clock */
<> 144:ef7eb2e8f9f7 206 __IO uint32_t clk_ctrl_6_i2cm; /* 0x0058 Control Settings for CLK6 - Clock for all I2C Masters */
<> 144:ef7eb2e8f9f7 207 __IO uint32_t clk_ctrl_7_i2cs; /* 0x005C Control Settings for CLK7 - I2C Slave Clock */
<> 144:ef7eb2e8f9f7 208 __IO uint32_t clk_ctrl_8_lcd_chpump; /* 0x0060 Control Settings for CLK8 - LCD Charge Pump Clock */
<> 144:ef7eb2e8f9f7 209 __IO uint32_t clk_ctrl_9_puf; /* 0x0064 Control Settings for CLK9 - PUF Clock */
<> 144:ef7eb2e8f9f7 210 __IO uint32_t clk_ctrl_10_prng; /* 0x0068 Control Settings for CLK10 - PRNG Clock */
<> 144:ef7eb2e8f9f7 211 __IO uint32_t clk_ctrl_11_wdt0; /* 0x006C Control Settings for CLK11 - Watchdog Timer 0 ScaledSysClk */
<> 144:ef7eb2e8f9f7 212 __IO uint32_t clk_ctrl_12_wdt1; /* 0x0070 Control Settings for CLK12 - Watchdog Timer 1 ScaledSysClk */
<> 144:ef7eb2e8f9f7 213 __IO uint32_t clk_ctrl_13_rtc_int_sync; /* 0x0074 Control Settings for CLK13 - RTC Interrupt Sync Clock */
<> 144:ef7eb2e8f9f7 214 __IO uint32_t clk_ctrl_14_dac0; /* 0x0078 Control Settings for CLK14 - 12-bit DAC 0 Clock */
<> 144:ef7eb2e8f9f7 215 __IO uint32_t clk_ctrl_15_dac1; /* 0x007C Control Settings for CLK15 - 12-bit DAC 1 Clock */
<> 144:ef7eb2e8f9f7 216 __IO uint32_t clk_ctrl_16_dac2; /* 0x0080 Control Settings for CLK16 - 8-bit DAC 0 Clock */
<> 144:ef7eb2e8f9f7 217 __IO uint32_t clk_ctrl_17_dac3; /* 0x0084 Control Settings for CLK17 - 8-bit DAC 1 Clock */
<> 144:ef7eb2e8f9f7 218 __I uint32_t rsv0088[30]; /* 0x0088 */
<> 144:ef7eb2e8f9f7 219 __IO uint32_t crypt_clk_ctrl_0_aes; /* 0x0100 Control Settings for Crypto Clock 0 - AES */
<> 144:ef7eb2e8f9f7 220 __IO uint32_t crypt_clk_ctrl_1_maa; /* 0x0104 Control Settings for Crypto Clock 1 - MAA */
<> 144:ef7eb2e8f9f7 221 __IO uint32_t crypt_clk_ctrl_2_prng; /* 0x0108 Control Settings for Crypto Clock 2 - PRNG */
<> 144:ef7eb2e8f9f7 222 __I uint32_t rsv010C[13]; /* 0x010C */
<> 144:ef7eb2e8f9f7 223 __IO uint32_t clk_gate_ctrl0; /* 0x0140 Dynamic Clock Gating Control Register 0 */
<> 144:ef7eb2e8f9f7 224 __IO uint32_t clk_gate_ctrl1; /* 0x0144 Dynamic Clock Gating Control Register 1 */
<> 144:ef7eb2e8f9f7 225 __IO uint32_t clk_gate_ctrl2; /* 0x0148 Dynamic Clock Gating Control Register 2 */
<> 144:ef7eb2e8f9f7 226 } mxc_clkman_regs_t;
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 /*
<> 144:ef7eb2e8f9f7 229 Register offsets for module CLKMAN.
<> 144:ef7eb2e8f9f7 230 */
<> 144:ef7eb2e8f9f7 231 #define MXC_R_CLKMAN_OFFS_CLK_CONFIG ((uint32_t)0x00000000UL)
<> 144:ef7eb2e8f9f7 232 #define MXC_R_CLKMAN_OFFS_CLK_CTRL ((uint32_t)0x00000004UL)
<> 144:ef7eb2e8f9f7 233 #define MXC_R_CLKMAN_OFFS_INTFL ((uint32_t)0x00000008UL)
<> 144:ef7eb2e8f9f7 234 #define MXC_R_CLKMAN_OFFS_INTEN ((uint32_t)0x0000000CUL)
<> 144:ef7eb2e8f9f7 235 #define MXC_R_CLKMAN_OFFS_TRIM_CALC ((uint32_t)0x00000010UL)
<> 144:ef7eb2e8f9f7 236 #define MXC_R_CLKMAN_OFFS_I2C_TIMER_CTRL ((uint32_t)0x00000024UL)
<> 144:ef7eb2e8f9f7 237 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_0_SYSTEM ((uint32_t)0x00000040UL)
<> 144:ef7eb2e8f9f7 238 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_1_GPIO ((uint32_t)0x00000044UL)
<> 144:ef7eb2e8f9f7 239 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_2_PT ((uint32_t)0x00000048UL)
<> 144:ef7eb2e8f9f7 240 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_3_SPI0 ((uint32_t)0x0000004CUL)
<> 144:ef7eb2e8f9f7 241 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_4_SPI1 ((uint32_t)0x00000050UL)
<> 144:ef7eb2e8f9f7 242 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_5_SPI2 ((uint32_t)0x00000054UL)
<> 144:ef7eb2e8f9f7 243 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_6_I2CM ((uint32_t)0x00000058UL)
<> 144:ef7eb2e8f9f7 244 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_7_I2CS ((uint32_t)0x0000005CUL)
<> 144:ef7eb2e8f9f7 245 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_8_LCD_CHPUMP ((uint32_t)0x00000060UL)
<> 144:ef7eb2e8f9f7 246 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_9_PUF ((uint32_t)0x00000064UL)
<> 144:ef7eb2e8f9f7 247 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_10_PRNG ((uint32_t)0x00000068UL)
<> 144:ef7eb2e8f9f7 248 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_11_WDT0 ((uint32_t)0x0000006CUL)
<> 144:ef7eb2e8f9f7 249 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_12_WDT1 ((uint32_t)0x00000070UL)
<> 144:ef7eb2e8f9f7 250 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_13_RTC_INT_SYNC ((uint32_t)0x00000074UL)
<> 144:ef7eb2e8f9f7 251 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_14_DAC0 ((uint32_t)0x00000078UL)
<> 144:ef7eb2e8f9f7 252 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_15_DAC1 ((uint32_t)0x0000007CUL)
<> 144:ef7eb2e8f9f7 253 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_16_DAC2 ((uint32_t)0x00000080UL)
<> 144:ef7eb2e8f9f7 254 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_17_DAC3 ((uint32_t)0x00000084UL)
<> 144:ef7eb2e8f9f7 255 #define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_0_AES ((uint32_t)0x00000100UL)
<> 144:ef7eb2e8f9f7 256 #define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_1_MAA ((uint32_t)0x00000104UL)
<> 144:ef7eb2e8f9f7 257 #define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_2_PRNG ((uint32_t)0x00000108UL)
<> 144:ef7eb2e8f9f7 258 #define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL0 ((uint32_t)0x00000140UL)
<> 144:ef7eb2e8f9f7 259 #define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL1 ((uint32_t)0x00000144UL)
<> 144:ef7eb2e8f9f7 260 #define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL2 ((uint32_t)0x00000148UL)
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 /*
<> 144:ef7eb2e8f9f7 263 Field positions and masks for module CLKMAN.
<> 144:ef7eb2e8f9f7 264 */
<> 144:ef7eb2e8f9f7 265 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_ENABLE_POS 0
<> 144:ef7eb2e8f9f7 266 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_ENABLE_POS))
<> 144:ef7eb2e8f9f7 267 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_BYPASS_POS 1
<> 144:ef7eb2e8f9f7 268 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_BYPASS ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_BYPASS_POS))
<> 144:ef7eb2e8f9f7 269 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_TEST_ENABLE_POS 2
<> 144:ef7eb2e8f9f7 270 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_TEST_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_TEST_ENABLE_POS))
<> 144:ef7eb2e8f9f7 271 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_GM_ADJUST_POS 4
<> 144:ef7eb2e8f9f7 272 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_GM_ADJUST ((uint32_t)(0x0000001FUL << MXC_F_CLKMAN_CLK_CONFIG_HFX_GM_ADJUST_POS))
<> 144:ef7eb2e8f9f7 273 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_DC_CONTROL_POS 9
<> 144:ef7eb2e8f9f7 274 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_DC_CONTROL ((uint32_t)(0x00000007UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_DC_CONTROL_POS))
<> 144:ef7eb2e8f9f7 275 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE_POS 12
<> 144:ef7eb2e8f9f7 276 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE_POS))
<> 144:ef7eb2e8f9f7 277 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_RESET_N_POS 13
<> 144:ef7eb2e8f9f7 278 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_RESET_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_RESET_N_POS))
<> 144:ef7eb2e8f9f7 279 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_INPUT_SELECT_POS 14
<> 144:ef7eb2e8f9f7 280 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_INPUT_SELECT ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_INPUT_SELECT_POS))
<> 144:ef7eb2e8f9f7 281 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT_POS 16
<> 144:ef7eb2e8f9f7 282 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT_POS))
<> 144:ef7eb2e8f9f7 283 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_8MHZ_ENABLE_POS 18
<> 144:ef7eb2e8f9f7 284 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_8MHZ_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_8MHZ_ENABLE_POS))
<> 144:ef7eb2e8f9f7 285 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_BYPASS_POS 19
<> 144:ef7eb2e8f9f7 286 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_BYPASS ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_BYPASS_POS))
<> 144:ef7eb2e8f9f7 287 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_STABILITY_COUNT_POS 20
<> 144:ef7eb2e8f9f7 288 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_STABILITY_COUNT ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CONFIG_PLL_STABILITY_COUNT_POS))
<> 144:ef7eb2e8f9f7 289 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS 24
<> 144:ef7eb2e8f9f7 290 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS))
<> 144:ef7eb2e8f9f7 291 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_RESET_N_POS 25
<> 144:ef7eb2e8f9f7 292 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_RESET_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_RESET_N_POS))
<> 144:ef7eb2e8f9f7 293 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS 28
<> 144:ef7eb2e8f9f7 294 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296 #define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS 1
<> 144:ef7eb2e8f9f7 297 #define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS))
<> 144:ef7eb2e8f9f7 298 #define MXC_F_CLKMAN_CLK_CTRL_AUTO_CLK_DISABLE_POS 3
<> 144:ef7eb2e8f9f7 299 #define MXC_F_CLKMAN_CLK_CTRL_AUTO_CLK_DISABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_AUTO_CLK_DISABLE_POS))
<> 144:ef7eb2e8f9f7 300 #define MXC_F_CLKMAN_CLK_CTRL_USB_GATE_N_POS 4
<> 144:ef7eb2e8f9f7 301 #define MXC_F_CLKMAN_CLK_CTRL_USB_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_USB_GATE_N_POS))
<> 144:ef7eb2e8f9f7 302 #define MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N_POS 8
<> 144:ef7eb2e8f9f7 303 #define MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N_POS))
<> 144:ef7eb2e8f9f7 304 #define MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT_POS 9
<> 144:ef7eb2e8f9f7 305 #define MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT_POS))
<> 144:ef7eb2e8f9f7 306 #define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_GATE_N_POS 12
<> 144:ef7eb2e8f9f7 307 #define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_CRYPTO_GATE_N_POS))
<> 144:ef7eb2e8f9f7 308 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_GATE_N_POS 16
<> 144:ef7eb2e8f9f7 309 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_GATE_N_POS))
<> 144:ef7eb2e8f9f7 310 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_SOURCE_SELECT_POS 17
<> 144:ef7eb2e8f9f7 311 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_SOURCE_SELECT_POS))
<> 144:ef7eb2e8f9f7 312 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_GATE_N_POS 20
<> 144:ef7eb2e8f9f7 313 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_GATE_N_POS))
<> 144:ef7eb2e8f9f7 314 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_SOURCE_SELECT_POS 21
<> 144:ef7eb2e8f9f7 315 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_SOURCE_SELECT_POS))
<> 144:ef7eb2e8f9f7 316 #define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS 24
<> 144:ef7eb2e8f9f7 317 #define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS))
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 #define MXC_F_CLKMAN_INTFL_RING_STABLE_POS 0
<> 144:ef7eb2e8f9f7 320 #define MXC_F_CLKMAN_INTFL_RING_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_RING_STABLE_POS))
<> 144:ef7eb2e8f9f7 321 #define MXC_F_CLKMAN_INTFL_PLL_STABLE_POS 1
<> 144:ef7eb2e8f9f7 322 #define MXC_F_CLKMAN_INTFL_PLL_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_PLL_STABLE_POS))
<> 144:ef7eb2e8f9f7 323 #define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS 2
<> 144:ef7eb2e8f9f7 324 #define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS))
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 #define MXC_F_CLKMAN_INTEN_RING_STABLE_POS 0
<> 144:ef7eb2e8f9f7 327 #define MXC_F_CLKMAN_INTEN_RING_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_RING_STABLE_POS))
<> 144:ef7eb2e8f9f7 328 #define MXC_F_CLKMAN_INTEN_PLL_STABLE_POS 1
<> 144:ef7eb2e8f9f7 329 #define MXC_F_CLKMAN_INTEN_PLL_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_PLL_STABLE_POS))
<> 144:ef7eb2e8f9f7 330 #define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS 2
<> 144:ef7eb2e8f9f7 331 #define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS))
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS 0
<> 144:ef7eb2e8f9f7 334 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS))
<> 144:ef7eb2e8f9f7 335 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS 1
<> 144:ef7eb2e8f9f7 336 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS))
<> 144:ef7eb2e8f9f7 337 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS 2
<> 144:ef7eb2e8f9f7 338 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS))
<> 144:ef7eb2e8f9f7 339 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS 3
<> 144:ef7eb2e8f9f7 340 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS))
<> 144:ef7eb2e8f9f7 341 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS 16
<> 144:ef7eb2e8f9f7 342 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS ((uint32_t)(0x000003FFUL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS))
<> 144:ef7eb2e8f9f7 343
<> 144:ef7eb2e8f9f7 344 #define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS 0
<> 144:ef7eb2e8f9f7 345 #define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS))
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 #define MXC_F_CLKMAN_CLK_CTRL_0_SYSTEM_SYS_CLK_SCALE_POS 0
<> 144:ef7eb2e8f9f7 348 #define MXC_F_CLKMAN_CLK_CTRL_0_SYSTEM_SYS_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_0_SYSTEM_SYS_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 349
<> 144:ef7eb2e8f9f7 350 #define MXC_F_CLKMAN_CLK_CTRL_1_GPIO_GPIO_CLK_SCALE_POS 0
<> 144:ef7eb2e8f9f7 351 #define MXC_F_CLKMAN_CLK_CTRL_1_GPIO_GPIO_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_1_GPIO_GPIO_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 #define MXC_F_CLKMAN_CLK_CTRL_2_PT_PULSE_TRAIN_CLK_SCALE_POS 0
<> 144:ef7eb2e8f9f7 354 #define MXC_F_CLKMAN_CLK_CTRL_2_PT_PULSE_TRAIN_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_2_PT_PULSE_TRAIN_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 #define MXC_F_CLKMAN_CLK_CTRL_3_SPI0_SPI0_CLK_SCALE_POS 0
<> 144:ef7eb2e8f9f7 357 #define MXC_F_CLKMAN_CLK_CTRL_3_SPI0_SPI0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_3_SPI0_SPI0_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 #define MXC_F_CLKMAN_CLK_CTRL_4_SPI1_SPI1_CLK_SCALE_POS 0
<> 144:ef7eb2e8f9f7 360 #define MXC_F_CLKMAN_CLK_CTRL_4_SPI1_SPI1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_4_SPI1_SPI1_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 361
<> 144:ef7eb2e8f9f7 362 #define MXC_F_CLKMAN_CLK_CTRL_5_SPI2_SPI2_CLK_SCALE_POS 0
<> 144:ef7eb2e8f9f7 363 #define MXC_F_CLKMAN_CLK_CTRL_5_SPI2_SPI2_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_5_SPI2_SPI2_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 #define MXC_F_CLKMAN_CLK_CTRL_6_I2CM_I2CM_CLK_SCALE_POS 0
<> 144:ef7eb2e8f9f7 366 #define MXC_F_CLKMAN_CLK_CTRL_6_I2CM_I2CM_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_6_I2CM_I2CM_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 367
<> 144:ef7eb2e8f9f7 368 #define MXC_F_CLKMAN_CLK_CTRL_7_I2CS_I2CS_CLK_SCALE_POS 0
<> 144:ef7eb2e8f9f7 369 #define MXC_F_CLKMAN_CLK_CTRL_7_I2CS_I2CS_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_7_I2CS_I2CS_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 #define MXC_F_CLKMAN_CLK_CTRL_8_LCD_CHPUMP_LCD_CLK_SCALE_POS 0
<> 144:ef7eb2e8f9f7 372 #define MXC_F_CLKMAN_CLK_CTRL_8_LCD_CHPUMP_LCD_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_8_LCD_CHPUMP_LCD_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 #define MXC_F_CLKMAN_CLK_CTRL_9_PUF_PUF_CLK_SCALE_POS 0
<> 144:ef7eb2e8f9f7 375 #define MXC_F_CLKMAN_CLK_CTRL_9_PUF_PUF_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_9_PUF_PUF_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 #define MXC_F_CLKMAN_CLK_CTRL_10_PRNG_PRNG_CLK_SCALE_POS 0
<> 144:ef7eb2e8f9f7 378 #define MXC_F_CLKMAN_CLK_CTRL_10_PRNG_PRNG_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_10_PRNG_PRNG_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 #define MXC_F_CLKMAN_CLK_CTRL_11_WDT0_WATCHDOG0_CLK_SCALE_POS 0
<> 144:ef7eb2e8f9f7 381 #define MXC_F_CLKMAN_CLK_CTRL_11_WDT0_WATCHDOG0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_11_WDT0_WATCHDOG0_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 382
<> 144:ef7eb2e8f9f7 383 #define MXC_F_CLKMAN_CLK_CTRL_12_WDT1_WATCHDOG1_CLK_SCALE_POS 0
<> 144:ef7eb2e8f9f7 384 #define MXC_F_CLKMAN_CLK_CTRL_12_WDT1_WATCHDOG1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_12_WDT1_WATCHDOG1_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 385
<> 144:ef7eb2e8f9f7 386 #define MXC_F_CLKMAN_CLK_CTRL_13_RTC_INT_SYNC_RTC_CLK_SCALE_POS 0
<> 144:ef7eb2e8f9f7 387 #define MXC_F_CLKMAN_CLK_CTRL_13_RTC_INT_SYNC_RTC_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_13_RTC_INT_SYNC_RTC_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 388
<> 144:ef7eb2e8f9f7 389 #define MXC_F_CLKMAN_CLK_CTRL_14_DAC0_DAC0_CLK_SCALE_POS 0
<> 144:ef7eb2e8f9f7 390 #define MXC_F_CLKMAN_CLK_CTRL_14_DAC0_DAC0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_14_DAC0_DAC0_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 391
<> 144:ef7eb2e8f9f7 392 #define MXC_F_CLKMAN_CLK_CTRL_15_DAC1_DAC1_CLK_SCALE_POS 0
<> 144:ef7eb2e8f9f7 393 #define MXC_F_CLKMAN_CLK_CTRL_15_DAC1_DAC1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_15_DAC1_DAC1_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 #define MXC_F_CLKMAN_CLK_CTRL_16_DAC2_DAC2_CLK_SCALE_POS 0
<> 144:ef7eb2e8f9f7 396 #define MXC_F_CLKMAN_CLK_CTRL_16_DAC2_DAC2_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_16_DAC2_DAC2_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 397
<> 144:ef7eb2e8f9f7 398 #define MXC_F_CLKMAN_CLK_CTRL_17_DAC3_DAC3_CLK_SCALE_POS 0
<> 144:ef7eb2e8f9f7 399 #define MXC_F_CLKMAN_CLK_CTRL_17_DAC3_DAC3_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_17_DAC3_DAC3_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS 0
<> 144:ef7eb2e8f9f7 402 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_UMAA_CLK_SCALE_POS 0
<> 144:ef7eb2e8f9f7 405 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_UMAA_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_UMAA_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 406
<> 144:ef7eb2e8f9f7 407 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS 0
<> 144:ef7eb2e8f9f7 408 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS))
<> 144:ef7eb2e8f9f7 409
<> 144:ef7eb2e8f9f7 410 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM3_CLK_GATER_POS 0
<> 144:ef7eb2e8f9f7 411 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM3_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_CM3_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 412 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSBUS_CLK_GATER_POS 2
<> 144:ef7eb2e8f9f7 413 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSBUS_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSBUS_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 414 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS 4
<> 144:ef7eb2e8f9f7 415 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 416 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS 6
<> 144:ef7eb2e8f9f7 417 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 418 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS 8
<> 144:ef7eb2e8f9f7 419 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 420 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS 10
<> 144:ef7eb2e8f9f7 421 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 422 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS 12
<> 144:ef7eb2e8f9f7 423 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 424 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART0_CLK_GATER_POS 14
<> 144:ef7eb2e8f9f7 425 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_UART0_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 426 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART1_CLK_GATER_POS 16
<> 144:ef7eb2e8f9f7 427 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_UART1_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 428 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER0_CLK_GATER_POS 18
<> 144:ef7eb2e8f9f7 429 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER0_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 430 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER1_CLK_GATER_POS 20
<> 144:ef7eb2e8f9f7 431 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER1_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 432 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER2_CLK_GATER_POS 22
<> 144:ef7eb2e8f9f7 433 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER2_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 434 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER3_CLK_GATER_POS 24
<> 144:ef7eb2e8f9f7 435 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER3_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER3_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 436 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS 26
<> 144:ef7eb2e8f9f7 437 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 438 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG1_CLK_GATER_POS 28
<> 144:ef7eb2e8f9f7 439 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG1_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 440 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS 30
<> 144:ef7eb2e8f9f7 441 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TESTACC_CLK_GATER_POS 0
<> 144:ef7eb2e8f9f7 444 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TESTACC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TESTACC_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 445 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_ADC_CLK_GATER_POS 2
<> 144:ef7eb2e8f9f7 446 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_ADC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_ADC_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 447 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_0_CLK_GATER_POS 4
<> 144:ef7eb2e8f9f7 448 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_0_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 449 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_1_CLK_GATER_POS 6
<> 144:ef7eb2e8f9f7 450 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_1_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 451 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_0_CLK_GATER_POS 8
<> 144:ef7eb2e8f9f7 452 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_0_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 453 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_1_CLK_GATER_POS 10
<> 144:ef7eb2e8f9f7 454 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_1_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 455 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_PMU_CLK_GATER_POS 12
<> 144:ef7eb2e8f9f7 456 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_PMU_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_PMU_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 457 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_LCD_CLK_GATER_POS 14
<> 144:ef7eb2e8f9f7 458 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_LCD_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_LCD_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 459 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS 16
<> 144:ef7eb2e8f9f7 460 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 461 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS 18
<> 144:ef7eb2e8f9f7 462 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 463 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI0_CLK_GATER_POS 20
<> 144:ef7eb2e8f9f7 464 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI0_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 465 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI1_CLK_GATER_POS 22
<> 144:ef7eb2e8f9f7 466 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI1_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 467 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI2_CLK_GATER_POS 24
<> 144:ef7eb2e8f9f7 468 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI2_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 469 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS 26
<> 144:ef7eb2e8f9f7 470 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 471 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS 28
<> 144:ef7eb2e8f9f7 472 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 473 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CS_CLK_GATER_POS 30
<> 144:ef7eb2e8f9f7 474 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CS_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CS_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 475
<> 144:ef7eb2e8f9f7 476 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_CRC_CLK_GATER_POS 0
<> 144:ef7eb2e8f9f7 477 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_CRC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_CRC_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 478 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_TPU_CLK_GATER_POS 2
<> 144:ef7eb2e8f9f7 479 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_TPU_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_TPU_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 480 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SSBMUX_CLK_GATER_POS 4
<> 144:ef7eb2e8f9f7 481 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SSBMUX_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SSBMUX_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 482 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_PAD_CLK_GATER_POS 6
<> 144:ef7eb2e8f9f7 483 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_PAD_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_PAD_CLK_GATER_POS))
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 486 }
<> 144:ef7eb2e8f9f7 487 #endif
<> 144:ef7eb2e8f9f7 488
<> 144:ef7eb2e8f9f7 489 /**
<> 144:ef7eb2e8f9f7 490 * @}
<> 144:ef7eb2e8f9f7 491 */
<> 144:ef7eb2e8f9f7 492
<> 144:ef7eb2e8f9f7 493 #endif /* _MXC_CLKMAN_REGS_H_ */