Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Maxim/TARGET_MAX32610/clkman_regs.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /*******************************************************************************
bogdanm 0:9b334a45a8ff 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
bogdanm 0:9b334a45a8ff 3 *
bogdanm 0:9b334a45a8ff 4 * Permission is hereby granted, free of charge, to any person obtaining a
bogdanm 0:9b334a45a8ff 5 * copy of this software and associated documentation files (the "Software"),
bogdanm 0:9b334a45a8ff 6 * to deal in the Software without restriction, including without limitation
bogdanm 0:9b334a45a8ff 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
bogdanm 0:9b334a45a8ff 8 * and/or sell copies of the Software, and to permit persons to whom the
bogdanm 0:9b334a45a8ff 9 * Software is furnished to do so, subject to the following conditions:
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 * The above copyright notice and this permission notice shall be included
bogdanm 0:9b334a45a8ff 12 * in all copies or substantial portions of the Software.
bogdanm 0:9b334a45a8ff 13 *
bogdanm 0:9b334a45a8ff 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
bogdanm 0:9b334a45a8ff 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
bogdanm 0:9b334a45a8ff 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
bogdanm 0:9b334a45a8ff 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
bogdanm 0:9b334a45a8ff 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
bogdanm 0:9b334a45a8ff 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
bogdanm 0:9b334a45a8ff 20 * OTHER DEALINGS IN THE SOFTWARE.
bogdanm 0:9b334a45a8ff 21 *
bogdanm 0:9b334a45a8ff 22 * Except as contained in this notice, the name of Maxim Integrated
bogdanm 0:9b334a45a8ff 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
bogdanm 0:9b334a45a8ff 24 * Products, Inc. Branding Policy.
bogdanm 0:9b334a45a8ff 25 *
bogdanm 0:9b334a45a8ff 26 * The mere transfer of this software does not imply any licenses
bogdanm 0:9b334a45a8ff 27 * of trade secrets, proprietary technology, copyrights, patents,
bogdanm 0:9b334a45a8ff 28 * trademarks, maskwork rights, or any other form of intellectual
bogdanm 0:9b334a45a8ff 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
bogdanm 0:9b334a45a8ff 30 * ownership rights.
bogdanm 0:9b334a45a8ff 31 *******************************************************************************
bogdanm 0:9b334a45a8ff 32 */
bogdanm 0:9b334a45a8ff 33
bogdanm 0:9b334a45a8ff 34 #ifndef _MXC_CLKMAN_REGS_H_
bogdanm 0:9b334a45a8ff 35 #define _MXC_CLKMAN_REGS_H_
bogdanm 0:9b334a45a8ff 36
bogdanm 0:9b334a45a8ff 37 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 38 extern "C" {
bogdanm 0:9b334a45a8ff 39 #endif
bogdanm 0:9b334a45a8ff 40
bogdanm 0:9b334a45a8ff 41 #include <stdint.h>
bogdanm 0:9b334a45a8ff 42
bogdanm 0:9b334a45a8ff 43 /**
bogdanm 0:9b334a45a8ff 44 * @file clkman_regs.h
bogdanm 0:9b334a45a8ff 45 * @addtogroup clkman CLKMAN
bogdanm 0:9b334a45a8ff 46 * @{
bogdanm 0:9b334a45a8ff 47 */
bogdanm 0:9b334a45a8ff 48
bogdanm 0:9b334a45a8ff 49 /**
bogdanm 0:9b334a45a8ff 50 * @brief Defines clock input selections for the phase locked loop.
bogdanm 0:9b334a45a8ff 51 */
bogdanm 0:9b334a45a8ff 52 typedef enum {
bogdanm 0:9b334a45a8ff 53 /** Input select for high frequency crystal oscillator */
bogdanm 0:9b334a45a8ff 54 MXC_E_CLKMAN_PLL_INPUT_SELECT_HFX = 0,
bogdanm 0:9b334a45a8ff 55 /** Input select for 24MHz ring oscillator */
bogdanm 0:9b334a45a8ff 56 MXC_E_CLKMAN_PLL_INPUT_SELECT_24MHZ_RO,
bogdanm 0:9b334a45a8ff 57 } mxc_clkman_pll_input_select_t;
bogdanm 0:9b334a45a8ff 58
bogdanm 0:9b334a45a8ff 59 /**
bogdanm 0:9b334a45a8ff 60 * @brief Defines clock input frequency for the phase locked loop.
bogdanm 0:9b334a45a8ff 61 */
bogdanm 0:9b334a45a8ff 62 typedef enum {
bogdanm 0:9b334a45a8ff 63 /** Input frequency of 24MHz */
bogdanm 0:9b334a45a8ff 64 MXC_E_CLKMAN_PLL_DIVISOR_SELECT_24MHZ = 0,
bogdanm 0:9b334a45a8ff 65 /** Input frequency of 12MHz */
bogdanm 0:9b334a45a8ff 66 MXC_E_CLKMAN_PLL_DIVISOR_SELECT_12MHZ,
bogdanm 0:9b334a45a8ff 67 /** Input frequency of 8MHz */
bogdanm 0:9b334a45a8ff 68 MXC_E_CLKMAN_PLL_DIVISOR_SELECT_8MHZ,
bogdanm 0:9b334a45a8ff 69 } mxc_clkman_pll_divisor_select_t;
bogdanm 0:9b334a45a8ff 70
bogdanm 0:9b334a45a8ff 71 /**
bogdanm 0:9b334a45a8ff 72 * @brief Defines terminal count for PLL stable.
bogdanm 0:9b334a45a8ff 73 */
bogdanm 0:9b334a45a8ff 74 typedef enum {
bogdanm 0:9b334a45a8ff 75 /** Clock stable after 2^8 = 256 clock cycles */
bogdanm 0:9b334a45a8ff 76 MXC_E_CLKMAN_STABILITY_COUNT_2_8_CLKS = 0,
bogdanm 0:9b334a45a8ff 77 /** Clock stable after 2^9 = 512 clock cycles */
bogdanm 0:9b334a45a8ff 78 MXC_E_CLKMAN_STABILITY_COUNT_2_9_CLKS,
bogdanm 0:9b334a45a8ff 79 /** Clock stable after 2^10 = 1024 clock cycles */
bogdanm 0:9b334a45a8ff 80 MXC_E_CLKMAN_STABILITY_COUNT_2_10_CLKS,
bogdanm 0:9b334a45a8ff 81 /** Clock stable after 2^11 = 2048 clock cycles */
bogdanm 0:9b334a45a8ff 82 MXC_E_CLKMAN_STABILITY_COUNT_2_11_CLKS,
bogdanm 0:9b334a45a8ff 83 /** Clock stable after 2^12 = 4096 clock cycles */
bogdanm 0:9b334a45a8ff 84 MXC_E_CLKMAN_STABILITY_COUNT_2_12_CLKS,
bogdanm 0:9b334a45a8ff 85 /** Clock stable after 2^13 = 8192 clock cycles */
bogdanm 0:9b334a45a8ff 86 MXC_E_CLKMAN_STABILITY_COUNT_2_13_CLKS,
bogdanm 0:9b334a45a8ff 87 /** Clock stable after 2^14 = 16384 clock cycles */
bogdanm 0:9b334a45a8ff 88 MXC_E_CLKMAN_STABILITY_COUNT_2_14_CLKS,
bogdanm 0:9b334a45a8ff 89 /** Clock stable after 2^15 = 32768 clock cycles */
bogdanm 0:9b334a45a8ff 90 MXC_E_CLKMAN_STABILITY_COUNT_2_15_CLKS,
bogdanm 0:9b334a45a8ff 91 /** Clock stable after 2^16 = 65536 clock cycles */
bogdanm 0:9b334a45a8ff 92 MXC_E_CLKMAN_STABILITY_COUNT_2_16_CLKS,
bogdanm 0:9b334a45a8ff 93 /** Clock stable after 2^17 = 131072 clock cycles */
bogdanm 0:9b334a45a8ff 94 MXC_E_CLKMAN_STABILITY_COUNT_2_17_CLKS,
bogdanm 0:9b334a45a8ff 95 /** Clock stable after 2^18 = 262144 clock cycles */
bogdanm 0:9b334a45a8ff 96 MXC_E_CLKMAN_STABILITY_COUNT_2_18_CLKS,
bogdanm 0:9b334a45a8ff 97 /** Clock stable after 2^19 = 524288 clock cycles */
bogdanm 0:9b334a45a8ff 98 MXC_E_CLKMAN_STABILITY_COUNT_2_19_CLKS,
bogdanm 0:9b334a45a8ff 99 /** Clock stable after 2^20 = 1048576 clock cycles */
bogdanm 0:9b334a45a8ff 100 MXC_E_CLKMAN_STABILITY_COUNT_2_20_CLKS,
bogdanm 0:9b334a45a8ff 101 /** Clock stable after 2^21 = 2097152 clock cycles */
bogdanm 0:9b334a45a8ff 102 MXC_E_CLKMAN_STABILITY_COUNT_2_21_CLKS,
bogdanm 0:9b334a45a8ff 103 /** Clock stable after 2^22 = 4194304 clock cycles */
bogdanm 0:9b334a45a8ff 104 MXC_E_CLKMAN_STABILITY_COUNT_2_22_CLKS,
bogdanm 0:9b334a45a8ff 105 /** Clock stable after 2^23 = 8388608 clock cycles */
bogdanm 0:9b334a45a8ff 106 MXC_E_CLKMAN_STABILITY_COUNT_2_23_CLKS
bogdanm 0:9b334a45a8ff 107 } mxc_clkman_stability_count_t;
bogdanm 0:9b334a45a8ff 108
bogdanm 0:9b334a45a8ff 109 /**
bogdanm 0:9b334a45a8ff 110 * @brief Defines clock source selections for system clock.
bogdanm 0:9b334a45a8ff 111 */
bogdanm 0:9b334a45a8ff 112 typedef enum {
bogdanm 0:9b334a45a8ff 113 /** Clock select for 24MHz ring oscillator divided by 8 (3MHz) */
bogdanm 0:9b334a45a8ff 114 MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO_DIV_8 = 0,
bogdanm 0:9b334a45a8ff 115 /** Clock select for 24MHz ring oscillator */
bogdanm 0:9b334a45a8ff 116 MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO,
bogdanm 0:9b334a45a8ff 117 /** Clock select for high frequency crystal oscillator */
bogdanm 0:9b334a45a8ff 118 MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_HFX,
bogdanm 0:9b334a45a8ff 119 /** Clock select for 48MHz phase locked loop output divided by 2 (24MHz) */
bogdanm 0:9b334a45a8ff 120 MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_PLL_48MHZ_DIV_2
bogdanm 0:9b334a45a8ff 121 } mxc_clkman_system_source_select_t;
bogdanm 0:9b334a45a8ff 122
bogdanm 0:9b334a45a8ff 123 /**
bogdanm 0:9b334a45a8ff 124 * @brief Defines clock source selections for analog to digital converter clock.
bogdanm 0:9b334a45a8ff 125 */
bogdanm 0:9b334a45a8ff 126 typedef enum {
bogdanm 0:9b334a45a8ff 127 /** Clock select for system clock frequency */
bogdanm 0:9b334a45a8ff 128 MXC_E_CLKMAN_ADC_SOURCE_SELECT_SYSTEM = 0,
bogdanm 0:9b334a45a8ff 129 /** Clock select for 8MHz phase locked loop output */
bogdanm 0:9b334a45a8ff 130 MXC_E_CLKMAN_ADC_SOURCE_SELECT_PLL_8MHZ,
bogdanm 0:9b334a45a8ff 131 /** Clock select for high frequency crystal oscillator */
bogdanm 0:9b334a45a8ff 132 MXC_E_CLKMAN_ADC_SOURCE_SELECT_HFX,
bogdanm 0:9b334a45a8ff 133 /** Clock select for 24MHz ring oscillator */
bogdanm 0:9b334a45a8ff 134 MXC_E_CLKMAN_ADC_SOURCE_SELECT_24MHZ_RO,
bogdanm 0:9b334a45a8ff 135 } mxc_clkman_adc_source_select_t;
bogdanm 0:9b334a45a8ff 136
bogdanm 0:9b334a45a8ff 137 /**
bogdanm 0:9b334a45a8ff 138 * @brief Defines clock source selections for watchdog timer clock.
bogdanm 0:9b334a45a8ff 139 */
bogdanm 0:9b334a45a8ff 140 typedef enum {
bogdanm 0:9b334a45a8ff 141 /** Clock select for system clock frequency */
bogdanm 0:9b334a45a8ff 142 MXC_E_CLKMAN_WDT_SOURCE_SELECT_SYSTEM = 0,
bogdanm 0:9b334a45a8ff 143 /** Clock select for 8MHz phase locked loop output */
bogdanm 0:9b334a45a8ff 144 MXC_E_CLKMAN_WDT_SOURCE_SELECT_RTC,
bogdanm 0:9b334a45a8ff 145 /** Clock select for high frequency crystal oscillator */
bogdanm 0:9b334a45a8ff 146 MXC_E_CLKMAN_WDT_SOURCE_SELECT_24MHZ_RO,
bogdanm 0:9b334a45a8ff 147 /** Clock select for 24MHz ring oscillator */
bogdanm 0:9b334a45a8ff 148 MXC_E_CLKMAN_WDT_SOURCE_SELECT_NANO,
bogdanm 0:9b334a45a8ff 149 } mxc_clkman_wdt_source_select_t;
bogdanm 0:9b334a45a8ff 150
bogdanm 0:9b334a45a8ff 151 /**
bogdanm 0:9b334a45a8ff 152 * @brief Defines clock scales for various clocks.
bogdanm 0:9b334a45a8ff 153 */
bogdanm 0:9b334a45a8ff 154 typedef enum {
bogdanm 0:9b334a45a8ff 155 /** Clock disabled */
bogdanm 0:9b334a45a8ff 156 MXC_E_CLKMAN_CLK_SCALE_DISABLED = 0,
bogdanm 0:9b334a45a8ff 157 /** Clock enabled */
bogdanm 0:9b334a45a8ff 158 MXC_E_CLKMAN_CLK_SCALE_ENABLED,
bogdanm 0:9b334a45a8ff 159 /** Clock scale for dividing by 2 */
bogdanm 0:9b334a45a8ff 160 MXC_E_CLKMAN_CLK_SCALE_DIV_2,
bogdanm 0:9b334a45a8ff 161 /** Clock scale for dividing by 4 */
bogdanm 0:9b334a45a8ff 162 MXC_E_CLKMAN_CLK_SCALE_DIV_4,
bogdanm 0:9b334a45a8ff 163 /** Clock scale for dividing by 8 */
bogdanm 0:9b334a45a8ff 164 MXC_E_CLKMAN_CLK_SCALE_DIV_8,
bogdanm 0:9b334a45a8ff 165 /** Clock scale for dividing by 16 */
bogdanm 0:9b334a45a8ff 166 MXC_E_CLKMAN_CLK_SCALE_DIV_16,
bogdanm 0:9b334a45a8ff 167 /** Clock scale for dividing by 32 */
bogdanm 0:9b334a45a8ff 168 MXC_E_CLKMAN_CLK_SCALE_DIV_32,
bogdanm 0:9b334a45a8ff 169 /** Clock scale for dividing by 64 */
bogdanm 0:9b334a45a8ff 170 MXC_E_CLKMAN_CLK_SCALE_DIV_64,
bogdanm 0:9b334a45a8ff 171 /** Clock scale for dividing by 128 */
bogdanm 0:9b334a45a8ff 172 MXC_E_CLKMAN_CLK_SCALE_DIV_128,
bogdanm 0:9b334a45a8ff 173 /** Clock scale for dividing by 256 */
bogdanm 0:9b334a45a8ff 174 MXC_E_CLKMAN_CLK_SCALE_DIV_256
bogdanm 0:9b334a45a8ff 175 } mxc_clkman_clk_scale_t;
bogdanm 0:9b334a45a8ff 176
bogdanm 0:9b334a45a8ff 177 /**
bogdanm 0:9b334a45a8ff 178 * @brief Defines Setting of the Clock Gates .
bogdanm 0:9b334a45a8ff 179 */
bogdanm 0:9b334a45a8ff 180 typedef enum {
bogdanm 0:9b334a45a8ff 181 /** Clock Gater is Off */
bogdanm 0:9b334a45a8ff 182 MXC_E_CLKMAN_CLK_GATE_OFF = 0,
bogdanm 0:9b334a45a8ff 183 /** Clock Gater is Dynamic */
bogdanm 0:9b334a45a8ff 184 MXC_E_CLKMAN_CLK_GATE_DYNAMIC,
bogdanm 0:9b334a45a8ff 185 /** Clock Gater is On */
bogdanm 0:9b334a45a8ff 186 MXC_E_CLKMAN_CLK_GATE_ON
bogdanm 0:9b334a45a8ff 187 } mxc_clkman_clk_gate_t;
bogdanm 0:9b334a45a8ff 188
bogdanm 0:9b334a45a8ff 189 /* Offset Register Description
bogdanm 0:9b334a45a8ff 190 ====== ===================================================================== */
bogdanm 0:9b334a45a8ff 191 typedef struct {
bogdanm 0:9b334a45a8ff 192 __IO uint32_t clk_config; /* 0x0000 System Clock Configuration */
bogdanm 0:9b334a45a8ff 193 __IO uint32_t clk_ctrl; /* 0x0004 System Clock Controls */
bogdanm 0:9b334a45a8ff 194 __IO uint32_t intfl; /* 0x0008 Interrupt Flags */
bogdanm 0:9b334a45a8ff 195 __IO uint32_t inten; /* 0x000C Interrupt Enable/Disable Controls */
bogdanm 0:9b334a45a8ff 196 __IO uint32_t trim_calc; /* 0x0010 Trim Calculation Controls */
bogdanm 0:9b334a45a8ff 197 __I uint32_t rsv0014[4]; /* 0x0014 */
bogdanm 0:9b334a45a8ff 198 __IO uint32_t i2c_timer_ctrl; /* 0x0024 I2C Timer Control */
bogdanm 0:9b334a45a8ff 199 __I uint32_t rsv0028[6]; /* 0x0028 */
bogdanm 0:9b334a45a8ff 200 __IO uint32_t clk_ctrl_0_system; /* 0x0040 Control Settings for CLK0 - System Clock */
bogdanm 0:9b334a45a8ff 201 __IO uint32_t clk_ctrl_1_gpio; /* 0x0044 Control Settings for CLK1 - GPIO Module Clock */
bogdanm 0:9b334a45a8ff 202 __IO uint32_t clk_ctrl_2_pt; /* 0x0048 Control Settings for CLK2 - Pulse Train Module Clock */
bogdanm 0:9b334a45a8ff 203 __IO uint32_t clk_ctrl_3_spi0; /* 0x004C Control Settings for CLK3 - SPI0 Master Clock */
bogdanm 0:9b334a45a8ff 204 __IO uint32_t clk_ctrl_4_spi1; /* 0x0050 Control Settings for CLK4 - SPI1 Master Clock */
bogdanm 0:9b334a45a8ff 205 __IO uint32_t clk_ctrl_5_spi2; /* 0x0054 Control Settings for CLK5 - SPI2 Master Clock */
bogdanm 0:9b334a45a8ff 206 __IO uint32_t clk_ctrl_6_i2cm; /* 0x0058 Control Settings for CLK6 - Clock for all I2C Masters */
bogdanm 0:9b334a45a8ff 207 __IO uint32_t clk_ctrl_7_i2cs; /* 0x005C Control Settings for CLK7 - I2C Slave Clock */
bogdanm 0:9b334a45a8ff 208 __IO uint32_t clk_ctrl_8_lcd_chpump; /* 0x0060 Control Settings for CLK8 - LCD Charge Pump Clock */
bogdanm 0:9b334a45a8ff 209 __IO uint32_t clk_ctrl_9_puf; /* 0x0064 Control Settings for CLK9 - PUF Clock */
bogdanm 0:9b334a45a8ff 210 __IO uint32_t clk_ctrl_10_prng; /* 0x0068 Control Settings for CLK10 - PRNG Clock */
bogdanm 0:9b334a45a8ff 211 __IO uint32_t clk_ctrl_11_wdt0; /* 0x006C Control Settings for CLK11 - Watchdog Timer 0 ScaledSysClk */
bogdanm 0:9b334a45a8ff 212 __IO uint32_t clk_ctrl_12_wdt1; /* 0x0070 Control Settings for CLK12 - Watchdog Timer 1 ScaledSysClk */
bogdanm 0:9b334a45a8ff 213 __IO uint32_t clk_ctrl_13_rtc_int_sync; /* 0x0074 Control Settings for CLK13 - RTC Interrupt Sync Clock */
bogdanm 0:9b334a45a8ff 214 __IO uint32_t clk_ctrl_14_dac0; /* 0x0078 Control Settings for CLK14 - 12-bit DAC 0 Clock */
bogdanm 0:9b334a45a8ff 215 __IO uint32_t clk_ctrl_15_dac1; /* 0x007C Control Settings for CLK15 - 12-bit DAC 1 Clock */
bogdanm 0:9b334a45a8ff 216 __IO uint32_t clk_ctrl_16_dac2; /* 0x0080 Control Settings for CLK16 - 8-bit DAC 0 Clock */
bogdanm 0:9b334a45a8ff 217 __IO uint32_t clk_ctrl_17_dac3; /* 0x0084 Control Settings for CLK17 - 8-bit DAC 1 Clock */
bogdanm 0:9b334a45a8ff 218 __I uint32_t rsv0088[30]; /* 0x0088 */
bogdanm 0:9b334a45a8ff 219 __IO uint32_t crypt_clk_ctrl_0_aes; /* 0x0100 Control Settings for Crypto Clock 0 - AES */
bogdanm 0:9b334a45a8ff 220 __IO uint32_t crypt_clk_ctrl_1_maa; /* 0x0104 Control Settings for Crypto Clock 1 - MAA */
bogdanm 0:9b334a45a8ff 221 __IO uint32_t crypt_clk_ctrl_2_prng; /* 0x0108 Control Settings for Crypto Clock 2 - PRNG */
bogdanm 0:9b334a45a8ff 222 __I uint32_t rsv010C[13]; /* 0x010C */
bogdanm 0:9b334a45a8ff 223 __IO uint32_t clk_gate_ctrl0; /* 0x0140 Dynamic Clock Gating Control Register 0 */
bogdanm 0:9b334a45a8ff 224 __IO uint32_t clk_gate_ctrl1; /* 0x0144 Dynamic Clock Gating Control Register 1 */
bogdanm 0:9b334a45a8ff 225 __IO uint32_t clk_gate_ctrl2; /* 0x0148 Dynamic Clock Gating Control Register 2 */
bogdanm 0:9b334a45a8ff 226 } mxc_clkman_regs_t;
bogdanm 0:9b334a45a8ff 227
bogdanm 0:9b334a45a8ff 228 /*
bogdanm 0:9b334a45a8ff 229 Register offsets for module CLKMAN.
bogdanm 0:9b334a45a8ff 230 */
bogdanm 0:9b334a45a8ff 231 #define MXC_R_CLKMAN_OFFS_CLK_CONFIG ((uint32_t)0x00000000UL)
bogdanm 0:9b334a45a8ff 232 #define MXC_R_CLKMAN_OFFS_CLK_CTRL ((uint32_t)0x00000004UL)
bogdanm 0:9b334a45a8ff 233 #define MXC_R_CLKMAN_OFFS_INTFL ((uint32_t)0x00000008UL)
bogdanm 0:9b334a45a8ff 234 #define MXC_R_CLKMAN_OFFS_INTEN ((uint32_t)0x0000000CUL)
bogdanm 0:9b334a45a8ff 235 #define MXC_R_CLKMAN_OFFS_TRIM_CALC ((uint32_t)0x00000010UL)
bogdanm 0:9b334a45a8ff 236 #define MXC_R_CLKMAN_OFFS_I2C_TIMER_CTRL ((uint32_t)0x00000024UL)
bogdanm 0:9b334a45a8ff 237 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_0_SYSTEM ((uint32_t)0x00000040UL)
bogdanm 0:9b334a45a8ff 238 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_1_GPIO ((uint32_t)0x00000044UL)
bogdanm 0:9b334a45a8ff 239 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_2_PT ((uint32_t)0x00000048UL)
bogdanm 0:9b334a45a8ff 240 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_3_SPI0 ((uint32_t)0x0000004CUL)
bogdanm 0:9b334a45a8ff 241 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_4_SPI1 ((uint32_t)0x00000050UL)
bogdanm 0:9b334a45a8ff 242 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_5_SPI2 ((uint32_t)0x00000054UL)
bogdanm 0:9b334a45a8ff 243 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_6_I2CM ((uint32_t)0x00000058UL)
bogdanm 0:9b334a45a8ff 244 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_7_I2CS ((uint32_t)0x0000005CUL)
bogdanm 0:9b334a45a8ff 245 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_8_LCD_CHPUMP ((uint32_t)0x00000060UL)
bogdanm 0:9b334a45a8ff 246 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_9_PUF ((uint32_t)0x00000064UL)
bogdanm 0:9b334a45a8ff 247 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_10_PRNG ((uint32_t)0x00000068UL)
bogdanm 0:9b334a45a8ff 248 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_11_WDT0 ((uint32_t)0x0000006CUL)
bogdanm 0:9b334a45a8ff 249 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_12_WDT1 ((uint32_t)0x00000070UL)
bogdanm 0:9b334a45a8ff 250 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_13_RTC_INT_SYNC ((uint32_t)0x00000074UL)
bogdanm 0:9b334a45a8ff 251 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_14_DAC0 ((uint32_t)0x00000078UL)
bogdanm 0:9b334a45a8ff 252 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_15_DAC1 ((uint32_t)0x0000007CUL)
bogdanm 0:9b334a45a8ff 253 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_16_DAC2 ((uint32_t)0x00000080UL)
bogdanm 0:9b334a45a8ff 254 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_17_DAC3 ((uint32_t)0x00000084UL)
bogdanm 0:9b334a45a8ff 255 #define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_0_AES ((uint32_t)0x00000100UL)
bogdanm 0:9b334a45a8ff 256 #define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_1_MAA ((uint32_t)0x00000104UL)
bogdanm 0:9b334a45a8ff 257 #define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_2_PRNG ((uint32_t)0x00000108UL)
bogdanm 0:9b334a45a8ff 258 #define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL0 ((uint32_t)0x00000140UL)
bogdanm 0:9b334a45a8ff 259 #define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL1 ((uint32_t)0x00000144UL)
bogdanm 0:9b334a45a8ff 260 #define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL2 ((uint32_t)0x00000148UL)
bogdanm 0:9b334a45a8ff 261
bogdanm 0:9b334a45a8ff 262 /*
bogdanm 0:9b334a45a8ff 263 Field positions and masks for module CLKMAN.
bogdanm 0:9b334a45a8ff 264 */
bogdanm 0:9b334a45a8ff 265 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_ENABLE_POS 0
bogdanm 0:9b334a45a8ff 266 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_ENABLE_POS))
bogdanm 0:9b334a45a8ff 267 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_BYPASS_POS 1
bogdanm 0:9b334a45a8ff 268 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_BYPASS ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_BYPASS_POS))
bogdanm 0:9b334a45a8ff 269 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_TEST_ENABLE_POS 2
bogdanm 0:9b334a45a8ff 270 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_TEST_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_TEST_ENABLE_POS))
bogdanm 0:9b334a45a8ff 271 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_GM_ADJUST_POS 4
bogdanm 0:9b334a45a8ff 272 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_GM_ADJUST ((uint32_t)(0x0000001FUL << MXC_F_CLKMAN_CLK_CONFIG_HFX_GM_ADJUST_POS))
bogdanm 0:9b334a45a8ff 273 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_DC_CONTROL_POS 9
bogdanm 0:9b334a45a8ff 274 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_DC_CONTROL ((uint32_t)(0x00000007UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_DC_CONTROL_POS))
bogdanm 0:9b334a45a8ff 275 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE_POS 12
bogdanm 0:9b334a45a8ff 276 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE_POS))
bogdanm 0:9b334a45a8ff 277 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_RESET_N_POS 13
bogdanm 0:9b334a45a8ff 278 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_RESET_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_RESET_N_POS))
bogdanm 0:9b334a45a8ff 279 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_INPUT_SELECT_POS 14
bogdanm 0:9b334a45a8ff 280 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_INPUT_SELECT ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_INPUT_SELECT_POS))
bogdanm 0:9b334a45a8ff 281 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT_POS 16
bogdanm 0:9b334a45a8ff 282 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT_POS))
bogdanm 0:9b334a45a8ff 283 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_8MHZ_ENABLE_POS 18
bogdanm 0:9b334a45a8ff 284 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_8MHZ_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_8MHZ_ENABLE_POS))
bogdanm 0:9b334a45a8ff 285 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_BYPASS_POS 19
bogdanm 0:9b334a45a8ff 286 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_BYPASS ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_BYPASS_POS))
bogdanm 0:9b334a45a8ff 287 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_STABILITY_COUNT_POS 20
bogdanm 0:9b334a45a8ff 288 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_STABILITY_COUNT ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CONFIG_PLL_STABILITY_COUNT_POS))
bogdanm 0:9b334a45a8ff 289 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS 24
bogdanm 0:9b334a45a8ff 290 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS))
bogdanm 0:9b334a45a8ff 291 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_RESET_N_POS 25
bogdanm 0:9b334a45a8ff 292 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_RESET_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_RESET_N_POS))
bogdanm 0:9b334a45a8ff 293 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS 28
bogdanm 0:9b334a45a8ff 294 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
bogdanm 0:9b334a45a8ff 295
bogdanm 0:9b334a45a8ff 296 #define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS 1
bogdanm 0:9b334a45a8ff 297 #define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS))
bogdanm 0:9b334a45a8ff 298 #define MXC_F_CLKMAN_CLK_CTRL_AUTO_CLK_DISABLE_POS 3
bogdanm 0:9b334a45a8ff 299 #define MXC_F_CLKMAN_CLK_CTRL_AUTO_CLK_DISABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_AUTO_CLK_DISABLE_POS))
bogdanm 0:9b334a45a8ff 300 #define MXC_F_CLKMAN_CLK_CTRL_USB_GATE_N_POS 4
bogdanm 0:9b334a45a8ff 301 #define MXC_F_CLKMAN_CLK_CTRL_USB_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_USB_GATE_N_POS))
bogdanm 0:9b334a45a8ff 302 #define MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N_POS 8
bogdanm 0:9b334a45a8ff 303 #define MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N_POS))
bogdanm 0:9b334a45a8ff 304 #define MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT_POS 9
bogdanm 0:9b334a45a8ff 305 #define MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT_POS))
bogdanm 0:9b334a45a8ff 306 #define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_GATE_N_POS 12
bogdanm 0:9b334a45a8ff 307 #define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_CRYPTO_GATE_N_POS))
bogdanm 0:9b334a45a8ff 308 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_GATE_N_POS 16
bogdanm 0:9b334a45a8ff 309 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_GATE_N_POS))
bogdanm 0:9b334a45a8ff 310 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_SOURCE_SELECT_POS 17
bogdanm 0:9b334a45a8ff 311 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_SOURCE_SELECT_POS))
bogdanm 0:9b334a45a8ff 312 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_GATE_N_POS 20
bogdanm 0:9b334a45a8ff 313 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_GATE_N_POS))
bogdanm 0:9b334a45a8ff 314 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_SOURCE_SELECT_POS 21
bogdanm 0:9b334a45a8ff 315 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_SOURCE_SELECT_POS))
bogdanm 0:9b334a45a8ff 316 #define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS 24
bogdanm 0:9b334a45a8ff 317 #define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS))
bogdanm 0:9b334a45a8ff 318
bogdanm 0:9b334a45a8ff 319 #define MXC_F_CLKMAN_INTFL_RING_STABLE_POS 0
bogdanm 0:9b334a45a8ff 320 #define MXC_F_CLKMAN_INTFL_RING_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_RING_STABLE_POS))
bogdanm 0:9b334a45a8ff 321 #define MXC_F_CLKMAN_INTFL_PLL_STABLE_POS 1
bogdanm 0:9b334a45a8ff 322 #define MXC_F_CLKMAN_INTFL_PLL_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_PLL_STABLE_POS))
bogdanm 0:9b334a45a8ff 323 #define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS 2
bogdanm 0:9b334a45a8ff 324 #define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS))
bogdanm 0:9b334a45a8ff 325
bogdanm 0:9b334a45a8ff 326 #define MXC_F_CLKMAN_INTEN_RING_STABLE_POS 0
bogdanm 0:9b334a45a8ff 327 #define MXC_F_CLKMAN_INTEN_RING_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_RING_STABLE_POS))
bogdanm 0:9b334a45a8ff 328 #define MXC_F_CLKMAN_INTEN_PLL_STABLE_POS 1
bogdanm 0:9b334a45a8ff 329 #define MXC_F_CLKMAN_INTEN_PLL_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_PLL_STABLE_POS))
bogdanm 0:9b334a45a8ff 330 #define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS 2
bogdanm 0:9b334a45a8ff 331 #define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS))
bogdanm 0:9b334a45a8ff 332
bogdanm 0:9b334a45a8ff 333 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS 0
bogdanm 0:9b334a45a8ff 334 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS))
bogdanm 0:9b334a45a8ff 335 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS 1
bogdanm 0:9b334a45a8ff 336 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS))
bogdanm 0:9b334a45a8ff 337 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS 2
bogdanm 0:9b334a45a8ff 338 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS))
bogdanm 0:9b334a45a8ff 339 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS 3
bogdanm 0:9b334a45a8ff 340 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS))
bogdanm 0:9b334a45a8ff 341 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS 16
bogdanm 0:9b334a45a8ff 342 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS ((uint32_t)(0x000003FFUL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS))
bogdanm 0:9b334a45a8ff 343
bogdanm 0:9b334a45a8ff 344 #define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS 0
bogdanm 0:9b334a45a8ff 345 #define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS))
bogdanm 0:9b334a45a8ff 346
bogdanm 0:9b334a45a8ff 347 #define MXC_F_CLKMAN_CLK_CTRL_0_SYSTEM_SYS_CLK_SCALE_POS 0
bogdanm 0:9b334a45a8ff 348 #define MXC_F_CLKMAN_CLK_CTRL_0_SYSTEM_SYS_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_0_SYSTEM_SYS_CLK_SCALE_POS))
bogdanm 0:9b334a45a8ff 349
bogdanm 0:9b334a45a8ff 350 #define MXC_F_CLKMAN_CLK_CTRL_1_GPIO_GPIO_CLK_SCALE_POS 0
bogdanm 0:9b334a45a8ff 351 #define MXC_F_CLKMAN_CLK_CTRL_1_GPIO_GPIO_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_1_GPIO_GPIO_CLK_SCALE_POS))
bogdanm 0:9b334a45a8ff 352
bogdanm 0:9b334a45a8ff 353 #define MXC_F_CLKMAN_CLK_CTRL_2_PT_PULSE_TRAIN_CLK_SCALE_POS 0
bogdanm 0:9b334a45a8ff 354 #define MXC_F_CLKMAN_CLK_CTRL_2_PT_PULSE_TRAIN_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_2_PT_PULSE_TRAIN_CLK_SCALE_POS))
bogdanm 0:9b334a45a8ff 355
bogdanm 0:9b334a45a8ff 356 #define MXC_F_CLKMAN_CLK_CTRL_3_SPI0_SPI0_CLK_SCALE_POS 0
bogdanm 0:9b334a45a8ff 357 #define MXC_F_CLKMAN_CLK_CTRL_3_SPI0_SPI0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_3_SPI0_SPI0_CLK_SCALE_POS))
bogdanm 0:9b334a45a8ff 358
bogdanm 0:9b334a45a8ff 359 #define MXC_F_CLKMAN_CLK_CTRL_4_SPI1_SPI1_CLK_SCALE_POS 0
bogdanm 0:9b334a45a8ff 360 #define MXC_F_CLKMAN_CLK_CTRL_4_SPI1_SPI1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_4_SPI1_SPI1_CLK_SCALE_POS))
bogdanm 0:9b334a45a8ff 361
bogdanm 0:9b334a45a8ff 362 #define MXC_F_CLKMAN_CLK_CTRL_5_SPI2_SPI2_CLK_SCALE_POS 0
bogdanm 0:9b334a45a8ff 363 #define MXC_F_CLKMAN_CLK_CTRL_5_SPI2_SPI2_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_5_SPI2_SPI2_CLK_SCALE_POS))
bogdanm 0:9b334a45a8ff 364
bogdanm 0:9b334a45a8ff 365 #define MXC_F_CLKMAN_CLK_CTRL_6_I2CM_I2CM_CLK_SCALE_POS 0
bogdanm 0:9b334a45a8ff 366 #define MXC_F_CLKMAN_CLK_CTRL_6_I2CM_I2CM_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_6_I2CM_I2CM_CLK_SCALE_POS))
bogdanm 0:9b334a45a8ff 367
bogdanm 0:9b334a45a8ff 368 #define MXC_F_CLKMAN_CLK_CTRL_7_I2CS_I2CS_CLK_SCALE_POS 0
bogdanm 0:9b334a45a8ff 369 #define MXC_F_CLKMAN_CLK_CTRL_7_I2CS_I2CS_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_7_I2CS_I2CS_CLK_SCALE_POS))
bogdanm 0:9b334a45a8ff 370
bogdanm 0:9b334a45a8ff 371 #define MXC_F_CLKMAN_CLK_CTRL_8_LCD_CHPUMP_LCD_CLK_SCALE_POS 0
bogdanm 0:9b334a45a8ff 372 #define MXC_F_CLKMAN_CLK_CTRL_8_LCD_CHPUMP_LCD_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_8_LCD_CHPUMP_LCD_CLK_SCALE_POS))
bogdanm 0:9b334a45a8ff 373
bogdanm 0:9b334a45a8ff 374 #define MXC_F_CLKMAN_CLK_CTRL_9_PUF_PUF_CLK_SCALE_POS 0
bogdanm 0:9b334a45a8ff 375 #define MXC_F_CLKMAN_CLK_CTRL_9_PUF_PUF_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_9_PUF_PUF_CLK_SCALE_POS))
bogdanm 0:9b334a45a8ff 376
bogdanm 0:9b334a45a8ff 377 #define MXC_F_CLKMAN_CLK_CTRL_10_PRNG_PRNG_CLK_SCALE_POS 0
bogdanm 0:9b334a45a8ff 378 #define MXC_F_CLKMAN_CLK_CTRL_10_PRNG_PRNG_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_10_PRNG_PRNG_CLK_SCALE_POS))
bogdanm 0:9b334a45a8ff 379
bogdanm 0:9b334a45a8ff 380 #define MXC_F_CLKMAN_CLK_CTRL_11_WDT0_WATCHDOG0_CLK_SCALE_POS 0
bogdanm 0:9b334a45a8ff 381 #define MXC_F_CLKMAN_CLK_CTRL_11_WDT0_WATCHDOG0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_11_WDT0_WATCHDOG0_CLK_SCALE_POS))
bogdanm 0:9b334a45a8ff 382
bogdanm 0:9b334a45a8ff 383 #define MXC_F_CLKMAN_CLK_CTRL_12_WDT1_WATCHDOG1_CLK_SCALE_POS 0
bogdanm 0:9b334a45a8ff 384 #define MXC_F_CLKMAN_CLK_CTRL_12_WDT1_WATCHDOG1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_12_WDT1_WATCHDOG1_CLK_SCALE_POS))
bogdanm 0:9b334a45a8ff 385
bogdanm 0:9b334a45a8ff 386 #define MXC_F_CLKMAN_CLK_CTRL_13_RTC_INT_SYNC_RTC_CLK_SCALE_POS 0
bogdanm 0:9b334a45a8ff 387 #define MXC_F_CLKMAN_CLK_CTRL_13_RTC_INT_SYNC_RTC_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_13_RTC_INT_SYNC_RTC_CLK_SCALE_POS))
bogdanm 0:9b334a45a8ff 388
bogdanm 0:9b334a45a8ff 389 #define MXC_F_CLKMAN_CLK_CTRL_14_DAC0_DAC0_CLK_SCALE_POS 0
bogdanm 0:9b334a45a8ff 390 #define MXC_F_CLKMAN_CLK_CTRL_14_DAC0_DAC0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_14_DAC0_DAC0_CLK_SCALE_POS))
bogdanm 0:9b334a45a8ff 391
bogdanm 0:9b334a45a8ff 392 #define MXC_F_CLKMAN_CLK_CTRL_15_DAC1_DAC1_CLK_SCALE_POS 0
bogdanm 0:9b334a45a8ff 393 #define MXC_F_CLKMAN_CLK_CTRL_15_DAC1_DAC1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_15_DAC1_DAC1_CLK_SCALE_POS))
bogdanm 0:9b334a45a8ff 394
bogdanm 0:9b334a45a8ff 395 #define MXC_F_CLKMAN_CLK_CTRL_16_DAC2_DAC2_CLK_SCALE_POS 0
bogdanm 0:9b334a45a8ff 396 #define MXC_F_CLKMAN_CLK_CTRL_16_DAC2_DAC2_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_16_DAC2_DAC2_CLK_SCALE_POS))
bogdanm 0:9b334a45a8ff 397
bogdanm 0:9b334a45a8ff 398 #define MXC_F_CLKMAN_CLK_CTRL_17_DAC3_DAC3_CLK_SCALE_POS 0
bogdanm 0:9b334a45a8ff 399 #define MXC_F_CLKMAN_CLK_CTRL_17_DAC3_DAC3_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_17_DAC3_DAC3_CLK_SCALE_POS))
bogdanm 0:9b334a45a8ff 400
bogdanm 0:9b334a45a8ff 401 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS 0
bogdanm 0:9b334a45a8ff 402 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS))
bogdanm 0:9b334a45a8ff 403
bogdanm 0:9b334a45a8ff 404 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_UMAA_CLK_SCALE_POS 0
bogdanm 0:9b334a45a8ff 405 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_UMAA_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_UMAA_CLK_SCALE_POS))
bogdanm 0:9b334a45a8ff 406
bogdanm 0:9b334a45a8ff 407 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS 0
bogdanm 0:9b334a45a8ff 408 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS))
bogdanm 0:9b334a45a8ff 409
bogdanm 0:9b334a45a8ff 410 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM3_CLK_GATER_POS 0
bogdanm 0:9b334a45a8ff 411 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM3_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_CM3_CLK_GATER_POS))
bogdanm 0:9b334a45a8ff 412 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSBUS_CLK_GATER_POS 2
bogdanm 0:9b334a45a8ff 413 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSBUS_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSBUS_CLK_GATER_POS))
bogdanm 0:9b334a45a8ff 414 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS 4
bogdanm 0:9b334a45a8ff 415 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS))
bogdanm 0:9b334a45a8ff 416 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS 6
bogdanm 0:9b334a45a8ff 417 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS))
bogdanm 0:9b334a45a8ff 418 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS 8
bogdanm 0:9b334a45a8ff 419 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS))
bogdanm 0:9b334a45a8ff 420 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS 10
bogdanm 0:9b334a45a8ff 421 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS))
bogdanm 0:9b334a45a8ff 422 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS 12
bogdanm 0:9b334a45a8ff 423 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS))
bogdanm 0:9b334a45a8ff 424 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART0_CLK_GATER_POS 14
bogdanm 0:9b334a45a8ff 425 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_UART0_CLK_GATER_POS))
bogdanm 0:9b334a45a8ff 426 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART1_CLK_GATER_POS 16
bogdanm 0:9b334a45a8ff 427 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_UART1_CLK_GATER_POS))
bogdanm 0:9b334a45a8ff 428 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER0_CLK_GATER_POS 18
bogdanm 0:9b334a45a8ff 429 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER0_CLK_GATER_POS))
bogdanm 0:9b334a45a8ff 430 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER1_CLK_GATER_POS 20
bogdanm 0:9b334a45a8ff 431 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER1_CLK_GATER_POS))
bogdanm 0:9b334a45a8ff 432 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER2_CLK_GATER_POS 22
bogdanm 0:9b334a45a8ff 433 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER2_CLK_GATER_POS))
bogdanm 0:9b334a45a8ff 434 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER3_CLK_GATER_POS 24
bogdanm 0:9b334a45a8ff 435 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER3_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER3_CLK_GATER_POS))
bogdanm 0:9b334a45a8ff 436 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS 26
bogdanm 0:9b334a45a8ff 437 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS))
bogdanm 0:9b334a45a8ff 438 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG1_CLK_GATER_POS 28
bogdanm 0:9b334a45a8ff 439 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG1_CLK_GATER_POS))
bogdanm 0:9b334a45a8ff 440 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS 30
bogdanm 0:9b334a45a8ff 441 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS))
bogdanm 0:9b334a45a8ff 442
bogdanm 0:9b334a45a8ff 443 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TESTACC_CLK_GATER_POS 0
bogdanm 0:9b334a45a8ff 444 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TESTACC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TESTACC_CLK_GATER_POS))
bogdanm 0:9b334a45a8ff 445 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_ADC_CLK_GATER_POS 2
bogdanm 0:9b334a45a8ff 446 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_ADC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_ADC_CLK_GATER_POS))
bogdanm 0:9b334a45a8ff 447 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_0_CLK_GATER_POS 4
bogdanm 0:9b334a45a8ff 448 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_0_CLK_GATER_POS))
bogdanm 0:9b334a45a8ff 449 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_1_CLK_GATER_POS 6
bogdanm 0:9b334a45a8ff 450 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_1_CLK_GATER_POS))
bogdanm 0:9b334a45a8ff 451 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_0_CLK_GATER_POS 8
bogdanm 0:9b334a45a8ff 452 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_0_CLK_GATER_POS))
bogdanm 0:9b334a45a8ff 453 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_1_CLK_GATER_POS 10
bogdanm 0:9b334a45a8ff 454 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_1_CLK_GATER_POS))
bogdanm 0:9b334a45a8ff 455 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_PMU_CLK_GATER_POS 12
bogdanm 0:9b334a45a8ff 456 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_PMU_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_PMU_CLK_GATER_POS))
bogdanm 0:9b334a45a8ff 457 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_LCD_CLK_GATER_POS 14
bogdanm 0:9b334a45a8ff 458 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_LCD_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_LCD_CLK_GATER_POS))
bogdanm 0:9b334a45a8ff 459 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS 16
bogdanm 0:9b334a45a8ff 460 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS))
bogdanm 0:9b334a45a8ff 461 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS 18
bogdanm 0:9b334a45a8ff 462 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS))
bogdanm 0:9b334a45a8ff 463 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI0_CLK_GATER_POS 20
bogdanm 0:9b334a45a8ff 464 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI0_CLK_GATER_POS))
bogdanm 0:9b334a45a8ff 465 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI1_CLK_GATER_POS 22
bogdanm 0:9b334a45a8ff 466 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI1_CLK_GATER_POS))
bogdanm 0:9b334a45a8ff 467 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI2_CLK_GATER_POS 24
bogdanm 0:9b334a45a8ff 468 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI2_CLK_GATER_POS))
bogdanm 0:9b334a45a8ff 469 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS 26
bogdanm 0:9b334a45a8ff 470 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS))
bogdanm 0:9b334a45a8ff 471 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS 28
bogdanm 0:9b334a45a8ff 472 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS))
bogdanm 0:9b334a45a8ff 473 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CS_CLK_GATER_POS 30
bogdanm 0:9b334a45a8ff 474 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CS_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CS_CLK_GATER_POS))
bogdanm 0:9b334a45a8ff 475
bogdanm 0:9b334a45a8ff 476 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_CRC_CLK_GATER_POS 0
bogdanm 0:9b334a45a8ff 477 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_CRC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_CRC_CLK_GATER_POS))
bogdanm 0:9b334a45a8ff 478 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_TPU_CLK_GATER_POS 2
bogdanm 0:9b334a45a8ff 479 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_TPU_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_TPU_CLK_GATER_POS))
bogdanm 0:9b334a45a8ff 480 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SSBMUX_CLK_GATER_POS 4
bogdanm 0:9b334a45a8ff 481 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SSBMUX_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SSBMUX_CLK_GATER_POS))
bogdanm 0:9b334a45a8ff 482 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_PAD_CLK_GATER_POS 6
bogdanm 0:9b334a45a8ff 483 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_PAD_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_PAD_CLK_GATER_POS))
bogdanm 0:9b334a45a8ff 484
bogdanm 0:9b334a45a8ff 485 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 486 }
bogdanm 0:9b334a45a8ff 487 #endif
bogdanm 0:9b334a45a8ff 488
bogdanm 0:9b334a45a8ff 489 /**
bogdanm 0:9b334a45a8ff 490 * @}
bogdanm 0:9b334a45a8ff 491 */
bogdanm 0:9b334a45a8ff 492
bogdanm 0:9b334a45a8ff 493 #endif /* _MXC_CLKMAN_REGS_H_ */