Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Maxim/TARGET_MAX32600/afe_regs.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
0:9b334a45a8ff 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*******************************************************************************
<> 144:ef7eb2e8f9f7 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 144:ef7eb2e8f9f7 5 * copy of this software and associated documentation files (the "Software"),
<> 144:ef7eb2e8f9f7 6 * to deal in the Software without restriction, including without limitation
<> 144:ef7eb2e8f9f7 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 144:ef7eb2e8f9f7 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 144:ef7eb2e8f9f7 9 * Software is furnished to do so, subject to the following conditions:
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * The above copyright notice and this permission notice shall be included
<> 144:ef7eb2e8f9f7 12 * in all copies or substantial portions of the Software.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 144:ef7eb2e8f9f7 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 144:ef7eb2e8f9f7 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 144:ef7eb2e8f9f7 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 144:ef7eb2e8f9f7 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 144:ef7eb2e8f9f7 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * Except as contained in this notice, the name of Maxim Integrated
<> 144:ef7eb2e8f9f7 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 144:ef7eb2e8f9f7 24 * Products, Inc. Branding Policy.
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * The mere transfer of this software does not imply any licenses
<> 144:ef7eb2e8f9f7 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 144:ef7eb2e8f9f7 28 * trademarks, maskwork rights, or any other form of intellectual
<> 144:ef7eb2e8f9f7 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 144:ef7eb2e8f9f7 30 * ownership rights.
<> 144:ef7eb2e8f9f7 31 *******************************************************************************
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #ifndef _MXC_AFE_REGS_H
<> 144:ef7eb2e8f9f7 35 #define _MXC_AFE_REGS_H
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 38 extern "C" {
<> 144:ef7eb2e8f9f7 39 #endif
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 #include <stdint.h>
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /**
<> 144:ef7eb2e8f9f7 44 * @file afe_regs.h
<> 144:ef7eb2e8f9f7 45 * @addtogroup afe AFE
<> 144:ef7eb2e8f9f7 46 * @{
<> 144:ef7eb2e8f9f7 47 */
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /**
<> 144:ef7eb2e8f9f7 50 * @brief Defines Configure Options for the LED Ports.
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52 typedef enum {
<> 144:ef7eb2e8f9f7 53 /** LED Sink Port 0 with OpAmp A, LED Sink Port 1 with OpAmp C */
<> 144:ef7eb2e8f9f7 54 MXC_E_AFE_LED_CFG_PORT_OPAMP_A_C = 0,
<> 144:ef7eb2e8f9f7 55 /** LED Sink Port 0 with OpAmp B, LED Sink Port 1 with OpAmp D */
<> 144:ef7eb2e8f9f7 56 MXC_E_AFE_LED_CFG_PORT_OPAMP_B_D,
<> 144:ef7eb2e8f9f7 57 /** Disable LED Sink Port 0,Disable LED Sink Port 1 */
<> 144:ef7eb2e8f9f7 58 MXC_E_AFE_LED_CFG_PORT_DISABLED,
<> 144:ef7eb2e8f9f7 59 } mxc_afe_led_cfg_port_t;
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 /**
<> 144:ef7eb2e8f9f7 62 * @brief Setup of Wake Up Detector for LPCs.
<> 144:ef7eb2e8f9f7 63 */
<> 144:ef7eb2e8f9f7 64 typedef enum {
<> 144:ef7eb2e8f9f7 65 /** IDLE */
<> 144:ef7eb2e8f9f7 66 MXC_E_AFE_EN_WUD_COMP_IDLE = 0,
<> 144:ef7eb2e8f9f7 67 /** Activate WUD for falling edges */
<> 144:ef7eb2e8f9f7 68 MXC_E_AFE_EN_WUD_COMP_FALLING_EDGE = 2,
<> 144:ef7eb2e8f9f7 69 /** Activate WUD for rising edges */
<> 144:ef7eb2e8f9f7 70 MXC_E_AFE_EN_WUD_COMP_RISING_EDGE = 3
<> 144:ef7eb2e8f9f7 71 } mxc_afe_en_wud_comp_t;
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 /**
<> 144:ef7eb2e8f9f7 74 * @brief LPC InMode.
<> 144:ef7eb2e8f9f7 75 */
<> 144:ef7eb2e8f9f7 76 typedef enum {
<> 144:ef7eb2e8f9f7 77 /** InMode: both Nch and Pch */
<> 144:ef7eb2e8f9f7 78 MXC_E_AFE_IN_MODE_COMP_NCH_PCH = 0,
<> 144:ef7eb2e8f9f7 79 /** InMode: only Nch */
<> 144:ef7eb2e8f9f7 80 MXC_E_AFE_IN_MODE_COMP_NCH,
<> 144:ef7eb2e8f9f7 81 /** InMode: only Pch */
<> 144:ef7eb2e8f9f7 82 MXC_E_AFE_IN_MODE_COMP_PCH,
<> 144:ef7eb2e8f9f7 83 } mxc_afe_in_mode_comp_t;
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 /**
<> 144:ef7eb2e8f9f7 86 * @brief LPC Bias.
<> 144:ef7eb2e8f9f7 87 */
<> 144:ef7eb2e8f9f7 88 typedef enum {
<> 144:ef7eb2e8f9f7 89 /** BIAS 0.52uA Delay 4.0us */
<> 144:ef7eb2e8f9f7 90 MXC_E_AFE_BIAS_MODE_COMP_0 = 0,
<> 144:ef7eb2e8f9f7 91 /** BIAS 1.4uA Delay 1.7us */
<> 144:ef7eb2e8f9f7 92 MXC_E_AFE_BIAS_MODE_COMP_1,
<> 144:ef7eb2e8f9f7 93 /** BIAS 2.8uA Delay 1.1us */
<> 144:ef7eb2e8f9f7 94 MXC_E_AFE_BIAS_MODE_COMP_2,
<> 144:ef7eb2e8f9f7 95 /** BIAS 5.1uA Delay 0.7us */
<> 144:ef7eb2e8f9f7 96 MXC_E_AFE_BIAS_MODE_COMP_3
<> 144:ef7eb2e8f9f7 97 } mxc_afe_bias_mode_comp_t;
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 /**
<> 144:ef7eb2e8f9f7 100 * @brief TMON Current Value.
<> 144:ef7eb2e8f9f7 101 */
<> 144:ef7eb2e8f9f7 102 typedef enum {
<> 144:ef7eb2e8f9f7 103 /** TMON Current 4uA */
<> 144:ef7eb2e8f9f7 104 MXC_E_AFE_TMON_CURRENT_VAL_0 = 0,
<> 144:ef7eb2e8f9f7 105 /** TMON Current 60uA */
<> 144:ef7eb2e8f9f7 106 MXC_E_AFE_TMON_CURRENT_VAL_1,
<> 144:ef7eb2e8f9f7 107 /** TMON Current 64uA */
<> 144:ef7eb2e8f9f7 108 MXC_E_AFE_TMON_CURRENT_VAL_2,
<> 144:ef7eb2e8f9f7 109 /** TMON Current 120uA */
<> 144:ef7eb2e8f9f7 110 MXC_E_AFE_TMON_CURRENT_VAL_3
<> 144:ef7eb2e8f9f7 111 } mxc_afe_tmon_current_t;
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 /**
<> 144:ef7eb2e8f9f7 114 * @brief REFADC and REFDAC Voltage Select.
<> 144:ef7eb2e8f9f7 115 */
<> 144:ef7eb2e8f9f7 116 typedef enum {
<> 144:ef7eb2e8f9f7 117 /** Voltage Reference = 1.024 V */
<> 144:ef7eb2e8f9f7 118 MXC_E_AFE_REF_VOLT_SEL_1024 = 0,
<> 144:ef7eb2e8f9f7 119 /** Voltage Reference = 1.5 V */
<> 144:ef7eb2e8f9f7 120 MXC_E_AFE_REF_VOLT_SEL_1500,
<> 144:ef7eb2e8f9f7 121 /** Voltage Reference = 2.048 V */
<> 144:ef7eb2e8f9f7 122 MXC_E_AFE_REF_VOLT_SEL_2048,
<> 144:ef7eb2e8f9f7 123 /** Voltage Reference = 2.5 V */
<> 144:ef7eb2e8f9f7 124 MXC_E_AFE_REF_VOLT_SEL_2500
<> 144:ef7eb2e8f9f7 125 } mxc_afe_ref_volt_sel_t;
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 /**
<> 144:ef7eb2e8f9f7 128 * @brief Selection for DAC VOltage Reference, REFADC or REFDAC.
<> 144:ef7eb2e8f9f7 129 */
<> 144:ef7eb2e8f9f7 130 typedef enum {
<> 144:ef7eb2e8f9f7 131 /** DAC Voltage Reference = REFADC */
<> 144:ef7eb2e8f9f7 132 MXC_E_AFE_DAC_REF_REFADC = 0,
<> 144:ef7eb2e8f9f7 133 /** DAC Voltage Reference = REFDAC */
<> 144:ef7eb2e8f9f7 134 MXC_E_AFE_DAC_REF_REFDAC
<> 144:ef7eb2e8f9f7 135 } mxc_afe_dac_ref_t;
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 /**
<> 144:ef7eb2e8f9f7 138 * @brief Selection for LPC Hysteresis.
<> 144:ef7eb2e8f9f7 139 */
<> 144:ef7eb2e8f9f7 140 typedef enum {
<> 144:ef7eb2e8f9f7 141 /** LPC Hysteresis = 0 mV */
<> 144:ef7eb2e8f9f7 142 MXC_E_AFE_HYST_COMP_0 = 0,
<> 144:ef7eb2e8f9f7 143 /** LPC Hysteresis = 7.5 mV */
<> 144:ef7eb2e8f9f7 144 MXC_E_AFE_HYST_COMP_1,
<> 144:ef7eb2e8f9f7 145 /** LPC Hysteresis = 15 mV */
<> 144:ef7eb2e8f9f7 146 MXC_E_AFE_HYST_COMP_2,
<> 144:ef7eb2e8f9f7 147 /** LPC Hysteresis = 30 mV */
<> 144:ef7eb2e8f9f7 148 MXC_E_AFE_HYST_COMP_3
<> 144:ef7eb2e8f9f7 149 } mxc_afe_hyst_comp_t;
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 /**
<> 144:ef7eb2e8f9f7 152 * @brief Selection for MUX for SCM_or_sel.
<> 144:ef7eb2e8f9f7 153 */
<> 144:ef7eb2e8f9f7 154 typedef enum {
<> 144:ef7eb2e8f9f7 155 /** SCM_or = HIZ */
<> 144:ef7eb2e8f9f7 156 MXC_E_AFE_SCM_OR_SEL_HIZ = 0,
<> 144:ef7eb2e8f9f7 157 /** SCM_or = SCM0 */
<> 144:ef7eb2e8f9f7 158 MXC_E_AFE_SCM_OR_SEL_SCM0,
<> 144:ef7eb2e8f9f7 159 /** SCM_or = SCM1 */
<> 144:ef7eb2e8f9f7 160 MXC_E_AFE_SCM_OR_SEL_SCM1,
<> 144:ef7eb2e8f9f7 161 /** SCM_or = SCM2 */
<> 144:ef7eb2e8f9f7 162 MXC_E_AFE_SCM_OR_SEL_SCM2,
<> 144:ef7eb2e8f9f7 163 /** SCM_or = SCM3 */
<> 144:ef7eb2e8f9f7 164 MXC_E_AFE_SCM_OR_SEL_SCM3
<> 144:ef7eb2e8f9f7 165 } mxc_afe_scm_or_sel_t;
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 /**
<> 144:ef7eb2e8f9f7 168 * @brief Selection for MUX for SNO_or_sel.
<> 144:ef7eb2e8f9f7 169 */
<> 144:ef7eb2e8f9f7 170 typedef enum {
<> 144:ef7eb2e8f9f7 171 /** SNO_or = HIZ */
<> 144:ef7eb2e8f9f7 172 MXC_E_AFE_SNO_OR_SEL_HIZ = 0,
<> 144:ef7eb2e8f9f7 173 /** SNO_or = SNO0 */
<> 144:ef7eb2e8f9f7 174 MXC_E_AFE_SNO_OR_SEL_SNO0,
<> 144:ef7eb2e8f9f7 175 /** SNO_or = SNO1 */
<> 144:ef7eb2e8f9f7 176 MXC_E_AFE_SNO_OR_SEL_SNO1,
<> 144:ef7eb2e8f9f7 177 /** SNO_or = SNO2 */
<> 144:ef7eb2e8f9f7 178 MXC_E_AFE_SNO_OR_SEL_SNO2,
<> 144:ef7eb2e8f9f7 179 /** SNO_or = SNO3 */
<> 144:ef7eb2e8f9f7 180 MXC_E_AFE_SNO_OR_SEL_SNO3
<> 144:ef7eb2e8f9f7 181 } mxc_afe_sno_or_sel_t;
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 /**
<> 144:ef7eb2e8f9f7 184 * @brief Selection for MUX DACx_sel.
<> 144:ef7eb2e8f9f7 185 */
<> 144:ef7eb2e8f9f7 186 typedef enum {
<> 144:ef7eb2e8f9f7 187 /** dacx = DACOP */
<> 144:ef7eb2e8f9f7 188 MXC_E_AFE_DACX_SEL_P = 0,
<> 144:ef7eb2e8f9f7 189 /** dacx = DACON */
<> 144:ef7eb2e8f9f7 190 MXC_E_AFE_DACX_SEL_N
<> 144:ef7eb2e8f9f7 191 } mxc_afe_dacx_sel_t;
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 /**
<> 144:ef7eb2e8f9f7 194 * @brief Selection for state of Switch.
<> 144:ef7eb2e8f9f7 195 */
<> 144:ef7eb2e8f9f7 196 typedef enum {
<> 144:ef7eb2e8f9f7 197 /** Switch is OPEN */
<> 144:ef7eb2e8f9f7 198 MXC_E_AFE_CLOSE_SPST_SWITCH_OPEN = 0,
<> 144:ef7eb2e8f9f7 199 /** Switch is CLOSED */
<> 144:ef7eb2e8f9f7 200 MXC_E_AFE_CLOSE_SPST_SWITCH_CLOSE
<> 144:ef7eb2e8f9f7 201 } mxc_afe_close_spst_t;
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 /**
<> 144:ef7eb2e8f9f7 204 * @brief Switch to Connect Positive Pad to GND.
<> 144:ef7eb2e8f9f7 205 */
<> 144:ef7eb2e8f9f7 206 typedef enum {
<> 144:ef7eb2e8f9f7 207 /** Positive Pad GND Switch OPEN */
<> 144:ef7eb2e8f9f7 208 MXC_E_AFE_GND_SEL_OPAMP_SWITCH_OPEN = 0,
<> 144:ef7eb2e8f9f7 209 /** Positive Pad GND Switch CLOSED */
<> 144:ef7eb2e8f9f7 210 MXC_E_AFE_GND_SEL_OPAMP_SWITCH_CLOSED
<> 144:ef7eb2e8f9f7 211 } mxc_afe_gnd_sel_opamp_t;
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 /**
<> 144:ef7eb2e8f9f7 214 * @brief MUX Selection for OpPsel.
<> 144:ef7eb2e8f9f7 215 */
<> 144:ef7eb2e8f9f7 216 typedef enum {
<> 144:ef7eb2e8f9f7 217 /** OpPsel = INx+ */
<> 144:ef7eb2e8f9f7 218 MXC_E_AFE_P_IN_SEL_OPAMP_INPLUS = 0,
<> 144:ef7eb2e8f9f7 219 /** OpPsel = DAC_or */
<> 144:ef7eb2e8f9f7 220 MXC_E_AFE_P_IN_SEL_OPAMP_DAC_OR,
<> 144:ef7eb2e8f9f7 221 /** OpPsel = SNO_or */
<> 144:ef7eb2e8f9f7 222 MXC_E_AFE_P_IN_SEL_OPAMP_SNO_OR,
<> 144:ef7eb2e8f9f7 223 /** OpPsel = DAC_or also output on INx+ */
<> 144:ef7eb2e8f9f7 224 MXC_E_AFE_P_IN_SEL_OPAMP_DAC_OR_AND_INPLUS
<> 144:ef7eb2e8f9f7 225 } mxc_afe_p_in_sel_opamp_t;
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 /**
<> 144:ef7eb2e8f9f7 228 * @brief MUX Selection for OpNsel.
<> 144:ef7eb2e8f9f7 229 */
<> 144:ef7eb2e8f9f7 230 typedef enum {
<> 144:ef7eb2e8f9f7 231 /** OpNsel = INx- */
<> 144:ef7eb2e8f9f7 232 MXC_E_AFE_N_IN_SEL_OPAMP_INMINUS = 0,
<> 144:ef7eb2e8f9f7 233 /** OpNsel = OUTx */
<> 144:ef7eb2e8f9f7 234 MXC_E_AFE_N_IN_SEL_OPAMP_OUT,
<> 144:ef7eb2e8f9f7 235 /** OpNsel = SCM_or */
<> 144:ef7eb2e8f9f7 236 MXC_E_AFE_N_IN_SEL_OPAMP_SCM_OR,
<> 144:ef7eb2e8f9f7 237 /**OpNsel = SCM_or also output on INx- */
<> 144:ef7eb2e8f9f7 238 MXC_E_AFE_N_IN_SEL_OPAMP_SCM_OR_AND_INMINUS,
<> 144:ef7eb2e8f9f7 239 } mxc_afe_n_in_sel_opamp_t;
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 /**
<> 144:ef7eb2e8f9f7 242 * @brief MUX Selection for DAC_sel.
<> 144:ef7eb2e8f9f7 243 */
<> 144:ef7eb2e8f9f7 244 typedef enum {
<> 144:ef7eb2e8f9f7 245 /** DAC_or = DAC0 */
<> 144:ef7eb2e8f9f7 246 MXC_E_AFE_DAC_SEL_DAC0 = 0,
<> 144:ef7eb2e8f9f7 247 /** DAC_or = DAC1 */
<> 144:ef7eb2e8f9f7 248 MXC_E_AFE_DAC_SEL_DAC1,
<> 144:ef7eb2e8f9f7 249 /** DAC_or = DAC2P */
<> 144:ef7eb2e8f9f7 250 MXC_E_AFE_DAC_SEL_DAC2P,
<> 144:ef7eb2e8f9f7 251 /** DAC_or = DAC3P */
<> 144:ef7eb2e8f9f7 252 MXC_E_AFE_DAC_SEL_DAC3P
<> 144:ef7eb2e8f9f7 253 } mxc_afe_dac_sel_t;
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 /**
<> 144:ef7eb2e8f9f7 256 * @brief MUX Selection for NPAD_sel.
<> 144:ef7eb2e8f9f7 257 */
<> 144:ef7eb2e8f9f7 258 typedef enum {
<> 144:ef7eb2e8f9f7 259 /** NPAD_Sel = HIZ */
<> 144:ef7eb2e8f9f7 260 MXC_E_AFE_NPAD_SEL_HIZ = 0,
<> 144:ef7eb2e8f9f7 261 /** NPAD_Sel = LED Observe Port */
<> 144:ef7eb2e8f9f7 262 MXC_E_AFE_NPAD_SEL_LED_OBS_PORT,
<> 144:ef7eb2e8f9f7 263 /** NPAD_Sel = DAC_or */
<> 144:ef7eb2e8f9f7 264 MXC_E_AFE_NPAD_SEL_DAC_OR,
<> 144:ef7eb2e8f9f7 265 /** NPAD_Sel = DAC_or and LED Observe Port */
<> 144:ef7eb2e8f9f7 266 MXC_E_AFE_NPAD_SEL_DAC_OR_AND_LED_OBS_PORT
<> 144:ef7eb2e8f9f7 267 } mxc_afe_npad_sel_t;
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269 /**
<> 144:ef7eb2e8f9f7 270 * @brief MUX Selection for CmpPSel.
<> 144:ef7eb2e8f9f7 271 */
<> 144:ef7eb2e8f9f7 272 typedef enum {
<> 144:ef7eb2e8f9f7 273 /** CmpPSel = INx+ */
<> 144:ef7eb2e8f9f7 274 MXC_E_AFE_POS_IN_SEL_COMP_INPLUS = 0,
<> 144:ef7eb2e8f9f7 275 /** CmpPSel = SCM */
<> 144:ef7eb2e8f9f7 276 MXC_E_AFE_POS_IN_SEL_COMP_SCM,
<> 144:ef7eb2e8f9f7 277 /** CmpPSel = dac1 */
<> 144:ef7eb2e8f9f7 278 MXC_E_AFE_POS_IN_SEL_COMP_DAC1,
<> 144:ef7eb2e8f9f7 279 /** CmpPSel = DAC3P */
<> 144:ef7eb2e8f9f7 280 MXC_E_AFE_POS_IN_SEL_COMP_DAC3P,
<> 144:ef7eb2e8f9f7 281 /** CmpPSel = LED Observe Port */
<> 144:ef7eb2e8f9f7 282 MXC_E_AFE_POS_IN_SEL_COMP_LED_OBS_PORT,
<> 144:ef7eb2e8f9f7 283 /** CmpPSel = dac1 also output on INx+ */
<> 144:ef7eb2e8f9f7 284 MXC_E_AFE_POS_IN_SEL_COMP_DAC1_AND_INPLUS,
<> 144:ef7eb2e8f9f7 285 /** CmpPSel = DAC3P also output on INx+ */
<> 144:ef7eb2e8f9f7 286 MXC_E_AFE_POS_IN_SEL_COMP_DAC3P_AND_INPLUS,
<> 144:ef7eb2e8f9f7 287 /** CmpPSel = dac1 also output on SCM */
<> 144:ef7eb2e8f9f7 288 MXC_E_AFE_POS_IN_SEL_COMP_DAC1_AND_SCM
<> 144:ef7eb2e8f9f7 289 } mxc_afe_pos_in_sel_comp_t;
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 /**
<> 144:ef7eb2e8f9f7 292 * @brief MUX Selection for CmpNSel.
<> 144:ef7eb2e8f9f7 293 */
<> 144:ef7eb2e8f9f7 294 typedef enum {
<> 144:ef7eb2e8f9f7 295 /** CmpNSel = INx- */
<> 144:ef7eb2e8f9f7 296 MXC_E_AFE_NEG_IN_SEL_COMP_INMINUS = 0,
<> 144:ef7eb2e8f9f7 297 /** CmpNSel = SNO */
<> 144:ef7eb2e8f9f7 298 MXC_E_AFE_NEG_IN_SEL_COMP_SNO,
<> 144:ef7eb2e8f9f7 299 /** CmpNSel = dac0 */
<> 144:ef7eb2e8f9f7 300 MXC_E_AFE_NEG_IN_SEL_COMP_DAC0,
<> 144:ef7eb2e8f9f7 301 /** CmpNSel = DAC2P */
<> 144:ef7eb2e8f9f7 302 MXC_E_AFE_NEG_IN_SEL_COMP_DAC2P,
<> 144:ef7eb2e8f9f7 303 /** CmpNSel = LED Observation Port */
<> 144:ef7eb2e8f9f7 304 MXC_E_AFE_NEG_IN_SEL_COMP_LED_OBS_PORT,
<> 144:ef7eb2e8f9f7 305 /** CmpNSel = dac0 also output on INx- */
<> 144:ef7eb2e8f9f7 306 MXC_E_AFE_NEG_IN_SEL_COMP_DAC0_AND_INMINUS,
<> 144:ef7eb2e8f9f7 307 /** CmpNSel = DAC2 also output on INx- */
<> 144:ef7eb2e8f9f7 308 MXC_E_AFE_NEG_IN_SEL_COMP_DAC2P_AND_INMINUS,
<> 144:ef7eb2e8f9f7 309 /** CmpNSel = DAC2 also output on SNO */
<> 144:ef7eb2e8f9f7 310 MXC_E_AFE_NEG_IN_SEL_COMP_DAC2P_AND_SNO
<> 144:ef7eb2e8f9f7 311 } mxc_afe_neg_in_sel_comp_t;
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 /* Offset Register Description
<> 144:ef7eb2e8f9f7 314 ====== ==================================================== */
<> 144:ef7eb2e8f9f7 315 typedef struct {
<> 144:ef7eb2e8f9f7 316 __IO uint32_t intr; /* 0x0000 Analog Front End Interrupt Flags and Enable/Disable */
<> 144:ef7eb2e8f9f7 317 __IO uint32_t ctrl0; /* 0x0004 Analog Front End Control 0 */
<> 144:ef7eb2e8f9f7 318 __IO uint32_t ctrl1; /* 0x0008 Analog Front End Control 1 */
<> 144:ef7eb2e8f9f7 319 __IO uint32_t ctrl2; /* 0x000C Analog Front End Control 2 */
<> 144:ef7eb2e8f9f7 320 __IO uint32_t ctrl3; /* 0x0010 Analog Front End Control 3 */
<> 144:ef7eb2e8f9f7 321 __IO uint32_t ctrl4; /* 0x0014 Analog Front End Control 4 */
<> 144:ef7eb2e8f9f7 322 __IO uint32_t ctrl5; /* 0x0018 Analog Front End Control 5 */
<> 144:ef7eb2e8f9f7 323 } mxc_afe_regs_t;
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 /*
<> 144:ef7eb2e8f9f7 326 Register offsets for module AFE.
<> 144:ef7eb2e8f9f7 327 */
<> 144:ef7eb2e8f9f7 328 #define MXC_R_AFE_OFFS_INTR ((uint32_t)0x00000000UL)
<> 144:ef7eb2e8f9f7 329 #define MXC_R_AFE_OFFS_CTRL0 ((uint32_t)0x00000004UL)
<> 144:ef7eb2e8f9f7 330 #define MXC_R_AFE_OFFS_CTRL1 ((uint32_t)0x00000008UL)
<> 144:ef7eb2e8f9f7 331 #define MXC_R_AFE_OFFS_CTRL2 ((uint32_t)0x0000000CUL)
<> 144:ef7eb2e8f9f7 332 #define MXC_R_AFE_OFFS_CTRL3 ((uint32_t)0x00000010UL)
<> 144:ef7eb2e8f9f7 333 #define MXC_R_AFE_OFFS_CTRL4 ((uint32_t)0x00000014UL)
<> 144:ef7eb2e8f9f7 334 #define MXC_R_AFE_OFFS_CTRL5 ((uint32_t)0x00000018UL)
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 /*
<> 144:ef7eb2e8f9f7 337 Field positions and masks for module AFE.
<> 144:ef7eb2e8f9f7 338 */
<> 144:ef7eb2e8f9f7 339 #define MXC_F_AFE_INTR_OP_COMP0_IF_POS 0
<> 144:ef7eb2e8f9f7 340 #define MXC_F_AFE_INTR_OP_COMP0_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP0_IF_POS))
<> 144:ef7eb2e8f9f7 341 #define MXC_F_AFE_INTR_OP_COMP1_IF_POS 1
<> 144:ef7eb2e8f9f7 342 #define MXC_F_AFE_INTR_OP_COMP1_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP1_IF_POS))
<> 144:ef7eb2e8f9f7 343 #define MXC_F_AFE_INTR_OP_COMP2_IF_POS 2
<> 144:ef7eb2e8f9f7 344 #define MXC_F_AFE_INTR_OP_COMP2_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP2_IF_POS))
<> 144:ef7eb2e8f9f7 345 #define MXC_F_AFE_INTR_OP_COMP3_IF_POS 3
<> 144:ef7eb2e8f9f7 346 #define MXC_F_AFE_INTR_OP_COMP3_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP3_IF_POS))
<> 144:ef7eb2e8f9f7 347 #define MXC_F_AFE_INTR_LP_COMP0_IF_POS 4
<> 144:ef7eb2e8f9f7 348 #define MXC_F_AFE_INTR_LP_COMP0_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP0_IF_POS))
<> 144:ef7eb2e8f9f7 349 #define MXC_F_AFE_INTR_LP_COMP1_IF_POS 5
<> 144:ef7eb2e8f9f7 350 #define MXC_F_AFE_INTR_LP_COMP1_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP1_IF_POS))
<> 144:ef7eb2e8f9f7 351 #define MXC_F_AFE_INTR_LP_COMP2_IF_POS 6
<> 144:ef7eb2e8f9f7 352 #define MXC_F_AFE_INTR_LP_COMP2_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP2_IF_POS))
<> 144:ef7eb2e8f9f7 353 #define MXC_F_AFE_INTR_LP_COMP3_IF_POS 7
<> 144:ef7eb2e8f9f7 354 #define MXC_F_AFE_INTR_LP_COMP3_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP3_IF_POS))
<> 144:ef7eb2e8f9f7 355 #define MXC_F_AFE_INTR_OP_COMP0_NMI_PMU_POS 8
<> 144:ef7eb2e8f9f7 356 #define MXC_F_AFE_INTR_OP_COMP0_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP0_NMI_PMU_POS))
<> 144:ef7eb2e8f9f7 357 #define MXC_F_AFE_INTR_OP_COMP1_NMI_PMU_POS 9
<> 144:ef7eb2e8f9f7 358 #define MXC_F_AFE_INTR_OP_COMP1_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP1_NMI_PMU_POS))
<> 144:ef7eb2e8f9f7 359 #define MXC_F_AFE_INTR_OP_COMP2_NMI_PMU_POS 10
<> 144:ef7eb2e8f9f7 360 #define MXC_F_AFE_INTR_OP_COMP2_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP2_NMI_PMU_POS))
<> 144:ef7eb2e8f9f7 361 #define MXC_F_AFE_INTR_OP_COMP3_NMI_PMU_POS 11
<> 144:ef7eb2e8f9f7 362 #define MXC_F_AFE_INTR_OP_COMP3_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP3_NMI_PMU_POS))
<> 144:ef7eb2e8f9f7 363 #define MXC_F_AFE_INTR_LP_COMP0_NMI_PMU_POS 12
<> 144:ef7eb2e8f9f7 364 #define MXC_F_AFE_INTR_LP_COMP0_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP0_NMI_PMU_POS))
<> 144:ef7eb2e8f9f7 365 #define MXC_F_AFE_INTR_LP_COMP1_NMI_PMU_POS 13
<> 144:ef7eb2e8f9f7 366 #define MXC_F_AFE_INTR_LP_COMP1_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP1_NMI_PMU_POS))
<> 144:ef7eb2e8f9f7 367 #define MXC_F_AFE_INTR_LP_COMP2_NMI_PMU_POS 14
<> 144:ef7eb2e8f9f7 368 #define MXC_F_AFE_INTR_LP_COMP2_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP2_NMI_PMU_POS))
<> 144:ef7eb2e8f9f7 369 #define MXC_F_AFE_INTR_LP_COMP3_NMI_PMU_POS 15
<> 144:ef7eb2e8f9f7 370 #define MXC_F_AFE_INTR_LP_COMP3_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP3_NMI_PMU_POS))
<> 144:ef7eb2e8f9f7 371 #define MXC_F_AFE_INTR_OP_COMP0_POL_POS 16
<> 144:ef7eb2e8f9f7 372 #define MXC_F_AFE_INTR_OP_COMP0_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP0_POL_POS))
<> 144:ef7eb2e8f9f7 373 #define MXC_F_AFE_INTR_OP_COMP1_POL_POS 17
<> 144:ef7eb2e8f9f7 374 #define MXC_F_AFE_INTR_OP_COMP1_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP1_POL_POS))
<> 144:ef7eb2e8f9f7 375 #define MXC_F_AFE_INTR_OP_COMP2_POL_POS 18
<> 144:ef7eb2e8f9f7 376 #define MXC_F_AFE_INTR_OP_COMP2_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP2_POL_POS))
<> 144:ef7eb2e8f9f7 377 #define MXC_F_AFE_INTR_OP_COMP3_POL_POS 19
<> 144:ef7eb2e8f9f7 378 #define MXC_F_AFE_INTR_OP_COMP3_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP3_POL_POS))
<> 144:ef7eb2e8f9f7 379 #define MXC_F_AFE_INTR_LP_COMP0_POL_POS 20
<> 144:ef7eb2e8f9f7 380 #define MXC_F_AFE_INTR_LP_COMP0_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP0_POL_POS))
<> 144:ef7eb2e8f9f7 381 #define MXC_F_AFE_INTR_LP_COMP1_POL_POS 21
<> 144:ef7eb2e8f9f7 382 #define MXC_F_AFE_INTR_LP_COMP1_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP1_POL_POS))
<> 144:ef7eb2e8f9f7 383 #define MXC_F_AFE_INTR_LP_COMP2_POL_POS 22
<> 144:ef7eb2e8f9f7 384 #define MXC_F_AFE_INTR_LP_COMP2_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP2_POL_POS))
<> 144:ef7eb2e8f9f7 385 #define MXC_F_AFE_INTR_LP_COMP3_POL_POS 23
<> 144:ef7eb2e8f9f7 386 #define MXC_F_AFE_INTR_LP_COMP3_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP3_POL_POS))
<> 144:ef7eb2e8f9f7 387 #define MXC_F_AFE_INTR_OP_COMP0_IE_POS 24
<> 144:ef7eb2e8f9f7 388 #define MXC_F_AFE_INTR_OP_COMP0_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP0_IE_POS))
<> 144:ef7eb2e8f9f7 389 #define MXC_F_AFE_INTR_OP_COMP1_IE_POS 25
<> 144:ef7eb2e8f9f7 390 #define MXC_F_AFE_INTR_OP_COMP1_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP1_IE_POS))
<> 144:ef7eb2e8f9f7 391 #define MXC_F_AFE_INTR_OP_COMP2_IE_POS 26
<> 144:ef7eb2e8f9f7 392 #define MXC_F_AFE_INTR_OP_COMP2_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP2_IE_POS))
<> 144:ef7eb2e8f9f7 393 #define MXC_F_AFE_INTR_OP_COMP3_IE_POS 27
<> 144:ef7eb2e8f9f7 394 #define MXC_F_AFE_INTR_OP_COMP3_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP3_IE_POS))
<> 144:ef7eb2e8f9f7 395 #define MXC_F_AFE_INTR_LP_COMP0_IE_POS 28
<> 144:ef7eb2e8f9f7 396 #define MXC_F_AFE_INTR_LP_COMP0_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP0_IE_POS))
<> 144:ef7eb2e8f9f7 397 #define MXC_F_AFE_INTR_LP_COMP1_IE_POS 29
<> 144:ef7eb2e8f9f7 398 #define MXC_F_AFE_INTR_LP_COMP1_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP1_IE_POS))
<> 144:ef7eb2e8f9f7 399 #define MXC_F_AFE_INTR_LP_COMP2_IE_POS 30
<> 144:ef7eb2e8f9f7 400 #define MXC_F_AFE_INTR_LP_COMP2_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP2_IE_POS))
<> 144:ef7eb2e8f9f7 401 #define MXC_F_AFE_INTR_LP_COMP3_IE_POS 31
<> 144:ef7eb2e8f9f7 402 #define MXC_F_AFE_INTR_LP_COMP3_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP3_IE_POS))
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 #define MXC_F_AFE_CTRL0_LED_CFG_POS 0
<> 144:ef7eb2e8f9f7 405 #define MXC_F_AFE_CTRL0_LED_CFG ((uint32_t)(0x0000000FUL << MXC_F_AFE_CTRL0_LED_CFG_POS))
<> 144:ef7eb2e8f9f7 406 #define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP0_POS 4
<> 144:ef7eb2e8f9f7 407 #define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL0_CLEAR_WUD_COMP0_POS))
<> 144:ef7eb2e8f9f7 408 #define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP1_POS 5
<> 144:ef7eb2e8f9f7 409 #define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL0_CLEAR_WUD_COMP1_POS))
<> 144:ef7eb2e8f9f7 410 #define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP2_POS 6
<> 144:ef7eb2e8f9f7 411 #define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL0_CLEAR_WUD_COMP2_POS))
<> 144:ef7eb2e8f9f7 412 #define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP3_POS 7
<> 144:ef7eb2e8f9f7 413 #define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL0_CLEAR_WUD_COMP3_POS))
<> 144:ef7eb2e8f9f7 414 #define MXC_F_AFE_CTRL0_EN_WUD_COMP0_POS 8
<> 144:ef7eb2e8f9f7 415 #define MXC_F_AFE_CTRL0_EN_WUD_COMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_EN_WUD_COMP0_POS))
<> 144:ef7eb2e8f9f7 416 #define MXC_F_AFE_CTRL0_EN_WUD_COMP1_POS 10
<> 144:ef7eb2e8f9f7 417 #define MXC_F_AFE_CTRL0_EN_WUD_COMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_EN_WUD_COMP1_POS))
<> 144:ef7eb2e8f9f7 418 #define MXC_F_AFE_CTRL0_EN_WUD_COMP2_POS 12
<> 144:ef7eb2e8f9f7 419 #define MXC_F_AFE_CTRL0_EN_WUD_COMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_EN_WUD_COMP2_POS))
<> 144:ef7eb2e8f9f7 420 #define MXC_F_AFE_CTRL0_EN_WUD_COMP3_POS 14
<> 144:ef7eb2e8f9f7 421 #define MXC_F_AFE_CTRL0_EN_WUD_COMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_EN_WUD_COMP3_POS))
<> 144:ef7eb2e8f9f7 422 #define MXC_F_AFE_CTRL0_IN_MODE_COMP0_POS 16
<> 144:ef7eb2e8f9f7 423 #define MXC_F_AFE_CTRL0_IN_MODE_COMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_IN_MODE_COMP0_POS))
<> 144:ef7eb2e8f9f7 424 #define MXC_F_AFE_CTRL0_IN_MODE_COMP1_POS 18
<> 144:ef7eb2e8f9f7 425 #define MXC_F_AFE_CTRL0_IN_MODE_COMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_IN_MODE_COMP1_POS))
<> 144:ef7eb2e8f9f7 426 #define MXC_F_AFE_CTRL0_IN_MODE_COMP2_POS 20
<> 144:ef7eb2e8f9f7 427 #define MXC_F_AFE_CTRL0_IN_MODE_COMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_IN_MODE_COMP2_POS))
<> 144:ef7eb2e8f9f7 428 #define MXC_F_AFE_CTRL0_IN_MODE_COMP3_POS 22
<> 144:ef7eb2e8f9f7 429 #define MXC_F_AFE_CTRL0_IN_MODE_COMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_IN_MODE_COMP3_POS))
<> 144:ef7eb2e8f9f7 430 #define MXC_F_AFE_CTRL0_BIAS_MODE_COMP0_POS 24
<> 144:ef7eb2e8f9f7 431 #define MXC_F_AFE_CTRL0_BIAS_MODE_COMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_BIAS_MODE_COMP0_POS))
<> 144:ef7eb2e8f9f7 432 #define MXC_F_AFE_CTRL0_BIAS_MODE_COMP1_POS 26
<> 144:ef7eb2e8f9f7 433 #define MXC_F_AFE_CTRL0_BIAS_MODE_COMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_BIAS_MODE_COMP1_POS))
<> 144:ef7eb2e8f9f7 434 #define MXC_F_AFE_CTRL0_BIAS_MODE_COMP2_POS 28
<> 144:ef7eb2e8f9f7 435 #define MXC_F_AFE_CTRL0_BIAS_MODE_COMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_BIAS_MODE_COMP2_POS))
<> 144:ef7eb2e8f9f7 436 #define MXC_F_AFE_CTRL0_BIAS_MODE_COMP3_POS 30
<> 144:ef7eb2e8f9f7 437 #define MXC_F_AFE_CTRL0_BIAS_MODE_COMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_BIAS_MODE_COMP3_POS))
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 #define MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_EN_POS 0
<> 144:ef7eb2e8f9f7 440 #define MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_EN ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_EN_POS))
<> 144:ef7eb2e8f9f7 441 #define MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_SEL_POS 1
<> 144:ef7eb2e8f9f7 442 #define MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_SEL ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_SEL_POS))
<> 144:ef7eb2e8f9f7 443 #define MXC_F_AFE_CTRL1_REF_DAC_FAST_PWRDN_EN_POS 3
<> 144:ef7eb2e8f9f7 444 #define MXC_F_AFE_CTRL1_REF_DAC_FAST_PWRDN_EN ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_DAC_FAST_PWRDN_EN_POS))
<> 144:ef7eb2e8f9f7 445 #define MXC_F_AFE_CTRL1_REF_ADC_FAST_PWRDN_EN_POS 4
<> 144:ef7eb2e8f9f7 446 #define MXC_F_AFE_CTRL1_REF_ADC_FAST_PWRDN_EN ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_ADC_FAST_PWRDN_EN_POS))
<> 144:ef7eb2e8f9f7 447 #define MXC_F_AFE_CTRL1_REF_BANDGAP_SEL_POS 5
<> 144:ef7eb2e8f9f7 448 #define MXC_F_AFE_CTRL1_REF_BANDGAP_SEL ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_BANDGAP_SEL_POS))
<> 144:ef7eb2e8f9f7 449 #define MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL_POS 6
<> 144:ef7eb2e8f9f7 450 #define MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL_POS))
<> 144:ef7eb2e8f9f7 451 #define MXC_F_AFE_CTRL1_REF_DAC_VOLT_SEL_POS 8
<> 144:ef7eb2e8f9f7 452 #define MXC_F_AFE_CTRL1_REF_DAC_VOLT_SEL ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_REF_DAC_VOLT_SEL_POS))
<> 144:ef7eb2e8f9f7 453 #define MXC_F_AFE_CTRL1_REF_SEL_POS 10
<> 144:ef7eb2e8f9f7 454 #define MXC_F_AFE_CTRL1_REF_SEL ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_SEL_POS))
<> 144:ef7eb2e8f9f7 455 #define MXC_F_AFE_CTRL1_REF_ADC_POWERUP_POS 11
<> 144:ef7eb2e8f9f7 456 #define MXC_F_AFE_CTRL1_REF_ADC_POWERUP ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_ADC_POWERUP_POS))
<> 144:ef7eb2e8f9f7 457 #define MXC_F_AFE_CTRL1_REF_DAC_POWERUP_POS 12
<> 144:ef7eb2e8f9f7 458 #define MXC_F_AFE_CTRL1_REF_DAC_POWERUP ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_DAC_POWERUP_POS))
<> 144:ef7eb2e8f9f7 459 #define MXC_F_AFE_CTRL1_REF_BLK_POWERUP_POS 13
<> 144:ef7eb2e8f9f7 460 #define MXC_F_AFE_CTRL1_REF_BLK_POWERUP ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_BLK_POWERUP_POS))
<> 144:ef7eb2e8f9f7 461 #define MXC_F_AFE_CTRL1_REF_ADC_COMP_POS 14
<> 144:ef7eb2e8f9f7 462 #define MXC_F_AFE_CTRL1_REF_ADC_COMP ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_ADC_COMP_POS))
<> 144:ef7eb2e8f9f7 463 #define MXC_F_AFE_CTRL1_REF_DAC_COMP_POS 15
<> 144:ef7eb2e8f9f7 464 #define MXC_F_AFE_CTRL1_REF_DAC_COMP ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_DAC_COMP_POS))
<> 144:ef7eb2e8f9f7 465 #define MXC_F_AFE_CTRL1_REF_ADC_TEST_GAIN_POS 16
<> 144:ef7eb2e8f9f7 466 #define MXC_F_AFE_CTRL1_REF_ADC_TEST_GAIN ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_REF_ADC_TEST_GAIN_POS))
<> 144:ef7eb2e8f9f7 467 #define MXC_F_AFE_CTRL1_REF_DAC_TEST_GAIN_POS 18
<> 144:ef7eb2e8f9f7 468 #define MXC_F_AFE_CTRL1_REF_DAC_TEST_GAIN ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_REF_DAC_TEST_GAIN_POS))
<> 144:ef7eb2e8f9f7 469 #define MXC_F_AFE_CTRL1_ABUS_PAGE_2_0_POS 20
<> 144:ef7eb2e8f9f7 470 #define MXC_F_AFE_CTRL1_ABUS_PAGE_2_0 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL1_ABUS_PAGE_2_0_POS))
<> 144:ef7eb2e8f9f7 471 #define MXC_F_AFE_CTRL1_PLL_TST_EN_POS 23
<> 144:ef7eb2e8f9f7 472 #define MXC_F_AFE_CTRL1_PLL_TST_EN ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_PLL_TST_EN_POS))
<> 144:ef7eb2e8f9f7 473 #define MXC_F_AFE_CTRL1_V1EXTADJ_POS 25
<> 144:ef7eb2e8f9f7 474 #define MXC_F_AFE_CTRL1_V1EXTADJ ((uint32_t)(0x0000001FUL << MXC_F_AFE_CTRL1_V1EXTADJ_POS))
<> 144:ef7eb2e8f9f7 475 #define MXC_F_AFE_CTRL1_TMON_CUR_SEL_POS 30
<> 144:ef7eb2e8f9f7 476 #define MXC_F_AFE_CTRL1_TMON_CUR_SEL ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_TMON_CUR_SEL_POS))
<> 144:ef7eb2e8f9f7 477
<> 144:ef7eb2e8f9f7 478 #define MXC_F_AFE_CTRL2_HYST_COMP0_POS 0
<> 144:ef7eb2e8f9f7 479 #define MXC_F_AFE_CTRL2_HYST_COMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL2_HYST_COMP0_POS))
<> 144:ef7eb2e8f9f7 480 #define MXC_F_AFE_CTRL2_HYST_COMP1_POS 2
<> 144:ef7eb2e8f9f7 481 #define MXC_F_AFE_CTRL2_HYST_COMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL2_HYST_COMP1_POS))
<> 144:ef7eb2e8f9f7 482 #define MXC_F_AFE_CTRL2_HYST_COMP2_POS 4
<> 144:ef7eb2e8f9f7 483 #define MXC_F_AFE_CTRL2_HYST_COMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL2_HYST_COMP2_POS))
<> 144:ef7eb2e8f9f7 484 #define MXC_F_AFE_CTRL2_HYST_COMP3_POS 6
<> 144:ef7eb2e8f9f7 485 #define MXC_F_AFE_CTRL2_HYST_COMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL2_HYST_COMP3_POS))
<> 144:ef7eb2e8f9f7 486 #define MXC_F_AFE_CTRL2_HY_POL_COMP0_POS 8
<> 144:ef7eb2e8f9f7 487 #define MXC_F_AFE_CTRL2_HY_POL_COMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_HY_POL_COMP0_POS))
<> 144:ef7eb2e8f9f7 488 #define MXC_F_AFE_CTRL2_HY_POL_COMP1_POS 9
<> 144:ef7eb2e8f9f7 489 #define MXC_F_AFE_CTRL2_HY_POL_COMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_HY_POL_COMP1_POS))
<> 144:ef7eb2e8f9f7 490 #define MXC_F_AFE_CTRL2_HY_POL_COMP2_POS 10
<> 144:ef7eb2e8f9f7 491 #define MXC_F_AFE_CTRL2_HY_POL_COMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_HY_POL_COMP2_POS))
<> 144:ef7eb2e8f9f7 492 #define MXC_F_AFE_CTRL2_HY_POL_COMP3_POS 11
<> 144:ef7eb2e8f9f7 493 #define MXC_F_AFE_CTRL2_HY_POL_COMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_HY_POL_COMP3_POS))
<> 144:ef7eb2e8f9f7 494 #define MXC_F_AFE_CTRL2_POWERUP_COMP0_POS 12
<> 144:ef7eb2e8f9f7 495 #define MXC_F_AFE_CTRL2_POWERUP_COMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_POWERUP_COMP0_POS))
<> 144:ef7eb2e8f9f7 496 #define MXC_F_AFE_CTRL2_POWERUP_COMP1_POS 13
<> 144:ef7eb2e8f9f7 497 #define MXC_F_AFE_CTRL2_POWERUP_COMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_POWERUP_COMP1_POS))
<> 144:ef7eb2e8f9f7 498 #define MXC_F_AFE_CTRL2_POWERUP_COMP2_POS 14
<> 144:ef7eb2e8f9f7 499 #define MXC_F_AFE_CTRL2_POWERUP_COMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_POWERUP_COMP2_POS))
<> 144:ef7eb2e8f9f7 500 #define MXC_F_AFE_CTRL2_POWERUP_COMP3_POS 15
<> 144:ef7eb2e8f9f7 501 #define MXC_F_AFE_CTRL2_POWERUP_COMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_POWERUP_COMP3_POS))
<> 144:ef7eb2e8f9f7 502 #define MXC_F_AFE_CTRL2_DACOUT_EN0_POS 16
<> 144:ef7eb2e8f9f7 503 #define MXC_F_AFE_CTRL2_DACOUT_EN0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DACOUT_EN0_POS))
<> 144:ef7eb2e8f9f7 504 #define MXC_F_AFE_CTRL2_DACOUT_EN1_POS 17
<> 144:ef7eb2e8f9f7 505 #define MXC_F_AFE_CTRL2_DACOUT_EN1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DACOUT_EN1_POS))
<> 144:ef7eb2e8f9f7 506 #define MXC_F_AFE_CTRL2_DACOUT_EN2_POS 18
<> 144:ef7eb2e8f9f7 507 #define MXC_F_AFE_CTRL2_DACOUT_EN2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DACOUT_EN2_POS))
<> 144:ef7eb2e8f9f7 508 #define MXC_F_AFE_CTRL2_DACOUT_EN3_POS 19
<> 144:ef7eb2e8f9f7 509 #define MXC_F_AFE_CTRL2_DACOUT_EN3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DACOUT_EN3_POS))
<> 144:ef7eb2e8f9f7 510 #define MXC_F_AFE_CTRL2_SCM_OR_SEL_POS 20
<> 144:ef7eb2e8f9f7 511 #define MXC_F_AFE_CTRL2_SCM_OR_SEL ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL2_SCM_OR_SEL_POS))
<> 144:ef7eb2e8f9f7 512 #define MXC_F_AFE_CTRL2_SNO_OR_SEL_POS 23
<> 144:ef7eb2e8f9f7 513 #define MXC_F_AFE_CTRL2_SNO_OR_SEL ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL2_SNO_OR_SEL_POS))
<> 144:ef7eb2e8f9f7 514 #define MXC_F_AFE_CTRL2_DAC0_SEL_POS 26
<> 144:ef7eb2e8f9f7 515 #define MXC_F_AFE_CTRL2_DAC0_SEL ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DAC0_SEL_POS))
<> 144:ef7eb2e8f9f7 516 #define MXC_F_AFE_CTRL2_DAC1_SEL_POS 27
<> 144:ef7eb2e8f9f7 517 #define MXC_F_AFE_CTRL2_DAC1_SEL ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DAC1_SEL_POS))
<> 144:ef7eb2e8f9f7 518
<> 144:ef7eb2e8f9f7 519 #define MXC_F_AFE_CTRL3_POWERUP_OPAMP0_POS 12
<> 144:ef7eb2e8f9f7 520 #define MXC_F_AFE_CTRL3_POWERUP_OPAMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_POWERUP_OPAMP0_POS))
<> 144:ef7eb2e8f9f7 521 #define MXC_F_AFE_CTRL3_POWERUP_OPAMP1_POS 13
<> 144:ef7eb2e8f9f7 522 #define MXC_F_AFE_CTRL3_POWERUP_OPAMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_POWERUP_OPAMP1_POS))
<> 144:ef7eb2e8f9f7 523 #define MXC_F_AFE_CTRL3_POWERUP_OPAMP2_POS 14
<> 144:ef7eb2e8f9f7 524 #define MXC_F_AFE_CTRL3_POWERUP_OPAMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_POWERUP_OPAMP2_POS))
<> 144:ef7eb2e8f9f7 525 #define MXC_F_AFE_CTRL3_POWERUP_OPAMP3_POS 15
<> 144:ef7eb2e8f9f7 526 #define MXC_F_AFE_CTRL3_POWERUP_OPAMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_POWERUP_OPAMP3_POS))
<> 144:ef7eb2e8f9f7 527 #define MXC_F_AFE_CTRL3_GND_SEL_OPAMP0_POS 16
<> 144:ef7eb2e8f9f7 528 #define MXC_F_AFE_CTRL3_GND_SEL_OPAMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_GND_SEL_OPAMP0_POS))
<> 144:ef7eb2e8f9f7 529 #define MXC_F_AFE_CTRL3_GND_SEL_OPAMP1_POS 17
<> 144:ef7eb2e8f9f7 530 #define MXC_F_AFE_CTRL3_GND_SEL_OPAMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_GND_SEL_OPAMP1_POS))
<> 144:ef7eb2e8f9f7 531 #define MXC_F_AFE_CTRL3_GND_SEL_OPAMP2_POS 18
<> 144:ef7eb2e8f9f7 532 #define MXC_F_AFE_CTRL3_GND_SEL_OPAMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_GND_SEL_OPAMP2_POS))
<> 144:ef7eb2e8f9f7 533 #define MXC_F_AFE_CTRL3_GND_SEL_OPAMP3_POS 19
<> 144:ef7eb2e8f9f7 534 #define MXC_F_AFE_CTRL3_GND_SEL_OPAMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_GND_SEL_OPAMP3_POS))
<> 144:ef7eb2e8f9f7 535 #define MXC_F_AFE_CTRL3_CLOSE_SPST0_POS 20
<> 144:ef7eb2e8f9f7 536 #define MXC_F_AFE_CTRL3_CLOSE_SPST0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_CLOSE_SPST0_POS))
<> 144:ef7eb2e8f9f7 537 #define MXC_F_AFE_CTRL3_CLOSE_SPST1_POS 21
<> 144:ef7eb2e8f9f7 538 #define MXC_F_AFE_CTRL3_CLOSE_SPST1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_CLOSE_SPST1_POS))
<> 144:ef7eb2e8f9f7 539 #define MXC_F_AFE_CTRL3_CLOSE_SPST2_POS 22
<> 144:ef7eb2e8f9f7 540 #define MXC_F_AFE_CTRL3_CLOSE_SPST2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_CLOSE_SPST2_POS))
<> 144:ef7eb2e8f9f7 541 #define MXC_F_AFE_CTRL3_CLOSE_SPST3_POS 23
<> 144:ef7eb2e8f9f7 542 #define MXC_F_AFE_CTRL3_CLOSE_SPST3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_CLOSE_SPST3_POS))
<> 144:ef7eb2e8f9f7 543 #define MXC_F_AFE_CTRL3_EN_PCH_OPAMP0_POS 24
<> 144:ef7eb2e8f9f7 544 #define MXC_F_AFE_CTRL3_EN_PCH_OPAMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_PCH_OPAMP0_POS))
<> 144:ef7eb2e8f9f7 545 #define MXC_F_AFE_CTRL3_EN_PCH_OPAMP1_POS 25
<> 144:ef7eb2e8f9f7 546 #define MXC_F_AFE_CTRL3_EN_PCH_OPAMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_PCH_OPAMP1_POS))
<> 144:ef7eb2e8f9f7 547 #define MXC_F_AFE_CTRL3_EN_PCH_OPAMP2_POS 26
<> 144:ef7eb2e8f9f7 548 #define MXC_F_AFE_CTRL3_EN_PCH_OPAMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_PCH_OPAMP2_POS))
<> 144:ef7eb2e8f9f7 549 #define MXC_F_AFE_CTRL3_EN_PCH_OPAMP3_POS 27
<> 144:ef7eb2e8f9f7 550 #define MXC_F_AFE_CTRL3_EN_PCH_OPAMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_PCH_OPAMP3_POS))
<> 144:ef7eb2e8f9f7 551 #define MXC_F_AFE_CTRL3_EN_NCH_OPAMP0_POS 28
<> 144:ef7eb2e8f9f7 552 #define MXC_F_AFE_CTRL3_EN_NCH_OPAMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_NCH_OPAMP0_POS))
<> 144:ef7eb2e8f9f7 553 #define MXC_F_AFE_CTRL3_EN_NCH_OPAMP1_POS 29
<> 144:ef7eb2e8f9f7 554 #define MXC_F_AFE_CTRL3_EN_NCH_OPAMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_NCH_OPAMP1_POS))
<> 144:ef7eb2e8f9f7 555 #define MXC_F_AFE_CTRL3_EN_NCH_OPAMP2_POS 30
<> 144:ef7eb2e8f9f7 556 #define MXC_F_AFE_CTRL3_EN_NCH_OPAMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_NCH_OPAMP2_POS))
<> 144:ef7eb2e8f9f7 557 #define MXC_F_AFE_CTRL3_EN_NCH_OPAMP3_POS 31
<> 144:ef7eb2e8f9f7 558 #define MXC_F_AFE_CTRL3_EN_NCH_OPAMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_NCH_OPAMP3_POS))
<> 144:ef7eb2e8f9f7 559
<> 144:ef7eb2e8f9f7 560 #define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP0_POS 0
<> 144:ef7eb2e8f9f7 561 #define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP0_POS))
<> 144:ef7eb2e8f9f7 562 #define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP1_POS 2
<> 144:ef7eb2e8f9f7 563 #define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP1_POS))
<> 144:ef7eb2e8f9f7 564 #define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP2_POS 4
<> 144:ef7eb2e8f9f7 565 #define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP2_POS))
<> 144:ef7eb2e8f9f7 566 #define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP3_POS 6
<> 144:ef7eb2e8f9f7 567 #define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP3_POS))
<> 144:ef7eb2e8f9f7 568 #define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP0_POS 8
<> 144:ef7eb2e8f9f7 569 #define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP0_POS))
<> 144:ef7eb2e8f9f7 570 #define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP1_POS 10
<> 144:ef7eb2e8f9f7 571 #define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP1_POS))
<> 144:ef7eb2e8f9f7 572 #define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP2_POS 12
<> 144:ef7eb2e8f9f7 573 #define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP2_POS))
<> 144:ef7eb2e8f9f7 574 #define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP3_POS 14
<> 144:ef7eb2e8f9f7 575 #define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP3_POS))
<> 144:ef7eb2e8f9f7 576 #define MXC_F_AFE_CTRL4_DAC_SEL_A_POS 16
<> 144:ef7eb2e8f9f7 577 #define MXC_F_AFE_CTRL4_DAC_SEL_A ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_DAC_SEL_A_POS))
<> 144:ef7eb2e8f9f7 578 #define MXC_F_AFE_CTRL4_DAC_SEL_B_POS 18
<> 144:ef7eb2e8f9f7 579 #define MXC_F_AFE_CTRL4_DAC_SEL_B ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_DAC_SEL_B_POS))
<> 144:ef7eb2e8f9f7 580 #define MXC_F_AFE_CTRL4_DAC_SEL_C_POS 20
<> 144:ef7eb2e8f9f7 581 #define MXC_F_AFE_CTRL4_DAC_SEL_C ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_DAC_SEL_C_POS))
<> 144:ef7eb2e8f9f7 582 #define MXC_F_AFE_CTRL4_DAC_SEL_D_POS 22
<> 144:ef7eb2e8f9f7 583 #define MXC_F_AFE_CTRL4_DAC_SEL_D ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_DAC_SEL_D_POS))
<> 144:ef7eb2e8f9f7 584 #define MXC_F_AFE_CTRL4_NPAD_SEL_A_POS 24
<> 144:ef7eb2e8f9f7 585 #define MXC_F_AFE_CTRL4_NPAD_SEL_A ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_NPAD_SEL_A_POS))
<> 144:ef7eb2e8f9f7 586 #define MXC_F_AFE_CTRL4_NPAD_SEL_B_POS 26
<> 144:ef7eb2e8f9f7 587 #define MXC_F_AFE_CTRL4_NPAD_SEL_B ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_NPAD_SEL_B_POS))
<> 144:ef7eb2e8f9f7 588 #define MXC_F_AFE_CTRL4_NPAD_SEL_C_POS 28
<> 144:ef7eb2e8f9f7 589 #define MXC_F_AFE_CTRL4_NPAD_SEL_C ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_NPAD_SEL_C_POS))
<> 144:ef7eb2e8f9f7 590 #define MXC_F_AFE_CTRL4_NPAD_SEL_D_POS 30
<> 144:ef7eb2e8f9f7 591 #define MXC_F_AFE_CTRL4_NPAD_SEL_D ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_NPAD_SEL_D_POS))
<> 144:ef7eb2e8f9f7 592
<> 144:ef7eb2e8f9f7 593 #define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP0_POS 0
<> 144:ef7eb2e8f9f7 594 #define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP0 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP0_POS))
<> 144:ef7eb2e8f9f7 595 #define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP1_POS 3
<> 144:ef7eb2e8f9f7 596 #define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP1 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP1_POS))
<> 144:ef7eb2e8f9f7 597 #define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP2_POS 6
<> 144:ef7eb2e8f9f7 598 #define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP2 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP2_POS))
<> 144:ef7eb2e8f9f7 599 #define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP3_POS 9
<> 144:ef7eb2e8f9f7 600 #define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP3 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP3_POS))
<> 144:ef7eb2e8f9f7 601 #define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP0_POS 12
<> 144:ef7eb2e8f9f7 602 #define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP0 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP0_POS))
<> 144:ef7eb2e8f9f7 603 #define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP1_POS 15
<> 144:ef7eb2e8f9f7 604 #define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP1 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP1_POS))
<> 144:ef7eb2e8f9f7 605 #define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP2_POS 18
<> 144:ef7eb2e8f9f7 606 #define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP2 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP2_POS))
<> 144:ef7eb2e8f9f7 607 #define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP3_POS 21
<> 144:ef7eb2e8f9f7 608 #define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP3 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP3_POS))
<> 144:ef7eb2e8f9f7 609 #define MXC_F_AFE_CTRL5_OP_CMP0_POS 24
<> 144:ef7eb2e8f9f7 610 #define MXC_F_AFE_CTRL5_OP_CMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL5_OP_CMP0_POS))
<> 144:ef7eb2e8f9f7 611 #define MXC_F_AFE_CTRL5_OP_CMP1_POS 25
<> 144:ef7eb2e8f9f7 612 #define MXC_F_AFE_CTRL5_OP_CMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL5_OP_CMP1_POS))
<> 144:ef7eb2e8f9f7 613 #define MXC_F_AFE_CTRL5_OP_CMP2_POS 26
<> 144:ef7eb2e8f9f7 614 #define MXC_F_AFE_CTRL5_OP_CMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL5_OP_CMP2_POS))
<> 144:ef7eb2e8f9f7 615 #define MXC_F_AFE_CTRL5_OP_CMP3_POS 27
<> 144:ef7eb2e8f9f7 616 #define MXC_F_AFE_CTRL5_OP_CMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL5_OP_CMP3_POS))
<> 144:ef7eb2e8f9f7 617
<> 144:ef7eb2e8f9f7 618 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 619 }
<> 144:ef7eb2e8f9f7 620 #endif
<> 144:ef7eb2e8f9f7 621
<> 144:ef7eb2e8f9f7 622 /**
<> 144:ef7eb2e8f9f7 623 * @}
<> 144:ef7eb2e8f9f7 624 */
<> 144:ef7eb2e8f9f7 625
<> 144:ef7eb2e8f9f7 626 #endif /* _MXC_AFE_REGS_H_ */