added prescaler for 16 bit pwm in LPC1347 target
Fork of mbed-dev by
targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_ARM_STD/startup_MKL46Z4.S@144:ef7eb2e8f9f7, 2016-09-02 (annotated)
- Committer:
- <>
- Date:
- Fri Sep 02 15:07:44 2016 +0100
- Revision:
- 144:ef7eb2e8f9f7
- Parent:
- 0:9b334a45a8ff
This updates the lib to the mbed lib v125
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | ;/***************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 2 | ; * @file: startup_MKL46Z4.s |
<> | 144:ef7eb2e8f9f7 | 3 | ; * @purpose: CMSIS Cortex-M0plus Core Device Startup File for the |
<> | 144:ef7eb2e8f9f7 | 4 | ; * MKL46Z4 |
<> | 144:ef7eb2e8f9f7 | 5 | ; * @version: 2.0 |
<> | 144:ef7eb2e8f9f7 | 6 | ; * @date: 2012-12-12 |
<> | 144:ef7eb2e8f9f7 | 7 | ; * |
<> | 144:ef7eb2e8f9f7 | 8 | ; * Copyright: 1997 - 2013 Freescale Semiconductor, Inc. All Rights Reserved. |
<> | 144:ef7eb2e8f9f7 | 9 | ;* |
<> | 144:ef7eb2e8f9f7 | 10 | ; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ |
<> | 144:ef7eb2e8f9f7 | 11 | ; * |
<> | 144:ef7eb2e8f9f7 | 12 | ; *****************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 13 | |
<> | 144:ef7eb2e8f9f7 | 14 | |
<> | 144:ef7eb2e8f9f7 | 15 | __initial_sp EQU 0x20006000 ; Top of RAM |
<> | 144:ef7eb2e8f9f7 | 16 | |
<> | 144:ef7eb2e8f9f7 | 17 | PRESERVE8 |
<> | 144:ef7eb2e8f9f7 | 18 | THUMB |
<> | 144:ef7eb2e8f9f7 | 19 | |
<> | 144:ef7eb2e8f9f7 | 20 | |
<> | 144:ef7eb2e8f9f7 | 21 | ; Vector Table Mapped to Address 0 at Reset |
<> | 144:ef7eb2e8f9f7 | 22 | |
<> | 144:ef7eb2e8f9f7 | 23 | AREA RESET, DATA, READONLY |
<> | 144:ef7eb2e8f9f7 | 24 | EXPORT __Vectors |
<> | 144:ef7eb2e8f9f7 | 25 | EXPORT __Vectors_End |
<> | 144:ef7eb2e8f9f7 | 26 | EXPORT __Vectors_Size |
<> | 144:ef7eb2e8f9f7 | 27 | |
<> | 144:ef7eb2e8f9f7 | 28 | __Vectors DCD __initial_sp ; Top of Stack |
<> | 144:ef7eb2e8f9f7 | 29 | DCD Reset_Handler ; Reset Handler |
<> | 144:ef7eb2e8f9f7 | 30 | DCD NMI_Handler ; NMI Handler |
<> | 144:ef7eb2e8f9f7 | 31 | DCD HardFault_Handler ; Hard Fault Handler |
<> | 144:ef7eb2e8f9f7 | 32 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 33 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 34 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 35 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 36 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 37 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 38 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 39 | DCD SVC_Handler ; SVCall Handler |
<> | 144:ef7eb2e8f9f7 | 40 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 41 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 42 | DCD PendSV_Handler ; PendSV Handler |
<> | 144:ef7eb2e8f9f7 | 43 | DCD SysTick_Handler ; SysTick Handler |
<> | 144:ef7eb2e8f9f7 | 44 | |
<> | 144:ef7eb2e8f9f7 | 45 | ; External Interrupts |
<> | 144:ef7eb2e8f9f7 | 46 | DCD DMA0_IRQHandler ; DMA channel 0 transfer complete/error interrupt |
<> | 144:ef7eb2e8f9f7 | 47 | DCD DMA1_IRQHandler ; DMA channel 1 transfer complete/error interrupt |
<> | 144:ef7eb2e8f9f7 | 48 | DCD DMA2_IRQHandler ; DMA channel 2 transfer complete/error interrupt |
<> | 144:ef7eb2e8f9f7 | 49 | DCD DMA3_IRQHandler ; DMA channel 3 transfer complete/error interrupt |
<> | 144:ef7eb2e8f9f7 | 50 | DCD Reserved20_IRQHandler ; Reserved interrupt 20 |
<> | 144:ef7eb2e8f9f7 | 51 | DCD FTFA_IRQHandler ; FTFA command complete/read collision interrupt |
<> | 144:ef7eb2e8f9f7 | 52 | DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning |
<> | 144:ef7eb2e8f9f7 | 53 | DCD LLW_IRQHandler ; Low Leakage Wakeup |
<> | 144:ef7eb2e8f9f7 | 54 | DCD I2C0_IRQHandler ; I2C0 interrupt |
<> | 144:ef7eb2e8f9f7 | 55 | DCD I2C1_IRQHandler ; I2C0 interrupt 25 |
<> | 144:ef7eb2e8f9f7 | 56 | DCD SPI0_IRQHandler ; SPI0 interrupt |
<> | 144:ef7eb2e8f9f7 | 57 | DCD SPI1_IRQHandler ; SPI1 interrupt |
<> | 144:ef7eb2e8f9f7 | 58 | DCD UART0_IRQHandler ; UART0 status/error interrupt |
<> | 144:ef7eb2e8f9f7 | 59 | DCD UART1_IRQHandler ; UART1 status/error interrupt |
<> | 144:ef7eb2e8f9f7 | 60 | DCD UART2_IRQHandler ; UART2 status/error interrupt |
<> | 144:ef7eb2e8f9f7 | 61 | DCD ADC0_IRQHandler ; ADC0 interrupt |
<> | 144:ef7eb2e8f9f7 | 62 | DCD CMP0_IRQHandler ; CMP0 interrupt |
<> | 144:ef7eb2e8f9f7 | 63 | DCD TPM0_IRQHandler ; TPM0 fault, overflow and channels interrupt |
<> | 144:ef7eb2e8f9f7 | 64 | DCD TPM1_IRQHandler ; TPM1 fault, overflow and channels interrupt |
<> | 144:ef7eb2e8f9f7 | 65 | DCD TPM2_IRQHandler ; TPM2 fault, overflow and channels interrupt |
<> | 144:ef7eb2e8f9f7 | 66 | DCD RTC_IRQHandler ; RTC interrupt |
<> | 144:ef7eb2e8f9f7 | 67 | DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt |
<> | 144:ef7eb2e8f9f7 | 68 | DCD PIT_IRQHandler ; PIT timer interrupt |
<> | 144:ef7eb2e8f9f7 | 69 | DCD I2S0_IRQHandler ; I2S0 transmit interrupt |
<> | 144:ef7eb2e8f9f7 | 70 | DCD USB0_IRQHandler ; USB0 interrupt |
<> | 144:ef7eb2e8f9f7 | 71 | DCD DAC0_IRQHandler ; DAC0 interrupt |
<> | 144:ef7eb2e8f9f7 | 72 | DCD TSI0_IRQHandler ; TSI0 interrupt |
<> | 144:ef7eb2e8f9f7 | 73 | DCD MCG_IRQHandler ; MCG interrupt |
<> | 144:ef7eb2e8f9f7 | 74 | DCD LPTimer_IRQHandler ; LPTimer interrupt |
<> | 144:ef7eb2e8f9f7 | 75 | DCD LCD_IRQHandler ; Segment LCD Interrupt |
<> | 144:ef7eb2e8f9f7 | 76 | DCD PORTA_IRQHandler ; Port A interrupt |
<> | 144:ef7eb2e8f9f7 | 77 | DCD PORTD_IRQHandler ; Port D interrupt |
<> | 144:ef7eb2e8f9f7 | 78 | __Vectors_End |
<> | 144:ef7eb2e8f9f7 | 79 | |
<> | 144:ef7eb2e8f9f7 | 80 | __Vectors_Size EQU __Vectors_End - __Vectors |
<> | 144:ef7eb2e8f9f7 | 81 | |
<> | 144:ef7eb2e8f9f7 | 82 | ; <h> Flash Configuration |
<> | 144:ef7eb2e8f9f7 | 83 | ; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset) |
<> | 144:ef7eb2e8f9f7 | 84 | ; <i> and security information that allows the MCU to restrict acces to the FTFL module. |
<> | 144:ef7eb2e8f9f7 | 85 | ; <h> Backdoor Comparison Key |
<> | 144:ef7eb2e8f9f7 | 86 | ; <o0> Backdoor Key 0 <0x0-0xFF:2> |
<> | 144:ef7eb2e8f9f7 | 87 | ; <o1> Backdoor Key 1 <0x0-0xFF:2> |
<> | 144:ef7eb2e8f9f7 | 88 | ; <o2> Backdoor Key 2 <0x0-0xFF:2> |
<> | 144:ef7eb2e8f9f7 | 89 | ; <o3> Backdoor Key 3 <0x0-0xFF:2> |
<> | 144:ef7eb2e8f9f7 | 90 | ; <o4> Backdoor Key 4 <0x0-0xFF:2> |
<> | 144:ef7eb2e8f9f7 | 91 | ; <o5> Backdoor Key 5 <0x0-0xFF:2> |
<> | 144:ef7eb2e8f9f7 | 92 | ; <o6> Backdoor Key 6 <0x0-0xFF:2> |
<> | 144:ef7eb2e8f9f7 | 93 | ; <o7> Backdoor Key 7 <0x0-0xFF:2> |
<> | 144:ef7eb2e8f9f7 | 94 | BackDoorK0 EQU 0xFF |
<> | 144:ef7eb2e8f9f7 | 95 | BackDoorK1 EQU 0xFF |
<> | 144:ef7eb2e8f9f7 | 96 | BackDoorK2 EQU 0xFF |
<> | 144:ef7eb2e8f9f7 | 97 | BackDoorK3 EQU 0xFF |
<> | 144:ef7eb2e8f9f7 | 98 | BackDoorK4 EQU 0xFF |
<> | 144:ef7eb2e8f9f7 | 99 | BackDoorK5 EQU 0xFF |
<> | 144:ef7eb2e8f9f7 | 100 | BackDoorK6 EQU 0xFF |
<> | 144:ef7eb2e8f9f7 | 101 | BackDoorK7 EQU 0xFF |
<> | 144:ef7eb2e8f9f7 | 102 | ; </h> |
<> | 144:ef7eb2e8f9f7 | 103 | ; <h> Program flash protection bytes (FPROT) |
<> | 144:ef7eb2e8f9f7 | 104 | ; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit. |
<> | 144:ef7eb2e8f9f7 | 105 | ; <i> Each bit protects a 1/32 region of the program flash memory. |
<> | 144:ef7eb2e8f9f7 | 106 | ; <h> FPROT0 |
<> | 144:ef7eb2e8f9f7 | 107 | ; <i> Program flash protection bytes |
<> | 144:ef7eb2e8f9f7 | 108 | ; <i> 1/32 - 8/32 region |
<> | 144:ef7eb2e8f9f7 | 109 | ; <o.0> FPROT0.0 |
<> | 144:ef7eb2e8f9f7 | 110 | ; <o.1> FPROT0.1 |
<> | 144:ef7eb2e8f9f7 | 111 | ; <o.2> FPROT0.2 |
<> | 144:ef7eb2e8f9f7 | 112 | ; <o.3> FPROT0.3 |
<> | 144:ef7eb2e8f9f7 | 113 | ; <o.4> FPROT0.4 |
<> | 144:ef7eb2e8f9f7 | 114 | ; <o.5> FPROT0.5 |
<> | 144:ef7eb2e8f9f7 | 115 | ; <o.6> FPROT0.6 |
<> | 144:ef7eb2e8f9f7 | 116 | ; <o.7> FPROT0.7 |
<> | 144:ef7eb2e8f9f7 | 117 | nFPROT0 EQU 0x00 |
<> | 144:ef7eb2e8f9f7 | 118 | FPROT0 EQU nFPROT0:EOR:0xFF |
<> | 144:ef7eb2e8f9f7 | 119 | ; </h> |
<> | 144:ef7eb2e8f9f7 | 120 | ; <h> FPROT1 |
<> | 144:ef7eb2e8f9f7 | 121 | ; <i> Program Flash Region Protect Register 1 |
<> | 144:ef7eb2e8f9f7 | 122 | ; <i> 9/32 - 16/32 region |
<> | 144:ef7eb2e8f9f7 | 123 | ; <o.0> FPROT1.0 |
<> | 144:ef7eb2e8f9f7 | 124 | ; <o.1> FPROT1.1 |
<> | 144:ef7eb2e8f9f7 | 125 | ; <o.2> FPROT1.2 |
<> | 144:ef7eb2e8f9f7 | 126 | ; <o.3> FPROT1.3 |
<> | 144:ef7eb2e8f9f7 | 127 | ; <o.4> FPROT1.4 |
<> | 144:ef7eb2e8f9f7 | 128 | ; <o.5> FPROT1.5 |
<> | 144:ef7eb2e8f9f7 | 129 | ; <o.6> FPROT1.6 |
<> | 144:ef7eb2e8f9f7 | 130 | ; <o.7> FPROT1.7 |
<> | 144:ef7eb2e8f9f7 | 131 | nFPROT1 EQU 0x00 |
<> | 144:ef7eb2e8f9f7 | 132 | FPROT1 EQU nFPROT1:EOR:0xFF |
<> | 144:ef7eb2e8f9f7 | 133 | ; </h> |
<> | 144:ef7eb2e8f9f7 | 134 | ; <h> FPROT2 |
<> | 144:ef7eb2e8f9f7 | 135 | ; <i> Program Flash Region Protect Register 2 |
<> | 144:ef7eb2e8f9f7 | 136 | ; <i> 17/32 - 24/32 region |
<> | 144:ef7eb2e8f9f7 | 137 | ; <o.0> FPROT2.0 |
<> | 144:ef7eb2e8f9f7 | 138 | ; <o.1> FPROT2.1 |
<> | 144:ef7eb2e8f9f7 | 139 | ; <o.2> FPROT2.2 |
<> | 144:ef7eb2e8f9f7 | 140 | ; <o.3> FPROT2.3 |
<> | 144:ef7eb2e8f9f7 | 141 | ; <o.4> FPROT2.4 |
<> | 144:ef7eb2e8f9f7 | 142 | ; <o.5> FPROT2.5 |
<> | 144:ef7eb2e8f9f7 | 143 | ; <o.6> FPROT2.6 |
<> | 144:ef7eb2e8f9f7 | 144 | ; <o.7> FPROT2.7 |
<> | 144:ef7eb2e8f9f7 | 145 | nFPROT2 EQU 0x00 |
<> | 144:ef7eb2e8f9f7 | 146 | FPROT2 EQU nFPROT2:EOR:0xFF |
<> | 144:ef7eb2e8f9f7 | 147 | ; </h> |
<> | 144:ef7eb2e8f9f7 | 148 | ; <h> FPROT3 |
<> | 144:ef7eb2e8f9f7 | 149 | ; <i> Program Flash Region Protect Register 3 |
<> | 144:ef7eb2e8f9f7 | 150 | ; <i> 25/32 - 32/32 region |
<> | 144:ef7eb2e8f9f7 | 151 | ; <o.0> FPROT3.0 |
<> | 144:ef7eb2e8f9f7 | 152 | ; <o.1> FPROT3.1 |
<> | 144:ef7eb2e8f9f7 | 153 | ; <o.2> FPROT3.2 |
<> | 144:ef7eb2e8f9f7 | 154 | ; <o.3> FPROT3.3 |
<> | 144:ef7eb2e8f9f7 | 155 | ; <o.4> FPROT3.4 |
<> | 144:ef7eb2e8f9f7 | 156 | ; <o.5> FPROT3.5 |
<> | 144:ef7eb2e8f9f7 | 157 | ; <o.6> FPROT3.6 |
<> | 144:ef7eb2e8f9f7 | 158 | ; <o.7> FPROT3.7 |
<> | 144:ef7eb2e8f9f7 | 159 | nFPROT3 EQU 0x00 |
<> | 144:ef7eb2e8f9f7 | 160 | FPROT3 EQU nFPROT3:EOR:0xFF |
<> | 144:ef7eb2e8f9f7 | 161 | ; </h> |
<> | 144:ef7eb2e8f9f7 | 162 | ; </h> |
<> | 144:ef7eb2e8f9f7 | 163 | ; </h> |
<> | 144:ef7eb2e8f9f7 | 164 | ; <h> Flash nonvolatile option byte (FOPT) |
<> | 144:ef7eb2e8f9f7 | 165 | ; <i> Allows the user to customize the operation of the MCU at boot time. |
<> | 144:ef7eb2e8f9f7 | 166 | ; <o.0> LPBOOT0 |
<> | 144:ef7eb2e8f9f7 | 167 | ; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x3 (divide by 4) |
<> | 144:ef7eb2e8f9f7 | 168 | ; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) or 0x0 (divide by 1) |
<> | 144:ef7eb2e8f9f7 | 169 | ; <o.4> LPBOOT1 |
<> | 144:ef7eb2e8f9f7 | 170 | ; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x1 (divide by 2) |
<> | 144:ef7eb2e8f9f7 | 171 | ; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) or 0x0 (divide by 1) |
<> | 144:ef7eb2e8f9f7 | 172 | ; <o.2> NMI_DIS |
<> | 144:ef7eb2e8f9f7 | 173 | ; <0=> NMI interrupts are always blocked |
<> | 144:ef7eb2e8f9f7 | 174 | ; <1=> NMI pin/interrupts reset default to enabled |
<> | 144:ef7eb2e8f9f7 | 175 | ; <o.3> RESET_PIN_CFG |
<> | 144:ef7eb2e8f9f7 | 176 | ; <0=> RESET pin is disabled following a POR and cannot be enabled as RESET function |
<> | 144:ef7eb2e8f9f7 | 177 | ; <1=> RESET pin is dedicated |
<> | 144:ef7eb2e8f9f7 | 178 | ; <o.3> FAST_INIT |
<> | 144:ef7eb2e8f9f7 | 179 | ; <0=> Slower initialization |
<> | 144:ef7eb2e8f9f7 | 180 | ; <1=> Fast Initialization |
<> | 144:ef7eb2e8f9f7 | 181 | FOPT EQU 0xFF |
<> | 144:ef7eb2e8f9f7 | 182 | ; </h> |
<> | 144:ef7eb2e8f9f7 | 183 | ; <h> Flash security byte (FSEC) |
<> | 144:ef7eb2e8f9f7 | 184 | ; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled", |
<> | 144:ef7eb2e8f9f7 | 185 | ; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!! |
<> | 144:ef7eb2e8f9f7 | 186 | ; <o.0..1> SEC |
<> | 144:ef7eb2e8f9f7 | 187 | ; <2=> MCU security status is unsecure |
<> | 144:ef7eb2e8f9f7 | 188 | ; <3=> MCU security status is secure |
<> | 144:ef7eb2e8f9f7 | 189 | ; <i> Flash Security |
<> | 144:ef7eb2e8f9f7 | 190 | ; <i> This bits define the security state of the MCU. |
<> | 144:ef7eb2e8f9f7 | 191 | ; <o.2..3> FSLACC |
<> | 144:ef7eb2e8f9f7 | 192 | ; <2=> Freescale factory access denied |
<> | 144:ef7eb2e8f9f7 | 193 | ; <3=> Freescale factory access granted |
<> | 144:ef7eb2e8f9f7 | 194 | ; <i> Freescale Failure Analysis Access Code |
<> | 144:ef7eb2e8f9f7 | 195 | ; <i> This bits define the security state of the MCU. |
<> | 144:ef7eb2e8f9f7 | 196 | ; <o.4..5> MEEN |
<> | 144:ef7eb2e8f9f7 | 197 | ; <2=> Mass erase is disabled |
<> | 144:ef7eb2e8f9f7 | 198 | ; <3=> Mass erase is enabled |
<> | 144:ef7eb2e8f9f7 | 199 | ; <i> Mass Erase Enable Bits |
<> | 144:ef7eb2e8f9f7 | 200 | ; <i> Enables and disables mass erase capability of the FTFL module |
<> | 144:ef7eb2e8f9f7 | 201 | ; <o.6..7> KEYEN |
<> | 144:ef7eb2e8f9f7 | 202 | ; <2=> Backdoor key access enabled |
<> | 144:ef7eb2e8f9f7 | 203 | ; <3=> Backdoor key access disabled |
<> | 144:ef7eb2e8f9f7 | 204 | ; <i> Backdoor key Security Enable |
<> | 144:ef7eb2e8f9f7 | 205 | ; <i> These bits enable and disable backdoor key access to the FTFL module. |
<> | 144:ef7eb2e8f9f7 | 206 | FSEC EQU 0xFE |
<> | 144:ef7eb2e8f9f7 | 207 | ; </h> |
<> | 144:ef7eb2e8f9f7 | 208 | |
<> | 144:ef7eb2e8f9f7 | 209 | IF :LNOT::DEF:RAM_TARGET |
<> | 144:ef7eb2e8f9f7 | 210 | AREA |.ARM.__at_0x400|, CODE, READONLY |
<> | 144:ef7eb2e8f9f7 | 211 | DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3 |
<> | 144:ef7eb2e8f9f7 | 212 | DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7 |
<> | 144:ef7eb2e8f9f7 | 213 | DCB FPROT0, FPROT1, FPROT2, FPROT3 |
<> | 144:ef7eb2e8f9f7 | 214 | DCB FSEC, FOPT, 0xFF, 0xFF |
<> | 144:ef7eb2e8f9f7 | 215 | ENDIF |
<> | 144:ef7eb2e8f9f7 | 216 | |
<> | 144:ef7eb2e8f9f7 | 217 | AREA |.text|, CODE, READONLY |
<> | 144:ef7eb2e8f9f7 | 218 | |
<> | 144:ef7eb2e8f9f7 | 219 | |
<> | 144:ef7eb2e8f9f7 | 220 | ; Reset Handler |
<> | 144:ef7eb2e8f9f7 | 221 | |
<> | 144:ef7eb2e8f9f7 | 222 | Reset_Handler PROC |
<> | 144:ef7eb2e8f9f7 | 223 | EXPORT Reset_Handler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 224 | IMPORT SystemInit |
<> | 144:ef7eb2e8f9f7 | 225 | IMPORT __main |
<> | 144:ef7eb2e8f9f7 | 226 | LDR R0, =SystemInit |
<> | 144:ef7eb2e8f9f7 | 227 | BLX R0 |
<> | 144:ef7eb2e8f9f7 | 228 | LDR R0, =__main |
<> | 144:ef7eb2e8f9f7 | 229 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 230 | ENDP |
<> | 144:ef7eb2e8f9f7 | 231 | |
<> | 144:ef7eb2e8f9f7 | 232 | |
<> | 144:ef7eb2e8f9f7 | 233 | ; Dummy Exception Handlers (infinite loops which can be modified) |
<> | 144:ef7eb2e8f9f7 | 234 | |
<> | 144:ef7eb2e8f9f7 | 235 | NMI_Handler PROC |
<> | 144:ef7eb2e8f9f7 | 236 | EXPORT NMI_Handler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 237 | B . |
<> | 144:ef7eb2e8f9f7 | 238 | ENDP |
<> | 144:ef7eb2e8f9f7 | 239 | HardFault_Handler\ |
<> | 144:ef7eb2e8f9f7 | 240 | PROC |
<> | 144:ef7eb2e8f9f7 | 241 | EXPORT HardFault_Handler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 242 | B . |
<> | 144:ef7eb2e8f9f7 | 243 | ENDP |
<> | 144:ef7eb2e8f9f7 | 244 | SVC_Handler PROC |
<> | 144:ef7eb2e8f9f7 | 245 | EXPORT SVC_Handler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 246 | B . |
<> | 144:ef7eb2e8f9f7 | 247 | ENDP |
<> | 144:ef7eb2e8f9f7 | 248 | PendSV_Handler PROC |
<> | 144:ef7eb2e8f9f7 | 249 | EXPORT PendSV_Handler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 250 | B . |
<> | 144:ef7eb2e8f9f7 | 251 | ENDP |
<> | 144:ef7eb2e8f9f7 | 252 | SysTick_Handler PROC |
<> | 144:ef7eb2e8f9f7 | 253 | EXPORT SysTick_Handler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 254 | B . |
<> | 144:ef7eb2e8f9f7 | 255 | ENDP |
<> | 144:ef7eb2e8f9f7 | 256 | |
<> | 144:ef7eb2e8f9f7 | 257 | Default_Handler PROC |
<> | 144:ef7eb2e8f9f7 | 258 | EXPORT DMA0_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 259 | EXPORT DMA1_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 260 | EXPORT DMA2_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 261 | EXPORT DMA3_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 262 | EXPORT Reserved20_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 263 | EXPORT FTFA_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 264 | EXPORT LVD_LVW_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 265 | EXPORT LLW_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 266 | EXPORT I2C0_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 267 | EXPORT I2C1_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 268 | EXPORT SPI0_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 269 | EXPORT SPI1_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 270 | EXPORT UART0_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 271 | EXPORT UART1_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 272 | EXPORT UART2_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 273 | EXPORT ADC0_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 274 | EXPORT CMP0_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 275 | EXPORT TPM0_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 276 | EXPORT TPM1_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 277 | EXPORT TPM2_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 278 | EXPORT RTC_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 279 | EXPORT RTC_Seconds_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 280 | EXPORT PIT_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 281 | EXPORT I2S0_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 282 | EXPORT USB0_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 283 | EXPORT DAC0_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 284 | EXPORT TSI0_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 285 | EXPORT MCG_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 286 | EXPORT LPTimer_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 287 | EXPORT LCD_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 288 | EXPORT PORTA_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 289 | EXPORT PORTD_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 290 | EXPORT DefaultISR [WEAK] |
<> | 144:ef7eb2e8f9f7 | 291 | |
<> | 144:ef7eb2e8f9f7 | 292 | DMA0_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 293 | DMA1_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 294 | DMA2_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 295 | DMA3_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 296 | Reserved20_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 297 | FTFA_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 298 | LVD_LVW_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 299 | LLW_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 300 | I2C0_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 301 | I2C1_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 302 | SPI0_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 303 | SPI1_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 304 | UART0_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 305 | UART1_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 306 | UART2_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 307 | ADC0_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 308 | CMP0_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 309 | TPM0_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 310 | TPM1_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 311 | TPM2_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 312 | RTC_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 313 | RTC_Seconds_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 314 | PIT_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 315 | I2S0_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 316 | USB0_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 317 | DAC0_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 318 | TSI0_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 319 | MCG_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 320 | LPTimer_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 321 | LCD_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 322 | PORTA_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 323 | PORTD_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 324 | DefaultISR |
<> | 144:ef7eb2e8f9f7 | 325 | |
<> | 144:ef7eb2e8f9f7 | 326 | B . |
<> | 144:ef7eb2e8f9f7 | 327 | |
<> | 144:ef7eb2e8f9f7 | 328 | ENDP |
<> | 144:ef7eb2e8f9f7 | 329 | |
<> | 144:ef7eb2e8f9f7 | 330 | |
<> | 144:ef7eb2e8f9f7 | 331 | ALIGN |
<> | 144:ef7eb2e8f9f7 | 332 | END |