Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/SMM_MPS2.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
80:bdf1132a57cf 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* MPS2 CMSIS Library
<> 144:ef7eb2e8f9f7 2 *
<> 144:ef7eb2e8f9f7 3 * Copyright (c) 2006-2016 ARM Limited
<> 144:ef7eb2e8f9f7 4 * All rights reserved.
<> 144:ef7eb2e8f9f7 5 *
<> 144:ef7eb2e8f9f7 6 * Redistribution and use in source and binary forms, with or without
<> 144:ef7eb2e8f9f7 7 * modification, are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 10 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 11 *
<> 144:ef7eb2e8f9f7 12 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 13 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 14 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 15 *
<> 144:ef7eb2e8f9f7 16 * 3. Neither the name of the copyright holder nor the names of its contributors
<> 144:ef7eb2e8f9f7 17 * may be used to endorse or promote products derived from this software without
<> 144:ef7eb2e8f9f7 18 * specific prior written permission.
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 144:ef7eb2e8f9f7 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
<> 144:ef7eb2e8f9f7 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 144:ef7eb2e8f9f7 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 144:ef7eb2e8f9f7 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 144:ef7eb2e8f9f7 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 144:ef7eb2e8f9f7 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 144:ef7eb2e8f9f7 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 144:ef7eb2e8f9f7 30 * POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 31 *******************************************************************************
<> 144:ef7eb2e8f9f7 32 * File: smm_mps2.h
<> 144:ef7eb2e8f9f7 33 * Release: Version 1.1
<> 144:ef7eb2e8f9f7 34 *******************************************************************************/
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 #ifndef __SMM_MPS2_H
<> 144:ef7eb2e8f9f7 37 #define __SMM_MPS2_H
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 #include "peripherallink.h" /* device specific header file */
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 #if defined ( __CC_ARM )
<> 144:ef7eb2e8f9f7 42 #pragma anon_unions
<> 144:ef7eb2e8f9f7 43 #endif
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 /******************************************************************************/
<> 144:ef7eb2e8f9f7 46 /* FPGA System Register declaration */
<> 144:ef7eb2e8f9f7 47 /******************************************************************************/
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 typedef struct
<> 144:ef7eb2e8f9f7 50 {
<> 144:ef7eb2e8f9f7 51 __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections
<> 144:ef7eb2e8f9f7 52 // [31:2] : Reserved
<> 144:ef7eb2e8f9f7 53 // [1:0] : LEDs
<> 144:ef7eb2e8f9f7 54 uint32_t RESERVED1[1];
<> 144:ef7eb2e8f9f7 55 __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons
<> 144:ef7eb2e8f9f7 56 // [31:2] : Reserved
<> 144:ef7eb2e8f9f7 57 // [1:0] : Buttons
<> 144:ef7eb2e8f9f7 58 uint32_t RESERVED2[1];
<> 144:ef7eb2e8f9f7 59 __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter
<> 144:ef7eb2e8f9f7 60 __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter
<> 144:ef7eb2e8f9f7 61 __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter
<> 144:ef7eb2e8f9f7 62 // Increments when 32-bit prescale counter reach zero
<> 144:ef7eb2e8f9f7 63 uint32_t RESERVED3[1];
<> 144:ef7eb2e8f9f7 64 __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler
<> 144:ef7eb2e8f9f7 65 // Bit[31:0] : reload value for prescale counter
<> 144:ef7eb2e8f9f7 66 __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter
<> 144:ef7eb2e8f9f7 67 // current value of the pre-scaler counter
<> 144:ef7eb2e8f9f7 68 // The Cycle Up Counter increment when the prescale down counter reach 0
<> 144:ef7eb2e8f9f7 69 // The pre-scaler counter is reloaded with PRESCALE after reaching 0.
<> 144:ef7eb2e8f9f7 70 uint32_t RESERVED4[9];
<> 144:ef7eb2e8f9f7 71 __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */
<> 144:ef7eb2e8f9f7 72 // [31:10] : Reserved
<> 144:ef7eb2e8f9f7 73 // [9] : SHIELD_1_SPI_nCS
<> 144:ef7eb2e8f9f7 74 // [8] : SHIELD_0_SPI_nCS
<> 144:ef7eb2e8f9f7 75 // [7] : ADC_SPI_nCS
<> 144:ef7eb2e8f9f7 76 // [6] : CLCD_BL_CTRL
<> 144:ef7eb2e8f9f7 77 // [5] : CLCD_RD
<> 144:ef7eb2e8f9f7 78 // [4] : CLCD_RS
<> 144:ef7eb2e8f9f7 79 // [3] : CLCD_RESET
<> 144:ef7eb2e8f9f7 80 // [2] : RESERVED
<> 144:ef7eb2e8f9f7 81 // [1] : SPI_nSS
<> 144:ef7eb2e8f9f7 82 // [0] : CLCD_CS
<> 144:ef7eb2e8f9f7 83 } MPS2_FPGAIO_TypeDef;
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 // MISC register bit definitions
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 #define CLCD_CS_Pos 0
<> 144:ef7eb2e8f9f7 88 #define CLCD_CS_Msk (1UL<<CLCD_CS_Pos)
<> 144:ef7eb2e8f9f7 89 #define SPI_nSS_Pos 1
<> 144:ef7eb2e8f9f7 90 #define SPI_nSS_Msk (1UL<<SPI_nSS_Pos)
<> 144:ef7eb2e8f9f7 91 #define CLCD_RESET_Pos 3
<> 144:ef7eb2e8f9f7 92 #define CLCD_RESET_Msk (1UL<<CLCD_RESET_Pos)
<> 144:ef7eb2e8f9f7 93 #define CLCD_RS_Pos 4
<> 144:ef7eb2e8f9f7 94 #define CLCD_RS_Msk (1UL<<CLCD_RS_Pos)
<> 144:ef7eb2e8f9f7 95 #define CLCD_RD_Pos 5
<> 144:ef7eb2e8f9f7 96 #define CLCD_RD_Msk (1UL<<CLCD_RD_Pos)
<> 144:ef7eb2e8f9f7 97 #define CLCD_BL_Pos 6
<> 144:ef7eb2e8f9f7 98 #define CLCD_BL_Msk (1UL<<CLCD_BL_Pos)
<> 144:ef7eb2e8f9f7 99 #define ADC_nCS_Pos 7
<> 144:ef7eb2e8f9f7 100 #define ADC_nCS_Msk (1UL<<ADC_nCS_Pos)
<> 144:ef7eb2e8f9f7 101 #define SHIELD_0_nCS_Pos 8
<> 144:ef7eb2e8f9f7 102 #define SHIELD_0_nCS_Msk (1UL<<SHIELD_0_nCS_Pos)
<> 144:ef7eb2e8f9f7 103 #define SHIELD_1_nCS_Pos 9
<> 144:ef7eb2e8f9f7 104 #define SHIELD_1_nCS_Msk (1UL<<SHIELD_1_nCS_Pos)
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 /******************************************************************************/
<> 144:ef7eb2e8f9f7 107 /* SCC Register declaration */
<> 144:ef7eb2e8f9f7 108 /******************************************************************************/
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 typedef struct //
<> 144:ef7eb2e8f9f7 111 {
<> 144:ef7eb2e8f9f7 112 __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT
<> 144:ef7eb2e8f9f7 113 // [31:1] : Reserved
<> 144:ef7eb2e8f9f7 114 // [0] 1 : REMAP BlockRam to ZBT
<> 144:ef7eb2e8f9f7 115 __IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs
<> 144:ef7eb2e8f9f7 116 // [31:8] : Reserved
<> 144:ef7eb2e8f9f7 117 // [7:0] : MCC LEDs
<> 144:ef7eb2e8f9f7 118 uint32_t RESERVED0[1];
<> 144:ef7eb2e8f9f7 119 __I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches
<> 144:ef7eb2e8f9f7 120 // [31:8] : Reserved
<> 144:ef7eb2e8f9f7 121 // [7:0] : These bits indicate state of the MCC switches
<> 144:ef7eb2e8f9f7 122 __I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision
<> 144:ef7eb2e8f9f7 123 // [31:4] : Reserved
<> 144:ef7eb2e8f9f7 124 // [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B
<> 144:ef7eb2e8f9f7 125 uint32_t RESERVED1[35];
<> 144:ef7eb2e8f9f7 126 __IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register
<> 144:ef7eb2e8f9f7 127 // [31:0] : Data
<> 144:ef7eb2e8f9f7 128 __IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register
<> 144:ef7eb2e8f9f7 129 // [31:0] : Data
<> 144:ef7eb2e8f9f7 130 __IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register
<> 144:ef7eb2e8f9f7 131 // [31] : Start (generates interrupt on write to this bit)
<> 144:ef7eb2e8f9f7 132 // [30] : R/W access
<> 144:ef7eb2e8f9f7 133 // [29:26] : Reserved
<> 144:ef7eb2e8f9f7 134 // [25:20] : Function value
<> 144:ef7eb2e8f9f7 135 // [19:12] : Reserved
<> 144:ef7eb2e8f9f7 136 // [11:0] : Device (value of 0/1/2 for supported clocks)
<> 144:ef7eb2e8f9f7 137 __IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information
<> 144:ef7eb2e8f9f7 138 // [31:2] : Reserved
<> 144:ef7eb2e8f9f7 139 // [1] : Error
<> 144:ef7eb2e8f9f7 140 // [0] : Complete
<> 144:ef7eb2e8f9f7 141 __IO uint32_t RESERVED2[20];
<> 144:ef7eb2e8f9f7 142 __IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register
<> 144:ef7eb2e8f9f7 143 // [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked
<> 144:ef7eb2e8f9f7 144 // [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked
<> 144:ef7eb2e8f9f7 145 // [15:1] : Reserved
<> 144:ef7eb2e8f9f7 146 // [0] : This bit indicates if all enabled DLLs are locked
<> 144:ef7eb2e8f9f7 147 uint32_t RESERVED3[957];
<> 144:ef7eb2e8f9f7 148 __I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register
<> 144:ef7eb2e8f9f7 149 // [31:24] : FPGA build number
<> 144:ef7eb2e8f9f7 150 // [23:20] : V2M-MPS2 target board revision (A = 0, B = 1)
<> 144:ef7eb2e8f9f7 151 // [19:11] : Reserved
<> 144:ef7eb2e8f9f7 152 // [10] : if “1” SCC_SW register has been implemented
<> 144:ef7eb2e8f9f7 153 // [9] : if “1” SCC_LED register has been implemented
<> 144:ef7eb2e8f9f7 154 // [8] : if “1” DLL lock register has been implemented
<> 144:ef7eb2e8f9f7 155 // [7:0] : number of SCC configuration register
<> 144:ef7eb2e8f9f7 156 __I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image
<> 144:ef7eb2e8f9f7 157 // [31:24] : Implementer ID: 0x41 = ARM
<> 144:ef7eb2e8f9f7 158 // [23:20] : Application note IP variant number
<> 144:ef7eb2e8f9f7 159 // [19:16] : IP Architecture: 0x4 =AHB
<> 144:ef7eb2e8f9f7 160 // [15:4] : Primary part number: 386 = AN386
<> 144:ef7eb2e8f9f7 161 // [3:0] : Application note IP revision number
<> 144:ef7eb2e8f9f7 162 } MPS2_SCC_TypeDef;
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 /******************************************************************************/
<> 144:ef7eb2e8f9f7 166 /* SSP Peripheral declaration */
<> 144:ef7eb2e8f9f7 167 /******************************************************************************/
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
<> 144:ef7eb2e8f9f7 170 {
<> 144:ef7eb2e8f9f7 171 __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0
<> 144:ef7eb2e8f9f7 172 // [31:16] : Reserved
<> 144:ef7eb2e8f9f7 173 // [15:8] : Serial clock rate
<> 144:ef7eb2e8f9f7 174 // [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only
<> 144:ef7eb2e8f9f7 175 // [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only
<> 144:ef7eb2e8f9f7 176 // [5:4] : Frame format
<> 144:ef7eb2e8f9f7 177 // [3:0] : Data Size Select
<> 144:ef7eb2e8f9f7 178 __IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1
<> 144:ef7eb2e8f9f7 179 // [31:4] : Reserved
<> 144:ef7eb2e8f9f7 180 // [3] : Slave-mode output disable
<> 144:ef7eb2e8f9f7 181 // [2] : Master or slave mode select
<> 144:ef7eb2e8f9f7 182 // [1] : Synchronous serial port enable
<> 144:ef7eb2e8f9f7 183 // [0] : Loop back mode
<> 144:ef7eb2e8f9f7 184 __IO uint32_t DR; // Offset: 0x008 (R/W) Data register
<> 144:ef7eb2e8f9f7 185 // [31:16] : Reserved
<> 144:ef7eb2e8f9f7 186 // [15:0] : Transmit/Receive FIFO
<> 144:ef7eb2e8f9f7 187 __I uint32_t SR; // Offset: 0x00C (R/ ) Status register
<> 144:ef7eb2e8f9f7 188 // [31:5] : Reserved
<> 144:ef7eb2e8f9f7 189 // [4] : PrimeCell SSP busy flag
<> 144:ef7eb2e8f9f7 190 // [3] : Receive FIFO full
<> 144:ef7eb2e8f9f7 191 // [2] : Receive FIFO not empty
<> 144:ef7eb2e8f9f7 192 // [1] : Transmit FIFO not full
<> 144:ef7eb2e8f9f7 193 // [0] : Transmit FIFO empty
<> 144:ef7eb2e8f9f7 194 __IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register
<> 144:ef7eb2e8f9f7 195 // [31:8] : Reserved
<> 144:ef7eb2e8f9f7 196 // [8:0] : Clock prescale divisor
<> 144:ef7eb2e8f9f7 197 __IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register
<> 144:ef7eb2e8f9f7 198 // [31:4] : Reserved
<> 144:ef7eb2e8f9f7 199 // [3] : Transmit FIFO interrupt mask
<> 144:ef7eb2e8f9f7 200 // [2] : Receive FIFO interrupt mask
<> 144:ef7eb2e8f9f7 201 // [1] : Receive timeout interrupt mask
<> 144:ef7eb2e8f9f7 202 // [0] : Receive overrun interrupt mask
<> 144:ef7eb2e8f9f7 203 __I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register
<> 144:ef7eb2e8f9f7 204 // [31:4] : Reserved
<> 144:ef7eb2e8f9f7 205 // [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt
<> 144:ef7eb2e8f9f7 206 // [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt
<> 144:ef7eb2e8f9f7 207 // [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt
<> 144:ef7eb2e8f9f7 208 // [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt
<> 144:ef7eb2e8f9f7 209 __I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register
<> 144:ef7eb2e8f9f7 210 // [31:4] : Reserved
<> 144:ef7eb2e8f9f7 211 // [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt
<> 144:ef7eb2e8f9f7 212 // [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt
<> 144:ef7eb2e8f9f7 213 // [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt
<> 144:ef7eb2e8f9f7 214 // [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt
<> 144:ef7eb2e8f9f7 215 __O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register
<> 144:ef7eb2e8f9f7 216 // [31:2] : Reserved
<> 144:ef7eb2e8f9f7 217 // [1] : Clears the SSPRTINTR interrupt
<> 144:ef7eb2e8f9f7 218 // [0] : Clears the SSPRORINTR interrupt
<> 144:ef7eb2e8f9f7 219 __IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register
<> 144:ef7eb2e8f9f7 220 // [31:2] : Reserved
<> 144:ef7eb2e8f9f7 221 // [1] : Transmit DMA Enable
<> 144:ef7eb2e8f9f7 222 // [0] : Receive DMA Enable
<> 144:ef7eb2e8f9f7 223 } MPS2_SSP_TypeDef;
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 // SSP_CR0 Control register 0
<> 144:ef7eb2e8f9f7 227 #define SSP_CR0_DSS_Pos 0 // Data Size Select
<> 144:ef7eb2e8f9f7 228 #define SSP_CR0_DSS_Msk (0xF<<SSP_CR0_DSS_Pos)
<> 144:ef7eb2e8f9f7 229 #define SSP_CR0_FRF_Pos 4 // Frame Format Select
<> 144:ef7eb2e8f9f7 230 #define SSP_CR0_FRF_Msk (3UL<<SSP_CR0_FRM_Pos)
<> 144:ef7eb2e8f9f7 231 #define SSP_CR0_SPO_Pos 6 // SSPCLKOUT polarity
<> 144:ef7eb2e8f9f7 232 #define SSP_CR0_SPO_Msk (1UL<<SSP_CR0_SPO_Pos)
<> 144:ef7eb2e8f9f7 233 #define SSP_CR0_SPH_Pos 7 // SSPCLKOUT phase
<> 144:ef7eb2e8f9f7 234 #define SSP_CR0_SPH_Msk (1UL<<SSP_CR0_SPH_Pos)
<> 144:ef7eb2e8f9f7 235 #define SSP_CR0_SCR_Pos 8 // Serial Clock Rate (divide)
<> 144:ef7eb2e8f9f7 236 #define SSP_CR0_SCR_Msk (0xFF<<SSP_CR0_SCR_Pos)
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 #define SSP_CR0_SCR_DFLT 0x0300 // Serial Clock Rate (divide), default set at 3
<> 144:ef7eb2e8f9f7 239 #define SSP_CR0_FRF_MOT 0x0000 // Frame format, Motorola
<> 144:ef7eb2e8f9f7 240 #define SSP_CR0_DSS_8 0x0007 // Data packet size, 8bits
<> 144:ef7eb2e8f9f7 241 #define SSP_CR0_DSS_16 0x000F // Data packet size, 16bits
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 // SSP_CR1 Control register 1
<> 144:ef7eb2e8f9f7 244 #define SSP_CR1_LBM_Pos 0 // Loop Back Mode
<> 144:ef7eb2e8f9f7 245 #define SSP_CR1_LBM_Msk (1UL<<SSP_CR1_LBM_Pos)
<> 144:ef7eb2e8f9f7 246 #define SSP_CR1_SSE_Pos 1 // Serial port enable
<> 144:ef7eb2e8f9f7 247 #define SSP_CR1_SSE_Msk (1UL<<SSP_CR1_SSE_Pos)
<> 144:ef7eb2e8f9f7 248 #define SSP_CR1_MS_Pos 2 // Master or Slave mode
<> 144:ef7eb2e8f9f7 249 #define SSP_CR1_MS_Msk (1UL<<SSP_CR1_MS_Pos)
<> 144:ef7eb2e8f9f7 250 #define SSP_CR1_SOD_Pos 3 // Slave Output mode Disable
<> 144:ef7eb2e8f9f7 251 #define SSP_CR1_SOD_Msk (1UL<<SSP_CR1_SOD_Pos)
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 // SSP_SR Status register
<> 144:ef7eb2e8f9f7 254 #define SSP_SR_TFE_Pos 0 // Transmit FIFO empty
<> 144:ef7eb2e8f9f7 255 #define SSP_SR_TFE_Msk (1UL<<SSP_SR_TFE_Pos)
<> 144:ef7eb2e8f9f7 256 #define SSP_SR_TNF_Pos 1 // Transmit FIFO not full
<> 144:ef7eb2e8f9f7 257 #define SSP_SR_TNF_Msk (1UL<<SSP_SR_TNF_Pos)
<> 144:ef7eb2e8f9f7 258 #define SSP_SR_RNE_Pos 2 // Receive FIFO not empty
<> 144:ef7eb2e8f9f7 259 #define SSP_SR_RNE_Msk (1UL<<SSP_SR_RNE_Pos)
<> 144:ef7eb2e8f9f7 260 #define SSP_SR_RFF_Pos 3 // Receive FIFO full
<> 144:ef7eb2e8f9f7 261 #define SSP_SR_RFF_Msk (1UL<<SSP_SR_RFF_Pos)
<> 144:ef7eb2e8f9f7 262 #define SSP_SR_BSY_Pos 4 // Busy
<> 144:ef7eb2e8f9f7 263 #define SSP_SR_BSY_Msk (1UL<<SSP_SR_BSY_Pos)
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 // SSP_CPSR Clock prescale register
<> 144:ef7eb2e8f9f7 266 #define SSP_CPSR_CPD_Pos 0 // Clock prescale divisor
<> 144:ef7eb2e8f9f7 267 #define SSP_CPSR_CPD_Msk (0xFF<<SSP_CPSR_CDP_Pos)
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269 #define SSP_CPSR_DFLT 0x0008 // Clock prescale (use with SCR), default set at 8
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 // SSPIMSC Interrupt mask set and clear register
<> 144:ef7eb2e8f9f7 272 #define SSP_IMSC_RORIM_Pos 0 // Receive overrun not Masked
<> 144:ef7eb2e8f9f7 273 #define SSP_IMSC_RORIM_Msk (1UL<<SSP_IMSC_RORIM_Pos)
<> 144:ef7eb2e8f9f7 274 #define SSP_IMSC_RTIM_Pos 1 // Receive timeout not Masked
<> 144:ef7eb2e8f9f7 275 #define SSP_IMSC_RTIM_Msk (1UL<<SSP_IMSC_RTIM_Pos)
<> 144:ef7eb2e8f9f7 276 #define SSP_IMSC_RXIM_Pos 2 // Receive FIFO not Masked
<> 144:ef7eb2e8f9f7 277 #define SSP_IMSC_RXIM_Msk (1UL<<SSP_IMSC_RXIM_Pos)
<> 144:ef7eb2e8f9f7 278 #define SSP_IMSC_TXIM_Pos 3 // Transmit FIFO not Masked
<> 144:ef7eb2e8f9f7 279 #define SSP_IMSC_TXIM_Msk (1UL<<SSP_IMSC_TXIM_Pos)
<> 144:ef7eb2e8f9f7 280
<> 144:ef7eb2e8f9f7 281 // SSPRIS Raw interrupt status register
<> 144:ef7eb2e8f9f7 282 #define SSP_RIS_RORRIS_Pos 0 // Raw Overrun interrupt flag
<> 144:ef7eb2e8f9f7 283 #define SSP_RIS_RORRIS_Msk (1UL<<SSP_RIS_RORRIS_Pos)
<> 144:ef7eb2e8f9f7 284 #define SSP_RIS_RTRIS_Pos 1 // Raw Timemout interrupt flag
<> 144:ef7eb2e8f9f7 285 #define SSP_RIS_RTRIS_Msk (1UL<<SSP_RIS_RTRIS_Pos)
<> 144:ef7eb2e8f9f7 286 #define SSP_RIS_RXRIS_Pos 2 // Raw Receive interrupt flag
<> 144:ef7eb2e8f9f7 287 #define SSP_RIS_RXRIS_Msk (1UL<<SSP_RIS_RXRIS_Pos)
<> 144:ef7eb2e8f9f7 288 #define SSP_RIS_TXRIS_Pos 3 // Raw Transmit interrupt flag
<> 144:ef7eb2e8f9f7 289 #define SSP_RIS_TXRIS_Msk (1UL<<SSP_RIS_TXRIS_Pos)
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 // SSPMIS Masked interrupt status register
<> 144:ef7eb2e8f9f7 292 #define SSP_MIS_RORMIS_Pos 0 // Masked Overrun interrupt flag
<> 144:ef7eb2e8f9f7 293 #define SSP_MIS_RORMIS_Msk (1UL<<SSP_MIS_RORMIS_Pos)
<> 144:ef7eb2e8f9f7 294 #define SSP_MIS_RTMIS_Pos 1 // Masked Timemout interrupt flag
<> 144:ef7eb2e8f9f7 295 #define SSP_MIS_RTMIS_Msk (1UL<<SSP_MIS_RTMIS_Pos)
<> 144:ef7eb2e8f9f7 296 #define SSP_MIS_RXMIS_Pos 2 // Masked Receive interrupt flag
<> 144:ef7eb2e8f9f7 297 #define SSP_MIS_RXMIS_Msk (1UL<<SSP_MIS_RXMIS_Pos)
<> 144:ef7eb2e8f9f7 298 #define SSP_MIS_TXMIS_Pos 3 // Masked Transmit interrupt flag
<> 144:ef7eb2e8f9f7 299 #define SSP_MIS_TXMIS_Msk (1UL<<SSP_MIS_TXMIS_Pos)
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 // SSPICR Interrupt clear register
<> 144:ef7eb2e8f9f7 302 #define SSP_ICR_RORIC_Pos 0 // Clears Overrun interrupt flag
<> 144:ef7eb2e8f9f7 303 #define SSP_ICR_RORIC_Msk (1UL<<SSP_ICR_RORIC_Pos)
<> 144:ef7eb2e8f9f7 304 #define SSP_ICR_RTIC_Pos 1 // Clears Timemout interrupt flag
<> 144:ef7eb2e8f9f7 305 #define SSP_ICR_RTIC_Msk (1UL<<SSP_ICR_RTIC_Pos)
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 // SSPDMACR DMA control register
<> 144:ef7eb2e8f9f7 308 #define SSP_DMACR_RXDMAE_Pos 0 // Enable Receive FIFO DMA
<> 144:ef7eb2e8f9f7 309 #define SSP_DMACR_RXDMAE_Msk (1UL<<SSP_DMACR_RXDMAE_Pos)
<> 144:ef7eb2e8f9f7 310 #define SSP_DMACR_TXDMAE_Pos 1 // Enable Transmit FIFO DMA
<> 144:ef7eb2e8f9f7 311 #define SSP_DMACR_TXDMAE_Msk (1UL<<SSP_DMACR_TXDMAE_Pos)
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 /******************************************************************************/
<> 144:ef7eb2e8f9f7 314 /* Audio and Touch Screen (I2C) Peripheral declaration */
<> 144:ef7eb2e8f9f7 315 /******************************************************************************/
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 typedef struct
<> 144:ef7eb2e8f9f7 318 {
<> 144:ef7eb2e8f9f7 319 union {
<> 144:ef7eb2e8f9f7 320 __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W)
<> 144:ef7eb2e8f9f7 321 __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ )
<> 144:ef7eb2e8f9f7 322 };
<> 144:ef7eb2e8f9f7 323 __O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W)
<> 144:ef7eb2e8f9f7 324 } MPS2_I2C_TypeDef;
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 #define SDA 1 << 1
<> 144:ef7eb2e8f9f7 327 #define SCL 1 << 0
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 /******************************************************************************/
<> 144:ef7eb2e8f9f7 331 /* Audio I2S Peripheral declaration */
<> 144:ef7eb2e8f9f7 332 /******************************************************************************/
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 typedef struct
<> 144:ef7eb2e8f9f7 335 {
<> 144:ef7eb2e8f9f7 336 /*!< Offset: 0x000 CONTROL Register (R/W) */
<> 144:ef7eb2e8f9f7 337 __IO uint32_t CONTROL; // <h> CONTROL </h>
<> 144:ef7eb2e8f9f7 338 // <o.0> TX Enable
<> 144:ef7eb2e8f9f7 339 // <0=> TX disabled
<> 144:ef7eb2e8f9f7 340 // <1=> TX enabled
<> 144:ef7eb2e8f9f7 341 // <o.1> TX IRQ Enable
<> 144:ef7eb2e8f9f7 342 // <0=> TX IRQ disabled
<> 144:ef7eb2e8f9f7 343 // <1=> TX IRQ enabled
<> 144:ef7eb2e8f9f7 344 // <o.2> RX Enable
<> 144:ef7eb2e8f9f7 345 // <0=> RX disabled
<> 144:ef7eb2e8f9f7 346 // <1=> RX enabled
<> 144:ef7eb2e8f9f7 347 // <o.3> RX IRQ Enable
<> 144:ef7eb2e8f9f7 348 // <0=> RX IRQ disabled
<> 144:ef7eb2e8f9f7 349 // <1=> RX IRQ enabled
<> 144:ef7eb2e8f9f7 350 // <o.10..8> TX Buffer Water Level
<> 144:ef7eb2e8f9f7 351 // <0=> / IRQ triggers when any space available
<> 144:ef7eb2e8f9f7 352 // <1=> / IRQ triggers when more than 1 space available
<> 144:ef7eb2e8f9f7 353 // <2=> / IRQ triggers when more than 2 space available
<> 144:ef7eb2e8f9f7 354 // <3=> / IRQ triggers when more than 3 space available
<> 144:ef7eb2e8f9f7 355 // <4=> Undefined!
<> 144:ef7eb2e8f9f7 356 // <5=> Undefined!
<> 144:ef7eb2e8f9f7 357 // <6=> Undefined!
<> 144:ef7eb2e8f9f7 358 // <7=> Undefined!
<> 144:ef7eb2e8f9f7 359 // <o.14..12> RX Buffer Water Level
<> 144:ef7eb2e8f9f7 360 // <0=> Undefined!
<> 144:ef7eb2e8f9f7 361 // <1=> / IRQ triggers when less than 1 space available
<> 144:ef7eb2e8f9f7 362 // <2=> / IRQ triggers when less than 2 space available
<> 144:ef7eb2e8f9f7 363 // <3=> / IRQ triggers when less than 3 space available
<> 144:ef7eb2e8f9f7 364 // <4=> / IRQ triggers when less than 4 space available
<> 144:ef7eb2e8f9f7 365 // <5=> Undefined!
<> 144:ef7eb2e8f9f7 366 // <6=> Undefined!
<> 144:ef7eb2e8f9f7 367 // <7=> Undefined!
<> 144:ef7eb2e8f9f7 368 // <o.16> FIFO reset
<> 144:ef7eb2e8f9f7 369 // <0=> Normal operation
<> 144:ef7eb2e8f9f7 370 // <1=> FIFO reset
<> 144:ef7eb2e8f9f7 371 // <o.17> Audio Codec reset
<> 144:ef7eb2e8f9f7 372 // <0=> Normal operation
<> 144:ef7eb2e8f9f7 373 // <1=> Assert audio Codec reset
<> 144:ef7eb2e8f9f7 374 /*!< Offset: 0x004 STATUS Register (R/ ) */
<> 144:ef7eb2e8f9f7 375 __I uint32_t STATUS; // <h> STATUS </h>
<> 144:ef7eb2e8f9f7 376 // <o.0> TX Buffer alert
<> 144:ef7eb2e8f9f7 377 // <0=> TX buffer don't need service yet
<> 144:ef7eb2e8f9f7 378 // <1=> TX buffer need service
<> 144:ef7eb2e8f9f7 379 // <o.1> RX Buffer alert
<> 144:ef7eb2e8f9f7 380 // <0=> RX buffer don't need service yet
<> 144:ef7eb2e8f9f7 381 // <1=> RX buffer need service
<> 144:ef7eb2e8f9f7 382 // <o.2> TX Buffer Empty
<> 144:ef7eb2e8f9f7 383 // <0=> TX buffer have data
<> 144:ef7eb2e8f9f7 384 // <1=> TX buffer empty
<> 144:ef7eb2e8f9f7 385 // <o.3> TX Buffer Full
<> 144:ef7eb2e8f9f7 386 // <0=> TX buffer not full
<> 144:ef7eb2e8f9f7 387 // <1=> TX buffer full
<> 144:ef7eb2e8f9f7 388 // <o.4> RX Buffer Empty
<> 144:ef7eb2e8f9f7 389 // <0=> RX buffer have data
<> 144:ef7eb2e8f9f7 390 // <1=> RX buffer empty
<> 144:ef7eb2e8f9f7 391 // <o.5> RX Buffer Full
<> 144:ef7eb2e8f9f7 392 // <0=> RX buffer not full
<> 144:ef7eb2e8f9f7 393 // <1=> RX buffer full
<> 144:ef7eb2e8f9f7 394 union {
<> 144:ef7eb2e8f9f7 395 /*!< Offset: 0x008 Error Status Register (R/ ) */
<> 144:ef7eb2e8f9f7 396 __I uint32_t ERROR; // <h> ERROR </h>
<> 144:ef7eb2e8f9f7 397 // <o.0> TX error
<> 144:ef7eb2e8f9f7 398 // <0=> Okay
<> 144:ef7eb2e8f9f7 399 // <1=> TX overrun/underrun
<> 144:ef7eb2e8f9f7 400 // <o.1> RX error
<> 144:ef7eb2e8f9f7 401 // <0=> Okay
<> 144:ef7eb2e8f9f7 402 // <1=> RX overrun/underrun
<> 144:ef7eb2e8f9f7 403 /*!< Offset: 0x008 Error Clear Register ( /W) */
<> 144:ef7eb2e8f9f7 404 __O uint32_t ERRORCLR; // <h> ERRORCLR </h>
<> 144:ef7eb2e8f9f7 405 // <o.0> TX error
<> 144:ef7eb2e8f9f7 406 // <0=> Okay
<> 144:ef7eb2e8f9f7 407 // <1=> Clear TX error
<> 144:ef7eb2e8f9f7 408 // <o.1> RX error
<> 144:ef7eb2e8f9f7 409 // <0=> Okay
<> 144:ef7eb2e8f9f7 410 // <1=> Clear RX error
<> 144:ef7eb2e8f9f7 411 };
<> 144:ef7eb2e8f9f7 412 /*!< Offset: 0x00C Divide ratio Register (R/W) */
<> 144:ef7eb2e8f9f7 413 __IO uint32_t DIVIDE; // <h> Divide ratio for Left/Right clock </h>
<> 144:ef7eb2e8f9f7 414 // <o.9..0> TX error (default 0x80)
<> 144:ef7eb2e8f9f7 415 /*!< Offset: 0x010 Transmit Buffer ( /W) */
<> 144:ef7eb2e8f9f7 416 __O uint32_t TXBUF; // <h> Transmit buffer </h>
<> 144:ef7eb2e8f9f7 417 // <o.15..0> Right channel
<> 144:ef7eb2e8f9f7 418 // <o.31..16> Left channel
<> 144:ef7eb2e8f9f7 419 /*!< Offset: 0x014 Receive Buffer (R/ ) */
<> 144:ef7eb2e8f9f7 420 __I uint32_t RXBUF; // <h> Receive buffer </h>
<> 144:ef7eb2e8f9f7 421 // <o.15..0> Right channel
<> 144:ef7eb2e8f9f7 422 // <o.31..16> Left channel
<> 144:ef7eb2e8f9f7 423 uint32_t RESERVED1[186];
<> 144:ef7eb2e8f9f7 424 __IO uint32_t ITCR; // <h> Integration Test Control Register </h>
<> 144:ef7eb2e8f9f7 425 // <o.0> ITEN
<> 144:ef7eb2e8f9f7 426 // <0=> Normal operation
<> 144:ef7eb2e8f9f7 427 // <1=> Integration Test mode enable
<> 144:ef7eb2e8f9f7 428 __O uint32_t ITIP1; // <h> Integration Test Input Register 1</h>
<> 144:ef7eb2e8f9f7 429 // <o.0> SDIN
<> 144:ef7eb2e8f9f7 430 __O uint32_t ITOP1; // <h> Integration Test Output Register 1</h>
<> 144:ef7eb2e8f9f7 431 // <o.0> SDOUT
<> 144:ef7eb2e8f9f7 432 // <o.1> SCLK
<> 144:ef7eb2e8f9f7 433 // <o.2> LRCK
<> 144:ef7eb2e8f9f7 434 // <o.3> IRQOUT
<> 144:ef7eb2e8f9f7 435 } MPS2_I2S_TypeDef;
<> 144:ef7eb2e8f9f7 436
<> 144:ef7eb2e8f9f7 437 #define I2S_CONTROL_TXEN_Pos 0
<> 144:ef7eb2e8f9f7 438 #define I2S_CONTROL_TXEN_Msk (1UL<<I2S_CONTROL_TXEN_Pos)
<> 144:ef7eb2e8f9f7 439
<> 144:ef7eb2e8f9f7 440 #define I2S_CONTROL_TXIRQEN_Pos 1
<> 144:ef7eb2e8f9f7 441 #define I2S_CONTROL_TXIRQEN_Msk (1UL<<I2S_CONTROL_TXIRQEN_Pos)
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443 #define I2S_CONTROL_RXEN_Pos 2
<> 144:ef7eb2e8f9f7 444 #define I2S_CONTROL_RXEN_Msk (1UL<<I2S_CONTROL_RXEN_Pos)
<> 144:ef7eb2e8f9f7 445
<> 144:ef7eb2e8f9f7 446 #define I2S_CONTROL_RXIRQEN_Pos 3
<> 144:ef7eb2e8f9f7 447 #define I2S_CONTROL_RXIRQEN_Msk (1UL<<I2S_CONTROL_RXIRQEN_Pos)
<> 144:ef7eb2e8f9f7 448
<> 144:ef7eb2e8f9f7 449 #define I2S_CONTROL_TXWLVL_Pos 8
<> 144:ef7eb2e8f9f7 450 #define I2S_CONTROL_TXWLVL_Msk (7UL<<I2S_CONTROL_TXWLVL_Pos)
<> 144:ef7eb2e8f9f7 451
<> 144:ef7eb2e8f9f7 452 #define I2S_CONTROL_RXWLVL_Pos 12
<> 144:ef7eb2e8f9f7 453 #define I2S_CONTROL_RXWLVL_Msk (7UL<<I2S_CONTROL_RXWLVL_Pos)
<> 144:ef7eb2e8f9f7 454 /* FIFO reset*/
<> 144:ef7eb2e8f9f7 455 #define I2S_CONTROL_FIFORST_Pos 16
<> 144:ef7eb2e8f9f7 456 #define I2S_CONTROL_FIFORST_Msk (1UL<<I2S_CONTROL_FIFORST_Pos)
<> 144:ef7eb2e8f9f7 457 /* Codec reset*/
<> 144:ef7eb2e8f9f7 458 #define I2S_CONTROL_CODECRST_Pos 17
<> 144:ef7eb2e8f9f7 459 #define I2S_CONTROL_CODECRST_Msk (1UL<<I2S_CONTROL_CODECRST_Pos)
<> 144:ef7eb2e8f9f7 460
<> 144:ef7eb2e8f9f7 461 #define I2S_STATUS_TXIRQ_Pos 0
<> 144:ef7eb2e8f9f7 462 #define I2S_STATUS_TXIRQ_Msk (1UL<<I2S_STATUS_TXIRQ_Pos)
<> 144:ef7eb2e8f9f7 463
<> 144:ef7eb2e8f9f7 464 #define I2S_STATUS_RXIRQ_Pos 1
<> 144:ef7eb2e8f9f7 465 #define I2S_STATUS_RXIRQ_Msk (1UL<<I2S_STATUS_RXIRQ_Pos)
<> 144:ef7eb2e8f9f7 466
<> 144:ef7eb2e8f9f7 467 #define I2S_STATUS_TXEmpty_Pos 2
<> 144:ef7eb2e8f9f7 468 #define I2S_STATUS_TXEmpty_Msk (1UL<<I2S_STATUS_TXEmpty_Pos)
<> 144:ef7eb2e8f9f7 469
<> 144:ef7eb2e8f9f7 470 #define I2S_STATUS_TXFull_Pos 3
<> 144:ef7eb2e8f9f7 471 #define I2S_STATUS_TXFull_Msk (1UL<<I2S_STATUS_TXFull_Pos)
<> 144:ef7eb2e8f9f7 472
<> 144:ef7eb2e8f9f7 473 #define I2S_STATUS_RXEmpty_Pos 4
<> 144:ef7eb2e8f9f7 474 #define I2S_STATUS_RXEmpty_Msk (1UL<<I2S_STATUS_RXEmpty_Pos)
<> 144:ef7eb2e8f9f7 475
<> 144:ef7eb2e8f9f7 476 #define I2S_STATUS_RXFull_Pos 5
<> 144:ef7eb2e8f9f7 477 #define I2S_STATUS_RXFull_Msk (1UL<<I2S_STATUS_RXFull_Pos)
<> 144:ef7eb2e8f9f7 478
<> 144:ef7eb2e8f9f7 479 #define I2S_ERROR_TXERR_Pos 0
<> 144:ef7eb2e8f9f7 480 #define I2S_ERROR_TXERR_Msk (1UL<<I2S_ERROR_TXERR_Pos)
<> 144:ef7eb2e8f9f7 481
<> 144:ef7eb2e8f9f7 482 #define I2S_ERROR_RXERR_Pos 1
<> 144:ef7eb2e8f9f7 483 #define I2S_ERROR_RXERR_Msk (1UL<<I2S_ERROR_RXERR_Pos)
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 /******************************************************************************/
<> 144:ef7eb2e8f9f7 486 /* SMSC9220 Register Definitions */
<> 144:ef7eb2e8f9f7 487 /******************************************************************************/
<> 144:ef7eb2e8f9f7 488
<> 144:ef7eb2e8f9f7 489 typedef struct // SMSC LAN9220
<> 144:ef7eb2e8f9f7 490 {
<> 144:ef7eb2e8f9f7 491 __I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0)
<> 144:ef7eb2e8f9f7 492 uint32_t RESERVED1[0x7];
<> 144:ef7eb2e8f9f7 493 __O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20)
<> 144:ef7eb2e8f9f7 494 uint32_t RESERVED2[0x7];
<> 144:ef7eb2e8f9f7 495
<> 144:ef7eb2e8f9f7 496 __I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40)
<> 144:ef7eb2e8f9f7 497 __I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44)
<> 144:ef7eb2e8f9f7 498 __I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48)
<> 144:ef7eb2e8f9f7 499 __I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C)
<> 144:ef7eb2e8f9f7 500
<> 144:ef7eb2e8f9f7 501 __I uint32_t ID_REV; // Chip ID and Revision (offset 0x50)
<> 144:ef7eb2e8f9f7 502 __IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54)
<> 144:ef7eb2e8f9f7 503 __IO uint32_t INT_STS; // Interrupt Status (offset 0x58)
<> 144:ef7eb2e8f9f7 504 __IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C)
<> 144:ef7eb2e8f9f7 505 uint32_t RESERVED3; // Reserved for future use (offset 0x60)
<> 144:ef7eb2e8f9f7 506 __I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64)
<> 144:ef7eb2e8f9f7 507 __IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68)
<> 144:ef7eb2e8f9f7 508 __IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C)
<> 144:ef7eb2e8f9f7 509 __IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70)
<> 144:ef7eb2e8f9f7 510 __IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74)
<> 144:ef7eb2e8f9f7 511 __IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78)
<> 144:ef7eb2e8f9f7 512 __I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C)
<> 144:ef7eb2e8f9f7 513 __I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80)
<> 144:ef7eb2e8f9f7 514 __IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84)
<> 144:ef7eb2e8f9f7 515 __IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88)
<> 144:ef7eb2e8f9f7 516 __IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C)
<> 144:ef7eb2e8f9f7 517 __I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90)
<> 144:ef7eb2e8f9f7 518 uint32_t RESERVED4; // Reserved for future use (offset 0x94)
<> 144:ef7eb2e8f9f7 519 __IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98)
<> 144:ef7eb2e8f9f7 520 __I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C)
<> 144:ef7eb2e8f9f7 521 __I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0)
<> 144:ef7eb2e8f9f7 522 __IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4)
<> 144:ef7eb2e8f9f7 523 __IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8)
<> 144:ef7eb2e8f9f7 524 __IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC)
<> 144:ef7eb2e8f9f7 525 __IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0)
<> 144:ef7eb2e8f9f7 526 __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4)
<> 144:ef7eb2e8f9f7 527
<> 144:ef7eb2e8f9f7 528 } SMSC9220_TypeDef;
<> 144:ef7eb2e8f9f7 529
<> 144:ef7eb2e8f9f7 530 // SMSC9220 MAC Registers Indices
<> 144:ef7eb2e8f9f7 531 #define SMSC9220_MAC_CR 0x1
<> 144:ef7eb2e8f9f7 532 #define SMSC9220_MAC_ADDRH 0x2
<> 144:ef7eb2e8f9f7 533 #define SMSC9220_MAC_ADDRL 0x3
<> 144:ef7eb2e8f9f7 534 #define SMSC9220_MAC_HASHH 0x4
<> 144:ef7eb2e8f9f7 535 #define SMSC9220_MAC_HASHL 0x5
<> 144:ef7eb2e8f9f7 536 #define SMSC9220_MAC_MII_ACC 0x6
<> 144:ef7eb2e8f9f7 537 #define SMSC9220_MAC_MII_DATA 0x7
<> 144:ef7eb2e8f9f7 538 #define SMSC9220_MAC_FLOW 0x8
<> 144:ef7eb2e8f9f7 539 #define SMSC9220_MAC_VLAN1 0x9
<> 144:ef7eb2e8f9f7 540 #define SMSC9220_MAC_VLAN2 0xA
<> 144:ef7eb2e8f9f7 541 #define SMSC9220_MAC_WUFF 0xB
<> 144:ef7eb2e8f9f7 542 #define SMSC9220_MAC_WUCSR 0xC
<> 144:ef7eb2e8f9f7 543
<> 144:ef7eb2e8f9f7 544 // SMSC9220 PHY Registers Indices
<> 144:ef7eb2e8f9f7 545 #define SMSC9220_PHY_BCONTROL 0x0
<> 144:ef7eb2e8f9f7 546 #define SMSC9220_PHY_BSTATUS 0x1
<> 144:ef7eb2e8f9f7 547 #define SMSC9220_PHY_ID1 0x2
<> 144:ef7eb2e8f9f7 548 #define SMSC9220_PHY_ID2 0x3
<> 144:ef7eb2e8f9f7 549 #define SMSC9220_PHY_ANEG_ADV 0x4
<> 144:ef7eb2e8f9f7 550 #define SMSC9220_PHY_ANEG_LPA 0x5
<> 144:ef7eb2e8f9f7 551 #define SMSC9220_PHY_ANEG_EXP 0x6
<> 144:ef7eb2e8f9f7 552 #define SMSC9220_PHY_MCONTROL 0x17
<> 144:ef7eb2e8f9f7 553 #define SMSC9220_PHY_MSTATUS 0x18
<> 144:ef7eb2e8f9f7 554 #define SMSC9220_PHY_CSINDICATE 0x27
<> 144:ef7eb2e8f9f7 555 #define SMSC9220_PHY_INTSRC 0x29
<> 144:ef7eb2e8f9f7 556 #define SMSC9220_PHY_INTMASK 0x30
<> 144:ef7eb2e8f9f7 557 #define SMSC9220_PHY_CS 0x31
<> 144:ef7eb2e8f9f7 558
<> 144:ef7eb2e8f9f7 559 /******************************************************************************/
<> 144:ef7eb2e8f9f7 560 /* Peripheral memory map */
<> 144:ef7eb2e8f9f7 561 /******************************************************************************/
<> 144:ef7eb2e8f9f7 562
<> 144:ef7eb2e8f9f7 563 #define MPS2_SSP1_BASE (0x40020000ul) /* User SSP Base Address */
<> 144:ef7eb2e8f9f7 564 #define MPS2_SSP0_BASE (0x40021000ul) /* CLCD SSP Base Address */
<> 144:ef7eb2e8f9f7 565 #define MPS2_TSC_I2C_BASE (0x40022000ul) /* Touch Screen I2C Base Address */
<> 144:ef7eb2e8f9f7 566 #define MPS2_AAIC_I2C_BASE (0x40023000ul) /* Audio Interface I2C Base Address */
<> 144:ef7eb2e8f9f7 567 #define MPS2_AAIC_I2S_BASE (0x40024000ul) /* Audio Interface I2S Base Address */
<> 144:ef7eb2e8f9f7 568 #define MPS2_SSP2_BASE (0x40025000ul) /* adc SSP Base Address */
<> 144:ef7eb2e8f9f7 569 #define MPS2_SSP3_BASE (0x40026000ul) /* Shield 0 SSP Base Address */
<> 144:ef7eb2e8f9f7 570 #define MPS2_SSP4_BASE (0x40027000ul) /* Shield 1 SSP Base Address */
<> 144:ef7eb2e8f9f7 571 #define MPS2_FPGAIO_BASE (0x40028000ul) /* FPGAIO Base Address */
<> 144:ef7eb2e8f9f7 572 #define MPS2_SHIELD0_I2C_BASE (0x40029000ul) /* Shield 0 I2C Base Address */
<> 144:ef7eb2e8f9f7 573 #define MPS2_SHIELD1_I2C_BASE (0x4002A000ul) /* Shield 1 I2C Base Address */
<> 144:ef7eb2e8f9f7 574 #define MPS2_SCC_BASE (0x4002F000ul) /* SCC Base Address */
<> 144:ef7eb2e8f9f7 575
<> 144:ef7eb2e8f9f7 576 #ifdef CORTEX_M7
<> 144:ef7eb2e8f9f7 577 #define SMSC9220_BASE (0xA0000000ul) /* Ethernet SMSC9220 Base Address */
<> 144:ef7eb2e8f9f7 578 #else
<> 144:ef7eb2e8f9f7 579 #define SMSC9220_BASE (0x40200000ul) /* Ethernet SMSC9220 Base Address */
<> 144:ef7eb2e8f9f7 580 #endif
<> 144:ef7eb2e8f9f7 581
<> 144:ef7eb2e8f9f7 582 #define MPS2_VGA_TEXT_BUFFER (0x41000000ul) /* VGA Text Buffer Address */
<> 144:ef7eb2e8f9f7 583 #define MPS2_VGA_BUFFER (0x41100000ul) /* VGA Buffer Base Address */
<> 144:ef7eb2e8f9f7 584
<> 144:ef7eb2e8f9f7 585 /******************************************************************************/
<> 144:ef7eb2e8f9f7 586 /* Peripheral declaration */
<> 144:ef7eb2e8f9f7 587 /******************************************************************************/
<> 144:ef7eb2e8f9f7 588
<> 144:ef7eb2e8f9f7 589 #define SMSC9220 ((SMSC9220_TypeDef *) SMSC9220_BASE )
<> 144:ef7eb2e8f9f7 590 #define MPS2_TS_I2C ((MPS2_I2C_TypeDef *) MPS2_TSC_I2C_BASE )
<> 144:ef7eb2e8f9f7 591 #define MPS2_AAIC_I2C ((MPS2_I2C_TypeDef *) MPS2_AAIC_I2C_BASE )
<> 144:ef7eb2e8f9f7 592 #define MPS2_SHIELD0_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD0_I2C_BASE )
<> 144:ef7eb2e8f9f7 593 #define MPS2_SHIELD1_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD1_I2C_BASE )
<> 144:ef7eb2e8f9f7 594 #define MPS2_AAIC_I2S ((MPS2_I2S_TypeDef *) MPS2_AAIC_I2S_BASE )
<> 144:ef7eb2e8f9f7 595 #define MPS2_FPGAIO ((MPS2_FPGAIO_TypeDef *) MPS2_FPGAIO_BASE )
<> 144:ef7eb2e8f9f7 596 #define MPS2_SCC ((MPS2_SCC_TypeDef *) MPS2_SCC_BASE )
<> 144:ef7eb2e8f9f7 597 #define MPS2_SSP0 ((MPS2_SSP_TypeDef *) MPS2_SSP0_BASE )
<> 144:ef7eb2e8f9f7 598 #define MPS2_SSP1 ((MPS2_SSP_TypeDef *) MPS2_SSP1_BASE )
<> 144:ef7eb2e8f9f7 599 #define MPS2_SSP2 ((MPS2_SSP_TypeDef *) MPS2_SSP2_BASE )
<> 144:ef7eb2e8f9f7 600 #define MPS2_SSP3 ((MPS2_SSP_TypeDef *) MPS2_SSP3_BASE )
<> 144:ef7eb2e8f9f7 601 #define MPS2_SSP4 ((MPS2_SSP_TypeDef *) MPS2_SSP4_BASE )
<> 144:ef7eb2e8f9f7 602
<> 144:ef7eb2e8f9f7 603 /******************************************************************************/
<> 144:ef7eb2e8f9f7 604 /* General Function Definitions */
<> 144:ef7eb2e8f9f7 605 /******************************************************************************/
<> 144:ef7eb2e8f9f7 606
<> 144:ef7eb2e8f9f7 607
<> 144:ef7eb2e8f9f7 608 /******************************************************************************/
<> 144:ef7eb2e8f9f7 609 /* General MACRO Definitions */
<> 144:ef7eb2e8f9f7 610 /******************************************************************************/
<> 144:ef7eb2e8f9f7 611
<> 144:ef7eb2e8f9f7 612
<> 144:ef7eb2e8f9f7 613
<> 144:ef7eb2e8f9f7 614 #endif /* __SMM_MPS2_H */