Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/TOOLCHAIN_GCC_ARM/startup_BEETLE.S@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 * BEETLE CMSIS Library
<> 144:ef7eb2e8f9f7 3 */
<> 144:ef7eb2e8f9f7 4 /*
<> 144:ef7eb2e8f9f7 5 * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
<> 144:ef7eb2e8f9f7 6 *
<> 144:ef7eb2e8f9f7 7 * SPDX-License-Identifier: Apache-2.0
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * Licensed under the Apache License, Version 2.0 (the License); you may
<> 144:ef7eb2e8f9f7 10 * not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 11 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 16 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
<> 144:ef7eb2e8f9f7 17 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 18 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 19 * limitations under the License.
<> 144:ef7eb2e8f9f7 20 */
<> 144:ef7eb2e8f9f7 21 /*
<> 144:ef7eb2e8f9f7 22 * This file is derivative of CMSIS V5.00 startup_ARMCM3.S
<> 144:ef7eb2e8f9f7 23 */
<> 144:ef7eb2e8f9f7 24 .syntax unified
<> 144:ef7eb2e8f9f7 25 .arch armv7-m
<> 144:ef7eb2e8f9f7 26
<> 144:ef7eb2e8f9f7 27 /* Memory Model
<> 144:ef7eb2e8f9f7 28 The HEAP starts at the end of the DATA section and grows upward.
<> 144:ef7eb2e8f9f7 29
<> 144:ef7eb2e8f9f7 30 The STACK starts at the end of the RAM and grows downward.
<> 144:ef7eb2e8f9f7 31
<> 144:ef7eb2e8f9f7 32 The HEAP and stack STACK are only checked at compile time:
<> 144:ef7eb2e8f9f7 33 (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 This is just a check for the bare minimum for the Heap+Stack area before
<> 144:ef7eb2e8f9f7 36 aborting compilation, it is not the run time limit:
<> 144:ef7eb2e8f9f7 37 Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
<> 144:ef7eb2e8f9f7 38 */
<> 144:ef7eb2e8f9f7 39 .section .stack
<> 144:ef7eb2e8f9f7 40 .align 3
<> 144:ef7eb2e8f9f7 41 #ifdef __STACK_SIZE
<> 144:ef7eb2e8f9f7 42 .equ Stack_Size, __STACK_SIZE
<> 144:ef7eb2e8f9f7 43 #else
<> 144:ef7eb2e8f9f7 44 .equ Stack_Size, 0x400
<> 144:ef7eb2e8f9f7 45 #endif
<> 144:ef7eb2e8f9f7 46 .globl __StackTop
<> 144:ef7eb2e8f9f7 47 .globl __StackLimit
<> 144:ef7eb2e8f9f7 48 __StackLimit:
<> 144:ef7eb2e8f9f7 49 .space Stack_Size
<> 144:ef7eb2e8f9f7 50 .size __StackLimit, . - __StackLimit
<> 144:ef7eb2e8f9f7 51 __StackTop:
<> 144:ef7eb2e8f9f7 52 .size __StackTop, . - __StackTop
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 .section .heap
<> 144:ef7eb2e8f9f7 55 .align 3
<> 144:ef7eb2e8f9f7 56 #ifdef __HEAP_SIZE
<> 144:ef7eb2e8f9f7 57 .equ Heap_Size, __HEAP_SIZE
<> 144:ef7eb2e8f9f7 58 #else
<> 144:ef7eb2e8f9f7 59 .equ Heap_Size, 0xC00
<> 144:ef7eb2e8f9f7 60 #endif
<> 144:ef7eb2e8f9f7 61 .globl __HeapBase
<> 144:ef7eb2e8f9f7 62 .globl __HeapLimit
<> 144:ef7eb2e8f9f7 63 __HeapBase:
<> 144:ef7eb2e8f9f7 64 .space Heap_Size
<> 144:ef7eb2e8f9f7 65 .size __HeapBase, . - __HeapBase
<> 144:ef7eb2e8f9f7 66 __HeapLimit:
<> 144:ef7eb2e8f9f7 67 .size __HeapLimit, . - __HeapLimit
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 .section .vector_table,"a",%progbits
<> 144:ef7eb2e8f9f7 70 .align 2
<> 144:ef7eb2e8f9f7 71 .globl __isr_vector
<> 144:ef7eb2e8f9f7 72 __isr_vector:
<> 144:ef7eb2e8f9f7 73 .long __StackTop /* Top of Stack */
<> 144:ef7eb2e8f9f7 74 .long Reset_Handler /* Reset Handler */
<> 144:ef7eb2e8f9f7 75 .long NMI_Handler /* NMI Handler */
<> 144:ef7eb2e8f9f7 76 .long HardFault_Handler /* Hard Fault Handler */
<> 144:ef7eb2e8f9f7 77 .long MemManage_Handler /* MPU Fault Handler */
<> 144:ef7eb2e8f9f7 78 .long BusFault_Handler /* Bus Fault Handler */
<> 144:ef7eb2e8f9f7 79 .long UsageFault_Handler /* Usage Fault Handler */
<> 144:ef7eb2e8f9f7 80 .long 0 /* Reserved */
<> 144:ef7eb2e8f9f7 81 .long 0 /* Reserved */
<> 144:ef7eb2e8f9f7 82 .long 0 /* Reserved */
<> 144:ef7eb2e8f9f7 83 .long 0 /* Reserved */
<> 144:ef7eb2e8f9f7 84 .long SVC_Handler /* SVCall Handler */
<> 144:ef7eb2e8f9f7 85 .long DebugMon_Handler /* Debug Monitor Handler */
<> 144:ef7eb2e8f9f7 86 .long 0 /* Reserved */
<> 144:ef7eb2e8f9f7 87 .long PendSV_Handler /* PendSV Handler */
<> 144:ef7eb2e8f9f7 88 .long SysTick_Handler /* SysTick Handler */
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 /* External interrupts */
<> 144:ef7eb2e8f9f7 91 .long UART0_Handler /* 0:UART 0 RX and TX Combined Interrupt */
<> 144:ef7eb2e8f9f7 92 .long Spare_Handler /* 1:Undefined */
<> 144:ef7eb2e8f9f7 93 .long UART1_Handler /* 2:UART 1 RX and TX Combined Interrupt */
<> 144:ef7eb2e8f9f7 94 .long I2C0_Handler /* 3:I2C 0 Interrupt */
<> 144:ef7eb2e8f9f7 95 .long I2C1_Handler /* 4:I2C 1 Interrupt */
<> 144:ef7eb2e8f9f7 96 .long RTC_Handler /* 5:RTC Interrupt */
<> 144:ef7eb2e8f9f7 97 .long PORT0_Handler /* 6:GPIO Port 0 combined Interrupt */
<> 144:ef7eb2e8f9f7 98 .long PORT1_ALL_Handler /* 7:GPIO Port 1 combined Interrupt */
<> 144:ef7eb2e8f9f7 99 .long TIMER0_Handler /* 8:TIMER 0 Interrupt */
<> 144:ef7eb2e8f9f7 100 .long TIMER1_Handler /* 9:TIMER 1 Interrupt */
<> 144:ef7eb2e8f9f7 101 .long DUALTIMER_Handler /* 10:Dual Timer Interrupt */
<> 144:ef7eb2e8f9f7 102 .long SPI0_Handler /* 11:SPI 0 Interrupt */
<> 144:ef7eb2e8f9f7 103 .long UARTOVF_Handler /* 12:UART 0,1,2 Overflow Interrupt */
<> 144:ef7eb2e8f9f7 104 .long SPI1_Handler /* 13:SPI 1 Interrupt */
<> 144:ef7eb2e8f9f7 105 .long QSPI_Handler /* 14:QUAD SPI Interrupt */
<> 144:ef7eb2e8f9f7 106 .long DMA_Handler /* 15:Touch Screen Interrupt */
<> 144:ef7eb2e8f9f7 107 .long PORT0_0_Handler /* 16:All P0 and P1I/O pins used as irq source */
<> 144:ef7eb2e8f9f7 108 .long PORT0_1_Handler /* 17:There are 16 pins in total */
<> 144:ef7eb2e8f9f7 109 .long PORT0_2_Handler /* 18: */
<> 144:ef7eb2e8f9f7 110 .long PORT0_3_Handler /* 19: */
<> 144:ef7eb2e8f9f7 111 .long PORT0_4_Handler /* 20: */
<> 144:ef7eb2e8f9f7 112 .long PORT0_5_Handler /* 21: */
<> 144:ef7eb2e8f9f7 113 .long PORT0_6_Handler /* 22: */
<> 144:ef7eb2e8f9f7 114 .long PORT0_7_Handler /* 23: */
<> 144:ef7eb2e8f9f7 115 .long PORT0_8_Handler /* 24: */
<> 144:ef7eb2e8f9f7 116 .long PORT0_9_Handler /* 25: */
<> 144:ef7eb2e8f9f7 117 .long PORT0_10_Handler /* 26: */
<> 144:ef7eb2e8f9f7 118 .long PORT0_11_Handler /* 27: */
<> 144:ef7eb2e8f9f7 119 .long PORT0_12_Handler /* 28: */
<> 144:ef7eb2e8f9f7 120 .long PORT0_13_Handler /* 29: */
<> 144:ef7eb2e8f9f7 121 .long PORT0_14_Handler /* 30: */
<> 144:ef7eb2e8f9f7 122 .long PORT0_15_Handler /* 31: */
<> 144:ef7eb2e8f9f7 123 .long SysError_Handler /* 32: System Error (Flash Cache) */
<> 144:ef7eb2e8f9f7 124 .long EFLASH_Handler /* 33: Embedded Flash */
<> 144:ef7eb2e8f9f7 125 .long LLCC_TXCMD_EMPTY_Handler /* 34: LLCC_TXCMDIRQ */
<> 144:ef7eb2e8f9f7 126 .long LLCC_TXEVT_EMPTY_Handler /* 35: LLCC_TXEVTIRQ */
<> 144:ef7eb2e8f9f7 127 .long LLCC_TXDMAH_DONE_Handler /* 36: LLCC_TXDMA0IRQ */
<> 144:ef7eb2e8f9f7 128 .long LLCC_TXDMAL_DONE_Handler /* 37: LLCC_TXDMA1IRQ */
<> 144:ef7eb2e8f9f7 129 .long LLCC_RXCMD_VALID_Handler /* 38: LLCC_RXCMDIRQ */
<> 144:ef7eb2e8f9f7 130 .long LLCC_RXEVT_VALID_Handler /* 39: LLCC_RXEVTIRQ */
<> 144:ef7eb2e8f9f7 131 .long LLCC_RXDMAH_DONE_Handler /* 40: LLCC_RXDMA0IRQ */
<> 144:ef7eb2e8f9f7 132 .long LLCC_RXDMAL_DONE_Handler /* 41: LLCC_RXDMA1IRQ */
<> 144:ef7eb2e8f9f7 133 .long PORT2_COMB_Handler /* 42: GPIO 2 */
<> 144:ef7eb2e8f9f7 134 .long PORT3_COMB_Handler /* 43: GPIO 3 */
<> 144:ef7eb2e8f9f7 135 .long TRNG_Handler /* 44: TRNG */
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 .size __isr_vector, . - __isr_vector
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 .section .text.Reset_Handler
<> 144:ef7eb2e8f9f7 140 .thumb
<> 144:ef7eb2e8f9f7 141 .thumb_func
<> 144:ef7eb2e8f9f7 142 .align 2
<> 144:ef7eb2e8f9f7 143 .globl Reset_Handler
<> 144:ef7eb2e8f9f7 144 .type Reset_Handler, %function
<> 144:ef7eb2e8f9f7 145 Reset_Handler:
<> 144:ef7eb2e8f9f7 146 /*
<> 144:ef7eb2e8f9f7 147 * Loop to copy data from read only memory to RAM. The ranges
<> 144:ef7eb2e8f9f7 148 * of copy from/to are specified by following symbols evaluated in
<> 144:ef7eb2e8f9f7 149 * linker script.
<> 144:ef7eb2e8f9f7 150 * _etext: End of code section, i.e., begin of data sections to copy from.
<> 144:ef7eb2e8f9f7 151 * __data_start__/__data_end__: RAM address range that data should be
<> 144:ef7eb2e8f9f7 152 * copied to. Both must be aligned to 4 bytes boundary.
<> 144:ef7eb2e8f9f7 153 */
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 ldr r1, =__etext
<> 144:ef7eb2e8f9f7 156 ldr r2, =__data_start__
<> 144:ef7eb2e8f9f7 157 ldr r3, =__data_end__
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 subs r3, r2
<> 144:ef7eb2e8f9f7 160 ble .Lflash_to_ram_loop_end
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 movs r4, 0
<> 144:ef7eb2e8f9f7 163 .Lflash_to_ram_loop:
<> 144:ef7eb2e8f9f7 164 ldr r0, [r1,r4]
<> 144:ef7eb2e8f9f7 165 str r0, [r2,r4]
<> 144:ef7eb2e8f9f7 166 adds r4, 4
<> 144:ef7eb2e8f9f7 167 cmp r4, r3
<> 144:ef7eb2e8f9f7 168 blt .Lflash_to_ram_loop
<> 144:ef7eb2e8f9f7 169 .Lflash_to_ram_loop_end:
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 /* Initialize .bss */
<> 144:ef7eb2e8f9f7 172 init_bss:
<> 144:ef7eb2e8f9f7 173 ldr r1, =__bss_start__
<> 144:ef7eb2e8f9f7 174 ldr r2, =__bss_end__
<> 144:ef7eb2e8f9f7 175 ldr r3, =bss_size
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 cmp r3, #0
<> 144:ef7eb2e8f9f7 178 beq system_startup
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 mov r4, #0
<> 144:ef7eb2e8f9f7 181 zero:
<> 144:ef7eb2e8f9f7 182 strb r4, [r1], #1
<> 144:ef7eb2e8f9f7 183 subs r3, r3, #1
<> 144:ef7eb2e8f9f7 184 bne zero
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 system_startup:
<> 144:ef7eb2e8f9f7 187 ldr r0, =SystemInit
<> 144:ef7eb2e8f9f7 188 blx r0
<> 144:ef7eb2e8f9f7 189 ldr r0, =_start
<> 144:ef7eb2e8f9f7 190 bx r0
<> 144:ef7eb2e8f9f7 191 .pool
<> 144:ef7eb2e8f9f7 192 .size Reset_Handler, . - Reset_Handler
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 .text
<> 144:ef7eb2e8f9f7 195 /*
<> 144:ef7eb2e8f9f7 196 * Macro to define default handlers. Default handler
<> 144:ef7eb2e8f9f7 197 * will be weak symbol and just dead loops. They can be
<> 144:ef7eb2e8f9f7 198 * overwritten by other handlers
<> 144:ef7eb2e8f9f7 199 */
<> 144:ef7eb2e8f9f7 200 .macro def_default_handler handler_name
<> 144:ef7eb2e8f9f7 201 .align 1
<> 144:ef7eb2e8f9f7 202 .thumb_func
<> 144:ef7eb2e8f9f7 203 .weak \handler_name
<> 144:ef7eb2e8f9f7 204 .type \handler_name, %function
<> 144:ef7eb2e8f9f7 205 \handler_name :
<> 144:ef7eb2e8f9f7 206 b .
<> 144:ef7eb2e8f9f7 207 .size \handler_name, . - \handler_name
<> 144:ef7eb2e8f9f7 208 .endm
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 def_default_handler NMI_Handler
<> 144:ef7eb2e8f9f7 211 def_default_handler HardFault_Handler
<> 144:ef7eb2e8f9f7 212 def_default_handler MemManage_Handler
<> 144:ef7eb2e8f9f7 213 def_default_handler BusFault_Handler
<> 144:ef7eb2e8f9f7 214 def_default_handler UsageFault_Handler
<> 144:ef7eb2e8f9f7 215 def_default_handler SVC_Handler
<> 144:ef7eb2e8f9f7 216 def_default_handler DebugMon_Handler
<> 144:ef7eb2e8f9f7 217 def_default_handler PendSV_Handler
<> 144:ef7eb2e8f9f7 218 def_default_handler SysTick_Handler
<> 144:ef7eb2e8f9f7 219 def_default_handler Default_Handler
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 .macro def_irq_default_handler handler_name
<> 144:ef7eb2e8f9f7 222 .weak \handler_name
<> 144:ef7eb2e8f9f7 223 .set \handler_name, Default_Handler
<> 144:ef7eb2e8f9f7 224 .endm
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 /* External interrupts */
<> 144:ef7eb2e8f9f7 227 def_irq_default_handler UART0_Handler /* 0:UART 0 RX and TX Combined Interrupt */
<> 144:ef7eb2e8f9f7 228 def_irq_default_handler Spare_Handler /* 1:Undefined */
<> 144:ef7eb2e8f9f7 229 def_irq_default_handler UART1_Handler /* 2:UART 1 RX and TX Combined Interrupt */
<> 144:ef7eb2e8f9f7 230 def_irq_default_handler I2C0_Handler /* 3:I2C 0 Interrupt */
<> 144:ef7eb2e8f9f7 231 def_irq_default_handler I2C1_Handler /* 4:I2C 1 Interrupt */
<> 144:ef7eb2e8f9f7 232 def_irq_default_handler RTC_Handler /* 5:RTC Interrupt */
<> 144:ef7eb2e8f9f7 233 def_irq_default_handler PORT0_Handler /* 6:GPIO Port 0 combined Interrupt */
<> 144:ef7eb2e8f9f7 234 def_irq_default_handler PORT1_ALL_Handler /* 7:GPIO Port 1 combined Interrupt */
<> 144:ef7eb2e8f9f7 235 def_irq_default_handler TIMER0_Handler /* 8:TIMER 0 Interrupt */
<> 144:ef7eb2e8f9f7 236 def_irq_default_handler TIMER1_Handler /* 9:TIMER 1 Interrupt */
<> 144:ef7eb2e8f9f7 237 def_irq_default_handler DUALTIMER_Handler /* 10:Dual Timer Interrupt */
<> 144:ef7eb2e8f9f7 238 def_irq_default_handler SPI0_Handler /* 11:SPI 0 Interrupt */
<> 144:ef7eb2e8f9f7 239 def_irq_default_handler UARTOVF_Handler /* 12:UART 0,1,2 Overflow Interrupt */
<> 144:ef7eb2e8f9f7 240 def_irq_default_handler SPI1_Handler /* 13:SPI 1 Interrupt */
<> 144:ef7eb2e8f9f7 241 def_irq_default_handler QSPI_Handler /* 14:QUAD SPI Interrupt */
<> 144:ef7eb2e8f9f7 242 def_irq_default_handler DMA_Handler /* 15:Touch Screen Interrupt */
<> 144:ef7eb2e8f9f7 243 def_irq_default_handler PORT0_0_Handler /* 16:All P0 and P1I/O pins used as irq source */
<> 144:ef7eb2e8f9f7 244 def_irq_default_handler PORT0_1_Handler /* 17:There are 16 pins in total */
<> 144:ef7eb2e8f9f7 245 def_irq_default_handler PORT0_2_Handler /* 18: */
<> 144:ef7eb2e8f9f7 246 def_irq_default_handler PORT0_3_Handler /* 19: */
<> 144:ef7eb2e8f9f7 247 def_irq_default_handler PORT0_4_Handler /* 20: */
<> 144:ef7eb2e8f9f7 248 def_irq_default_handler PORT0_5_Handler /* 21: */
<> 144:ef7eb2e8f9f7 249 def_irq_default_handler PORT0_6_Handler /* 22: */
<> 144:ef7eb2e8f9f7 250 def_irq_default_handler PORT0_7_Handler /* 23: */
<> 144:ef7eb2e8f9f7 251 def_irq_default_handler PORT0_8_Handler /* 24: */
<> 144:ef7eb2e8f9f7 252 def_irq_default_handler PORT0_9_Handler /* 25: */
<> 144:ef7eb2e8f9f7 253 def_irq_default_handler PORT0_10_Handler /* 26: */
<> 144:ef7eb2e8f9f7 254 def_irq_default_handler PORT0_11_Handler /* 27: */
<> 144:ef7eb2e8f9f7 255 def_irq_default_handler PORT0_12_Handler /* 28: */
<> 144:ef7eb2e8f9f7 256 def_irq_default_handler PORT0_13_Handler /* 29: */
<> 144:ef7eb2e8f9f7 257 def_irq_default_handler PORT0_14_Handler /* 30: */
<> 144:ef7eb2e8f9f7 258 def_irq_default_handler PORT0_15_Handler /* 31: */
<> 144:ef7eb2e8f9f7 259 def_irq_default_handler SysError_Handler /* 32: System Error (Flash Cache) */
<> 144:ef7eb2e8f9f7 260 def_irq_default_handler EFLASH_Handler /* 33: Embedded Flash */
<> 144:ef7eb2e8f9f7 261 def_irq_default_handler LLCC_TXCMD_EMPTY_Handler /* 34: LLCC_TXCMDIRQ */
<> 144:ef7eb2e8f9f7 262 def_irq_default_handler LLCC_TXEVT_EMPTY_Handler /* 35: LLCC_TXEVTIRQ */
<> 144:ef7eb2e8f9f7 263 def_irq_default_handler LLCC_TXDMAH_DONE_Handler /* 36: LLCC_TXDMA0IRQ */
<> 144:ef7eb2e8f9f7 264 def_irq_default_handler LLCC_TXDMAL_DONE_Handler /* 37: LLCC_TXDMA1IRQ */
<> 144:ef7eb2e8f9f7 265 def_irq_default_handler LLCC_RXCMD_VALID_Handler /* 38: LLCC_RXCMDIRQ */
<> 144:ef7eb2e8f9f7 266 def_irq_default_handler LLCC_RXEVT_VALID_Handler /* 39: LLCC_RXEVTIRQ */
<> 144:ef7eb2e8f9f7 267 def_irq_default_handler LLCC_RXDMAH_DONE_Handler /* 40: LLCC_RXDMA0IRQ */
<> 144:ef7eb2e8f9f7 268 def_irq_default_handler LLCC_RXDMAL_DONE_Handler /* 41: LLCC_RXDMA1IRQ */
<> 144:ef7eb2e8f9f7 269 def_irq_default_handler PORT2_COMB_Handler /* 42: GPIO 2 */
<> 144:ef7eb2e8f9f7 270 def_irq_default_handler PORT3_COMB_Handler /* 43: GPIO 3 */
<> 144:ef7eb2e8f9f7 271 def_irq_default_handler TRNG_Handler /* 44: TRNG */
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 .end