Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/CMSDK_BEID.h@80:bdf1132a57cf, 2016-03-02 (annotated)

Committer:
mbed_official
Date:
Wed Mar 02 14:30:11 2016 +0000
Revision:
80:bdf1132a57cf
Synchronized with git revision de3b14ec9234d586b155fd24badc22775489a3dc



Full URL: https://github.com/mbedmicro/mbed/commit/de3b14ec9234d586b155fd24badc22775489a3dc/



latest changes to add arduino support, plus fixes for IOTSS BEID

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 80:bdf1132a57cf 1 /* MPS2 CMSIS Library
mbed_official 80:bdf1132a57cf 2 *
mbed_official 80:bdf1132a57cf 3 * Copyright (c) 2006-2016 ARM Limited
mbed_official 80:bdf1132a57cf 4 * All rights reserved.
mbed_official 80:bdf1132a57cf 5 *
mbed_official 80:bdf1132a57cf 6 * Redistribution and use in source and binary forms, with or without
mbed_official 80:bdf1132a57cf 7 * modification, are permitted provided that the following conditions are met:
mbed_official 80:bdf1132a57cf 8 *
mbed_official 80:bdf1132a57cf 9 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 80:bdf1132a57cf 10 * this list of conditions and the following disclaimer.
mbed_official 80:bdf1132a57cf 11 *
mbed_official 80:bdf1132a57cf 12 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 80:bdf1132a57cf 13 * this list of conditions and the following disclaimer in the documentation
mbed_official 80:bdf1132a57cf 14 * and/or other materials provided with the distribution.
mbed_official 80:bdf1132a57cf 15 *
mbed_official 80:bdf1132a57cf 16 * 3. Neither the name of the copyright holder nor the names of its contributors
mbed_official 80:bdf1132a57cf 17 * may be used to endorse or promote products derived from this software without
mbed_official 80:bdf1132a57cf 18 * specific prior written permission.
mbed_official 80:bdf1132a57cf 19 *
mbed_official 80:bdf1132a57cf 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 80:bdf1132a57cf 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 80:bdf1132a57cf 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mbed_official 80:bdf1132a57cf 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
mbed_official 80:bdf1132a57cf 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mbed_official 80:bdf1132a57cf 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mbed_official 80:bdf1132a57cf 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbed_official 80:bdf1132a57cf 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbed_official 80:bdf1132a57cf 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mbed_official 80:bdf1132a57cf 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbed_official 80:bdf1132a57cf 30 * POSSIBILITY OF SUCH DAMAGE.
mbed_official 80:bdf1132a57cf 31 *******************************************************************************
mbed_official 80:bdf1132a57cf 32 * @file CMSDK_BEID.h
mbed_official 80:bdf1132a57cf 33 * @brief CMSIS Core Peripheral Access Layer Header File for
mbed_official 80:bdf1132a57cf 34 * CMSDK_BEID Device
mbed_official 80:bdf1132a57cf 35 *
mbed_official 80:bdf1132a57cf 36 *******************************************************************************/
mbed_official 80:bdf1132a57cf 37
mbed_official 80:bdf1132a57cf 38
mbed_official 80:bdf1132a57cf 39 #ifndef CMSDK_BEID_H
mbed_official 80:bdf1132a57cf 40 #define CMSDK_BEID_H
mbed_official 80:bdf1132a57cf 41
mbed_official 80:bdf1132a57cf 42 #ifdef __cplusplus
mbed_official 80:bdf1132a57cf 43 extern "C" {
mbed_official 80:bdf1132a57cf 44 #endif
mbed_official 80:bdf1132a57cf 45
mbed_official 80:bdf1132a57cf 46
mbed_official 80:bdf1132a57cf 47 /* ------------------------- Interrupt Number Definition ------------------------ */
mbed_official 80:bdf1132a57cf 48
mbed_official 80:bdf1132a57cf 49 typedef enum IRQn
mbed_official 80:bdf1132a57cf 50 {
mbed_official 80:bdf1132a57cf 51 /* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
mbed_official 80:bdf1132a57cf 52 NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
mbed_official 80:bdf1132a57cf 53 HardFault_IRQn = -13, /* 3 HardFault Interrupt */
mbed_official 80:bdf1132a57cf 54 MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
mbed_official 80:bdf1132a57cf 55 BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
mbed_official 80:bdf1132a57cf 56 UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
mbed_official 80:bdf1132a57cf 57 SVCall_IRQn = -5, /* 11 SV Call Interrupt */
mbed_official 80:bdf1132a57cf 58 DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
mbed_official 80:bdf1132a57cf 59 PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
mbed_official 80:bdf1132a57cf 60 SysTick_IRQn = -1, /* 15 System Tick Interrupt */
mbed_official 80:bdf1132a57cf 61
mbed_official 80:bdf1132a57cf 62 /* ---------------------- CMSDK_CM3 Specific Interrupt Numbers ------------------ */
mbed_official 80:bdf1132a57cf 63 UART0_IRQn = 0, /* UART 0 RX and TX Combined Interrupt */
mbed_official 80:bdf1132a57cf 64 Spare_IRQn = 1, /* Undefined */
mbed_official 80:bdf1132a57cf 65 UART1_IRQn = 2, /* UART 1 RX and TX Combined Interrupt */
mbed_official 80:bdf1132a57cf 66 I2C0_IRQn = 3, /* I2C 0 Interrupt */
mbed_official 80:bdf1132a57cf 67 I2C1_IRQn = 4, /* I2C 1 Interrupt */
mbed_official 80:bdf1132a57cf 68 RTC_IRQn = 5, /* RTC Interrupt */
mbed_official 80:bdf1132a57cf 69 PORT0_ALL_IRQn = 6, /* GPIO Port 0 combined Interrupt */
mbed_official 80:bdf1132a57cf 70 PORT1_ALL_IRQn = 7, /* GPIO Port 1 combined Interrupt */
mbed_official 80:bdf1132a57cf 71 TIMER0_IRQn = 8, /* TIMER 0 Interrupt */
mbed_official 80:bdf1132a57cf 72 TIMER1_IRQn = 9, /* TIMER 1 Interrupt */
mbed_official 80:bdf1132a57cf 73 DUALTIMER_IRQn = 10, /* Dual Timer Interrupt */
mbed_official 80:bdf1132a57cf 74 SPI0_IRQn = 11, /* SPI 0 Interrupt */
mbed_official 80:bdf1132a57cf 75 UARTOVF_IRQn = 12, /* UART 0,1,2 Overflow Interrupt */
mbed_official 80:bdf1132a57cf 76 SPI1_IRQn = 13, /* SPI 1 Interrupt */
mbed_official 80:bdf1132a57cf 77 RESERVED0_IRQn = 14, /* Reserved */
mbed_official 80:bdf1132a57cf 78 TSC_IRQn = 15, /* Touch Screen Interrupt */
mbed_official 80:bdf1132a57cf 79 PORT01_0_IRQn = 16, /* GPIO Port 0 pin 0 Handler */
mbed_official 80:bdf1132a57cf 80 PORT01_1_IRQn = 17, /* GPIO Port 0 pin 1 Handler */
mbed_official 80:bdf1132a57cf 81 PORT01_2_IRQn = 18, /* GPIO Port 0 pin 2 Handler */
mbed_official 80:bdf1132a57cf 82 PORT01_3_IRQn = 19, /* GPIO Port 0 pin 3 Handler */
mbed_official 80:bdf1132a57cf 83 PORT01_4_IRQn = 20, /* GPIO Port 0 pin 4 Handler */
mbed_official 80:bdf1132a57cf 84 PORT01_5_IRQn = 21, /* GPIO Port 0 pin 5 Handler */
mbed_official 80:bdf1132a57cf 85 PORT01_6_IRQn = 22, /* GPIO Port 0 pin 6 Handler */
mbed_official 80:bdf1132a57cf 86 PORT01_7_IRQn = 23, /* GPIO Port 0 pin 7 Handler */
mbed_official 80:bdf1132a57cf 87 PORT01_8_IRQn = 24, /* GPIO Port 0 pin 8 Handler */
mbed_official 80:bdf1132a57cf 88 PORT01_9_IRQn = 25, /* GPIO Port 0 pin 9 Handler */
mbed_official 80:bdf1132a57cf 89 PORT01_10_IRQn = 26, /* GPIO Port 0 pin 10 Handler */
mbed_official 80:bdf1132a57cf 90 PORT01_11_IRQn = 27, /* GPIO Port 0 pin 11 Handler */
mbed_official 80:bdf1132a57cf 91 PORT01_12_IRQn = 28, /* GPIO Port 0 pin 12 Handler */
mbed_official 80:bdf1132a57cf 92 PORT01_13_IRQn = 29, /* GPIO Port 0 pin 13 Handler */
mbed_official 80:bdf1132a57cf 93 PORT01_14_IRQn = 30, /* GPIO Port 0 pin 14 Handler */
mbed_official 80:bdf1132a57cf 94 PORT01_15_IRQn = 31, /* GPIO Port 0 pin 15 Handler */
mbed_official 80:bdf1132a57cf 95 SYSERROR_IRQn = 32, /* System Error Interrupt */
mbed_official 80:bdf1132a57cf 96 EFLASH_IRQn = 33, /* Embedded Flash Interrupt */
mbed_official 80:bdf1132a57cf 97 RESERVED1_IRQn = 34, /* Reserved */
mbed_official 80:bdf1132a57cf 98 RESERVED2_IRQn = 35, /* Reserved */
mbed_official 80:bdf1132a57cf 99 RESERVED3_IRQn = 36, /* Reserved */
mbed_official 80:bdf1132a57cf 100 RESERVED4_IRQn = 37, /* Reserved */
mbed_official 80:bdf1132a57cf 101 RESERVED5_IRQn = 38, /* Reserved */
mbed_official 80:bdf1132a57cf 102 RESERVED6_IRQn = 39, /* Reserved */
mbed_official 80:bdf1132a57cf 103 RESERVED7_IRQn = 40, /* Reserved */
mbed_official 80:bdf1132a57cf 104 RESERVED8_IRQn = 41, /* Reserved */
mbed_official 80:bdf1132a57cf 105 PORT2_ALL_IRQn = 42, /* GPIO Port 2 combined Interrupt */
mbed_official 80:bdf1132a57cf 106 PORT3_ALL_IRQn = 43, /* GPIO Port 3 combined Interrupt */
mbed_official 80:bdf1132a57cf 107 TRNG_IRQn = 44, /* Random number generator Interrupt */
mbed_official 80:bdf1132a57cf 108 UART2_IRQn = 45, /* UART 2 RX and TX Combined Interrupt */
mbed_official 80:bdf1132a57cf 109 UART3_IRQn = 46, /* UART 3 RX and TX Combined Interrupt */
mbed_official 80:bdf1132a57cf 110 ETHERNET_IRQn = 47, /* Ethernet interrupt t.b.a. */
mbed_official 80:bdf1132a57cf 111 I2S_IRQn = 48, /* I2S Interrupt */
mbed_official 80:bdf1132a57cf 112 MPS2_SPI0_IRQn = 49, /* SPI Interrupt (spi header) */
mbed_official 80:bdf1132a57cf 113 MPS2_SPI1_IRQn = 50, /* SPI Interrupt (clcd) */
mbed_official 80:bdf1132a57cf 114 MPS2_SPI2_IRQn = 51, /* SPI Interrupt (spi 1 ADC replacement) */
mbed_official 80:bdf1132a57cf 115 MPS2_SPI3_IRQn = 52, /* SPI Interrupt (spi 0 shield 0 replacement) */
mbed_official 80:bdf1132a57cf 116 MPS2_SPI4_IRQn = 53 /* SPI Interrupt (shield 1) */
mbed_official 80:bdf1132a57cf 117 } IRQn_Type;
mbed_official 80:bdf1132a57cf 118
mbed_official 80:bdf1132a57cf 119
mbed_official 80:bdf1132a57cf 120 /* ================================================================================ */
mbed_official 80:bdf1132a57cf 121 /* ================ Processor and Core Peripheral Section ================ */
mbed_official 80:bdf1132a57cf 122 /* ================================================================================ */
mbed_official 80:bdf1132a57cf 123
mbed_official 80:bdf1132a57cf 124 /* -------- Configuration of the Cortex-M3 Processor and Core Peripherals ------- */
mbed_official 80:bdf1132a57cf 125 #define __BEID_REV 0x0201 /* Core revision r2p1 */
mbed_official 80:bdf1132a57cf 126 #define __MPU_PRESENT 1 /* MPU present or not */
mbed_official 80:bdf1132a57cf 127 #define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
mbed_official 80:bdf1132a57cf 128 #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
mbed_official 80:bdf1132a57cf 129
mbed_official 80:bdf1132a57cf 130 #include <core_cm3.h> /* Processor and core peripherals */
mbed_official 80:bdf1132a57cf 131 #include "system_CMSDK_BEID.h" /* System Header */
mbed_official 80:bdf1132a57cf 132
mbed_official 80:bdf1132a57cf 133
mbed_official 80:bdf1132a57cf 134 /* ================================================================================ */
mbed_official 80:bdf1132a57cf 135 /* ================ Device Specific Peripheral Section ================ */
mbed_official 80:bdf1132a57cf 136 /* ================================================================================ */
mbed_official 80:bdf1132a57cf 137
mbed_official 80:bdf1132a57cf 138 /* ------------------- Start of section using anonymous unions ------------------ */
mbed_official 80:bdf1132a57cf 139 #if defined ( __CC_ARM )
mbed_official 80:bdf1132a57cf 140 #pragma push
mbed_official 80:bdf1132a57cf 141 #pragma anon_unions
mbed_official 80:bdf1132a57cf 142 #elif defined(__ICCARM__)
mbed_official 80:bdf1132a57cf 143 #pragma language=extended
mbed_official 80:bdf1132a57cf 144 #elif defined(__GNUC__)
mbed_official 80:bdf1132a57cf 145 /* anonymous unions are enabled by default */
mbed_official 80:bdf1132a57cf 146 #elif defined(__TMS470__)
mbed_official 80:bdf1132a57cf 147 /* anonymous unions are enabled by default */
mbed_official 80:bdf1132a57cf 148 #elif defined(__TASKING__)
mbed_official 80:bdf1132a57cf 149 #pragma warning 586
mbed_official 80:bdf1132a57cf 150 #else
mbed_official 80:bdf1132a57cf 151 #warning Not supported compiler type
mbed_official 80:bdf1132a57cf 152 #endif
mbed_official 80:bdf1132a57cf 153
mbed_official 80:bdf1132a57cf 154 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
mbed_official 80:bdf1132a57cf 155 typedef struct
mbed_official 80:bdf1132a57cf 156 {
mbed_official 80:bdf1132a57cf 157 __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */
mbed_official 80:bdf1132a57cf 158 __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */
mbed_official 80:bdf1132a57cf 159 __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */
mbed_official 80:bdf1132a57cf 160 union {
mbed_official 80:bdf1132a57cf 161 __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
mbed_official 80:bdf1132a57cf 162 __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
mbed_official 80:bdf1132a57cf 163 };
mbed_official 80:bdf1132a57cf 164 __IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */
mbed_official 80:bdf1132a57cf 165
mbed_official 80:bdf1132a57cf 166 } CMSDK_UART_TypeDef;
mbed_official 80:bdf1132a57cf 167
mbed_official 80:bdf1132a57cf 168 /* CMSDK_UART DATA Register Definitions */
mbed_official 80:bdf1132a57cf 169
mbed_official 80:bdf1132a57cf 170 #define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position */
mbed_official 80:bdf1132a57cf 171 #define CMSDK_UART_DATA_Msk (0xFFul << CMSDK_UART_DATA_Pos) /* CMSDK_UART DATA: DATA Mask */
mbed_official 80:bdf1132a57cf 172
mbed_official 80:bdf1132a57cf 173 #define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position */
mbed_official 80:bdf1132a57cf 174 #define CMSDK_UART_STATE_RXOR_Msk (0x1ul << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask */
mbed_official 80:bdf1132a57cf 175
mbed_official 80:bdf1132a57cf 176 #define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position */
mbed_official 80:bdf1132a57cf 177 #define CMSDK_UART_STATE_TXOR_Msk (0x1ul << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask */
mbed_official 80:bdf1132a57cf 178
mbed_official 80:bdf1132a57cf 179 #define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position */
mbed_official 80:bdf1132a57cf 180 #define CMSDK_UART_STATE_RXBF_Msk (0x1ul << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask */
mbed_official 80:bdf1132a57cf 181
mbed_official 80:bdf1132a57cf 182 #define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position */
mbed_official 80:bdf1132a57cf 183 #define CMSDK_UART_STATE_TXBF_Msk (0x1ul << CMSDK_UART_STATE_TXBF_Pos ) /* CMSDK_UART STATE: TXBF Mask */
mbed_official 80:bdf1132a57cf 184
mbed_official 80:bdf1132a57cf 185 #define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position */
mbed_official 80:bdf1132a57cf 186 #define CMSDK_UART_CTRL_HSTM_Msk (0x01ul << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask */
mbed_official 80:bdf1132a57cf 187
mbed_official 80:bdf1132a57cf 188 #define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position */
mbed_official 80:bdf1132a57cf 189 #define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask */
mbed_official 80:bdf1132a57cf 190
mbed_official 80:bdf1132a57cf 191 #define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position */
mbed_official 80:bdf1132a57cf 192 #define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask */
mbed_official 80:bdf1132a57cf 193
mbed_official 80:bdf1132a57cf 194 #define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position */
mbed_official 80:bdf1132a57cf 195 #define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask */
mbed_official 80:bdf1132a57cf 196
mbed_official 80:bdf1132a57cf 197 #define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position */
mbed_official 80:bdf1132a57cf 198 #define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask */
mbed_official 80:bdf1132a57cf 199
mbed_official 80:bdf1132a57cf 200 #define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position */
mbed_official 80:bdf1132a57cf 201 #define CMSDK_UART_CTRL_RXEN_Msk (0x01ul << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask */
mbed_official 80:bdf1132a57cf 202
mbed_official 80:bdf1132a57cf 203 #define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position */
mbed_official 80:bdf1132a57cf 204 #define CMSDK_UART_CTRL_TXEN_Msk (0x01ul << CMSDK_UART_CTRL_TXEN_Pos) /* CMSDK_UART CTRL: TXEN Mask */
mbed_official 80:bdf1132a57cf 205
mbed_official 80:bdf1132a57cf 206 #define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /* CMSDK_UART CTRL: RXORIRQ Position */
mbed_official 80:bdf1132a57cf 207 #define CMSDK_UART_CTRL_RXORIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /* CMSDK_UART CTRL: RXORIRQ Mask */
mbed_official 80:bdf1132a57cf 208
mbed_official 80:bdf1132a57cf 209 #define CMSDK_UART_CTRL_TXORIRQ_Pos 2 /* CMSDK_UART CTRL: TXORIRQ Position */
mbed_official 80:bdf1132a57cf 210 #define CMSDK_UART_CTRL_TXORIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQ_Pos) /* CMSDK_UART CTRL: TXORIRQ Mask */
mbed_official 80:bdf1132a57cf 211
mbed_official 80:bdf1132a57cf 212 #define CMSDK_UART_CTRL_RXIRQ_Pos 1 /* CMSDK_UART CTRL: RXIRQ Position */
mbed_official 80:bdf1132a57cf 213 #define CMSDK_UART_CTRL_RXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQ_Pos) /* CMSDK_UART CTRL: RXIRQ Mask */
mbed_official 80:bdf1132a57cf 214
mbed_official 80:bdf1132a57cf 215 #define CMSDK_UART_CTRL_TXIRQ_Pos 0 /* CMSDK_UART CTRL: TXIRQ Position */
mbed_official 80:bdf1132a57cf 216 #define CMSDK_UART_CTRL_TXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQ_Pos) /* CMSDK_UART CTRL: TXIRQ Mask */
mbed_official 80:bdf1132a57cf 217
mbed_official 80:bdf1132a57cf 218 #define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position */
mbed_official 80:bdf1132a57cf 219 #define CMSDK_UART_BAUDDIV_Msk (0xFFFFFul << CMSDK_UART_BAUDDIV_Pos) /* CMSDK_UART BAUDDIV: BAUDDIV Mask */
mbed_official 80:bdf1132a57cf 220
mbed_official 80:bdf1132a57cf 221
mbed_official 80:bdf1132a57cf 222 /*----------------------------- Timer (TIMER) -------------------------------*/
mbed_official 80:bdf1132a57cf 223 typedef struct
mbed_official 80:bdf1132a57cf 224 {
mbed_official 80:bdf1132a57cf 225 __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */
mbed_official 80:bdf1132a57cf 226 __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */
mbed_official 80:bdf1132a57cf 227 __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */
mbed_official 80:bdf1132a57cf 228 union {
mbed_official 80:bdf1132a57cf 229 __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
mbed_official 80:bdf1132a57cf 230 __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
mbed_official 80:bdf1132a57cf 231 };
mbed_official 80:bdf1132a57cf 232
mbed_official 80:bdf1132a57cf 233 } CMSDK_TIMER_TypeDef;
mbed_official 80:bdf1132a57cf 234
mbed_official 80:bdf1132a57cf 235 /* CMSDK_TIMER CTRL Register Definitions */
mbed_official 80:bdf1132a57cf 236
mbed_official 80:bdf1132a57cf 237 #define CMSDK_TIMER_CTRL_IRQEN_Pos 3 /* CMSDK_TIMER CTRL: IRQEN Position */
mbed_official 80:bdf1132a57cf 238 #define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01ul << CMSDK_TIMER_CTRL_IRQEN_Pos) /* CMSDK_TIMER CTRL: IRQEN Mask */
mbed_official 80:bdf1132a57cf 239
mbed_official 80:bdf1132a57cf 240 #define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2 /* CMSDK_TIMER CTRL: SELEXTCLK Position */
mbed_official 80:bdf1132a57cf 241 #define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /* CMSDK_TIMER CTRL: SELEXTCLK Mask */
mbed_official 80:bdf1132a57cf 242
mbed_official 80:bdf1132a57cf 243 #define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1 /* CMSDK_TIMER CTRL: SELEXTEN Position */
mbed_official 80:bdf1132a57cf 244 #define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /* CMSDK_TIMER CTRL: SELEXTEN Mask */
mbed_official 80:bdf1132a57cf 245
mbed_official 80:bdf1132a57cf 246 #define CMSDK_TIMER_CTRL_EN_Pos 0 /* CMSDK_TIMER CTRL: EN Position */
mbed_official 80:bdf1132a57cf 247 #define CMSDK_TIMER_CTRL_EN_Msk (0x01ul << CMSDK_TIMER_CTRL_EN_Pos) /* CMSDK_TIMER CTRL: EN Mask */
mbed_official 80:bdf1132a57cf 248
mbed_official 80:bdf1132a57cf 249 #define CMSDK_TIMER_VAL_CURRENT_Pos 0 /* CMSDK_TIMER VALUE: CURRENT Position */
mbed_official 80:bdf1132a57cf 250 #define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFul << CMSDK_TIMER_VAL_CURRENT_Pos) /* CMSDK_TIMER VALUE: CURRENT Mask */
mbed_official 80:bdf1132a57cf 251
mbed_official 80:bdf1132a57cf 252 #define CMSDK_TIMER_RELOAD_VAL_Pos 0 /* CMSDK_TIMER RELOAD: RELOAD Position */
mbed_official 80:bdf1132a57cf 253 #define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFul << CMSDK_TIMER_RELOAD_VAL_Pos) /* CMSDK_TIMER RELOAD: RELOAD Mask */
mbed_official 80:bdf1132a57cf 254
mbed_official 80:bdf1132a57cf 255 #define CMSDK_TIMER_INTSTATUS_Pos 0 /* CMSDK_TIMER INTSTATUS: INTSTATUSPosition */
mbed_official 80:bdf1132a57cf 256 #define CMSDK_TIMER_INTSTATUS_Msk (0x01ul << CMSDK_TIMER_INTSTATUS_Pos) /* CMSDK_TIMER INTSTATUS: INTSTATUSMask */
mbed_official 80:bdf1132a57cf 257
mbed_official 80:bdf1132a57cf 258 #define CMSDK_TIMER_INTCLEAR_Pos 0 /* CMSDK_TIMER INTCLEAR: INTCLEAR Position */
mbed_official 80:bdf1132a57cf 259 #define CMSDK_TIMER_INTCLEAR_Msk (0x01ul << CMSDK_TIMER_INTCLEAR_Pos) /* CMSDK_TIMER INTCLEAR: INTCLEAR Mask */
mbed_official 80:bdf1132a57cf 260
mbed_official 80:bdf1132a57cf 261
mbed_official 80:bdf1132a57cf 262 /*------------- Timer (TIM) --------------------------------------------------*/
mbed_official 80:bdf1132a57cf 263 typedef struct
mbed_official 80:bdf1132a57cf 264 {
mbed_official 80:bdf1132a57cf 265 __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
mbed_official 80:bdf1132a57cf 266 __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
mbed_official 80:bdf1132a57cf 267 __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
mbed_official 80:bdf1132a57cf 268 __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
mbed_official 80:bdf1132a57cf 269 __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
mbed_official 80:bdf1132a57cf 270 __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
mbed_official 80:bdf1132a57cf 271 __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
mbed_official 80:bdf1132a57cf 272 uint32_t RESERVED0;
mbed_official 80:bdf1132a57cf 273 __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
mbed_official 80:bdf1132a57cf 274 __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
mbed_official 80:bdf1132a57cf 275 __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
mbed_official 80:bdf1132a57cf 276 __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
mbed_official 80:bdf1132a57cf 277 __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
mbed_official 80:bdf1132a57cf 278 __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
mbed_official 80:bdf1132a57cf 279 __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
mbed_official 80:bdf1132a57cf 280 uint32_t RESERVED1[945];
mbed_official 80:bdf1132a57cf 281 __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */
mbed_official 80:bdf1132a57cf 282 __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */
mbed_official 80:bdf1132a57cf 283 } CMSDK_DUALTIMER_BOTH_TypeDef;
mbed_official 80:bdf1132a57cf 284
mbed_official 80:bdf1132a57cf 285 #define CMSDK_DUALTIMER1_LOAD_Pos 0 /* CMSDK_DUALTIMER1 LOAD: LOAD Position */
mbed_official 80:bdf1132a57cf 286 #define CMSDK_DUALTIMER1_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_LOAD_Pos) /* CMSDK_DUALTIMER1 LOAD: LOAD Mask */
mbed_official 80:bdf1132a57cf 287
mbed_official 80:bdf1132a57cf 288 #define CMSDK_DUALTIMER1_VALUE_Pos 0 /* CMSDK_DUALTIMER1 VALUE: VALUE Position */
mbed_official 80:bdf1132a57cf 289 #define CMSDK_DUALTIMER1_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_VALUE_Pos) /* CMSDK_DUALTIMER1 VALUE: VALUE Mask */
mbed_official 80:bdf1132a57cf 290
mbed_official 80:bdf1132a57cf 291 #define CMSDK_DUALTIMER1_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Position */
mbed_official 80:bdf1132a57cf 292 #define CMSDK_DUALTIMER1_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_EN_Pos) /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Mask */
mbed_official 80:bdf1132a57cf 293
mbed_official 80:bdf1132a57cf 294 #define CMSDK_DUALTIMER1_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Position */
mbed_official 80:bdf1132a57cf 295 #define CMSDK_DUALTIMER1_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_MODE_Pos) /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Mask */
mbed_official 80:bdf1132a57cf 296
mbed_official 80:bdf1132a57cf 297 #define CMSDK_DUALTIMER1_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Position */
mbed_official 80:bdf1132a57cf 298 #define CMSDK_DUALTIMER1_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Mask */
mbed_official 80:bdf1132a57cf 299
mbed_official 80:bdf1132a57cf 300 #define CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Position */
mbed_official 80:bdf1132a57cf 301 #define CMSDK_DUALTIMER1_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Mask */
mbed_official 80:bdf1132a57cf 302
mbed_official 80:bdf1132a57cf 303 #define CMSDK_DUALTIMER1_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Position */
mbed_official 80:bdf1132a57cf 304 #define CMSDK_DUALTIMER1_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Mask */
mbed_official 80:bdf1132a57cf 305
mbed_official 80:bdf1132a57cf 306 #define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Position */
mbed_official 80:bdf1132a57cf 307 #define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
mbed_official 80:bdf1132a57cf 308
mbed_official 80:bdf1132a57cf 309 #define CMSDK_DUALTIMER1_INTCLR_Pos 0 /* CMSDK_DUALTIMER1 INTCLR: INT Clear Position */
mbed_official 80:bdf1132a57cf 310 #define CMSDK_DUALTIMER1_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER1_INTCLR_Pos) /* CMSDK_DUALTIMER1 INTCLR: INT Clear Mask */
mbed_official 80:bdf1132a57cf 311
mbed_official 80:bdf1132a57cf 312 #define CMSDK_DUALTIMER1_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Position */
mbed_official 80:bdf1132a57cf 313 #define CMSDK_DUALTIMER1_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Mask */
mbed_official 80:bdf1132a57cf 314
mbed_official 80:bdf1132a57cf 315 #define CMSDK_DUALTIMER1_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Position */
mbed_official 80:bdf1132a57cf 316 #define CMSDK_DUALTIMER1_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Mask */
mbed_official 80:bdf1132a57cf 317
mbed_official 80:bdf1132a57cf 318 #define CMSDK_DUALTIMER1_BGLOAD_Pos 0 /* CMSDK_DUALTIMER1 BGLOAD: Background Load Position */
mbed_official 80:bdf1132a57cf 319 #define CMSDK_DUALTIMER1_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_BGLOAD_Pos) /* CMSDK_DUALTIMER1 BGLOAD: Background Load Mask */
mbed_official 80:bdf1132a57cf 320
mbed_official 80:bdf1132a57cf 321 #define CMSDK_DUALTIMER2_LOAD_Pos 0 /* CMSDK_DUALTIMER2 LOAD: LOAD Position */
mbed_official 80:bdf1132a57cf 322 #define CMSDK_DUALTIMER2_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_LOAD_Pos) /* CMSDK_DUALTIMER2 LOAD: LOAD Mask */
mbed_official 80:bdf1132a57cf 323
mbed_official 80:bdf1132a57cf 324 #define CMSDK_DUALTIMER2_VALUE_Pos 0 /* CMSDK_DUALTIMER2 VALUE: VALUE Position */
mbed_official 80:bdf1132a57cf 325 #define CMSDK_DUALTIMER2_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_VALUE_Pos) /* CMSDK_DUALTIMER2 VALUE: VALUE Mask */
mbed_official 80:bdf1132a57cf 326
mbed_official 80:bdf1132a57cf 327 #define CMSDK_DUALTIMER2_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Position */
mbed_official 80:bdf1132a57cf 328 #define CMSDK_DUALTIMER2_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_EN_Pos) /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Mask */
mbed_official 80:bdf1132a57cf 329
mbed_official 80:bdf1132a57cf 330 #define CMSDK_DUALTIMER2_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Position */
mbed_official 80:bdf1132a57cf 331 #define CMSDK_DUALTIMER2_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_MODE_Pos) /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Mask */
mbed_official 80:bdf1132a57cf 332
mbed_official 80:bdf1132a57cf 333 #define CMSDK_DUALTIMER2_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Position */
mbed_official 80:bdf1132a57cf 334 #define CMSDK_DUALTIMER2_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Mask */
mbed_official 80:bdf1132a57cf 335
mbed_official 80:bdf1132a57cf 336 #define CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Position */
mbed_official 80:bdf1132a57cf 337 #define CMSDK_DUALTIMER2_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Mask */
mbed_official 80:bdf1132a57cf 338
mbed_official 80:bdf1132a57cf 339 #define CMSDK_DUALTIMER2_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Position */
mbed_official 80:bdf1132a57cf 340 #define CMSDK_DUALTIMER2_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Mask */
mbed_official 80:bdf1132a57cf 341
mbed_official 80:bdf1132a57cf 342 #define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Position */
mbed_official 80:bdf1132a57cf 343 #define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
mbed_official 80:bdf1132a57cf 344
mbed_official 80:bdf1132a57cf 345 #define CMSDK_DUALTIMER2_INTCLR_Pos 0 /* CMSDK_DUALTIMER2 INTCLR: INT Clear Position */
mbed_official 80:bdf1132a57cf 346 #define CMSDK_DUALTIMER2_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER2_INTCLR_Pos) /* CMSDK_DUALTIMER2 INTCLR: INT Clear Mask */
mbed_official 80:bdf1132a57cf 347
mbed_official 80:bdf1132a57cf 348 #define CMSDK_DUALTIMER2_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Position */
mbed_official 80:bdf1132a57cf 349 #define CMSDK_DUALTIMER2_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Mask */
mbed_official 80:bdf1132a57cf 350
mbed_official 80:bdf1132a57cf 351 #define CMSDK_DUALTIMER2_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Position */
mbed_official 80:bdf1132a57cf 352 #define CMSDK_DUALTIMER2_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Mask */
mbed_official 80:bdf1132a57cf 353
mbed_official 80:bdf1132a57cf 354 #define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /* CMSDK_DUALTIMER2 BGLOAD: Background Load Position */
mbed_official 80:bdf1132a57cf 355 #define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */
mbed_official 80:bdf1132a57cf 356
mbed_official 80:bdf1132a57cf 357
mbed_official 80:bdf1132a57cf 358 typedef struct
mbed_official 80:bdf1132a57cf 359 {
mbed_official 80:bdf1132a57cf 360 __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */
mbed_official 80:bdf1132a57cf 361 __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */
mbed_official 80:bdf1132a57cf 362 __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */
mbed_official 80:bdf1132a57cf 363 __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */
mbed_official 80:bdf1132a57cf 364 __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */
mbed_official 80:bdf1132a57cf 365 __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */
mbed_official 80:bdf1132a57cf 366 __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */
mbed_official 80:bdf1132a57cf 367 } CMSDK_DUALTIMER_SINGLE_TypeDef;
mbed_official 80:bdf1132a57cf 368
mbed_official 80:bdf1132a57cf 369 #define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */
mbed_official 80:bdf1132a57cf 370 #define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_LOAD_Pos) /* CMSDK_DUALTIMER LOAD: LOAD Mask */
mbed_official 80:bdf1132a57cf 371
mbed_official 80:bdf1132a57cf 372 #define CMSDK_DUALTIMER_VALUE_Pos 0 /* CMSDK_DUALTIMER VALUE: VALUE Position */
mbed_official 80:bdf1132a57cf 373 #define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_VALUE_Pos) /* CMSDK_DUALTIMER VALUE: VALUE Mask */
mbed_official 80:bdf1132a57cf 374
mbed_official 80:bdf1132a57cf 375 #define CMSDK_DUALTIMER_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */
mbed_official 80:bdf1132a57cf 376 #define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_EN_Pos) /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */
mbed_official 80:bdf1132a57cf 377
mbed_official 80:bdf1132a57cf 378 #define CMSDK_DUALTIMER_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */
mbed_official 80:bdf1132a57cf 379 #define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_MODE_Pos) /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */
mbed_official 80:bdf1132a57cf 380
mbed_official 80:bdf1132a57cf 381 #define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */
mbed_official 80:bdf1132a57cf 382 #define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */
mbed_official 80:bdf1132a57cf 383
mbed_official 80:bdf1132a57cf 384 #define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */
mbed_official 80:bdf1132a57cf 385 #define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */
mbed_official 80:bdf1132a57cf 386
mbed_official 80:bdf1132a57cf 387 #define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */
mbed_official 80:bdf1132a57cf 388 #define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */
mbed_official 80:bdf1132a57cf 389
mbed_official 80:bdf1132a57cf 390 #define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */
mbed_official 80:bdf1132a57cf 391 #define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */
mbed_official 80:bdf1132a57cf 392
mbed_official 80:bdf1132a57cf 393 #define CMSDK_DUALTIMER_INTCLR_Pos 0 /* CMSDK_DUALTIMER INTCLR: INT Clear Position */
mbed_official 80:bdf1132a57cf 394 #define CMSDK_DUALTIMER_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER_INTCLR_Pos) /* CMSDK_DUALTIMER INTCLR: INT Clear Mask */
mbed_official 80:bdf1132a57cf 395
mbed_official 80:bdf1132a57cf 396 #define CMSDK_DUALTIMER_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */
mbed_official 80:bdf1132a57cf 397 #define CMSDK_DUALTIMER_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */
mbed_official 80:bdf1132a57cf 398
mbed_official 80:bdf1132a57cf 399 #define CMSDK_DUALTIMER_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */
mbed_official 80:bdf1132a57cf 400 #define CMSDK_DUALTIMER_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */
mbed_official 80:bdf1132a57cf 401
mbed_official 80:bdf1132a57cf 402 #define CMSDK_DUALTIMER_BGLOAD_Pos 0 /* CMSDK_DUALTIMER BGLOAD: Background Load Position */
mbed_official 80:bdf1132a57cf 403 #define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_BGLOAD_Pos) /* CMSDK_DUALTIMER BGLOAD: Background Load Mask */
mbed_official 80:bdf1132a57cf 404
mbed_official 80:bdf1132a57cf 405
mbed_official 80:bdf1132a57cf 406 /*-------------------- General Purpose Input Output (GPIO) -------------------*/
mbed_official 80:bdf1132a57cf 407 typedef struct
mbed_official 80:bdf1132a57cf 408 {
mbed_official 80:bdf1132a57cf 409 __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */
mbed_official 80:bdf1132a57cf 410 __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */
mbed_official 80:bdf1132a57cf 411 uint32_t RESERVED0[2];
mbed_official 80:bdf1132a57cf 412 __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */
mbed_official 80:bdf1132a57cf 413 __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */
mbed_official 80:bdf1132a57cf 414 __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */
mbed_official 80:bdf1132a57cf 415 __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */
mbed_official 80:bdf1132a57cf 416 __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */
mbed_official 80:bdf1132a57cf 417 __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */
mbed_official 80:bdf1132a57cf 418 __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */
mbed_official 80:bdf1132a57cf 419 __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */
mbed_official 80:bdf1132a57cf 420 __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */
mbed_official 80:bdf1132a57cf 421 __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */
mbed_official 80:bdf1132a57cf 422 union {
mbed_official 80:bdf1132a57cf 423 __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */
mbed_official 80:bdf1132a57cf 424 __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */
mbed_official 80:bdf1132a57cf 425 };
mbed_official 80:bdf1132a57cf 426 uint32_t RESERVED1[241];
mbed_official 80:bdf1132a57cf 427 __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */
mbed_official 80:bdf1132a57cf 428 __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */
mbed_official 80:bdf1132a57cf 429 } CMSDK_GPIO_TypeDef;
mbed_official 80:bdf1132a57cf 430
mbed_official 80:bdf1132a57cf 431 #define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */
mbed_official 80:bdf1132a57cf 432 #define CMSDK_GPIO_DATA_Msk (0xFFFFul << CMSDK_GPIO_DATA_Pos) /* CMSDK_GPIO DATA: DATA Mask */
mbed_official 80:bdf1132a57cf 433
mbed_official 80:bdf1132a57cf 434 #define CMSDK_GPIO_DATAOUT_Pos 0 /* CMSDK_GPIO DATAOUT: DATAOUT Position */
mbed_official 80:bdf1132a57cf 435 #define CMSDK_GPIO_DATAOUT_Msk (0xFFFFul << CMSDK_GPIO_DATAOUT_Pos) /* CMSDK_GPIO DATAOUT: DATAOUT Mask */
mbed_official 80:bdf1132a57cf 436
mbed_official 80:bdf1132a57cf 437 #define CMSDK_GPIO_OUTENSET_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */
mbed_official 80:bdf1132a57cf 438 #define CMSDK_GPIO_OUTENSET_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */
mbed_official 80:bdf1132a57cf 439
mbed_official 80:bdf1132a57cf 440 #define CMSDK_GPIO_OUTENCLR_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */
mbed_official 80:bdf1132a57cf 441 #define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */
mbed_official 80:bdf1132a57cf 442
mbed_official 80:bdf1132a57cf 443 #define CMSDK_GPIO_ALTFUNCSET_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
mbed_official 80:bdf1132a57cf 444 #define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
mbed_official 80:bdf1132a57cf 445
mbed_official 80:bdf1132a57cf 446 #define CMSDK_GPIO_ALTFUNCCLR_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
mbed_official 80:bdf1132a57cf 447 #define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
mbed_official 80:bdf1132a57cf 448
mbed_official 80:bdf1132a57cf 449 #define CMSDK_GPIO_INTENSET_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */
mbed_official 80:bdf1132a57cf 450 #define CMSDK_GPIO_INTENSET_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */
mbed_official 80:bdf1132a57cf 451
mbed_official 80:bdf1132a57cf 452 #define CMSDK_GPIO_INTENCLR_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */
mbed_official 80:bdf1132a57cf 453 #define CMSDK_GPIO_INTENCLR_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */
mbed_official 80:bdf1132a57cf 454
mbed_official 80:bdf1132a57cf 455 #define CMSDK_GPIO_INTTYPESET_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
mbed_official 80:bdf1132a57cf 456 #define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
mbed_official 80:bdf1132a57cf 457
mbed_official 80:bdf1132a57cf 458 #define CMSDK_GPIO_INTTYPECLR_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
mbed_official 80:bdf1132a57cf 459 #define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
mbed_official 80:bdf1132a57cf 460
mbed_official 80:bdf1132a57cf 461 #define CMSDK_GPIO_INTPOLSET_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */
mbed_official 80:bdf1132a57cf 462 #define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */
mbed_official 80:bdf1132a57cf 463
mbed_official 80:bdf1132a57cf 464 #define CMSDK_GPIO_INTPOLCLR_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */
mbed_official 80:bdf1132a57cf 465 #define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */
mbed_official 80:bdf1132a57cf 466
mbed_official 80:bdf1132a57cf 467 #define CMSDK_GPIO_INTSTATUS_Pos 0 /* CMSDK_GPIO INTSTATUS: INTSTATUS Position */
mbed_official 80:bdf1132a57cf 468 #define CMSDK_GPIO_INTSTATUS_Msk (0xFFul << CMSDK_GPIO_INTSTATUS_Pos) /* CMSDK_GPIO INTSTATUS: INTSTATUS Mask */
mbed_official 80:bdf1132a57cf 469
mbed_official 80:bdf1132a57cf 470 #define CMSDK_GPIO_INTCLEAR_Pos 0 /* CMSDK_GPIO INTCLEAR: INTCLEAR Position */
mbed_official 80:bdf1132a57cf 471 #define CMSDK_GPIO_INTCLEAR_Msk (0xFFul << CMSDK_GPIO_INTCLEAR_Pos) /* CMSDK_GPIO INTCLEAR: INTCLEAR Mask */
mbed_official 80:bdf1132a57cf 472
mbed_official 80:bdf1132a57cf 473 #define CMSDK_GPIO_MASKLOWBYTE_Pos 0 /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */
mbed_official 80:bdf1132a57cf 474 #define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFul << CMSDK_GPIO_MASKLOWBYTE_Pos) /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */
mbed_official 80:bdf1132a57cf 475
mbed_official 80:bdf1132a57cf 476 #define CMSDK_GPIO_MASKHIGHBYTE_Pos 0 /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */
mbed_official 80:bdf1132a57cf 477 #define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00ul << CMSDK_GPIO_MASKHIGHBYTE_Pos) /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */
mbed_official 80:bdf1132a57cf 478
mbed_official 80:bdf1132a57cf 479
mbed_official 80:bdf1132a57cf 480 /*------------- System Control (SYSCON) --------------------------------------*/
mbed_official 80:bdf1132a57cf 481 typedef struct
mbed_official 80:bdf1132a57cf 482 {
mbed_official 80:bdf1132a57cf 483 __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */
mbed_official 80:bdf1132a57cf 484 __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */
mbed_official 80:bdf1132a57cf 485 __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */
mbed_official 80:bdf1132a57cf 486 __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */
mbed_official 80:bdf1132a57cf 487 __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */
mbed_official 80:bdf1132a57cf 488 uint32_t RESERVED0[3];
mbed_official 80:bdf1132a57cf 489 __IO uint32_t AHBPER0SET; /* Offset: 0x020 (R/W)AHB peripheral access control set */
mbed_official 80:bdf1132a57cf 490 __IO uint32_t AHBPER0CLR; /* Offset: 0x024 (R/W)AHB peripheral access control clear */
mbed_official 80:bdf1132a57cf 491 uint32_t RESERVED1[2];
mbed_official 80:bdf1132a57cf 492 __IO uint32_t APBPER0SET; /* Offset: 0x030 (R/W)APB peripheral access control set */
mbed_official 80:bdf1132a57cf 493 __IO uint32_t APBPER0CLR; /* Offset: 0x034 (R/W)APB peripheral access control clear */
mbed_official 80:bdf1132a57cf 494 uint32_t RESERVED2[2];
mbed_official 80:bdf1132a57cf 495 __IO uint32_t MAINCLK; /* Offset: 0x040 (R/W) Main Clock Control Register */
mbed_official 80:bdf1132a57cf 496 __IO uint32_t AUXCLK; /* Offset: 0x044 (R/W) Auxiliary / RTC Control Register */
mbed_official 80:bdf1132a57cf 497 __IO uint32_t PLLCTRL; /* Offset: 0x048 (R/W) PLL Control Register */
mbed_official 80:bdf1132a57cf 498 __IO uint32_t PLLSTATUS; /* Offset: 0x04C (R/W) PLL Status Register */
mbed_official 80:bdf1132a57cf 499 __IO uint32_t SLEEPCFG; /* Offset: 0x050 (R/W) Sleep Control Register */
mbed_official 80:bdf1132a57cf 500 __IO uint32_t FLASHAUXCFG; /* Offset: 0x054 (R/W) Flash auxiliary settings Control Register */
mbed_official 80:bdf1132a57cf 501 uint32_t RESERVED3[10];
mbed_official 80:bdf1132a57cf 502 __IO uint32_t AHBCLKCFG0SET; /* Offset: 0x080 (R/W) AHB Peripheral Clock set in Active state */
mbed_official 80:bdf1132a57cf 503 __IO uint32_t AHBCLKCFG0CLR; /* Offset: 0x084 (R/W) AHB Peripheral Clock clear in Active state */
mbed_official 80:bdf1132a57cf 504 __IO uint32_t AHBCLKCFG1SET; /* Offset: 0x088 (R/W) AHB Peripheral Clock set in Sleep state */
mbed_official 80:bdf1132a57cf 505 __IO uint32_t AHBCLKCFG1CLR; /* Offset: 0x08C (R/W) AHB Peripheral Clock clear in Sleep state */
mbed_official 80:bdf1132a57cf 506 __IO uint32_t AHBCLKCFG2SET; /* Offset: 0x090 (R/W) AHB Peripheral Clock set in Deep Sleep state */
mbed_official 80:bdf1132a57cf 507 __IO uint32_t AHBCLKCFG2CLR; /* Offset: 0x094 (R/W) AHB Peripheral Clock clear in Deep Sleep state */
mbed_official 80:bdf1132a57cf 508 uint32_t RESERVED4[2];
mbed_official 80:bdf1132a57cf 509 __IO uint32_t APBCLKCFG0SET; /* Offset: 0x0A0 (R/W) APB Peripheral Clock set in Active state */
mbed_official 80:bdf1132a57cf 510 __IO uint32_t APBCLKCFG0CLR; /* Offset: 0x0A4 (R/W) APB Peripheral Clock clear in Active state */
mbed_official 80:bdf1132a57cf 511 __IO uint32_t APBCLKCFG1SET; /* Offset: 0x0A8 (R/W) APB Peripheral Clock set in Sleep state */
mbed_official 80:bdf1132a57cf 512 __IO uint32_t APBCLKCFG1CLR; /* Offset: 0x0AC (R/W) APB Peripheral Clock clear in Sleep state */
mbed_official 80:bdf1132a57cf 513 __IO uint32_t APBCLKCFG2SET; /* Offset: 0x0B0 (R/W) APB Peripheral Clock set in Deep Sleep state */
mbed_official 80:bdf1132a57cf 514 __IO uint32_t APBCLKCFG2CLR; /* Offset: 0x0B4 (R/W) APB Peripheral Clock clear in Deep Sleep state */
mbed_official 80:bdf1132a57cf 515 uint32_t RESERVED5[2];
mbed_official 80:bdf1132a57cf 516 __IO uint32_t AHBPRST0SET; /* Offset: 0x0C0 (R/W) AHB Peripheral reset select set */
mbed_official 80:bdf1132a57cf 517 __IO uint32_t AHBPRST0CLR; /* Offset: 0x0C4 (R/W) AHB Peripheral reset select clear */
mbed_official 80:bdf1132a57cf 518 __IO uint32_t APBPRST0SET; /* Offset: 0x0C8 (R/W) APB Peripheral reset select set */
mbed_official 80:bdf1132a57cf 519 __IO uint32_t APBPRST0CLR; /* Offset: 0x0CC (R/W) APB Peripheral reset select clear */
mbed_official 80:bdf1132a57cf 520 __IO uint32_t PWRDNCFG0SET; /* Offset: 0x0D0 (R/W) AHB Power down sleep wakeup source set */
mbed_official 80:bdf1132a57cf 521 __IO uint32_t PWRDNCFG0CLR; /* Offset: 0x0D4 (R/W) AHB Power down sleep wakeup source clear */
mbed_official 80:bdf1132a57cf 522 __IO uint32_t PWRDNCFG1SET; /* Offset: 0x0D8 (R/W) APB Power down sleep wakeup source set */
mbed_official 80:bdf1132a57cf 523 __IO uint32_t PWRDNCFG1CLR; /* Offset: 0x0DC (R/W) APB Power down sleep wakeup source clear */
mbed_official 80:bdf1132a57cf 524 __O uint32_t RTCRESET; /* Offset: 0x0E0 ( /W) RTC reset */
mbed_official 80:bdf1132a57cf 525 __IO uint32_t EVENTCFG; /* Offset: 0x0E4 (R/W) Event interface Control Register */
mbed_official 80:bdf1132a57cf 526 uint32_t RESERVED6[2];
mbed_official 80:bdf1132a57cf 527 __IO uint32_t PWROVRIDE0; /* Offset: 0x0F0 (R/W) SRAM Power control overide */
mbed_official 80:bdf1132a57cf 528 __IO uint32_t PWROVRIDE1; /* Offset: 0x0F4 (R/W) Embedded Flash Power control overide */
mbed_official 80:bdf1132a57cf 529 __I uint32_t MEMORYSTATUS; /* Offset: 0x0F8 (R/ ) Memory Status Register */
mbed_official 80:bdf1132a57cf 530 uint32_t RESERVED7[1];
mbed_official 80:bdf1132a57cf 531 __IO uint32_t GPIOPADCFG0; /* Offset: 0x100 (R/W) IO pad settings */
mbed_official 80:bdf1132a57cf 532 __IO uint32_t GPIOPADCFG1; /* Offset: 0x104 (R/W) IO pad settings */
mbed_official 80:bdf1132a57cf 533 __IO uint32_t TESTMODECFG; /* Offset: 0x108 (R/W) Testmode boot bypass */
mbed_official 80:bdf1132a57cf 534 } CMSDK_SYSCON_TypeDef;
mbed_official 80:bdf1132a57cf 535
mbed_official 80:bdf1132a57cf 536 #define CMSDK_SYSCON_REMAP_Pos 0
mbed_official 80:bdf1132a57cf 537 #define CMSDK_SYSCON_REMAP_Msk (0x01ul << CMSDK_SYSCON_REMAP_Pos) /* CMSDK_SYSCON MEME_CTRL: REMAP Mask */
mbed_official 80:bdf1132a57cf 538
mbed_official 80:bdf1132a57cf 539 #define CMSDK_SYSCON_PMUCTRL_EN_Pos 0
mbed_official 80:bdf1132a57cf 540 #define CMSDK_SYSCON_PMUCTRL_EN_Msk (0x01ul << CMSDK_SYSCON_PMUCTRL_EN_Pos) /* CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask */
mbed_official 80:bdf1132a57cf 541
mbed_official 80:bdf1132a57cf 542 #define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos 0
mbed_official 80:bdf1132a57cf 543 #define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk (0x01ul << CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos) /* CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask */
mbed_official 80:bdf1132a57cf 544
mbed_official 80:bdf1132a57cf 545 #define CMSDK_SYSCON_EMICTRL_SIZE_Pos 24
mbed_official 80:bdf1132a57cf 546 #define CMSDK_SYSCON_EMICTRL_SIZE_Msk (0x00001ul << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /* CMSDK_SYSCON EMICTRL: SIZE Mask */
mbed_official 80:bdf1132a57cf 547
mbed_official 80:bdf1132a57cf 548 #define CMSDK_SYSCON_EMICTRL_TACYC_Pos 16
mbed_official 80:bdf1132a57cf 549 #define CMSDK_SYSCON_EMICTRL_TACYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /* CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask */
mbed_official 80:bdf1132a57cf 550
mbed_official 80:bdf1132a57cf 551 #define CMSDK_SYSCON_EMICTRL_WCYC_Pos 8
mbed_official 80:bdf1132a57cf 552 #define CMSDK_SYSCON_EMICTRL_WCYC_Msk (0x00003ul << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /* CMSDK_SYSCON EMICTRL: WRITECYCLE Mask */
mbed_official 80:bdf1132a57cf 553
mbed_official 80:bdf1132a57cf 554 #define CMSDK_SYSCON_EMICTRL_RCYC_Pos 0
mbed_official 80:bdf1132a57cf 555 #define CMSDK_SYSCON_EMICTRL_RCYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_RCYC_Pos) /* CMSDK_SYSCON EMICTRL: READCYCLE Mask */
mbed_official 80:bdf1132a57cf 556
mbed_official 80:bdf1132a57cf 557 #define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos 0
mbed_official 80:bdf1132a57cf 558 #define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask */
mbed_official 80:bdf1132a57cf 559
mbed_official 80:bdf1132a57cf 560 #define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos 1
mbed_official 80:bdf1132a57cf 561 #define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask */
mbed_official 80:bdf1132a57cf 562
mbed_official 80:bdf1132a57cf 563 #define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2
mbed_official 80:bdf1132a57cf 564 #define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /* CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */
mbed_official 80:bdf1132a57cf 565
mbed_official 80:bdf1132a57cf 566
mbed_official 80:bdf1132a57cf 567 /*------------- PL230 uDMA (PL230) --------------------------------------*/
mbed_official 80:bdf1132a57cf 568 typedef struct
mbed_official 80:bdf1132a57cf 569 {
mbed_official 80:bdf1132a57cf 570 __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */
mbed_official 80:bdf1132a57cf 571 __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */
mbed_official 80:bdf1132a57cf 572 __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */
mbed_official 80:bdf1132a57cf 573 __I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */
mbed_official 80:bdf1132a57cf 574 __I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */
mbed_official 80:bdf1132a57cf 575 __O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */
mbed_official 80:bdf1132a57cf 576 __IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */
mbed_official 80:bdf1132a57cf 577 __O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */
mbed_official 80:bdf1132a57cf 578 __IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */
mbed_official 80:bdf1132a57cf 579 __O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */
mbed_official 80:bdf1132a57cf 580 __IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */
mbed_official 80:bdf1132a57cf 581 __O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */
mbed_official 80:bdf1132a57cf 582 __IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */
mbed_official 80:bdf1132a57cf 583 __O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */
mbed_official 80:bdf1132a57cf 584 __IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */
mbed_official 80:bdf1132a57cf 585 __O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */
mbed_official 80:bdf1132a57cf 586 uint32_t RESERVED0[3];
mbed_official 80:bdf1132a57cf 587 __IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */
mbed_official 80:bdf1132a57cf 588
mbed_official 80:bdf1132a57cf 589 } CMSDK_PL230_TypeDef;
mbed_official 80:bdf1132a57cf 590
mbed_official 80:bdf1132a57cf 591 #define PL230_DMA_CHNL_BITS 0
mbed_official 80:bdf1132a57cf 592
mbed_official 80:bdf1132a57cf 593 #define CMSDK_PL230_DMA_STATUS_MSTREN_Pos 0 /* CMSDK_PL230 DMA STATUS: MSTREN Position */
mbed_official 80:bdf1132a57cf 594 #define CMSDK_PL230_DMA_STATUS_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_MSTREN_Pos) /* CMSDK_PL230 DMA STATUS: MSTREN Mask */
mbed_official 80:bdf1132a57cf 595
mbed_official 80:bdf1132a57cf 596 #define CMSDK_PL230_DMA_STATUS_STATE_Pos 0 /* CMSDK_PL230 DMA STATUS: STATE Position */
mbed_official 80:bdf1132a57cf 597 #define CMSDK_PL230_DMA_STATUS_STATE_Msk (0x0000000Ful << CMSDK_PL230_DMA_STATUS_STATE_Pos) /* CMSDK_PL230 DMA STATUS: STATE Mask */
mbed_official 80:bdf1132a57cf 598
mbed_official 80:bdf1132a57cf 599 #define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos 0 /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Position */
mbed_official 80:bdf1132a57cf 600 #define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Msk (0x0000001Ful << CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos) /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Mask */
mbed_official 80:bdf1132a57cf 601
mbed_official 80:bdf1132a57cf 602 #define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos 0 /* CMSDK_PL230 DMA STATUS: TEST_STATUS Position */
mbed_official 80:bdf1132a57cf 603 #define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos) /* CMSDK_PL230 DMA STATUS: TEST_STATUS Mask */
mbed_official 80:bdf1132a57cf 604
mbed_official 80:bdf1132a57cf 605 #define CMSDK_PL230_DMA_CFG_MSTREN_Pos 0 /* CMSDK_PL230 DMA CFG: MSTREN Position */
mbed_official 80:bdf1132a57cf 606 #define CMSDK_PL230_DMA_CFG_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_MSTREN_Pos) /* CMSDK_PL230 DMA CFG: MSTREN Mask */
mbed_official 80:bdf1132a57cf 607
mbed_official 80:bdf1132a57cf 608 #define CMSDK_PL230_DMA_CFG_CPCCACHE_Pos 2 /* CMSDK_PL230 DMA CFG: CPCCACHE Position */
mbed_official 80:bdf1132a57cf 609 #define CMSDK_PL230_DMA_CFG_CPCCACHE_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCCACHE_Pos) /* CMSDK_PL230 DMA CFG: CPCCACHE Mask */
mbed_official 80:bdf1132a57cf 610
mbed_official 80:bdf1132a57cf 611 #define CMSDK_PL230_DMA_CFG_CPCBUF_Pos 1 /* CMSDK_PL230 DMA CFG: CPCBUF Position */
mbed_official 80:bdf1132a57cf 612 #define CMSDK_PL230_DMA_CFG_CPCBUF_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCBUF_Pos) /* CMSDK_PL230 DMA CFG: CPCBUF Mask */
mbed_official 80:bdf1132a57cf 613
mbed_official 80:bdf1132a57cf 614 #define CMSDK_PL230_DMA_CFG_CPCPRIV_Pos 0 /* CMSDK_PL230 DMA CFG: CPCPRIV Position */
mbed_official 80:bdf1132a57cf 615 #define CMSDK_PL230_DMA_CFG_CPCPRIV_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCPRIV_Pos) /* CMSDK_PL230 DMA CFG: CPCPRIV Mask */
mbed_official 80:bdf1132a57cf 616
mbed_official 80:bdf1132a57cf 617 #define CMSDK_PL230_CTRL_BASE_PTR_Pos PL230_DMA_CHNL_BITS + 5 /* CMSDK_PL230 STATUS: BASE_PTR Position */
mbed_official 80:bdf1132a57cf 618 #define CMSDK_PL230_CTRL_BASE_PTR_Msk (0x0FFFFFFFul << CMSDK_PL230_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: BASE_PTR Mask */
mbed_official 80:bdf1132a57cf 619
mbed_official 80:bdf1132a57cf 620 #define CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos 0 /* CMSDK_PL230 STATUS: MSTREN Position */
mbed_official 80:bdf1132a57cf 621 #define CMSDK_PL230_ALT_CTRL_BASE_PTR_Msk (0xFFFFFFFFul << CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: MSTREN Mask */
mbed_official 80:bdf1132a57cf 622
mbed_official 80:bdf1132a57cf 623 #define CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos 0 /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Position */
mbed_official 80:bdf1132a57cf 624 #define CMSDK_PL230_DMA_WAITONREQ_STATUS_Msk (0xFFFFFFFFul << CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos) /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Mask */
mbed_official 80:bdf1132a57cf 625
mbed_official 80:bdf1132a57cf 626 #define CMSDK_PL230_CHNL_SW_REQUEST_Pos 0 /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Position */
mbed_official 80:bdf1132a57cf 627 #define CMSDK_PL230_CHNL_SW_REQUEST_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_SW_REQUEST_Pos) /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Mask */
mbed_official 80:bdf1132a57cf 628
mbed_official 80:bdf1132a57cf 629 #define CMSDK_PL230_CHNL_USEBURST_SET_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: SET Position */
mbed_official 80:bdf1132a57cf 630 #define CMSDK_PL230_CHNL_USEBURST_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_SET_Pos) /* CMSDK_PL230 CHNL_USEBURST: SET Mask */
mbed_official 80:bdf1132a57cf 631
mbed_official 80:bdf1132a57cf 632 #define CMSDK_PL230_CHNL_USEBURST_CLR_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: CLR Position */
mbed_official 80:bdf1132a57cf 633 #define CMSDK_PL230_CHNL_USEBURST_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_CLR_Pos) /* CMSDK_PL230 CHNL_USEBURST: CLR Mask */
mbed_official 80:bdf1132a57cf 634
mbed_official 80:bdf1132a57cf 635 #define CMSDK_PL230_CHNL_REQ_MASK_SET_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: SET Position */
mbed_official 80:bdf1132a57cf 636 #define CMSDK_PL230_CHNL_REQ_MASK_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_SET_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: SET Mask */
mbed_official 80:bdf1132a57cf 637
mbed_official 80:bdf1132a57cf 638 #define CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: CLR Position */
mbed_official 80:bdf1132a57cf 639 #define CMSDK_PL230_CHNL_REQ_MASK_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: CLR Mask */
mbed_official 80:bdf1132a57cf 640
mbed_official 80:bdf1132a57cf 641 #define CMSDK_PL230_CHNL_ENABLE_SET_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: SET Position */
mbed_official 80:bdf1132a57cf 642 #define CMSDK_PL230_CHNL_ENABLE_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_SET_Pos) /* CMSDK_PL230 CHNL_ENABLE: SET Mask */
mbed_official 80:bdf1132a57cf 643
mbed_official 80:bdf1132a57cf 644 #define CMSDK_PL230_CHNL_ENABLE_CLR_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: CLR Position */
mbed_official 80:bdf1132a57cf 645 #define CMSDK_PL230_CHNL_ENABLE_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_CLR_Pos) /* CMSDK_PL230 CHNL_ENABLE: CLR Mask */
mbed_official 80:bdf1132a57cf 646
mbed_official 80:bdf1132a57cf 647 #define CMSDK_PL230_CHNL_PRI_ALT_SET_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: SET Position */
mbed_official 80:bdf1132a57cf 648 #define CMSDK_PL230_CHNL_PRI_ALT_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_SET_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: SET Mask */
mbed_official 80:bdf1132a57cf 649
mbed_official 80:bdf1132a57cf 650 #define CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: CLR Position */
mbed_official 80:bdf1132a57cf 651 #define CMSDK_PL230_CHNL_PRI_ALT_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: CLR Mask */
mbed_official 80:bdf1132a57cf 652
mbed_official 80:bdf1132a57cf 653 #define CMSDK_PL230_CHNL_PRIORITY_SET_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: SET Position */
mbed_official 80:bdf1132a57cf 654 #define CMSDK_PL230_CHNL_PRIORITY_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_SET_Pos) /* CMSDK_PL230 CHNL_PRIORITY: SET Mask */
mbed_official 80:bdf1132a57cf 655
mbed_official 80:bdf1132a57cf 656 #define CMSDK_PL230_CHNL_PRIORITY_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: CLR Position */
mbed_official 80:bdf1132a57cf 657 #define CMSDK_PL230_CHNL_PRIORITY_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_CLR_Pos) /* CMSDK_PL230 CHNL_PRIORITY: CLR Mask */
mbed_official 80:bdf1132a57cf 658
mbed_official 80:bdf1132a57cf 659 #define CMSDK_PL230_ERR_CLR_Pos 0 /* CMSDK_PL230 ERR: CLR Position */
mbed_official 80:bdf1132a57cf 660 #define CMSDK_PL230_ERR_CLR_Msk (0x00000001ul << CMSDK_PL230_ERR_CLR_Pos) /* CMSDK_PL230 ERR: CLR Mask */
mbed_official 80:bdf1132a57cf 661
mbed_official 80:bdf1132a57cf 662
mbed_official 80:bdf1132a57cf 663 /*------------------- Watchdog ----------------------------------------------*/
mbed_official 80:bdf1132a57cf 664 typedef struct
mbed_official 80:bdf1132a57cf 665 {
mbed_official 80:bdf1132a57cf 666
mbed_official 80:bdf1132a57cf 667 __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */
mbed_official 80:bdf1132a57cf 668 __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */
mbed_official 80:bdf1132a57cf 669 __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */
mbed_official 80:bdf1132a57cf 670 __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */
mbed_official 80:bdf1132a57cf 671 __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */
mbed_official 80:bdf1132a57cf 672 __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */
mbed_official 80:bdf1132a57cf 673 uint32_t RESERVED0[762];
mbed_official 80:bdf1132a57cf 674 __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */
mbed_official 80:bdf1132a57cf 675 uint32_t RESERVED1[191];
mbed_official 80:bdf1132a57cf 676 __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */
mbed_official 80:bdf1132a57cf 677 __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */
mbed_official 80:bdf1132a57cf 678 }CMSDK_WATCHDOG_TypeDef;
mbed_official 80:bdf1132a57cf 679
mbed_official 80:bdf1132a57cf 680 #define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */
mbed_official 80:bdf1132a57cf 681 #define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */
mbed_official 80:bdf1132a57cf 682
mbed_official 80:bdf1132a57cf 683 #define CMSDK_Watchdog_VALUE_Pos 0 /* CMSDK_Watchdog VALUE: VALUE Position */
mbed_official 80:bdf1132a57cf 684 #define CMSDK_Watchdog_VALUE_Msk (0xFFFFFFFFul << CMSDK_Watchdog_VALUE_Pos) /* CMSDK_Watchdog VALUE: VALUE Mask */
mbed_official 80:bdf1132a57cf 685
mbed_official 80:bdf1132a57cf 686 #define CMSDK_Watchdog_CTRL_RESEN_Pos 1 /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position */
mbed_official 80:bdf1132a57cf 687 #define CMSDK_Watchdog_CTRL_RESEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_RESEN_Pos) /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask */
mbed_official 80:bdf1132a57cf 688
mbed_official 80:bdf1132a57cf 689 #define CMSDK_Watchdog_CTRL_INTEN_Pos 0 /* CMSDK_Watchdog CTRL_INTEN: Int Enable Position */
mbed_official 80:bdf1132a57cf 690 #define CMSDK_Watchdog_CTRL_INTEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_INTEN_Pos) /* CMSDK_Watchdog CTRL_INTEN: Int Enable Mask */
mbed_official 80:bdf1132a57cf 691
mbed_official 80:bdf1132a57cf 692 #define CMSDK_Watchdog_INTCLR_Pos 0 /* CMSDK_Watchdog INTCLR: Int Clear Position */
mbed_official 80:bdf1132a57cf 693 #define CMSDK_Watchdog_INTCLR_Msk (0x1ul << CMSDK_Watchdog_INTCLR_Pos) /* CMSDK_Watchdog INTCLR: Int Clear Mask */
mbed_official 80:bdf1132a57cf 694
mbed_official 80:bdf1132a57cf 695 #define CMSDK_Watchdog_RAWINTSTAT_Pos 0 /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position */
mbed_official 80:bdf1132a57cf 696 #define CMSDK_Watchdog_RAWINTSTAT_Msk (0x1ul << CMSDK_Watchdog_RAWINTSTAT_Pos) /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask */
mbed_official 80:bdf1132a57cf 697
mbed_official 80:bdf1132a57cf 698 #define CMSDK_Watchdog_MASKINTSTAT_Pos 0 /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position */
mbed_official 80:bdf1132a57cf 699 #define CMSDK_Watchdog_MASKINTSTAT_Msk (0x1ul << CMSDK_Watchdog_MASKINTSTAT_Pos) /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask */
mbed_official 80:bdf1132a57cf 700
mbed_official 80:bdf1132a57cf 701 #define CMSDK_Watchdog_LOCK_Pos 0 /* CMSDK_Watchdog LOCK: LOCK Position */
mbed_official 80:bdf1132a57cf 702 #define CMSDK_Watchdog_LOCK_Msk (0x1ul << CMSDK_Watchdog_LOCK_Pos) /* CMSDK_Watchdog LOCK: LOCK Mask */
mbed_official 80:bdf1132a57cf 703
mbed_official 80:bdf1132a57cf 704 #define CMSDK_Watchdog_INTEGTESTEN_Pos 0 /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position */
mbed_official 80:bdf1132a57cf 705 #define CMSDK_Watchdog_INTEGTESTEN_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTEN_Pos) /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask */
mbed_official 80:bdf1132a57cf 706
mbed_official 80:bdf1132a57cf 707 #define CMSDK_Watchdog_INTEGTESTOUTSET_Pos 1 /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position */
mbed_official 80:bdf1132a57cf 708 #define CMSDK_Watchdog_INTEGTESTOUTSET_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTOUTSET_Pos) /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask */
mbed_official 80:bdf1132a57cf 709
mbed_official 80:bdf1132a57cf 710
mbed_official 80:bdf1132a57cf 711
mbed_official 80:bdf1132a57cf 712 /* -------------------- End of section using anonymous unions ------------------- */
mbed_official 80:bdf1132a57cf 713 #if defined ( __CC_ARM )
mbed_official 80:bdf1132a57cf 714 #pragma pop
mbed_official 80:bdf1132a57cf 715 #elif defined(__ICCARM__)
mbed_official 80:bdf1132a57cf 716 /* leave anonymous unions enabled */
mbed_official 80:bdf1132a57cf 717 #elif defined(__GNUC__)
mbed_official 80:bdf1132a57cf 718 /* anonymous unions are enabled by default */
mbed_official 80:bdf1132a57cf 719 #elif defined(__TMS470__)
mbed_official 80:bdf1132a57cf 720 /* anonymous unions are enabled by default */
mbed_official 80:bdf1132a57cf 721 #elif defined(__TASKING__)
mbed_official 80:bdf1132a57cf 722 #pragma warning restore
mbed_official 80:bdf1132a57cf 723 #else
mbed_official 80:bdf1132a57cf 724 #warning Not supported compiler type
mbed_official 80:bdf1132a57cf 725 #endif
mbed_official 80:bdf1132a57cf 726
mbed_official 80:bdf1132a57cf 727
mbed_official 80:bdf1132a57cf 728
mbed_official 80:bdf1132a57cf 729
mbed_official 80:bdf1132a57cf 730 /* ================================================================================ */
mbed_official 80:bdf1132a57cf 731 /* ================ Peripheral memory map ================ */
mbed_official 80:bdf1132a57cf 732 /* ================================================================================ */
mbed_official 80:bdf1132a57cf 733
mbed_official 80:bdf1132a57cf 734 /* Peripheral and SRAM base address */
mbed_official 80:bdf1132a57cf 735 #define CMSDK_FLASH_BASE (0x00000000UL)
mbed_official 80:bdf1132a57cf 736 #define CMSDK_SRAM_BASE (0x20000000UL)
mbed_official 80:bdf1132a57cf 737 #define CMSDK_PERIPH_BASE (0x40000000UL)
mbed_official 80:bdf1132a57cf 738
mbed_official 80:bdf1132a57cf 739 #define CMSDK_RAM_BASE (0x20000000UL)
mbed_official 80:bdf1132a57cf 740 #define CMSDK_APB_BASE (0x40000000UL)
mbed_official 80:bdf1132a57cf 741 #define CMSDK_AHB_BASE (0x40010000UL)
mbed_official 80:bdf1132a57cf 742
mbed_official 80:bdf1132a57cf 743 /* APB peripherals */
mbed_official 80:bdf1132a57cf 744 #define CMSDK_TIMER0_BASE (CMSDK_APB_BASE + 0x0000UL)
mbed_official 80:bdf1132a57cf 745 #define CMSDK_TIMER1_BASE (CMSDK_APB_BASE + 0x1000UL)
mbed_official 80:bdf1132a57cf 746 #define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0x2000UL)
mbed_official 80:bdf1132a57cf 747 #define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE)
mbed_official 80:bdf1132a57cf 748 #define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL)
mbed_official 80:bdf1132a57cf 749 #define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL)
mbed_official 80:bdf1132a57cf 750 #define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL)
mbed_official 80:bdf1132a57cf 751 #define CMSDK_UART2_BASE (0x4002C000UL)
mbed_official 80:bdf1132a57cf 752 #define CMSDK_UART3_BASE (0x4002D000UL)
mbed_official 80:bdf1132a57cf 753 #define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL)
mbed_official 80:bdf1132a57cf 754
mbed_official 80:bdf1132a57cf 755 /* AHB peripherals */
mbed_official 80:bdf1132a57cf 756 #define CMSDK_GPIO0_BASE (CMSDK_AHB_BASE + 0x0000UL)
mbed_official 80:bdf1132a57cf 757 #define CMSDK_GPIO1_BASE (CMSDK_AHB_BASE + 0x1000UL)
mbed_official 80:bdf1132a57cf 758 #define CMSDK_GPIO2_BASE (CMSDK_AHB_BASE + 0x2000UL)
mbed_official 80:bdf1132a57cf 759 #define CMSDK_GPIO3_BASE (CMSDK_AHB_BASE + 0x3000UL)
mbed_official 80:bdf1132a57cf 760 #define CMSDK_GPIO4_BASE (0x40030000UL)
mbed_official 80:bdf1132a57cf 761 #define CMSDK_GPIO5_BASE (0x40031000UL)
mbed_official 80:bdf1132a57cf 762 #define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0xF000UL)
mbed_official 80:bdf1132a57cf 763
mbed_official 80:bdf1132a57cf 764
mbed_official 80:bdf1132a57cf 765 /* ================================================================================ */
mbed_official 80:bdf1132a57cf 766 /* ================ Peripheral declaration ================ */
mbed_official 80:bdf1132a57cf 767 /* ================================================================================ */
mbed_official 80:bdf1132a57cf 768
mbed_official 80:bdf1132a57cf 769 #define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE )
mbed_official 80:bdf1132a57cf 770 #define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE )
mbed_official 80:bdf1132a57cf 771 #define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE )
mbed_official 80:bdf1132a57cf 772 #define CMSDK_UART3 ((CMSDK_UART_TypeDef *) CMSDK_UART3_BASE )
mbed_official 80:bdf1132a57cf 773 #define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE )
mbed_official 80:bdf1132a57cf 774 #define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE )
mbed_official 80:bdf1132a57cf 775 #define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE )
mbed_official 80:bdf1132a57cf 776 #define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE )
mbed_official 80:bdf1132a57cf 777 #define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE )
mbed_official 80:bdf1132a57cf 778 #define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE )
mbed_official 80:bdf1132a57cf 779 //#define CMSDK_DMA ((CMSDK_PL230_TypeDef *) CMSDK_PL230_BASE )
mbed_official 80:bdf1132a57cf 780 #define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE )
mbed_official 80:bdf1132a57cf 781 #define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE )
mbed_official 80:bdf1132a57cf 782 #define CMSDK_GPIO2 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO2_BASE )
mbed_official 80:bdf1132a57cf 783 #define CMSDK_GPIO3 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO3_BASE )
mbed_official 80:bdf1132a57cf 784 #define CMSDK_GPIO4 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO4_BASE )
mbed_official 80:bdf1132a57cf 785 #define CMSDK_GPIO5 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO5_BASE )
mbed_official 80:bdf1132a57cf 786 #define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE )
mbed_official 80:bdf1132a57cf 787
mbed_official 80:bdf1132a57cf 788
mbed_official 80:bdf1132a57cf 789 #ifdef __cplusplus
mbed_official 80:bdf1132a57cf 790 }
mbed_official 80:bdf1132a57cf 791 #endif
mbed_official 80:bdf1132a57cf 792
mbed_official 80:bdf1132a57cf 793 #endif /* CMSDK_BEID_H */