Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_timer.c@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 2 * @file em_timer.c
<> 144:ef7eb2e8f9f7 3 * @brief Timer/counter (TIMER) Peripheral API
<> 144:ef7eb2e8f9f7 4 * @version 4.2.1
<> 144:ef7eb2e8f9f7 5 *******************************************************************************
<> 144:ef7eb2e8f9f7 6 * @section License
<> 144:ef7eb2e8f9f7 7 * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
<> 144:ef7eb2e8f9f7 8 *******************************************************************************
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Permission is granted to anyone to use this software for any purpose,
<> 144:ef7eb2e8f9f7 11 * including commercial applications, and to alter it and redistribute it
<> 144:ef7eb2e8f9f7 12 * freely, subject to the following restrictions:
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * 1. The origin of this software must not be misrepresented; you must not
<> 144:ef7eb2e8f9f7 15 * claim that you wrote the original software.
<> 144:ef7eb2e8f9f7 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 144:ef7eb2e8f9f7 17 * misrepresented as being the original software.
<> 144:ef7eb2e8f9f7 18 * 3. This notice may not be removed or altered from any source distribution.
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
<> 144:ef7eb2e8f9f7 21 * obligation to support this Software. Silicon Labs is providing the
<> 144:ef7eb2e8f9f7 22 * Software "AS IS", with no express or implied warranties of any kind,
<> 144:ef7eb2e8f9f7 23 * including, but not limited to, any implied warranties of merchantability
<> 144:ef7eb2e8f9f7 24 * or fitness for any particular purpose or warranties against infringement
<> 144:ef7eb2e8f9f7 25 * of any proprietary rights of a third party.
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * Silicon Labs will not be liable for any consequential, incidental, or
<> 144:ef7eb2e8f9f7 28 * special damages, or any other relief, or for any claim by any third party,
<> 144:ef7eb2e8f9f7 29 * arising from your use of this Software.
<> 144:ef7eb2e8f9f7 30 *
<> 144:ef7eb2e8f9f7 31 ******************************************************************************/
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 #include "em_timer.h"
<> 144:ef7eb2e8f9f7 34 #if defined(TIMER_COUNT) && (TIMER_COUNT > 0)
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 #include "em_assert.h"
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 39 * @addtogroup EM_Library
<> 144:ef7eb2e8f9f7 40 * @{
<> 144:ef7eb2e8f9f7 41 ******************************************************************************/
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 44 * @addtogroup TIMER
<> 144:ef7eb2e8f9f7 45 * @brief Timer/Counter (TIMER) Peripheral API
<> 144:ef7eb2e8f9f7 46 * @details
<> 144:ef7eb2e8f9f7 47 * The timer module consists of three main parts:
<> 144:ef7eb2e8f9f7 48 * @li General timer config and enable control.
<> 144:ef7eb2e8f9f7 49 * @li Compare/capture control.
<> 144:ef7eb2e8f9f7 50 * @li Dead time insertion control (may not be available for all timers).
<> 144:ef7eb2e8f9f7 51 * @{
<> 144:ef7eb2e8f9f7 52 ******************************************************************************/
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /*******************************************************************************
<> 144:ef7eb2e8f9f7 56 ************************** GLOBAL FUNCTIONS *******************************
<> 144:ef7eb2e8f9f7 57 ******************************************************************************/
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 60 * @brief
<> 144:ef7eb2e8f9f7 61 * Initialize TIMER.
<> 144:ef7eb2e8f9f7 62 *
<> 144:ef7eb2e8f9f7 63 * @details
<> 144:ef7eb2e8f9f7 64 * Notice that counter top must be configured separately with for instance
<> 144:ef7eb2e8f9f7 65 * TIMER_TopSet(). In addition, compare/capture and dead-time insertion
<> 144:ef7eb2e8f9f7 66 * init must be initialized separately if used. That should probably
<> 144:ef7eb2e8f9f7 67 * be done prior to the use of this function if configuring the TIMER to
<> 144:ef7eb2e8f9f7 68 * start when initialization is completed.
<> 144:ef7eb2e8f9f7 69 *
<> 144:ef7eb2e8f9f7 70 * @param[in] timer
<> 144:ef7eb2e8f9f7 71 * Pointer to TIMER peripheral register block.
<> 144:ef7eb2e8f9f7 72 *
<> 144:ef7eb2e8f9f7 73 * @param[in] init
<> 144:ef7eb2e8f9f7 74 * Pointer to TIMER initialization structure.
<> 144:ef7eb2e8f9f7 75 ******************************************************************************/
<> 144:ef7eb2e8f9f7 76 void TIMER_Init(TIMER_TypeDef *timer, const TIMER_Init_TypeDef *init)
<> 144:ef7eb2e8f9f7 77 {
<> 144:ef7eb2e8f9f7 78 EFM_ASSERT(TIMER_REF_VALID(timer));
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 /* Stop timer if specified to be disabled (dosn't hurt if already stopped) */
<> 144:ef7eb2e8f9f7 81 if (!(init->enable))
<> 144:ef7eb2e8f9f7 82 {
<> 144:ef7eb2e8f9f7 83 timer->CMD = TIMER_CMD_STOP;
<> 144:ef7eb2e8f9f7 84 }
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 /* Reset counter */
<> 144:ef7eb2e8f9f7 87 timer->CNT = _TIMER_CNT_RESETVALUE;
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 timer->CTRL = ((uint32_t)(init->prescale) << _TIMER_CTRL_PRESC_SHIFT)
<> 144:ef7eb2e8f9f7 90 | ((uint32_t)(init->clkSel) << _TIMER_CTRL_CLKSEL_SHIFT)
<> 144:ef7eb2e8f9f7 91 | ((uint32_t)(init->fallAction) << _TIMER_CTRL_FALLA_SHIFT)
<> 144:ef7eb2e8f9f7 92 | ((uint32_t)(init->riseAction) << _TIMER_CTRL_RISEA_SHIFT)
<> 144:ef7eb2e8f9f7 93 | ((uint32_t)(init->mode) << _TIMER_CTRL_MODE_SHIFT)
<> 144:ef7eb2e8f9f7 94 | (init->debugRun ? TIMER_CTRL_DEBUGRUN : 0)
<> 144:ef7eb2e8f9f7 95 | (init->dmaClrAct ? TIMER_CTRL_DMACLRACT : 0)
<> 144:ef7eb2e8f9f7 96 | (init->quadModeX4 ? TIMER_CTRL_QDM_X4 : 0)
<> 144:ef7eb2e8f9f7 97 | (init->oneShot ? TIMER_CTRL_OSMEN : 0)
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 #if defined(TIMER_CTRL_X2CNT) && defined(TIMER_CTRL_ATI)
<> 144:ef7eb2e8f9f7 100 | (init->count2x ? TIMER_CTRL_X2CNT : 0)
<> 144:ef7eb2e8f9f7 101 | (init->ati ? TIMER_CTRL_ATI : 0)
<> 144:ef7eb2e8f9f7 102 #endif
<> 144:ef7eb2e8f9f7 103 | (init->sync ? TIMER_CTRL_SYNC : 0);
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 /* Start timer if specified to be enabled (dosn't hurt if already started) */
<> 144:ef7eb2e8f9f7 106 if (init->enable)
<> 144:ef7eb2e8f9f7 107 {
<> 144:ef7eb2e8f9f7 108 timer->CMD = TIMER_CMD_START;
<> 144:ef7eb2e8f9f7 109 }
<> 144:ef7eb2e8f9f7 110 }
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 114 * @brief
<> 144:ef7eb2e8f9f7 115 * Initialize TIMER compare/capture channel.
<> 144:ef7eb2e8f9f7 116 *
<> 144:ef7eb2e8f9f7 117 * @details
<> 144:ef7eb2e8f9f7 118 * Notice that if operating channel in compare mode, the CCV and CCVB register
<> 144:ef7eb2e8f9f7 119 * must be set separately as required.
<> 144:ef7eb2e8f9f7 120 *
<> 144:ef7eb2e8f9f7 121 * @param[in] timer
<> 144:ef7eb2e8f9f7 122 * Pointer to TIMER peripheral register block.
<> 144:ef7eb2e8f9f7 123 *
<> 144:ef7eb2e8f9f7 124 * @param[in] ch
<> 144:ef7eb2e8f9f7 125 * Compare/capture channel to init for.
<> 144:ef7eb2e8f9f7 126 *
<> 144:ef7eb2e8f9f7 127 * @param[in] init
<> 144:ef7eb2e8f9f7 128 * Pointer to TIMER initialization structure.
<> 144:ef7eb2e8f9f7 129 ******************************************************************************/
<> 144:ef7eb2e8f9f7 130 void TIMER_InitCC(TIMER_TypeDef *timer,
<> 144:ef7eb2e8f9f7 131 unsigned int ch,
<> 144:ef7eb2e8f9f7 132 const TIMER_InitCC_TypeDef *init)
<> 144:ef7eb2e8f9f7 133 {
<> 144:ef7eb2e8f9f7 134 EFM_ASSERT(TIMER_REF_VALID(timer));
<> 144:ef7eb2e8f9f7 135 EFM_ASSERT(TIMER_CH_VALID(ch));
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 timer->CC[ch].CTRL =
<> 144:ef7eb2e8f9f7 138 ((uint32_t)(init->eventCtrl) << _TIMER_CC_CTRL_ICEVCTRL_SHIFT)
<> 144:ef7eb2e8f9f7 139 | ((uint32_t)(init->edge) << _TIMER_CC_CTRL_ICEDGE_SHIFT)
<> 144:ef7eb2e8f9f7 140 | ((uint32_t)(init->prsSel) << _TIMER_CC_CTRL_PRSSEL_SHIFT)
<> 144:ef7eb2e8f9f7 141 | ((uint32_t)(init->cufoa) << _TIMER_CC_CTRL_CUFOA_SHIFT)
<> 144:ef7eb2e8f9f7 142 | ((uint32_t)(init->cofoa) << _TIMER_CC_CTRL_COFOA_SHIFT)
<> 144:ef7eb2e8f9f7 143 | ((uint32_t)(init->cmoa) << _TIMER_CC_CTRL_CMOA_SHIFT)
<> 144:ef7eb2e8f9f7 144 | ((uint32_t)(init->mode) << _TIMER_CC_CTRL_MODE_SHIFT)
<> 144:ef7eb2e8f9f7 145 | (init->filter ? TIMER_CC_CTRL_FILT_ENABLE : 0)
<> 144:ef7eb2e8f9f7 146 | (init->prsInput ? TIMER_CC_CTRL_INSEL_PRS : 0)
<> 144:ef7eb2e8f9f7 147 | (init->coist ? TIMER_CC_CTRL_COIST : 0)
<> 144:ef7eb2e8f9f7 148 | (init->outInvert ? TIMER_CC_CTRL_OUTINV : 0);
<> 144:ef7eb2e8f9f7 149 }
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 #if defined(_TIMER_DTCTRL_MASK)
<> 144:ef7eb2e8f9f7 153 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 154 * @brief
<> 144:ef7eb2e8f9f7 155 * Initialize the TIMER DTI unit.
<> 144:ef7eb2e8f9f7 156 *
<> 144:ef7eb2e8f9f7 157 * @param[in] timer
<> 144:ef7eb2e8f9f7 158 * Pointer to TIMER peripheral register block.
<> 144:ef7eb2e8f9f7 159 *
<> 144:ef7eb2e8f9f7 160 * @param[in] init
<> 144:ef7eb2e8f9f7 161 * Pointer to TIMER DTI initialization structure.
<> 144:ef7eb2e8f9f7 162 ******************************************************************************/
<> 144:ef7eb2e8f9f7 163 void TIMER_InitDTI(TIMER_TypeDef *timer, const TIMER_InitDTI_TypeDef *init)
<> 144:ef7eb2e8f9f7 164 {
<> 144:ef7eb2e8f9f7 165 EFM_ASSERT(TIMER0 == timer);
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 /* Make sure the DTI unit is disabled while initializing. */
<> 144:ef7eb2e8f9f7 168 TIMER_EnableDTI (timer, false);
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 /* Setup the DTCTRL register.
<> 144:ef7eb2e8f9f7 171 The enable bit will be set at the end of the function if specified. */
<> 144:ef7eb2e8f9f7 172 timer->DTCTRL =
<> 144:ef7eb2e8f9f7 173 (init->autoRestart ? TIMER_DTCTRL_DTDAS : 0)
<> 144:ef7eb2e8f9f7 174 | (init->activeLowOut ? TIMER_DTCTRL_DTIPOL : 0)
<> 144:ef7eb2e8f9f7 175 | (init->invertComplementaryOut ? TIMER_DTCTRL_DTCINV : 0)
<> 144:ef7eb2e8f9f7 176 | (init->enablePrsSource ? TIMER_DTCTRL_DTPRSEN : 0)
<> 144:ef7eb2e8f9f7 177 | ((uint32_t)(init->prsSel) << _TIMER_DTCTRL_DTPRSSEL_SHIFT);
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 /* Setup the DTTIME register. */
<> 144:ef7eb2e8f9f7 180 timer->DTTIME =
<> 144:ef7eb2e8f9f7 181 ((uint32_t)(init->prescale) << _TIMER_DTTIME_DTPRESC_SHIFT)
<> 144:ef7eb2e8f9f7 182 | ((uint32_t)(init->riseTime) << _TIMER_DTTIME_DTRISET_SHIFT)
<> 144:ef7eb2e8f9f7 183 | ((uint32_t)(init->fallTime) << _TIMER_DTTIME_DTFALLT_SHIFT);
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 /* Setup the DTFC register. */
<> 144:ef7eb2e8f9f7 186 timer->DTFC =
<> 144:ef7eb2e8f9f7 187 (init->enableFaultSourceCoreLockup ? TIMER_DTFC_DTLOCKUPFEN : 0)
<> 144:ef7eb2e8f9f7 188 | (init->enableFaultSourceDebugger ? TIMER_DTFC_DTDBGFEN : 0)
<> 144:ef7eb2e8f9f7 189 | (init->enableFaultSourcePrsSel0 ? TIMER_DTFC_DTPRS0FEN : 0)
<> 144:ef7eb2e8f9f7 190 | (init->enableFaultSourcePrsSel1 ? TIMER_DTFC_DTPRS1FEN : 0)
<> 144:ef7eb2e8f9f7 191 | ((uint32_t)(init->faultAction) << _TIMER_DTFC_DTFA_SHIFT)
<> 144:ef7eb2e8f9f7 192 | ((uint32_t)(init->faultSourcePrsSel0) << _TIMER_DTFC_DTPRS0FSEL_SHIFT)
<> 144:ef7eb2e8f9f7 193 | ((uint32_t)(init->faultSourcePrsSel1) << _TIMER_DTFC_DTPRS1FSEL_SHIFT);
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 /* Setup the DTOGEN register. */
<> 144:ef7eb2e8f9f7 196 timer->DTOGEN = init->outputsEnableMask;
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 /* Clear any previous DTI faults. */
<> 144:ef7eb2e8f9f7 199 TIMER_ClearDTIFault(timer, TIMER_GetDTIFault(timer));
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 /* Enable/disable before returning. */
<> 144:ef7eb2e8f9f7 202 TIMER_EnableDTI (timer, init->enable);
<> 144:ef7eb2e8f9f7 203 }
<> 144:ef7eb2e8f9f7 204 #endif
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 208 * @brief
<> 144:ef7eb2e8f9f7 209 * Reset TIMER to same state as after a HW reset.
<> 144:ef7eb2e8f9f7 210 *
<> 144:ef7eb2e8f9f7 211 * @note
<> 144:ef7eb2e8f9f7 212 * The ROUTE register is NOT reset by this function, in order to allow for
<> 144:ef7eb2e8f9f7 213 * centralized setup of this feature.
<> 144:ef7eb2e8f9f7 214 *
<> 144:ef7eb2e8f9f7 215 * @param[in] timer
<> 144:ef7eb2e8f9f7 216 * Pointer to TIMER peripheral register block.
<> 144:ef7eb2e8f9f7 217 ******************************************************************************/
<> 144:ef7eb2e8f9f7 218 void TIMER_Reset(TIMER_TypeDef *timer)
<> 144:ef7eb2e8f9f7 219 {
<> 144:ef7eb2e8f9f7 220 int i;
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 EFM_ASSERT(TIMER_REF_VALID(timer));
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 /* Make sure disabled first, before resetting other registers */
<> 144:ef7eb2e8f9f7 225 timer->CMD = TIMER_CMD_STOP;
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 timer->CTRL = _TIMER_CTRL_RESETVALUE;
<> 144:ef7eb2e8f9f7 228 timer->IEN = _TIMER_IEN_RESETVALUE;
<> 144:ef7eb2e8f9f7 229 timer->IFC = _TIMER_IFC_MASK;
<> 144:ef7eb2e8f9f7 230 timer->TOP = _TIMER_TOP_RESETVALUE;
<> 144:ef7eb2e8f9f7 231 timer->TOPB = _TIMER_TOPB_RESETVALUE;
<> 144:ef7eb2e8f9f7 232 timer->CNT = _TIMER_CNT_RESETVALUE;
<> 144:ef7eb2e8f9f7 233 /* Do not reset route register, setting should be done independently */
<> 144:ef7eb2e8f9f7 234 /* (Note: ROUTE register may be locked by DTLOCK register.) */
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236 for (i = 0; TIMER_CH_VALID(i); i++)
<> 144:ef7eb2e8f9f7 237 {
<> 144:ef7eb2e8f9f7 238 timer->CC[i].CTRL = _TIMER_CC_CTRL_RESETVALUE;
<> 144:ef7eb2e8f9f7 239 timer->CC[i].CCV = _TIMER_CC_CCV_RESETVALUE;
<> 144:ef7eb2e8f9f7 240 timer->CC[i].CCVB = _TIMER_CC_CCVB_RESETVALUE;
<> 144:ef7eb2e8f9f7 241 }
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 /* Reset dead time insertion module, no effect on timers without DTI */
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 #if defined(TIMER_DTLOCK_LOCKKEY_UNLOCK)
<> 144:ef7eb2e8f9f7 246 /* Unlock DTI registers first in case locked */
<> 144:ef7eb2e8f9f7 247 timer->DTLOCK = TIMER_DTLOCK_LOCKKEY_UNLOCK;
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 timer->DTCTRL = _TIMER_DTCTRL_RESETVALUE;
<> 144:ef7eb2e8f9f7 250 timer->DTTIME = _TIMER_DTTIME_RESETVALUE;
<> 144:ef7eb2e8f9f7 251 timer->DTFC = _TIMER_DTFC_RESETVALUE;
<> 144:ef7eb2e8f9f7 252 timer->DTOGEN = _TIMER_DTOGEN_RESETVALUE;
<> 144:ef7eb2e8f9f7 253 timer->DTFAULTC = _TIMER_DTFAULTC_MASK;
<> 144:ef7eb2e8f9f7 254 #endif
<> 144:ef7eb2e8f9f7 255 }
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 /** @} (end addtogroup TIMER) */
<> 144:ef7eb2e8f9f7 259 /** @} (end addtogroup EM_Library) */
<> 144:ef7eb2e8f9f7 260 #endif /* defined(TIMER_COUNT) && (TIMER_COUNT > 0) */