Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_ldma.c@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
50:a417edff4437 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 50:a417edff4437 1 /***************************************************************************//**
mbed_official 50:a417edff4437 2 * @file em_ldma.c
mbed_official 50:a417edff4437 3 * @brief Direct memory access (LDMA) module peripheral API
mbed_official 50:a417edff4437 4 * @version 4.2.1
mbed_official 50:a417edff4437 5 *******************************************************************************
mbed_official 50:a417edff4437 6 * @section License
mbed_official 50:a417edff4437 7 * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
mbed_official 50:a417edff4437 8 *******************************************************************************
mbed_official 50:a417edff4437 9 *
mbed_official 50:a417edff4437 10 * Permission is granted to anyone to use this software for any purpose,
mbed_official 50:a417edff4437 11 * including commercial applications, and to alter it and redistribute it
mbed_official 50:a417edff4437 12 * freely, subject to the following restrictions:
mbed_official 50:a417edff4437 13 *
mbed_official 50:a417edff4437 14 * 1. The origin of this software must not be misrepresented; you must not
mbed_official 50:a417edff4437 15 * claim that you wrote the original software.@n
mbed_official 50:a417edff4437 16 * 2. Altered source versions must be plainly marked as such, and must not be
mbed_official 50:a417edff4437 17 * misrepresented as being the original software.@n
mbed_official 50:a417edff4437 18 * 3. This notice may not be removed or altered from any source distribution.
mbed_official 50:a417edff4437 19 *
mbed_official 50:a417edff4437 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
mbed_official 50:a417edff4437 21 * obligation to support this Software. Silicon Labs is providing the
mbed_official 50:a417edff4437 22 * Software "AS IS", with no express or implied warranties of any kind,
mbed_official 50:a417edff4437 23 * including, but not limited to, any implied warranties of merchantability
mbed_official 50:a417edff4437 24 * or fitness for any particular purpose or warranties against infringement
mbed_official 50:a417edff4437 25 * of any proprietary rights of a third party.
mbed_official 50:a417edff4437 26 *
mbed_official 50:a417edff4437 27 * Silicon Labs will not be liable for any consequential, incidental, or
mbed_official 50:a417edff4437 28 * special damages, or any other relief, or for any claim by any third party,
mbed_official 50:a417edff4437 29 * arising from your use of this Software.
mbed_official 50:a417edff4437 30 *
mbed_official 50:a417edff4437 31 ******************************************************************************/
mbed_official 50:a417edff4437 32
mbed_official 50:a417edff4437 33 #include "em_ldma.h"
mbed_official 50:a417edff4437 34
mbed_official 50:a417edff4437 35 #if defined( LDMA_PRESENT ) && ( LDMA_COUNT == 1 )
mbed_official 50:a417edff4437 36
mbed_official 50:a417edff4437 37 #include <stddef.h>
mbed_official 50:a417edff4437 38 #include "em_assert.h"
mbed_official 50:a417edff4437 39 #include "em_bus.h"
mbed_official 50:a417edff4437 40 #include "em_cmu.h"
mbed_official 50:a417edff4437 41 #include "em_int.h"
mbed_official 50:a417edff4437 42
mbed_official 50:a417edff4437 43 /***************************************************************************//**
mbed_official 50:a417edff4437 44 * @addtogroup EM_Library
mbed_official 50:a417edff4437 45 * @{
mbed_official 50:a417edff4437 46 ******************************************************************************/
mbed_official 50:a417edff4437 47
mbed_official 50:a417edff4437 48 /***************************************************************************//**
mbed_official 50:a417edff4437 49 @addtogroup LDMA
mbed_official 50:a417edff4437 50 @brief Direct Memory Access (LDMA) Peripheral API
mbed_official 50:a417edff4437 51 @details
mbed_official 50:a417edff4437 52 The LDMA API functions provide full support for the LDMA peripheral.
mbed_official 50:a417edff4437 53
mbed_official 50:a417edff4437 54 The LDMA supports these DMA transfer types:
mbed_official 50:a417edff4437 55
mbed_official 50:a417edff4437 56 @li Memory to memory.
mbed_official 50:a417edff4437 57 @li Memory to peripheral.
mbed_official 50:a417edff4437 58 @li Peripheral to memory.
mbed_official 50:a417edff4437 59 @li Peripheral to peripheral.
mbed_official 50:a417edff4437 60 @li Constant value to memory.
mbed_official 50:a417edff4437 61
mbed_official 50:a417edff4437 62 The LDMA supports linked lists of DMA descriptors allowing:
mbed_official 50:a417edff4437 63
mbed_official 50:a417edff4437 64 @li Circular and ping-pong buffer transfers.
mbed_official 50:a417edff4437 65 @li Scatter-gather transfers.
mbed_official 50:a417edff4437 66 @li Looped transfers.
mbed_official 50:a417edff4437 67
mbed_official 50:a417edff4437 68 The LDMA has some advanced features:
mbed_official 50:a417edff4437 69
mbed_official 50:a417edff4437 70 @li Intra-channel synchronization (SYNC), allowing hardware events to
mbed_official 50:a417edff4437 71 pause and restart a DMA sequence.
mbed_official 50:a417edff4437 72 @li Immediate-write (WRI), allowing the DMA to write a constant anywhere
mbed_official 50:a417edff4437 73 in the memory map.
mbed_official 50:a417edff4437 74 @li Complex flow control allowing if-else constructs.
mbed_official 50:a417edff4437 75
mbed_official 50:a417edff4437 76 A basic understanding of the LDMA controller is assumed. Please refer to
mbed_official 50:a417edff4437 77 the reference manual for further details. The LDMA examples described
mbed_official 50:a417edff4437 78 in the reference manual are particularly helpful in understanding LDMA
mbed_official 50:a417edff4437 79 operations.
mbed_official 50:a417edff4437 80
mbed_official 50:a417edff4437 81 In order to use the DMA controller, the initialization function @ref
mbed_official 50:a417edff4437 82 LDMA_Init() must have been executed once (normally during system init).
mbed_official 50:a417edff4437 83
mbed_official 50:a417edff4437 84 DMA transfers are initiated by a call to @ref LDMA_StartTransfer(), the
mbed_official 50:a417edff4437 85 transfer properties are controlled by the contents of @ref LDMA_TransferCfg_t
mbed_official 50:a417edff4437 86 and @ref LDMA_Descriptor_t structure parameters.
mbed_official 50:a417edff4437 87 The @htmlonly LDMA_Descriptor_t @endhtmlonly structure parameter may be a
mbed_official 50:a417edff4437 88 pointer to an array of descriptors, the descriptors in the array should
mbed_official 50:a417edff4437 89 be linked together as needed.
mbed_official 50:a417edff4437 90
mbed_official 50:a417edff4437 91 Transfer and descriptor initialization macros are provided for the most common
mbed_official 50:a417edff4437 92 transfer types. Due to the flexibility of the LDMA peripheral only a small
mbed_official 50:a417edff4437 93 subset of all possible initializer macros are provided, the user should create
mbed_official 50:a417edff4437 94 new one's when needed.
mbed_official 50:a417edff4437 95
mbed_official 50:a417edff4437 96 @note The LDMA module does not implement the LDMA interrupt handler. A
mbed_official 50:a417edff4437 97 template for a handler is include in the code.
mbed_official 50:a417edff4437 98
mbed_official 50:a417edff4437 99 <b> Examples of LDMA usage: </b>
mbed_official 50:a417edff4437 100
mbed_official 50:a417edff4437 101 A simple memory to memory transfer:
mbed_official 50:a417edff4437 102 @verbatim
mbed_official 50:a417edff4437 103 // A single transfer of 4 half words.
mbed_official 50:a417edff4437 104
mbed_official 50:a417edff4437 105 const LDMA_TransferCfg_t memTransfer = LDMA_TRANSFER_CFG_MEMORY();
mbed_official 50:a417edff4437 106 const LDMA_Descriptor_t xfer = LDMA_DESCRIPTOR_SINGLE_M2M_HALF( src, dest, 4 );
mbed_official 50:a417edff4437 107 LDMA_Init_t init = LDMA_INIT_DEFAULT;
mbed_official 50:a417edff4437 108
mbed_official 50:a417edff4437 109 LDMA_Init( &init );
mbed_official 50:a417edff4437 110
mbed_official 50:a417edff4437 111 LDMA_StartTransfer( 0, (void*)&memTransfer, (void*)&xfer );
mbed_official 50:a417edff4437 112 @endverbatim
mbed_official 50:a417edff4437 113
mbed_official 50:a417edff4437 114 @n A list of two memory to memory transfers:
mbed_official 50:a417edff4437 115 @verbatim
mbed_official 50:a417edff4437 116 // A transfer of 4 half words which links to another transfer of 4 half words.
mbed_official 50:a417edff4437 117
mbed_official 50:a417edff4437 118 const LDMA_TransferCfg_t memTransfer = LDMA_TRANSFER_CFG_MEMORY();
mbed_official 50:a417edff4437 119
mbed_official 50:a417edff4437 120 const LDMA_Descriptor_t xfer[] =
mbed_official 50:a417edff4437 121 {
mbed_official 50:a417edff4437 122 LDMA_DESCRIPTOR_LINKREL_M2M_HALF( src, dest , 4, 1 ),
mbed_official 50:a417edff4437 123 LDMA_DESCRIPTOR_SINGLE_M2M_HALF ( src, dest + 10, 4 )
mbed_official 50:a417edff4437 124 };
mbed_official 50:a417edff4437 125
mbed_official 50:a417edff4437 126 LDMA_Init_t init = LDMA_INIT_DEFAULT;
mbed_official 50:a417edff4437 127
mbed_official 50:a417edff4437 128 LDMA_Init( &init );
mbed_official 50:a417edff4437 129
mbed_official 50:a417edff4437 130 LDMA_StartTransfer( 0, (void*)&memTransfer, (void*)&xfer );
mbed_official 50:a417edff4437 131 @endverbatim
mbed_official 50:a417edff4437 132
mbed_official 50:a417edff4437 133 @n A list of three memory to memory transfers:
mbed_official 50:a417edff4437 134 @verbatim
mbed_official 50:a417edff4437 135 // A transfer of 4 half words which links to another transfer of 4 half words,
mbed_official 50:a417edff4437 136 // which again links to a third transfer of 4 half words.
mbed_official 50:a417edff4437 137
mbed_official 50:a417edff4437 138 const LDMA_TransferCfg_t memTransfer = LDMA_TRANSFER_CFG_MEMORY();
mbed_official 50:a417edff4437 139
mbed_official 50:a417edff4437 140 const LDMA_Descriptor_t xfer[] =
mbed_official 50:a417edff4437 141 {
mbed_official 50:a417edff4437 142 LDMA_DESCRIPTOR_LINKREL_M2M_HALF( src , dest , 4, 1 ),
mbed_official 50:a417edff4437 143 LDMA_DESCRIPTOR_LINKREL_M2M_HALF( src + 2, dest + 5 , 4, 1 ),
mbed_official 50:a417edff4437 144 LDMA_DESCRIPTOR_SINGLE_M2M_HALF ( src + 4, dest + 10, 4 )
mbed_official 50:a417edff4437 145 };
mbed_official 50:a417edff4437 146
mbed_official 50:a417edff4437 147 LDMA_Init_t init = LDMA_INIT_DEFAULT;
mbed_official 50:a417edff4437 148
mbed_official 50:a417edff4437 149 LDMA_Init( &init );
mbed_official 50:a417edff4437 150
mbed_official 50:a417edff4437 151 LDMA_StartTransfer( 0, (void*)&memTransfer, (void*)&xfer );
mbed_official 50:a417edff4437 152 @endverbatim
mbed_official 50:a417edff4437 153
mbed_official 50:a417edff4437 154 @n DMA from serial port peripheral to memory:
mbed_official 50:a417edff4437 155 @verbatim
mbed_official 50:a417edff4437 156 // Transfer 4 chars from USART1.
mbed_official 50:a417edff4437 157
mbed_official 50:a417edff4437 158 const LDMA_TransferCfg_t periTransferRx =
mbed_official 50:a417edff4437 159 LDMA_TRANSFER_CFG_PERIPHERAL( ldmaPeripheralSignal_USART1_RXDATAV );
mbed_official 50:a417edff4437 160
mbed_official 50:a417edff4437 161 const LDMA_Descriptor_t xfer =
mbed_official 50:a417edff4437 162 LDMA_DESCRIPTOR_SINGLE_P2M_BYTE( &USART1->RXDATA, // Peripheral address
mbed_official 50:a417edff4437 163 dest, // Destination (SRAM)
mbed_official 50:a417edff4437 164 4 ); // Number of bytes
mbed_official 50:a417edff4437 165
mbed_official 50:a417edff4437 166 LDMA_Init_t init = LDMA_INIT_DEFAULT;
mbed_official 50:a417edff4437 167
mbed_official 50:a417edff4437 168 LDMA_Init( &init );
mbed_official 50:a417edff4437 169
mbed_official 50:a417edff4437 170 LDMA_StartTransfer( 0, (void*)&periTransferRx, (void*)&xfer );
mbed_official 50:a417edff4437 171 @endverbatim
mbed_official 50:a417edff4437 172
mbed_official 50:a417edff4437 173 @n Ping pong DMA from serial port peripheral to memory:
mbed_official 50:a417edff4437 174 @verbatim
mbed_official 50:a417edff4437 175 // Ping Pong transfer from USART1.
mbed_official 50:a417edff4437 176
mbed_official 50:a417edff4437 177 static char buff1[5];
mbed_official 50:a417edff4437 178 static char buff2[5];
mbed_official 50:a417edff4437 179
mbed_official 50:a417edff4437 180 const LDMA_TransferCfg_t periTransferRx =
mbed_official 50:a417edff4437 181 LDMA_TRANSFER_CFG_PERIPHERAL( ldmaPeripheralSignal_USART1_RXDATAV );
mbed_official 50:a417edff4437 182
mbed_official 50:a417edff4437 183 const LDMA_Descriptor_t xfer[] =
mbed_official 50:a417edff4437 184 {
mbed_official 50:a417edff4437 185 // Note the 1 and -1 link jump increments. This will cause each DMA transfer
mbed_official 50:a417edff4437 186 // to link to the other one in an endless loop.
mbed_official 50:a417edff4437 187 LDMA_DESCRIPTOR_LINKREL_P2M_BYTE( &USART1->RXDATA, // Peripheral address
mbed_official 50:a417edff4437 188 buff1, // Destination (SRAM)
mbed_official 50:a417edff4437 189 5, // Number of bytes
mbed_official 50:a417edff4437 190 1 ), // Next descriptor
mbed_official 50:a417edff4437 191 LDMA_DESCRIPTOR_LINKREL_P2M_BYTE( &USART1->RXDATA, // Peripheral address
mbed_official 50:a417edff4437 192 buff2, // Destination (SRAM)
mbed_official 50:a417edff4437 193 5, // Number of bytes
mbed_official 50:a417edff4437 194 -1 ) // Next descriptor
mbed_official 50:a417edff4437 195 };
mbed_official 50:a417edff4437 196
mbed_official 50:a417edff4437 197 LDMA_Init_t init = LDMA_INIT_DEFAULT;
mbed_official 50:a417edff4437 198
mbed_official 50:a417edff4437 199 LDMA_Init( &init );
mbed_official 50:a417edff4437 200
mbed_official 50:a417edff4437 201 LDMA_StartTransfer( 0, (void*)&periTransferRx, (void*)&xfer );
mbed_official 50:a417edff4437 202 @endverbatim
mbed_official 50:a417edff4437 203 * @{ *************************************************************************/
mbed_official 50:a417edff4437 204
mbed_official 50:a417edff4437 205 #if defined( LDMA_IRQ_HANDLER_TEMPLATE )
mbed_official 50:a417edff4437 206 /***************************************************************************//**
mbed_official 50:a417edff4437 207 * @brief
mbed_official 50:a417edff4437 208 * Template for an LDMA IRQ handler.
mbed_official 50:a417edff4437 209 ******************************************************************************/
mbed_official 50:a417edff4437 210 void LDMA_IRQHandler( void )
mbed_official 50:a417edff4437 211 {
mbed_official 50:a417edff4437 212 uint32_t pending, chnum, chmask;
mbed_official 50:a417edff4437 213
mbed_official 50:a417edff4437 214 /* Get all pending and enabled interrupts */
mbed_official 50:a417edff4437 215 pending = LDMA->IF;
mbed_official 50:a417edff4437 216 pending &= LDMA->IEN;
mbed_official 50:a417edff4437 217
mbed_official 50:a417edff4437 218 /* Check for LDMA error */
mbed_official 50:a417edff4437 219 if ( pending & LDMA_IF_ERROR )
mbed_official 50:a417edff4437 220 {
mbed_official 50:a417edff4437 221 /* Loop here to enable the debugger to see what has happened */
mbed_official 50:a417edff4437 222 while (1)
mbed_official 50:a417edff4437 223 ;
mbed_official 50:a417edff4437 224 }
mbed_official 50:a417edff4437 225
mbed_official 50:a417edff4437 226 /* Iterate over all LDMA channels. */
mbed_official 50:a417edff4437 227 for ( chnum = 0, chmask = 1;
mbed_official 50:a417edff4437 228 chnum < DMA_CHAN_COUNT;
mbed_official 50:a417edff4437 229 chnum++, chmask <<= 1 )
mbed_official 50:a417edff4437 230 {
mbed_official 50:a417edff4437 231 if ( pending & chmask )
mbed_official 50:a417edff4437 232 {
mbed_official 50:a417edff4437 233 /* Clear interrupt flag. */
mbed_official 50:a417edff4437 234 LDMA->IFC = chmask;
mbed_official 50:a417edff4437 235
mbed_official 50:a417edff4437 236 /* Do more stuff here, execute callbacks etc. */
mbed_official 50:a417edff4437 237 }
mbed_official 50:a417edff4437 238 }
mbed_official 50:a417edff4437 239 }
mbed_official 50:a417edff4437 240 #endif
mbed_official 50:a417edff4437 241
mbed_official 50:a417edff4437 242 /***************************************************************************//**
mbed_official 50:a417edff4437 243 * @brief
mbed_official 50:a417edff4437 244 * De-initialize the LDMA controller.
mbed_official 50:a417edff4437 245 *
mbed_official 50:a417edff4437 246 * LDMA interrupts are disabled and the LDMA clock is stopped.
mbed_official 50:a417edff4437 247 ******************************************************************************/
mbed_official 50:a417edff4437 248 void LDMA_DeInit( void )
mbed_official 50:a417edff4437 249 {
mbed_official 50:a417edff4437 250 NVIC_DisableIRQ( LDMA_IRQn );
mbed_official 50:a417edff4437 251 LDMA->IEN = 0;
mbed_official 50:a417edff4437 252 LDMA->CHEN = 0;
mbed_official 50:a417edff4437 253 CMU_ClockEnable( cmuClock_LDMA, false );
mbed_official 50:a417edff4437 254 }
mbed_official 50:a417edff4437 255
mbed_official 50:a417edff4437 256 /***************************************************************************//**
mbed_official 50:a417edff4437 257 * @brief
mbed_official 50:a417edff4437 258 * Initialize the LDMA controller.
mbed_official 50:a417edff4437 259 *
mbed_official 50:a417edff4437 260 * @param[in] init
mbed_official 50:a417edff4437 261 * Pointer to initialization structure used to configure the setup.
mbed_official 50:a417edff4437 262 ******************************************************************************/
mbed_official 50:a417edff4437 263 void LDMA_Init( LDMA_Init_t *init )
mbed_official 50:a417edff4437 264 {
mbed_official 50:a417edff4437 265 EFM_ASSERT( init != NULL );
mbed_official 50:a417edff4437 266 EFM_ASSERT( !( ( init->ldmaInitCtrlNumFixed << _LDMA_CTRL_NUMFIXED_SHIFT )
mbed_official 50:a417edff4437 267 & ~_LDMA_CTRL_NUMFIXED_MASK ) );
mbed_official 50:a417edff4437 268 EFM_ASSERT( !( ( init->ldmaInitCtrlSyncPrsClrEn << _LDMA_CTRL_SYNCPRSCLREN_SHIFT )
mbed_official 50:a417edff4437 269 & ~_LDMA_CTRL_SYNCPRSCLREN_MASK ) );
mbed_official 50:a417edff4437 270 EFM_ASSERT( !( ( init->ldmaInitCtrlSyncPrsSetEn << _LDMA_CTRL_SYNCPRSSETEN_SHIFT )
mbed_official 50:a417edff4437 271 & ~_LDMA_CTRL_SYNCPRSSETEN_MASK ) );
mbed_official 50:a417edff4437 272 EFM_ASSERT( init->ldmaInitIrqPriority < ( 1 << __NVIC_PRIO_BITS ) );
mbed_official 50:a417edff4437 273
mbed_official 50:a417edff4437 274 CMU_ClockEnable( cmuClock_LDMA, true );
mbed_official 50:a417edff4437 275
mbed_official 50:a417edff4437 276 LDMA->CTRL = ( init->ldmaInitCtrlNumFixed << _LDMA_CTRL_NUMFIXED_SHIFT )
mbed_official 50:a417edff4437 277 | ( init->ldmaInitCtrlSyncPrsClrEn << _LDMA_CTRL_SYNCPRSCLREN_SHIFT )
mbed_official 50:a417edff4437 278 | ( init->ldmaInitCtrlSyncPrsSetEn << _LDMA_CTRL_SYNCPRSSETEN_SHIFT );
mbed_official 50:a417edff4437 279
mbed_official 50:a417edff4437 280 LDMA->CHEN = 0;
mbed_official 50:a417edff4437 281 LDMA->DBGHALT = 0;
mbed_official 50:a417edff4437 282 LDMA->REQDIS = 0;
mbed_official 50:a417edff4437 283
mbed_official 50:a417edff4437 284 /* Enable LDMA error interrupt. */
mbed_official 50:a417edff4437 285 LDMA->IEN = LDMA_IEN_ERROR;
mbed_official 50:a417edff4437 286 LDMA->IFC = 0xFFFFFFFF;
mbed_official 50:a417edff4437 287
mbed_official 50:a417edff4437 288 NVIC_ClearPendingIRQ( LDMA_IRQn );
mbed_official 50:a417edff4437 289
mbed_official 50:a417edff4437 290 /* Range is 0..7, 0 is highest priority. */
mbed_official 50:a417edff4437 291 NVIC_SetPriority( LDMA_IRQn, init->ldmaInitIrqPriority );
mbed_official 50:a417edff4437 292
mbed_official 50:a417edff4437 293 NVIC_EnableIRQ( LDMA_IRQn );
mbed_official 50:a417edff4437 294 }
mbed_official 50:a417edff4437 295
mbed_official 50:a417edff4437 296 /***************************************************************************//**
mbed_official 50:a417edff4437 297 * @brief
mbed_official 50:a417edff4437 298 * Start a DMA transfer.
mbed_official 50:a417edff4437 299 *
mbed_official 50:a417edff4437 300 * @param[in] ch
mbed_official 50:a417edff4437 301 * DMA channel.
mbed_official 50:a417edff4437 302 *
mbed_official 50:a417edff4437 303 * @param[in] transfer
mbed_official 50:a417edff4437 304 * Initialization structure used to configure the transfer.
mbed_official 50:a417edff4437 305 *
mbed_official 50:a417edff4437 306 * @param[in] descriptor
mbed_official 50:a417edff4437 307 * Transfer descriptor, can be an array of descriptors linked together.
mbed_official 50:a417edff4437 308 ******************************************************************************/
mbed_official 50:a417edff4437 309 void LDMA_StartTransfer( int ch,
mbed_official 50:a417edff4437 310 LDMA_TransferCfg_t *transfer,
mbed_official 50:a417edff4437 311 LDMA_Descriptor_t *descriptor )
mbed_official 50:a417edff4437 312 {
mbed_official 50:a417edff4437 313 uint32_t tmp;
mbed_official 50:a417edff4437 314 uint32_t chMask = 1 << ch;
mbed_official 50:a417edff4437 315
mbed_official 50:a417edff4437 316 EFM_ASSERT( ch < DMA_CHAN_COUNT );
mbed_official 50:a417edff4437 317 EFM_ASSERT( transfer != NULL );
mbed_official 50:a417edff4437 318 EFM_ASSERT( !( transfer->ldmaReqSel & ~_LDMA_CH_REQSEL_MASK ) );
mbed_official 50:a417edff4437 319
mbed_official 50:a417edff4437 320 EFM_ASSERT( !( ( transfer->ldmaCtrlSyncPrsClrOff << _LDMA_CTRL_SYNCPRSCLREN_SHIFT )
mbed_official 50:a417edff4437 321 & ~_LDMA_CTRL_SYNCPRSCLREN_MASK ) );
mbed_official 50:a417edff4437 322 EFM_ASSERT( !( ( transfer->ldmaCtrlSyncPrsClrOn << _LDMA_CTRL_SYNCPRSCLREN_SHIFT )
mbed_official 50:a417edff4437 323 & ~_LDMA_CTRL_SYNCPRSCLREN_MASK ) );
mbed_official 50:a417edff4437 324 EFM_ASSERT( !( ( transfer->ldmaCtrlSyncPrsSetOff << _LDMA_CTRL_SYNCPRSSETEN_SHIFT )
mbed_official 50:a417edff4437 325 & ~_LDMA_CTRL_SYNCPRSSETEN_MASK ) );
mbed_official 50:a417edff4437 326 EFM_ASSERT( !( ( transfer->ldmaCtrlSyncPrsSetOn << _LDMA_CTRL_SYNCPRSSETEN_SHIFT )
mbed_official 50:a417edff4437 327 & ~_LDMA_CTRL_SYNCPRSSETEN_MASK ) );
mbed_official 50:a417edff4437 328
mbed_official 50:a417edff4437 329 EFM_ASSERT( !( ( transfer->ldmaCfgArbSlots << _LDMA_CH_CFG_ARBSLOTS_SHIFT )
mbed_official 50:a417edff4437 330 & ~_LDMA_CH_CFG_ARBSLOTS_MASK ) );
mbed_official 50:a417edff4437 331 EFM_ASSERT( !( ( transfer->ldmaCfgSrcIncSign << _LDMA_CH_CFG_SRCINCSIGN_SHIFT )
mbed_official 50:a417edff4437 332 & ~_LDMA_CH_CFG_SRCINCSIGN_MASK ) );
mbed_official 50:a417edff4437 333 EFM_ASSERT( !( ( transfer->ldmaCfgDstIncSign << _LDMA_CH_CFG_DSTINCSIGN_SHIFT )
mbed_official 50:a417edff4437 334 & ~_LDMA_CH_CFG_DSTINCSIGN_MASK ) );
mbed_official 50:a417edff4437 335 EFM_ASSERT( !( ( transfer->ldmaLoopCnt << _LDMA_CH_LOOP_LOOPCNT_SHIFT )
mbed_official 50:a417edff4437 336 & ~_LDMA_CH_LOOP_LOOPCNT_MASK ) );
mbed_official 50:a417edff4437 337
mbed_official 50:a417edff4437 338 LDMA->CH[ ch ].REQSEL = transfer->ldmaReqSel;
mbed_official 50:a417edff4437 339
mbed_official 50:a417edff4437 340 LDMA->CH[ ch ].LOOP =
mbed_official 50:a417edff4437 341 ( transfer->ldmaLoopCnt << _LDMA_CH_LOOP_LOOPCNT_SHIFT );
mbed_official 50:a417edff4437 342
mbed_official 50:a417edff4437 343 LDMA->CH[ ch ].CFG =
mbed_official 50:a417edff4437 344 ( transfer->ldmaCfgArbSlots << _LDMA_CH_CFG_ARBSLOTS_SHIFT )
mbed_official 50:a417edff4437 345 | ( transfer->ldmaCfgSrcIncSign << _LDMA_CH_CFG_SRCINCSIGN_SHIFT )
mbed_official 50:a417edff4437 346 | ( transfer->ldmaCfgDstIncSign << _LDMA_CH_CFG_DSTINCSIGN_SHIFT );
mbed_official 50:a417edff4437 347
mbed_official 50:a417edff4437 348 /* Set descriptor address. */
mbed_official 50:a417edff4437 349 LDMA->CH[ ch ].LINK = (uint32_t)descriptor & _LDMA_CH_LINK_LINKADDR_MASK;
mbed_official 50:a417edff4437 350
mbed_official 50:a417edff4437 351 /* Clear pending channel interrupt. */
mbed_official 50:a417edff4437 352 LDMA->IFC = chMask;
mbed_official 50:a417edff4437 353
mbed_official 50:a417edff4437 354 /* Critical region. */
mbed_official 50:a417edff4437 355 INT_Disable();
mbed_official 50:a417edff4437 356
mbed_official 50:a417edff4437 357 /* Enable channel interrupt. */
mbed_official 50:a417edff4437 358 LDMA->IEN |= chMask;
mbed_official 50:a417edff4437 359
mbed_official 50:a417edff4437 360 if ( transfer->ldmaReqDis )
mbed_official 50:a417edff4437 361 {
mbed_official 50:a417edff4437 362 LDMA->REQDIS |= chMask;
mbed_official 50:a417edff4437 363 }
mbed_official 50:a417edff4437 364
mbed_official 50:a417edff4437 365 if ( transfer->ldmaDbgHalt )
mbed_official 50:a417edff4437 366 {
mbed_official 50:a417edff4437 367 LDMA->DBGHALT |= chMask;
mbed_official 50:a417edff4437 368 }
mbed_official 50:a417edff4437 369
mbed_official 50:a417edff4437 370 tmp = LDMA->CTRL;
mbed_official 50:a417edff4437 371
mbed_official 50:a417edff4437 372 if ( transfer->ldmaCtrlSyncPrsClrOff )
mbed_official 50:a417edff4437 373 {
mbed_official 50:a417edff4437 374 tmp &= ~_LDMA_CTRL_SYNCPRSCLREN_MASK
mbed_official 50:a417edff4437 375 | (~transfer->ldmaCtrlSyncPrsClrOff << _LDMA_CTRL_SYNCPRSCLREN_SHIFT);
mbed_official 50:a417edff4437 376 }
mbed_official 50:a417edff4437 377
mbed_official 50:a417edff4437 378 if ( transfer->ldmaCtrlSyncPrsClrOn )
mbed_official 50:a417edff4437 379 {
mbed_official 50:a417edff4437 380 tmp |= transfer->ldmaCtrlSyncPrsClrOn << _LDMA_CTRL_SYNCPRSCLREN_SHIFT;
mbed_official 50:a417edff4437 381 }
mbed_official 50:a417edff4437 382
mbed_official 50:a417edff4437 383 if ( transfer->ldmaCtrlSyncPrsSetOff )
mbed_official 50:a417edff4437 384 {
mbed_official 50:a417edff4437 385 tmp &= ~_LDMA_CTRL_SYNCPRSSETEN_MASK
mbed_official 50:a417edff4437 386 | (~transfer->ldmaCtrlSyncPrsSetOff << _LDMA_CTRL_SYNCPRSSETEN_SHIFT);
mbed_official 50:a417edff4437 387 }
mbed_official 50:a417edff4437 388
mbed_official 50:a417edff4437 389 if ( transfer->ldmaCtrlSyncPrsSetOn )
mbed_official 50:a417edff4437 390 {
mbed_official 50:a417edff4437 391 tmp |= transfer->ldmaCtrlSyncPrsSetOn << _LDMA_CTRL_SYNCPRSSETEN_SHIFT;
mbed_official 50:a417edff4437 392 }
mbed_official 50:a417edff4437 393
mbed_official 50:a417edff4437 394 LDMA->CTRL = tmp;
mbed_official 50:a417edff4437 395
mbed_official 50:a417edff4437 396 BUS_RegMaskedClear(&LDMA->CHDONE, chMask); /* Clear the done flag. */
mbed_official 50:a417edff4437 397 LDMA->LINKLOAD = chMask; /* Enable descriptor load. */
mbed_official 50:a417edff4437 398 BUS_RegMaskedSet(&LDMA->CHEN, chMask); /* Enable channel. */
mbed_official 50:a417edff4437 399
mbed_official 50:a417edff4437 400 /* Critical region end. */
mbed_official 50:a417edff4437 401 INT_Enable();
mbed_official 50:a417edff4437 402 }
mbed_official 50:a417edff4437 403
mbed_official 50:a417edff4437 404 /***************************************************************************//**
mbed_official 50:a417edff4437 405 * @brief
mbed_official 50:a417edff4437 406 * Stop a DMA transfer.
mbed_official 50:a417edff4437 407 *
mbed_official 50:a417edff4437 408 * @note
mbed_official 50:a417edff4437 409 * The DMA will complete the current AHB burst transfer before stopping.
mbed_official 50:a417edff4437 410 *
mbed_official 50:a417edff4437 411 * @param[in] ch
mbed_official 50:a417edff4437 412 * DMA channel to stop.
mbed_official 50:a417edff4437 413 ******************************************************************************/
mbed_official 50:a417edff4437 414 void LDMA_StopTransfer( int ch )
mbed_official 50:a417edff4437 415 {
mbed_official 50:a417edff4437 416 uint32_t chMask = 1 << ch;
mbed_official 50:a417edff4437 417
mbed_official 50:a417edff4437 418 EFM_ASSERT( ch < DMA_CHAN_COUNT );
mbed_official 50:a417edff4437 419
mbed_official 50:a417edff4437 420 INT_Disable();
mbed_official 50:a417edff4437 421
mbed_official 50:a417edff4437 422 LDMA->IEN &= ~chMask;
mbed_official 50:a417edff4437 423 BUS_RegMaskedClear(&LDMA->CHEN, chMask);
mbed_official 50:a417edff4437 424
mbed_official 50:a417edff4437 425 INT_Enable();
mbed_official 50:a417edff4437 426 }
mbed_official 50:a417edff4437 427
mbed_official 50:a417edff4437 428 /***************************************************************************//**
mbed_official 50:a417edff4437 429 * @brief
mbed_official 50:a417edff4437 430 * Check if a DMA transfer has completed.
mbed_official 50:a417edff4437 431 *
mbed_official 50:a417edff4437 432 * @param[in] ch
mbed_official 50:a417edff4437 433 * DMA channel to check.
mbed_official 50:a417edff4437 434 *
mbed_official 50:a417edff4437 435 * @return
mbed_official 50:a417edff4437 436 * True if transfer has completed, false if not.
mbed_official 50:a417edff4437 437 ******************************************************************************/
mbed_official 50:a417edff4437 438 bool LDMA_TransferDone( int ch )
mbed_official 50:a417edff4437 439 {
mbed_official 50:a417edff4437 440 bool retVal = false;
mbed_official 50:a417edff4437 441 uint32_t chMask = 1 << ch;
mbed_official 50:a417edff4437 442
mbed_official 50:a417edff4437 443 EFM_ASSERT( ch < DMA_CHAN_COUNT );
mbed_official 50:a417edff4437 444
mbed_official 50:a417edff4437 445 INT_Disable();
mbed_official 50:a417edff4437 446 if ( ( ( LDMA->CHEN & chMask ) == 0 )
mbed_official 50:a417edff4437 447 && ( ( LDMA->CHDONE & chMask ) == chMask ) )
mbed_official 50:a417edff4437 448 {
mbed_official 50:a417edff4437 449 retVal = true;
mbed_official 50:a417edff4437 450 }
mbed_official 50:a417edff4437 451 INT_Enable();
mbed_official 50:a417edff4437 452 return retVal;
mbed_official 50:a417edff4437 453 }
mbed_official 50:a417edff4437 454
mbed_official 50:a417edff4437 455 /***************************************************************************//**
mbed_official 50:a417edff4437 456 * @brief
mbed_official 50:a417edff4437 457 * Get number of items remaining in a transfer.
mbed_official 50:a417edff4437 458 *
mbed_official 50:a417edff4437 459 * @note
mbed_official 50:a417edff4437 460 * This function is does not take into account that a DMA transfers with
mbed_official 50:a417edff4437 461 * a chain of linked transfers might be ongoing. It will only check the
mbed_official 50:a417edff4437 462 * count for the current transfer.
mbed_official 50:a417edff4437 463 *
mbed_official 50:a417edff4437 464 * @param[in] ch
mbed_official 50:a417edff4437 465 * The channel number of the transfer to check.
mbed_official 50:a417edff4437 466 *
mbed_official 50:a417edff4437 467 * @return
mbed_official 50:a417edff4437 468 * Number of items remaining in the transfer.
mbed_official 50:a417edff4437 469 ******************************************************************************/
mbed_official 50:a417edff4437 470 uint32_t LDMA_TransferRemainingCount( int ch )
mbed_official 50:a417edff4437 471 {
mbed_official 50:a417edff4437 472 uint32_t remaining, done, iflag;
mbed_official 50:a417edff4437 473 uint32_t chMask = 1 << ch;
mbed_official 50:a417edff4437 474
mbed_official 50:a417edff4437 475 EFM_ASSERT( ch < DMA_CHAN_COUNT );
mbed_official 50:a417edff4437 476
mbed_official 50:a417edff4437 477 INT_Disable();
mbed_official 50:a417edff4437 478 iflag = LDMA->IF;
mbed_official 50:a417edff4437 479 done = LDMA->CHDONE;
mbed_official 50:a417edff4437 480 remaining = LDMA->CH[ ch ].CTRL;
mbed_official 50:a417edff4437 481 INT_Enable();
mbed_official 50:a417edff4437 482
mbed_official 50:a417edff4437 483 iflag &= chMask;
mbed_official 50:a417edff4437 484 done &= chMask;
mbed_official 50:a417edff4437 485 remaining = ( remaining
mbed_official 50:a417edff4437 486 & _LDMA_CH_CTRL_XFERCNT_MASK )
mbed_official 50:a417edff4437 487 >> _LDMA_CH_CTRL_XFERCNT_SHIFT;
mbed_official 50:a417edff4437 488
mbed_official 50:a417edff4437 489 if ( done || ( ( remaining == 0 ) && iflag ) )
mbed_official 50:a417edff4437 490 {
mbed_official 50:a417edff4437 491 return 0;
mbed_official 50:a417edff4437 492 }
mbed_official 50:a417edff4437 493
mbed_official 50:a417edff4437 494 return remaining + 1;
mbed_official 50:a417edff4437 495 }
mbed_official 50:a417edff4437 496
mbed_official 50:a417edff4437 497 /** @} (end addtogroup LDMA) */
mbed_official 50:a417edff4437 498 /** @} (end addtogroup EM_Library) */
mbed_official 50:a417edff4437 499 #endif /* defined( LDMA_PRESENT ) && ( LDMA_COUNT == 1 ) */