Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_STM/TARGET_STM32F1/pinmap.c@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 *******************************************************************************
<> 144:ef7eb2e8f9f7 3 * Copyright (c) 2014, STMicroelectronics
<> 144:ef7eb2e8f9f7 4 * All rights reserved.
<> 144:ef7eb2e8f9f7 5 *
<> 144:ef7eb2e8f9f7 6 * Redistribution and use in source and binary forms, with or without
<> 144:ef7eb2e8f9f7 7 * modification, are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 10 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 11 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 12 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 13 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 14 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 15 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 16 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 17 *
<> 144:ef7eb2e8f9f7 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 28 *******************************************************************************
<> 144:ef7eb2e8f9f7 29 */
<> 144:ef7eb2e8f9f7 30 #include "mbed_assert.h"
<> 144:ef7eb2e8f9f7 31 #include "pinmap.h"
<> 144:ef7eb2e8f9f7 32 #include "PortNames.h"
<> 144:ef7eb2e8f9f7 33 #include "mbed_error.h"
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 // GPIO mode look-up table
<> 144:ef7eb2e8f9f7 36 // Warning: the elements order must be the same as the one defined in PinNames.h
<> 144:ef7eb2e8f9f7 37 static const uint32_t gpio_mode[13] = {
<> 144:ef7eb2e8f9f7 38 GPIO_MODE_INPUT, // 0 = STM_MODE_INPUT
<> 144:ef7eb2e8f9f7 39 GPIO_MODE_OUTPUT_PP, // 1 = STM_MODE_OUTPUT_PP
<> 144:ef7eb2e8f9f7 40 GPIO_MODE_OUTPUT_OD, // 2 = STM_MODE_OUTPUT_OD
<> 144:ef7eb2e8f9f7 41 GPIO_MODE_AF_PP, // 3 = STM_MODE_AF_PP
<> 144:ef7eb2e8f9f7 42 GPIO_MODE_AF_OD, // 4 = STM_MODE_AF_OD
<> 144:ef7eb2e8f9f7 43 GPIO_MODE_ANALOG, // 5 = STM_MODE_ANALOG
<> 144:ef7eb2e8f9f7 44 GPIO_MODE_IT_RISING, // 6 = STM_MODE_IT_RISING
<> 144:ef7eb2e8f9f7 45 GPIO_MODE_IT_FALLING, // 7 = STM_MODE_IT_FALLING
<> 144:ef7eb2e8f9f7 46 GPIO_MODE_IT_RISING_FALLING, // 8 = STM_MODE_IT_RISING_FALLING
<> 144:ef7eb2e8f9f7 47 GPIO_MODE_EVT_RISING, // 9 = STM_MODE_EVT_RISING
<> 144:ef7eb2e8f9f7 48 GPIO_MODE_EVT_FALLING, // 10 = STM_MODE_EVT_FALLING
<> 144:ef7eb2e8f9f7 49 GPIO_MODE_EVT_RISING_FALLING, // 11 = STM_MODE_EVT_RISING_FALLING
<> 144:ef7eb2e8f9f7 50 0x10000000 // 12 = STM_MODE_IT_EVT_RESET (not in STM32Cube HAL)
<> 144:ef7eb2e8f9f7 51 };
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 // Enable GPIO clock and return GPIO base address
<> 144:ef7eb2e8f9f7 54 uint32_t Set_GPIO_Clock(uint32_t port_idx)
<> 144:ef7eb2e8f9f7 55 {
<> 144:ef7eb2e8f9f7 56 uint32_t gpio_add = 0;
<> 144:ef7eb2e8f9f7 57 switch (port_idx) {
<> 144:ef7eb2e8f9f7 58 case PortA:
<> 144:ef7eb2e8f9f7 59 gpio_add = GPIOA_BASE;
<> 144:ef7eb2e8f9f7 60 __GPIOA_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 61 break;
<> 144:ef7eb2e8f9f7 62 case PortB:
<> 144:ef7eb2e8f9f7 63 gpio_add = GPIOB_BASE;
<> 144:ef7eb2e8f9f7 64 __GPIOB_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 65 break;
<> 144:ef7eb2e8f9f7 66 case PortC:
<> 144:ef7eb2e8f9f7 67 gpio_add = GPIOC_BASE;
<> 144:ef7eb2e8f9f7 68 __GPIOC_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 69 break;
<> 144:ef7eb2e8f9f7 70 case PortD:
<> 144:ef7eb2e8f9f7 71 gpio_add = GPIOD_BASE;
<> 144:ef7eb2e8f9f7 72 __GPIOD_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 73 break;
<> 144:ef7eb2e8f9f7 74 default:
<> 144:ef7eb2e8f9f7 75 error("Pinmap error: wrong port number.");
<> 144:ef7eb2e8f9f7 76 break;
<> 144:ef7eb2e8f9f7 77 }
<> 144:ef7eb2e8f9f7 78 return gpio_add;
<> 144:ef7eb2e8f9f7 79 }
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 /**
<> 144:ef7eb2e8f9f7 82 * Configure pin (input, output, alternate function or analog) + output speed + AF
<> 144:ef7eb2e8f9f7 83 */
<> 144:ef7eb2e8f9f7 84 void pin_function(PinName pin, int data)
<> 144:ef7eb2e8f9f7 85 {
<> 144:ef7eb2e8f9f7 86 MBED_ASSERT(pin != (PinName)NC);
<> 144:ef7eb2e8f9f7 87 // Get the pin informations
<> 144:ef7eb2e8f9f7 88 uint32_t mode = STM_PIN_MODE(data);
<> 144:ef7eb2e8f9f7 89 uint32_t pupd = STM_PIN_PUPD(data);
<> 144:ef7eb2e8f9f7 90 uint32_t afnum = STM_PIN_AFNUM(data);
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 uint32_t port_index = STM_PORT(pin);
<> 144:ef7eb2e8f9f7 93 uint32_t pin_index = STM_PIN(pin);
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 // Enable GPIO clock
<> 144:ef7eb2e8f9f7 96 uint32_t gpio_add = Set_GPIO_Clock(port_index);
<> 144:ef7eb2e8f9f7 97 GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 // Enable AFIO clock
<> 144:ef7eb2e8f9f7 100 __HAL_RCC_AFIO_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 // Configure Alternate Function
<> 144:ef7eb2e8f9f7 103 // Warning: Must be done before the GPIO is initialized
<> 144:ef7eb2e8f9f7 104 if (afnum > 0) {
<> 144:ef7eb2e8f9f7 105 switch (afnum) {
<> 144:ef7eb2e8f9f7 106 case 1: // Remap SPI1
<> 144:ef7eb2e8f9f7 107 __HAL_AFIO_REMAP_SPI1_ENABLE();
<> 144:ef7eb2e8f9f7 108 break;
<> 144:ef7eb2e8f9f7 109 case 2: // Remap I2C1
<> 144:ef7eb2e8f9f7 110 __HAL_AFIO_REMAP_I2C1_ENABLE();
<> 144:ef7eb2e8f9f7 111 break;
<> 144:ef7eb2e8f9f7 112 case 3: // Remap USART1
<> 144:ef7eb2e8f9f7 113 __HAL_AFIO_REMAP_USART1_ENABLE();
<> 144:ef7eb2e8f9f7 114 break;
<> 144:ef7eb2e8f9f7 115 case 4: // Remap USART2
<> 144:ef7eb2e8f9f7 116 __HAL_AFIO_REMAP_USART2_ENABLE();
<> 144:ef7eb2e8f9f7 117 break;
<> 144:ef7eb2e8f9f7 118 case 5: // Partial Remap USART3
<> 144:ef7eb2e8f9f7 119 __HAL_AFIO_REMAP_USART3_PARTIAL();
<> 144:ef7eb2e8f9f7 120 break;
<> 144:ef7eb2e8f9f7 121 case 6: // Partial Remap TIM1
<> 144:ef7eb2e8f9f7 122 __HAL_AFIO_REMAP_TIM1_PARTIAL();
<> 144:ef7eb2e8f9f7 123 break;
<> 144:ef7eb2e8f9f7 124 case 7: // Partial Remap TIM3
<> 144:ef7eb2e8f9f7 125 __HAL_AFIO_REMAP_TIM3_PARTIAL();
<> 144:ef7eb2e8f9f7 126 break;
<> 144:ef7eb2e8f9f7 127 case 8: // Full Remap TIM2
<> 144:ef7eb2e8f9f7 128 __HAL_AFIO_REMAP_TIM2_ENABLE();
<> 144:ef7eb2e8f9f7 129 break;
<> 144:ef7eb2e8f9f7 130 case 9: // Full Remap TIM3
<> 144:ef7eb2e8f9f7 131 __HAL_AFIO_REMAP_TIM3_ENABLE();
<> 144:ef7eb2e8f9f7 132 break;
<> 144:ef7eb2e8f9f7 133 default:
<> 144:ef7eb2e8f9f7 134 break;
<> 144:ef7eb2e8f9f7 135 }
<> 144:ef7eb2e8f9f7 136 }
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 // Configure GPIO
<> 144:ef7eb2e8f9f7 139 GPIO_InitTypeDef GPIO_InitStructure;
<> 144:ef7eb2e8f9f7 140 GPIO_InitStructure.Pin = (uint32_t)(1 << pin_index);
<> 144:ef7eb2e8f9f7 141 GPIO_InitStructure.Mode = gpio_mode[mode];
<> 144:ef7eb2e8f9f7 142 GPIO_InitStructure.Pull = pupd;
<> 144:ef7eb2e8f9f7 143 GPIO_InitStructure.Speed = GPIO_SPEED_HIGH;
<> 144:ef7eb2e8f9f7 144 HAL_GPIO_Init(gpio, &GPIO_InitStructure);
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 // Disconnect JTAG-DP + SW-DP signals.
<> 144:ef7eb2e8f9f7 147 // Warning: Need to reconnect under reset
<> 144:ef7eb2e8f9f7 148 if ((pin == PA_13) || (pin == PA_14)) {
<> 144:ef7eb2e8f9f7 149 __HAL_AFIO_REMAP_SWJ_DISABLE(); // JTAG-DP Disabled and SW-DP Disabled
<> 144:ef7eb2e8f9f7 150 }
<> 144:ef7eb2e8f9f7 151 if ((pin == PA_15) || (pin == PB_3) || (pin == PB_4)) {
<> 144:ef7eb2e8f9f7 152 __HAL_AFIO_REMAP_SWJ_NOJTAG(); // JTAG-DP Disabled and SW-DP enabled
<> 144:ef7eb2e8f9f7 153 }
<> 144:ef7eb2e8f9f7 154 }
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 /**
<> 144:ef7eb2e8f9f7 157 * Configure pin pull-up/pull-down
<> 144:ef7eb2e8f9f7 158 */
<> 144:ef7eb2e8f9f7 159 void pin_mode(PinName pin, PinMode mode)
<> 144:ef7eb2e8f9f7 160 {
<> 144:ef7eb2e8f9f7 161 MBED_ASSERT(pin != (PinName)NC);
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 uint32_t port_index = STM_PORT(pin);
<> 144:ef7eb2e8f9f7 164 uint32_t pin_index = STM_PIN(pin);
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 // Enable GPIO clock
<> 144:ef7eb2e8f9f7 167 uint32_t gpio_add = Set_GPIO_Clock(port_index);
<> 144:ef7eb2e8f9f7 168 GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 // Configure open-drain and pull-up/down
<> 144:ef7eb2e8f9f7 171 switch (mode) {
<> 144:ef7eb2e8f9f7 172 case PullNone:
<> 144:ef7eb2e8f9f7 173 break;
<> 144:ef7eb2e8f9f7 174 case PullUp:
<> 144:ef7eb2e8f9f7 175 case PullDown:
<> 144:ef7eb2e8f9f7 176 // Set pull-up / pull-down for Input mode
<> 144:ef7eb2e8f9f7 177 if (pin_index < 8) {
<> 144:ef7eb2e8f9f7 178 if ((gpio->CRL & (0x03 << (pin_index * 4))) == 0) { // MODE bits = Input mode
<> 144:ef7eb2e8f9f7 179 gpio->CRL |= (0x08 << (pin_index * 4)); // Set pull-up / pull-down
<> 144:ef7eb2e8f9f7 180 gpio->CRL &= ~(0x04 << (pin_index * 4)); // ENSURES GPIOx_CRL.CNFx.bit0 = 0
<> 144:ef7eb2e8f9f7 181 }
<> 144:ef7eb2e8f9f7 182 } else {
<> 144:ef7eb2e8f9f7 183 if ((gpio->CRH & (0x03 << ((pin_index % 8) * 4))) == 0) { // MODE bits = Input mode
<> 144:ef7eb2e8f9f7 184 gpio->CRH |= (0x08 << ((pin_index % 8) * 4)); // Set pull-up / pull-down
<> 144:ef7eb2e8f9f7 185 gpio->CRH &= ~(0x04 << ((pin_index % 8) * 4)); // ENSURES GPIOx_CRH.CNFx.bit0 = 0
<> 144:ef7eb2e8f9f7 186 }
<> 144:ef7eb2e8f9f7 187 }
<> 144:ef7eb2e8f9f7 188 // Now it's time to setup properly if pullup or pulldown. This is done in ODR register:
<> 144:ef7eb2e8f9f7 189 // set pull-up => bit=1, set pull-down => bit = 0
<> 144:ef7eb2e8f9f7 190 if (mode == PullUp) {
<> 144:ef7eb2e8f9f7 191 gpio->ODR |= (0x01 << (pin_index)); // Set pull-up
<> 144:ef7eb2e8f9f7 192 } else{
<> 144:ef7eb2e8f9f7 193 gpio->ODR &= ~(0x01 << (pin_index)); // Set pull-down
<> 144:ef7eb2e8f9f7 194 }
<> 144:ef7eb2e8f9f7 195 break;
<> 144:ef7eb2e8f9f7 196 case OpenDrain:
<> 144:ef7eb2e8f9f7 197 // Set open-drain for Output mode (General Purpose or Alternate Function)
<> 144:ef7eb2e8f9f7 198 if (pin_index < 8) {
<> 144:ef7eb2e8f9f7 199 if ((gpio->CRL & (0x03 << (pin_index * 4))) > 0) { // MODE bits = Output mode
<> 144:ef7eb2e8f9f7 200 gpio->CRL |= (0x04 << (pin_index * 4)); // Set open-drain
<> 144:ef7eb2e8f9f7 201 }
<> 144:ef7eb2e8f9f7 202 } else {
<> 144:ef7eb2e8f9f7 203 if ((gpio->CRH & (0x03 << ((pin_index % 8) * 4))) > 0) { // MODE bits = Output mode
<> 144:ef7eb2e8f9f7 204 gpio->CRH |= (0x04 << ((pin_index % 8) * 4)); // Set open-drain
<> 144:ef7eb2e8f9f7 205 }
<> 144:ef7eb2e8f9f7 206 }
<> 144:ef7eb2e8f9f7 207 break;
<> 144:ef7eb2e8f9f7 208 default:
<> 144:ef7eb2e8f9f7 209 break;
<> 144:ef7eb2e8f9f7 210 }
<> 144:ef7eb2e8f9f7 211 }