Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/ethernet_api.c@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
119:3921aeca8633 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 119:3921aeca8633 1 /* mbed Microcontroller Library
mbed_official 119:3921aeca8633 2 * Copyright (c) 2006-2013 ARM Limited
mbed_official 119:3921aeca8633 3 *
mbed_official 119:3921aeca8633 4 * Licensed under the Apache License, Version 2.0 (the "License");
mbed_official 119:3921aeca8633 5 * you may not use this file except in compliance with the License.
mbed_official 119:3921aeca8633 6 * You may obtain a copy of the License at
mbed_official 119:3921aeca8633 7 *
mbed_official 119:3921aeca8633 8 * http://www.apache.org/licenses/LICENSE-2.0
mbed_official 119:3921aeca8633 9 *
mbed_official 119:3921aeca8633 10 * Unless required by applicable law or agreed to in writing, software
mbed_official 119:3921aeca8633 11 * distributed under the License is distributed on an "AS IS" BASIS,
mbed_official 119:3921aeca8633 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 119:3921aeca8633 13 * See the License for the specific language governing permissions and
mbed_official 119:3921aeca8633 14 * limitations under the License.
mbed_official 119:3921aeca8633 15 */
mbed_official 119:3921aeca8633 16 #include <string.h>
mbed_official 119:3921aeca8633 17 #include "ethernet_api.h"
mbed_official 119:3921aeca8633 18 #include "cmsis.h"
mbed_official 119:3921aeca8633 19 #include "mbed_interface.h"
mbed_official 119:3921aeca8633 20 #include "toolchain.h"
mbed_official 119:3921aeca8633 21 #include "mbed_error.h"
mbed_official 119:3921aeca8633 22 #include "ether_iodefine.h"
mbed_official 119:3921aeca8633 23 #include "ethernetext_api.h"
mbed_official 119:3921aeca8633 24
mbed_official 119:3921aeca8633 25 /* Descriptor info */
mbed_official 119:3921aeca8633 26 #define NUM_OF_TX_DESCRIPTOR (16)
mbed_official 119:3921aeca8633 27 #define NUM_OF_RX_DESCRIPTOR (16)
mbed_official 119:3921aeca8633 28 #define SIZE_OF_BUFFER (1600) /* Must be an integral multiple of 32 */
mbed_official 119:3921aeca8633 29 #define MAX_SEND_SIZE (1514)
mbed_official 119:3921aeca8633 30 /* Ethernet Descriptor Value Define */
mbed_official 119:3921aeca8633 31 #define TD0_TFP_TOP_BOTTOM (0x30000000)
mbed_official 119:3921aeca8633 32 #define TD0_TACT (0x80000000)
mbed_official 119:3921aeca8633 33 #define TD0_TDLE (0x40000000)
mbed_official 119:3921aeca8633 34 #define RD0_RACT (0x80000000)
mbed_official 119:3921aeca8633 35 #define RD0_RDLE (0x40000000)
mbed_official 119:3921aeca8633 36 #define RD0_RFE (0x08000000)
mbed_official 119:3921aeca8633 37 #define RD0_RCSE (0x04000000)
mbed_official 119:3921aeca8633 38 #define RD0_RFS (0x03FF0000)
mbed_official 119:3921aeca8633 39 #define RD0_RCS (0x0000FFFF)
mbed_official 119:3921aeca8633 40 #define RD0_RFS_RFOF (0x02000000)
mbed_official 119:3921aeca8633 41 #define RD0_RFS_RUAF (0x00400000)
mbed_official 119:3921aeca8633 42 #define RD0_RFS_RRF (0x00100000)
mbed_official 119:3921aeca8633 43 #define RD0_RFS_RTLF (0x00080000)
mbed_official 119:3921aeca8633 44 #define RD0_RFS_RTSF (0x00040000)
mbed_official 119:3921aeca8633 45 #define RD0_RFS_PRE (0x00020000)
mbed_official 119:3921aeca8633 46 #define RD0_RFS_CERF (0x00010000)
mbed_official 119:3921aeca8633 47 #define RD0_RFS_ERROR (RD0_RFS_RFOF | RD0_RFS_RUAF | RD0_RFS_RRF | RD0_RFS_RTLF | \
mbed_official 119:3921aeca8633 48 RD0_RFS_RTSF | RD0_RFS_PRE | RD0_RFS_CERF)
mbed_official 119:3921aeca8633 49 #define RD1_RDL_MSK (0x0000FFFF)
mbed_official 119:3921aeca8633 50 /* PHY Register */
mbed_official 119:3921aeca8633 51 #define BASIC_MODE_CONTROL_REG (0)
mbed_official 119:3921aeca8633 52 #define BASIC_MODE_STATUS_REG (1)
mbed_official 119:3921aeca8633 53 #define PHY_IDENTIFIER1_REG (2)
mbed_official 119:3921aeca8633 54 #define PHY_IDENTIFIER2_REG (3)
mbed_official 119:3921aeca8633 55 #define PHY_SP_CTL_STS_REG (31)
mbed_official 119:3921aeca8633 56 /* MII management interface access */
mbed_official 119:3921aeca8633 57 #define PHY_ADDR (0) /* Confirm the pin connection of the PHY-LSI */
mbed_official 119:3921aeca8633 58 #define PHY_ST (1)
mbed_official 119:3921aeca8633 59 #define PHY_WRITE (1)
mbed_official 119:3921aeca8633 60 #define PHY_READ (2)
mbed_official 119:3921aeca8633 61 #define MDC_WAIT (6) /* 400ns/4 */
mbed_official 119:3921aeca8633 62 #define BASIC_STS_MSK_LINK (0x0004) /* Link Status */
mbed_official 119:3921aeca8633 63 #define BASIC_STS_MSK_AUTO_CMP (0x0020) /* Auto-Negotiate Complete */
mbed_official 119:3921aeca8633 64 #define M_PHY_ID (0xFFFFFFF0)
mbed_official 119:3921aeca8633 65 #define PHY_ID_LAN8710A (0x0007C0F0)
mbed_official 119:3921aeca8633 66 /* ETHERPIR0 */
mbed_official 119:3921aeca8633 67 #define PIR0_MDI (0x00000008)
mbed_official 119:3921aeca8633 68 #define PIR0_MDO (0x00000004)
mbed_official 119:3921aeca8633 69 #define PIR0_MMD (0x00000002)
mbed_official 119:3921aeca8633 70 #define PIR0_MDC (0x00000001)
mbed_official 119:3921aeca8633 71 #define PIR0_MDC_HIGH (0x00000001)
mbed_official 119:3921aeca8633 72 #define PIR0_MDC_LOW (0x00000000)
mbed_official 119:3921aeca8633 73 /* ETHEREDRRR0 */
mbed_official 119:3921aeca8633 74 #define EDRRR0_RR (0x00000001)
mbed_official 119:3921aeca8633 75 /* ETHEREDTRR0 */
mbed_official 119:3921aeca8633 76 #define EDTRR0_TR (0x00000003)
mbed_official 119:3921aeca8633 77 /* software wait */
mbed_official 119:3921aeca8633 78 #define LOOP_100us (6700) /* Loop counter for software wait 6666=100us/((1/400MHz)*6cyc) */
mbed_official 119:3921aeca8633 79
mbed_official 119:3921aeca8633 80 #define EDMAC_EESIPR_INI_RECV (0x0205001F) /* 0x02000000 : Detect reception suspended */
mbed_official 119:3921aeca8633 81 /* 0x00040000 : Detect frame reception */
mbed_official 119:3921aeca8633 82 /* 0x00010000 : Receive FIFO overflow */
mbed_official 119:3921aeca8633 83 /* 0x00000010 : Residual bit frame reception */
mbed_official 119:3921aeca8633 84 /* 0x00000008 : Long frame reception */
mbed_official 119:3921aeca8633 85 /* 0x00000004 : Short frame reception */
mbed_official 119:3921aeca8633 86 /* 0x00000002 : PHY-LSI reception error */
mbed_official 119:3921aeca8633 87 /* 0x00000001 : Receive frame CRC error */
mbed_official 119:3921aeca8633 88 #define EDMAC_EESIPR_INI_EtherC (0x00400000) /* 0x00400000 : E-MAC status register */
mbed_official 119:3921aeca8633 89
mbed_official 119:3921aeca8633 90 /* Send descriptor */
mbed_official 119:3921aeca8633 91 typedef struct tag_edmac_send_desc {
mbed_official 119:3921aeca8633 92 uint32_t td0;
mbed_official 119:3921aeca8633 93 uint32_t td1;
mbed_official 119:3921aeca8633 94 uint8_t *td2;
mbed_official 119:3921aeca8633 95 uint32_t padding4;
mbed_official 119:3921aeca8633 96 } edmac_send_desc_t;
mbed_official 119:3921aeca8633 97
mbed_official 119:3921aeca8633 98 /* Receive descriptor */
mbed_official 119:3921aeca8633 99 typedef struct tag_edmac_recv_desc {
mbed_official 119:3921aeca8633 100 uint32_t rd0;
mbed_official 119:3921aeca8633 101 uint32_t rd1;
mbed_official 119:3921aeca8633 102 uint8_t *rd2;
mbed_official 119:3921aeca8633 103 uint32_t padding4;
mbed_official 119:3921aeca8633 104 } edmac_recv_desc_t;
mbed_official 119:3921aeca8633 105
mbed_official 119:3921aeca8633 106 /* memory */
mbed_official 119:3921aeca8633 107 /* The whole transmit/receive descriptors (must be allocated in 16-byte boundaries) */
mbed_official 119:3921aeca8633 108 /* Transmit/receive buffers (must be allocated in 16-byte boundaries) */
mbed_official 119:3921aeca8633 109 #if defined(__ICCARM__)
mbed_official 119:3921aeca8633 110 #pragma data_alignment=16
mbed_official 119:3921aeca8633 111 static uint8_t ethernet_nc_memory[(sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR) +
mbed_official 119:3921aeca8633 112 (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR) +
mbed_official 119:3921aeca8633 113 (NUM_OF_TX_DESCRIPTOR * SIZE_OF_BUFFER) +
mbed_official 119:3921aeca8633 114 (NUM_OF_RX_DESCRIPTOR * SIZE_OF_BUFFER)] //16 bytes aligned!
mbed_official 119:3921aeca8633 115 @ ".mirrorram";
mbed_official 119:3921aeca8633 116 #else
mbed_official 119:3921aeca8633 117 static uint8_t ethernet_nc_memory[(sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR) +
mbed_official 119:3921aeca8633 118 (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR) +
mbed_official 119:3921aeca8633 119 (NUM_OF_TX_DESCRIPTOR * SIZE_OF_BUFFER) +
mbed_official 119:3921aeca8633 120 (NUM_OF_RX_DESCRIPTOR * SIZE_OF_BUFFER)]
mbed_official 119:3921aeca8633 121 __attribute((section("NC_BSS"),aligned(16))); //16 bytes aligned!
mbed_official 119:3921aeca8633 122 #endif
mbed_official 119:3921aeca8633 123 static int32_t rx_read_offset; /* read offset */
mbed_official 119:3921aeca8633 124 static int32_t tx_wite_offset; /* write offset */
mbed_official 119:3921aeca8633 125 static uint32_t send_top_index;
mbed_official 119:3921aeca8633 126 static uint32_t recv_top_index;
mbed_official 119:3921aeca8633 127 static int32_t Interrupt_priority;
mbed_official 119:3921aeca8633 128 static edmac_send_desc_t *p_eth_desc_dsend = NULL;
mbed_official 119:3921aeca8633 129 static edmac_recv_desc_t *p_eth_desc_drecv = NULL;
mbed_official 119:3921aeca8633 130 static edmac_recv_desc_t *p_recv_end_desc = NULL;
mbed_official 119:3921aeca8633 131 static ethernetext_cb_fnc *p_recv_cb_fnc = NULL;
mbed_official 119:3921aeca8633 132 static char mac_addr[6] = {0x00, 0x02, 0xF7, 0xF0, 0x00, 0x00}; /* MAC Address */
mbed_official 119:3921aeca8633 133 static uint32_t phy_id = 0;
mbed_official 119:3921aeca8633 134 static uint32_t start_stop = 1; /* 0:stop 1:start */
mbed_official 119:3921aeca8633 135
mbed_official 119:3921aeca8633 136 /* function */
mbed_official 119:3921aeca8633 137 static void lan_reg_reset(void);
mbed_official 119:3921aeca8633 138 static void lan_desc_create(void);
mbed_official 119:3921aeca8633 139 static void lan_reg_set(int32_t link);
mbed_official 119:3921aeca8633 140 static uint16_t phy_reg_read(uint16_t reg_addr);
mbed_official 119:3921aeca8633 141 static void phy_reg_write(uint16_t reg_addr, uint16_t data);
mbed_official 119:3921aeca8633 142 static void mii_preamble(void);
mbed_official 119:3921aeca8633 143 static void mii_cmd(uint16_t reg_addr, uint32_t option);
mbed_official 119:3921aeca8633 144 static void mii_reg_read(uint16_t *data);
mbed_official 119:3921aeca8633 145 static void mii_reg_write(uint16_t data);
mbed_official 119:3921aeca8633 146 static void mii_z(void);
mbed_official 119:3921aeca8633 147 static void mii_write_1(void);
mbed_official 119:3921aeca8633 148 static void mii_write_0(void);
mbed_official 119:3921aeca8633 149 static void set_ether_pir(uint32_t set_data);
mbed_official 119:3921aeca8633 150 static void wait_100us(int32_t wait_cnt);
mbed_official 119:3921aeca8633 151
mbed_official 119:3921aeca8633 152
mbed_official 119:3921aeca8633 153 int ethernetext_init(ethernet_cfg_t *p_ethcfg) {
mbed_official 119:3921aeca8633 154 int32_t i;
mbed_official 119:3921aeca8633 155 uint16_t val;
mbed_official 119:3921aeca8633 156
mbed_official 119:3921aeca8633 157 CPGSTBCR7 &= ~(CPG_STBCR7_BIT_MSTP74); /* enable ETHER clock */
mbed_official 119:3921aeca8633 158
mbed_official 119:3921aeca8633 159 /* -->4F<-- P1_14(ET_COL) */
mbed_official 119:3921aeca8633 160 GPIOPMC1 |= 0x4000;
mbed_official 119:3921aeca8633 161 GPIOPFCAE1 &= ~0x4000;
mbed_official 119:3921aeca8633 162 GPIOPFCE1 |= 0x4000;
mbed_official 119:3921aeca8633 163 GPIOPFC1 |= 0x4000;
mbed_official 119:3921aeca8633 164 GPIOPIPC1 |= 0x4000;
mbed_official 119:3921aeca8633 165
mbed_official 119:3921aeca8633 166 /* -->2F<-- P2_0(ET_TXCLK), P2_1(ET_TXER), P2_2(ET_TXEN), P2_3(ET_CRS), P2_4(ET_TXD0),
mbed_official 119:3921aeca8633 167 P2_5(ET_TXD1), P2_6(ET_TXD2), P2_7(ET_TXD3), P2_8(ET_RXD0), P2_9(ET_RXD1), P2_10(ET_RXD2) P2_11(ET_RXD3) */
mbed_official 119:3921aeca8633 168 GPIOPMC2 |= 0x0FFF;
mbed_official 119:3921aeca8633 169 GPIOPFCAE2 &= ~0x0FFF;
mbed_official 119:3921aeca8633 170 GPIOPFCE2 &= ~0x0FFF;
mbed_official 119:3921aeca8633 171 GPIOPFC2 |= 0x0FFF;
mbed_official 119:3921aeca8633 172 GPIOPIPC2 |= 0x0FFF;
mbed_official 119:3921aeca8633 173
mbed_official 119:3921aeca8633 174 /* -->3F<-- P3_3(ET_MDIO), P3_4(ET_RXCLK), P3_5(ET_RXER), P3_6(ET_RXDV) */
mbed_official 119:3921aeca8633 175 GPIOPMC3 |= 0x0078;
mbed_official 119:3921aeca8633 176 GPIOPFCAE3 &= ~0x0078;
mbed_official 119:3921aeca8633 177 GPIOPFCE3 &= ~0x0078;
mbed_official 119:3921aeca8633 178 GPIOPFC3 |= 0x0078;
mbed_official 119:3921aeca8633 179 GPIOPIPC3 |= 0x0078;
mbed_official 119:3921aeca8633 180
mbed_official 119:3921aeca8633 181 /* -->3F<-- P7_0(ET_MDC) */
mbed_official 119:3921aeca8633 182 GPIOPMC7 |= 0x0001;
mbed_official 119:3921aeca8633 183 GPIOPFCAE7 &= ~0x0001;
mbed_official 119:3921aeca8633 184 GPIOPFCE7 |= 0x0001;
mbed_official 119:3921aeca8633 185 GPIOPFC7 &= ~0x0001;
mbed_official 119:3921aeca8633 186 GPIOPIPC7 |= 0x0001;
mbed_official 119:3921aeca8633 187
mbed_official 119:3921aeca8633 188 /* Resets the E-MAC,E-DMAC */
mbed_official 119:3921aeca8633 189 lan_reg_reset();
mbed_official 119:3921aeca8633 190
mbed_official 119:3921aeca8633 191 /* Resets the PHY-LSI */
mbed_official 119:3921aeca8633 192 phy_reg_write(BASIC_MODE_CONTROL_REG, 0x8000);
mbed_official 119:3921aeca8633 193 for (i = 10000; i > 0; i--) {
mbed_official 119:3921aeca8633 194 val = phy_reg_read(BASIC_MODE_CONTROL_REG);
mbed_official 119:3921aeca8633 195 if (((uint32_t)val & 0x8000uL) == 0) {
mbed_official 119:3921aeca8633 196 break; /* Reset complete */
mbed_official 119:3921aeca8633 197 }
mbed_official 119:3921aeca8633 198 }
mbed_official 119:3921aeca8633 199
mbed_official 119:3921aeca8633 200 phy_id = ((uint32_t)phy_reg_read(PHY_IDENTIFIER1_REG) << 16)
mbed_official 119:3921aeca8633 201 | (uint32_t)phy_reg_read(PHY_IDENTIFIER2_REG);
mbed_official 119:3921aeca8633 202
mbed_official 119:3921aeca8633 203 Interrupt_priority = p_ethcfg->int_priority;
mbed_official 119:3921aeca8633 204 p_recv_cb_fnc = p_ethcfg->recv_cb;
mbed_official 119:3921aeca8633 205 start_stop = 1;
mbed_official 119:3921aeca8633 206
mbed_official 119:3921aeca8633 207 if (p_ethcfg->ether_mac != NULL) {
mbed_official 119:3921aeca8633 208 (void)memcpy(mac_addr, p_ethcfg->ether_mac, sizeof(mac_addr));
mbed_official 119:3921aeca8633 209 } else {
mbed_official 119:3921aeca8633 210 ethernet_address(mac_addr); /* Get MAC Address */
mbed_official 119:3921aeca8633 211 }
mbed_official 119:3921aeca8633 212
mbed_official 119:3921aeca8633 213 return 0;
mbed_official 119:3921aeca8633 214 }
mbed_official 119:3921aeca8633 215
mbed_official 119:3921aeca8633 216 void ethernetext_start_stop(int32_t mode) {
mbed_official 119:3921aeca8633 217 if (mode == 1) {
mbed_official 119:3921aeca8633 218 /* start */
mbed_official 119:3921aeca8633 219 ETHEREDTRR0 |= EDTRR0_TR;
mbed_official 119:3921aeca8633 220 ETHEREDRRR0 |= EDRRR0_RR;
mbed_official 119:3921aeca8633 221 start_stop = 1;
mbed_official 119:3921aeca8633 222 } else {
mbed_official 119:3921aeca8633 223 /* stop */
mbed_official 119:3921aeca8633 224 ETHEREDTRR0 &= ~EDTRR0_TR;
mbed_official 119:3921aeca8633 225 ETHEREDRRR0 &= ~EDRRR0_RR;
mbed_official 119:3921aeca8633 226 start_stop = 0;
mbed_official 119:3921aeca8633 227 }
mbed_official 119:3921aeca8633 228 }
mbed_official 119:3921aeca8633 229
mbed_official 119:3921aeca8633 230 int ethernetext_chk_link_mode(void) {
mbed_official 119:3921aeca8633 231 int32_t link;
mbed_official 119:3921aeca8633 232 uint16_t data;
mbed_official 119:3921aeca8633 233
mbed_official 119:3921aeca8633 234 if ((phy_id & M_PHY_ID) == PHY_ID_LAN8710A) {
mbed_official 119:3921aeca8633 235 data = phy_reg_read(PHY_SP_CTL_STS_REG);
mbed_official 119:3921aeca8633 236 switch (((uint32_t)data >> 2) & 0x00000007) {
mbed_official 119:3921aeca8633 237 case 0x0001:
mbed_official 119:3921aeca8633 238 link = HALF_10M;
mbed_official 119:3921aeca8633 239 break;
mbed_official 119:3921aeca8633 240 case 0x0005:
mbed_official 119:3921aeca8633 241 link = FULL_10M;
mbed_official 119:3921aeca8633 242 break;
mbed_official 119:3921aeca8633 243 case 0x0002:
mbed_official 119:3921aeca8633 244 link = HALF_TX;
mbed_official 119:3921aeca8633 245 break;
mbed_official 119:3921aeca8633 246 case 0x0006:
mbed_official 119:3921aeca8633 247 link = FULL_TX;
mbed_official 119:3921aeca8633 248 break;
mbed_official 119:3921aeca8633 249 default:
mbed_official 119:3921aeca8633 250 link = NEGO_FAIL;
mbed_official 119:3921aeca8633 251 break;
mbed_official 119:3921aeca8633 252 }
mbed_official 119:3921aeca8633 253 } else {
mbed_official 119:3921aeca8633 254 link = NEGO_FAIL;
mbed_official 119:3921aeca8633 255 }
mbed_official 119:3921aeca8633 256
mbed_official 119:3921aeca8633 257 return link;
mbed_official 119:3921aeca8633 258 }
mbed_official 119:3921aeca8633 259
mbed_official 119:3921aeca8633 260 void ethernetext_set_link_mode(int32_t link) {
mbed_official 119:3921aeca8633 261 lan_reg_reset(); /* Resets the E-MAC,E-DMAC */
mbed_official 119:3921aeca8633 262 lan_desc_create(); /* Initialize of buffer memory */
mbed_official 119:3921aeca8633 263 lan_reg_set(link); /* E-DMAC, E-MAC initialization */
mbed_official 119:3921aeca8633 264 }
mbed_official 119:3921aeca8633 265
mbed_official 119:3921aeca8633 266 int ethernet_init() {
mbed_official 119:3921aeca8633 267 ethernet_cfg_t ethcfg;
mbed_official 119:3921aeca8633 268
mbed_official 119:3921aeca8633 269 ethcfg.int_priority = 5;
mbed_official 119:3921aeca8633 270 ethcfg.recv_cb = NULL;
mbed_official 119:3921aeca8633 271 ethcfg.ether_mac = NULL;
mbed_official 119:3921aeca8633 272 ethernetext_init(&ethcfg);
mbed_official 119:3921aeca8633 273 ethernet_set_link(-1, 0); /* Auto-Negotiation */
mbed_official 119:3921aeca8633 274
mbed_official 119:3921aeca8633 275 return 0;
mbed_official 119:3921aeca8633 276 }
mbed_official 119:3921aeca8633 277
mbed_official 119:3921aeca8633 278 void ethernet_free() {
mbed_official 119:3921aeca8633 279 ETHERARSTR |= 0x00000001; /* ETHER software reset */
mbed_official 119:3921aeca8633 280 CPGSTBCR7 |= CPG_STBCR7_BIT_MSTP74; /* disable ETHER clock */
mbed_official 119:3921aeca8633 281 }
mbed_official 119:3921aeca8633 282
mbed_official 119:3921aeca8633 283 int ethernet_write(const char *data, int slen) {
mbed_official 119:3921aeca8633 284 edmac_send_desc_t *p_send_desc;
mbed_official 119:3921aeca8633 285 int32_t copy_size;
mbed_official 119:3921aeca8633 286
mbed_official 119:3921aeca8633 287 if ((p_eth_desc_dsend == NULL) || (data == NULL) || (slen < 0)
mbed_official 119:3921aeca8633 288 || (tx_wite_offset < 0) || (tx_wite_offset >= MAX_SEND_SIZE)) {
mbed_official 119:3921aeca8633 289 copy_size = 0;
mbed_official 119:3921aeca8633 290 } else {
mbed_official 119:3921aeca8633 291 p_send_desc = &p_eth_desc_dsend[send_top_index]; /* Current descriptor */
mbed_official 119:3921aeca8633 292 if ((p_send_desc->td0 & TD0_TACT) != 0) {
mbed_official 119:3921aeca8633 293 copy_size = 0;
mbed_official 119:3921aeca8633 294 } else {
mbed_official 119:3921aeca8633 295 copy_size = MAX_SEND_SIZE - tx_wite_offset;
mbed_official 119:3921aeca8633 296 if (copy_size > slen) {
mbed_official 119:3921aeca8633 297 copy_size = slen;
mbed_official 119:3921aeca8633 298 }
mbed_official 119:3921aeca8633 299 (void)memcpy(&p_send_desc->td2[tx_wite_offset], data, copy_size);
mbed_official 119:3921aeca8633 300 tx_wite_offset += copy_size;
mbed_official 119:3921aeca8633 301 }
mbed_official 119:3921aeca8633 302 }
mbed_official 119:3921aeca8633 303
mbed_official 119:3921aeca8633 304 return copy_size;
mbed_official 119:3921aeca8633 305 }
mbed_official 119:3921aeca8633 306
mbed_official 119:3921aeca8633 307 int ethernet_send() {
mbed_official 119:3921aeca8633 308 edmac_send_desc_t *p_send_desc;
mbed_official 119:3921aeca8633 309 int32_t ret;
mbed_official 119:3921aeca8633 310
mbed_official 119:3921aeca8633 311 if ((p_eth_desc_dsend == NULL) || (tx_wite_offset <= 0)) {
mbed_official 119:3921aeca8633 312 ret = 0;
mbed_official 119:3921aeca8633 313 } else {
mbed_official 119:3921aeca8633 314 /* Transfer 1 frame */
mbed_official 119:3921aeca8633 315 p_send_desc = &p_eth_desc_dsend[send_top_index]; /* Current descriptor */
mbed_official 119:3921aeca8633 316
mbed_official 119:3921aeca8633 317 /* Sets the frame length */
mbed_official 119:3921aeca8633 318 p_send_desc->td1 = ((uint32_t)tx_wite_offset << 16);
mbed_official 119:3921aeca8633 319 tx_wite_offset = 0;
mbed_official 119:3921aeca8633 320
mbed_official 119:3921aeca8633 321 /* Sets the transmit descriptor to transmit again */
mbed_official 119:3921aeca8633 322 p_send_desc->td0 &= (TD0_TACT | TD0_TDLE | TD0_TFP_TOP_BOTTOM);
mbed_official 119:3921aeca8633 323 p_send_desc->td0 |= TD0_TACT;
mbed_official 119:3921aeca8633 324 if ((start_stop == 1) && ((ETHEREDTRR0 & EDTRR0_TR) != EDTRR0_TR)) {
mbed_official 119:3921aeca8633 325 ETHEREDTRR0 |= EDTRR0_TR;
mbed_official 119:3921aeca8633 326 }
mbed_official 119:3921aeca8633 327
mbed_official 119:3921aeca8633 328 /* Update the current descriptor */
mbed_official 119:3921aeca8633 329 send_top_index++;
mbed_official 119:3921aeca8633 330 if (send_top_index >= NUM_OF_TX_DESCRIPTOR) {
mbed_official 119:3921aeca8633 331 send_top_index = 0;
mbed_official 119:3921aeca8633 332 }
mbed_official 119:3921aeca8633 333 ret = 1;
mbed_official 119:3921aeca8633 334 }
mbed_official 119:3921aeca8633 335
mbed_official 119:3921aeca8633 336 return ret;
mbed_official 119:3921aeca8633 337 }
mbed_official 119:3921aeca8633 338
mbed_official 119:3921aeca8633 339 int ethernet_receive() {
mbed_official 119:3921aeca8633 340 edmac_recv_desc_t *p_recv_desc;
mbed_official 119:3921aeca8633 341 int32_t receive_size = 0;
mbed_official 119:3921aeca8633 342
mbed_official 119:3921aeca8633 343 if (p_eth_desc_drecv != NULL) {
mbed_official 119:3921aeca8633 344 if (p_recv_end_desc != NULL) {
mbed_official 119:3921aeca8633 345 /* Sets the receive descriptor to receive again */
mbed_official 119:3921aeca8633 346 p_recv_end_desc->rd0 &= (RD0_RACT | RD0_RDLE);
mbed_official 119:3921aeca8633 347 p_recv_end_desc->rd0 |= RD0_RACT;
mbed_official 119:3921aeca8633 348 if ((start_stop == 1) && ((ETHEREDRRR0 & EDRRR0_RR) == 0)) {
mbed_official 119:3921aeca8633 349 ETHEREDRRR0 |= EDRRR0_RR;
mbed_official 119:3921aeca8633 350 }
mbed_official 119:3921aeca8633 351 p_recv_end_desc = NULL;
mbed_official 119:3921aeca8633 352 }
mbed_official 119:3921aeca8633 353
mbed_official 119:3921aeca8633 354 p_recv_desc = &p_eth_desc_drecv[recv_top_index]; /* Current descriptor */
mbed_official 119:3921aeca8633 355 if ((p_recv_desc->rd0 & RD0_RACT) == 0) {
mbed_official 119:3921aeca8633 356 /* Receives 1 frame */
mbed_official 119:3921aeca8633 357 if (((p_recv_desc->rd0 & RD0_RFE) != 0) && ((p_recv_desc->rd0 & RD0_RFS_ERROR) != 0)) {
mbed_official 119:3921aeca8633 358 /* Receive frame error */
mbed_official 119:3921aeca8633 359 /* Sets the receive descriptor to receive again */
mbed_official 119:3921aeca8633 360 p_recv_desc->rd0 &= (RD0_RACT | RD0_RDLE);
mbed_official 119:3921aeca8633 361 p_recv_desc->rd0 |= RD0_RACT;
mbed_official 119:3921aeca8633 362 if ((start_stop == 1) && ((ETHEREDRRR0 & EDRRR0_RR) == 0)) {
mbed_official 119:3921aeca8633 363 ETHEREDRRR0 |= EDRRR0_RR;
mbed_official 119:3921aeca8633 364 }
mbed_official 119:3921aeca8633 365 } else {
mbed_official 119:3921aeca8633 366 /* Copies the received frame */
mbed_official 119:3921aeca8633 367 rx_read_offset = 0;
mbed_official 119:3921aeca8633 368 p_recv_end_desc = p_recv_desc;
mbed_official 119:3921aeca8633 369 receive_size = (p_recv_desc->rd1 & RD1_RDL_MSK); /* number of bytes received */
mbed_official 119:3921aeca8633 370 }
mbed_official 119:3921aeca8633 371
mbed_official 119:3921aeca8633 372 /* Update the current descriptor */
mbed_official 119:3921aeca8633 373 recv_top_index++;
mbed_official 119:3921aeca8633 374 if (recv_top_index >= NUM_OF_TX_DESCRIPTOR) {
mbed_official 119:3921aeca8633 375 recv_top_index = 0;
mbed_official 119:3921aeca8633 376 }
mbed_official 119:3921aeca8633 377 }
mbed_official 119:3921aeca8633 378 }
mbed_official 119:3921aeca8633 379
mbed_official 119:3921aeca8633 380 return receive_size;
mbed_official 119:3921aeca8633 381 }
mbed_official 119:3921aeca8633 382
mbed_official 119:3921aeca8633 383 int ethernet_read(char *data, int dlen) {
mbed_official 119:3921aeca8633 384 edmac_recv_desc_t *p_recv_desc = p_recv_end_desc; /* Read top descriptor */
mbed_official 119:3921aeca8633 385 int32_t copy_size;
mbed_official 119:3921aeca8633 386
mbed_official 119:3921aeca8633 387 if ((data == NULL) || (dlen < 0) || (p_recv_desc == NULL)) {
mbed_official 119:3921aeca8633 388 copy_size = 0;
mbed_official 119:3921aeca8633 389 } else {
mbed_official 119:3921aeca8633 390 copy_size = (p_recv_desc->rd1 & RD1_RDL_MSK) - rx_read_offset;
mbed_official 119:3921aeca8633 391 if (copy_size > dlen) {
mbed_official 119:3921aeca8633 392 copy_size = dlen;
mbed_official 119:3921aeca8633 393 }
mbed_official 119:3921aeca8633 394 (void)memcpy(data, &p_recv_desc->rd2[rx_read_offset], (size_t)copy_size);
mbed_official 119:3921aeca8633 395 rx_read_offset += copy_size;
mbed_official 119:3921aeca8633 396 }
mbed_official 119:3921aeca8633 397
mbed_official 119:3921aeca8633 398 return copy_size;
mbed_official 119:3921aeca8633 399 }
mbed_official 119:3921aeca8633 400
mbed_official 119:3921aeca8633 401 void ethernet_address(char *mac) {
mbed_official 119:3921aeca8633 402 if (mac != NULL) {
mbed_official 119:3921aeca8633 403 mbed_mac_address(mac); /* Get MAC Address */
mbed_official 119:3921aeca8633 404 }
mbed_official 119:3921aeca8633 405 }
mbed_official 119:3921aeca8633 406
mbed_official 119:3921aeca8633 407 int ethernet_link(void) {
mbed_official 119:3921aeca8633 408 int32_t ret;
mbed_official 119:3921aeca8633 409 uint16_t data;
mbed_official 119:3921aeca8633 410
mbed_official 119:3921aeca8633 411 data = phy_reg_read(BASIC_MODE_STATUS_REG);
mbed_official 119:3921aeca8633 412 if (((uint32_t)data & BASIC_STS_MSK_LINK) != 0) {
mbed_official 119:3921aeca8633 413 ret = 1;
mbed_official 119:3921aeca8633 414 } else {
mbed_official 119:3921aeca8633 415 ret = 0;
mbed_official 119:3921aeca8633 416 }
mbed_official 119:3921aeca8633 417
mbed_official 119:3921aeca8633 418 return ret;
mbed_official 119:3921aeca8633 419 }
mbed_official 119:3921aeca8633 420
mbed_official 119:3921aeca8633 421 void ethernet_set_link(int speed, int duplex) {
mbed_official 119:3921aeca8633 422 uint16_t data;
mbed_official 119:3921aeca8633 423 int32_t i;
mbed_official 119:3921aeca8633 424 int32_t link;
mbed_official 119:3921aeca8633 425
mbed_official 119:3921aeca8633 426 if ((speed < 0) || (speed > 1)) {
mbed_official 119:3921aeca8633 427 data = 0x1000; /* Auto-Negotiation Enable */
mbed_official 119:3921aeca8633 428 phy_reg_write(BASIC_MODE_CONTROL_REG, data);
mbed_official 119:3921aeca8633 429 for (i = 0; i < 1000; i++) {
mbed_official 119:3921aeca8633 430 data = phy_reg_read(BASIC_MODE_STATUS_REG);
mbed_official 119:3921aeca8633 431 if (((uint32_t)data & BASIC_STS_MSK_AUTO_CMP) != 0) {
mbed_official 119:3921aeca8633 432 break;
mbed_official 119:3921aeca8633 433 }
mbed_official 119:3921aeca8633 434 wait_100us(10);
mbed_official 119:3921aeca8633 435 }
mbed_official 119:3921aeca8633 436 } else {
mbed_official 119:3921aeca8633 437 data = (uint16_t)(((uint32_t)speed << 13) | ((uint32_t)duplex << 8));
mbed_official 119:3921aeca8633 438 phy_reg_write(BASIC_MODE_CONTROL_REG, data);
mbed_official 119:3921aeca8633 439 wait_100us(1);
mbed_official 119:3921aeca8633 440 }
mbed_official 119:3921aeca8633 441
mbed_official 119:3921aeca8633 442 link = ethernetext_chk_link_mode();
mbed_official 119:3921aeca8633 443 ethernetext_set_link_mode(link);
mbed_official 119:3921aeca8633 444 }
mbed_official 119:3921aeca8633 445
mbed_official 119:3921aeca8633 446 void INT_Ether(void) {
mbed_official 119:3921aeca8633 447 uint32_t stat_edmac;
mbed_official 119:3921aeca8633 448 uint32_t stat_etherc;
mbed_official 119:3921aeca8633 449
mbed_official 119:3921aeca8633 450 /* Clear the interrupt request flag */
mbed_official 119:3921aeca8633 451 stat_edmac = (ETHEREESR0 & ETHEREESIPR0); /* Targets are restricted to allowed interrupts */
mbed_official 119:3921aeca8633 452 ETHEREESR0 = stat_edmac;
mbed_official 119:3921aeca8633 453 /* Reception-related */
mbed_official 119:3921aeca8633 454 if (stat_edmac & EDMAC_EESIPR_INI_RECV) {
mbed_official 119:3921aeca8633 455 if (p_recv_cb_fnc != NULL) {
mbed_official 119:3921aeca8633 456 p_recv_cb_fnc();
mbed_official 119:3921aeca8633 457 }
mbed_official 119:3921aeca8633 458 }
mbed_official 119:3921aeca8633 459 /* E-MAC-related */
mbed_official 119:3921aeca8633 460 if (stat_edmac & EDMAC_EESIPR_INI_EtherC) {
mbed_official 119:3921aeca8633 461 /* Clear the interrupt request flag */
mbed_official 119:3921aeca8633 462 stat_etherc = (ETHERECSR0 & ETHERECSIPR0); /* Targets are restricted to allowed interrupts */
mbed_official 119:3921aeca8633 463 ETHERECSR0 = stat_etherc;
mbed_official 119:3921aeca8633 464 }
mbed_official 119:3921aeca8633 465 }
mbed_official 119:3921aeca8633 466
mbed_official 119:3921aeca8633 467 static void lan_reg_reset(void) {
mbed_official 119:3921aeca8633 468 volatile int32_t j = 400; /* Wait for B dia 256 cycles ((I dia/B dia)*256)/6cyc = 8*256/6 = 342 */
mbed_official 119:3921aeca8633 469
mbed_official 119:3921aeca8633 470 ETHERARSTR |= 0x00000001; /* ETHER software reset */
mbed_official 119:3921aeca8633 471 while (j--) {
mbed_official 119:3921aeca8633 472 /* Do Nothing */
mbed_official 119:3921aeca8633 473 }
mbed_official 119:3921aeca8633 474
mbed_official 119:3921aeca8633 475 ETHEREDSR0 |= 0x00000003; /* E-DMAC software reset */
mbed_official 119:3921aeca8633 476 ETHEREDMR0 |= 0x00000003; /* Set SWRR and SWRT simultaneously */
mbed_official 119:3921aeca8633 477
mbed_official 119:3921aeca8633 478 /* Check clear software reset */
mbed_official 119:3921aeca8633 479 while ((ETHEREDMR0 & 0x00000003) != 0) {
mbed_official 119:3921aeca8633 480 /* Do Nothing */
mbed_official 119:3921aeca8633 481 }
mbed_official 119:3921aeca8633 482 }
mbed_official 119:3921aeca8633 483
mbed_official 119:3921aeca8633 484 static void lan_desc_create(void) {
mbed_official 119:3921aeca8633 485 int32_t i;
mbed_official 119:3921aeca8633 486 uint8_t *p_memory_top;
mbed_official 119:3921aeca8633 487
mbed_official 119:3921aeca8633 488 (void)memset((void *)ethernet_nc_memory, 0, sizeof(ethernet_nc_memory));
mbed_official 119:3921aeca8633 489 p_memory_top = ethernet_nc_memory;
mbed_official 119:3921aeca8633 490
mbed_official 119:3921aeca8633 491 /* Descriptor area configuration */
mbed_official 119:3921aeca8633 492 p_eth_desc_dsend = (edmac_send_desc_t *)p_memory_top;
mbed_official 119:3921aeca8633 493 p_memory_top += (sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR);
mbed_official 119:3921aeca8633 494 p_eth_desc_drecv = (edmac_recv_desc_t *)p_memory_top;
mbed_official 119:3921aeca8633 495 p_memory_top += (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR);
mbed_official 119:3921aeca8633 496
mbed_official 119:3921aeca8633 497 /* Transmit descriptor */
mbed_official 119:3921aeca8633 498 for (i = 0; i < NUM_OF_TX_DESCRIPTOR; i++) {
mbed_official 119:3921aeca8633 499 p_eth_desc_dsend[i].td2 = p_memory_top; /* TD2 TBA */
mbed_official 119:3921aeca8633 500 p_memory_top += SIZE_OF_BUFFER;
mbed_official 119:3921aeca8633 501 p_eth_desc_dsend[i].td1 = 0; /* TD1 TDL */
mbed_official 119:3921aeca8633 502 p_eth_desc_dsend[i].td0 = TD0_TFP_TOP_BOTTOM; /* TD0:1frame/1buf1buf, transmission disabled */
mbed_official 119:3921aeca8633 503 }
mbed_official 119:3921aeca8633 504 p_eth_desc_dsend[i - 1].td0 |= TD0_TDLE; /* Set the last descriptor */
mbed_official 119:3921aeca8633 505
mbed_official 119:3921aeca8633 506 /* Receive descriptor */
mbed_official 119:3921aeca8633 507 for (i = 0; i < NUM_OF_RX_DESCRIPTOR; i++) {
mbed_official 119:3921aeca8633 508 p_eth_desc_drecv[i].rd2 = p_memory_top; /* RD2 RBA */
mbed_official 119:3921aeca8633 509 p_memory_top += SIZE_OF_BUFFER;
mbed_official 119:3921aeca8633 510 p_eth_desc_drecv[i].rd1 = ((uint32_t)SIZE_OF_BUFFER << 16); /* RD1 RBL */
mbed_official 119:3921aeca8633 511 p_eth_desc_drecv[i].rd0 = RD0_RACT; /* RD0:reception enabled */
mbed_official 119:3921aeca8633 512 }
mbed_official 119:3921aeca8633 513 p_eth_desc_drecv[i - 1].rd0 |= RD0_RDLE; /* Set the last descriptor */
mbed_official 119:3921aeca8633 514
mbed_official 119:3921aeca8633 515 /* Initialize descriptor management information */
mbed_official 119:3921aeca8633 516 send_top_index = 0;
mbed_official 119:3921aeca8633 517 recv_top_index = 0;
mbed_official 119:3921aeca8633 518 rx_read_offset = 0;
mbed_official 119:3921aeca8633 519 tx_wite_offset = 0;
mbed_official 119:3921aeca8633 520 p_recv_end_desc = NULL;
mbed_official 119:3921aeca8633 521 }
mbed_official 119:3921aeca8633 522
mbed_official 119:3921aeca8633 523 static void lan_reg_set(int32_t link) {
mbed_official 119:3921aeca8633 524 /* MAC address setting */
mbed_official 119:3921aeca8633 525 ETHERMAHR0 = ((uint32_t)mac_addr[0] << 24)
mbed_official 119:3921aeca8633 526 | ((uint32_t)mac_addr[1] << 16)
mbed_official 119:3921aeca8633 527 | ((uint32_t)mac_addr[2] << 8)
mbed_official 119:3921aeca8633 528 | (uint32_t)mac_addr[3];
mbed_official 119:3921aeca8633 529 ETHERMALR0 = ((uint32_t)mac_addr[4] << 8)
mbed_official 119:3921aeca8633 530 | (uint32_t)mac_addr[5];
mbed_official 119:3921aeca8633 531
mbed_official 119:3921aeca8633 532 /* E-DMAC */
mbed_official 119:3921aeca8633 533 ETHERTDLAR0 = (uint32_t)&p_eth_desc_dsend[0];
mbed_official 119:3921aeca8633 534 ETHERRDLAR0 = (uint32_t)&p_eth_desc_drecv[0];
mbed_official 119:3921aeca8633 535 ETHERTDFAR0 = (uint32_t)&p_eth_desc_dsend[0];
mbed_official 119:3921aeca8633 536 ETHERRDFAR0 = (uint32_t)&p_eth_desc_drecv[0];
mbed_official 119:3921aeca8633 537 ETHERTDFXR0 = (uint32_t)&p_eth_desc_dsend[NUM_OF_TX_DESCRIPTOR - 1];
mbed_official 119:3921aeca8633 538 ETHERRDFXR0 = (uint32_t)&p_eth_desc_drecv[NUM_OF_RX_DESCRIPTOR - 1];
mbed_official 119:3921aeca8633 539 ETHERTDFFR0 |= 0x00000001; /* TDLF Transmit Descriptor Queue Last Flag : Last descriptor (1) */
mbed_official 119:3921aeca8633 540 ETHERRDFFR0 |= 0x00000001; /* RDLF Receive Descriptor Queue Last Flag : Last descriptor (1) */
mbed_official 119:3921aeca8633 541 ETHEREDMR0 |= 0x00000040; /* Little endian */
mbed_official 119:3921aeca8633 542 ETHERTRSCER0 &= ~0x0003009F; /* All clear */
mbed_official 119:3921aeca8633 543 ETHERTFTR0 &= ~0x000007FF; /* TFT[10:0] Transmit FIFO Threshold : Store and forward modes (H'000) */
mbed_official 119:3921aeca8633 544 ETHERFDR0 |= 0x00000707; /* Transmit FIFO Size:2048 bytes, Receive FIFO Size:2048 bytes */
mbed_official 119:3921aeca8633 545 ETHERRMCR0 |= 0x00000001; /* RNC Receive Enable Control : Continuous reception enabled (1) */
mbed_official 119:3921aeca8633 546 ETHERFCFTR0 &= ~0x001F00FF;
mbed_official 119:3921aeca8633 547 ETHERFCFTR0 |= 0x00070007;
mbed_official 119:3921aeca8633 548 ETHERRPADIR0 &= ~0x001FFFFF; /* Padding Size:No padding insertion, Padding Slot:Inserts at first byte */
mbed_official 119:3921aeca8633 549
mbed_official 119:3921aeca8633 550 /* E-MAC */
mbed_official 119:3921aeca8633 551 ETHERECMR0 &= ~0x04BF2063; /* All clear */
mbed_official 119:3921aeca8633 552 ETHERRFLR0 &= ~0x0003FFFF; /* RFL[17:0] Receive Frame Length : 1518 bytes (H'00000) */
mbed_official 119:3921aeca8633 553 ETHERAPR0 &= ~0x0000FFFF; /* AP[15:0] Automatic PAUSE : Flow control is disabled (H'0000) */
mbed_official 119:3921aeca8633 554 ETHERMPR0 &= ~0x0000FFFF; /* MP[15:0] Manual PAUSE : Flow control is disabled (H'0000) */
mbed_official 119:3921aeca8633 555 ETHERTPAUSER0 &= ~0x0000FFFF; /* Upper Limit for Automatic PAUSE Frame : Retransmit count is unlimited */
mbed_official 119:3921aeca8633 556 ETHERCSMR &= ~0xC000003F; /* The result of checksum is not written back to the receive descriptor */
mbed_official 119:3921aeca8633 557 if ((link == FULL_TX) || (link == FULL_10M) || (link == NEGO_FAIL)) {
mbed_official 119:3921aeca8633 558 ETHERECMR0 |= 0x00000002; /* Set to full-duplex mode */
mbed_official 119:3921aeca8633 559 } else {
mbed_official 119:3921aeca8633 560 ETHERECMR0 &= ~0x00000002; /* Set to half-duplex mode */
mbed_official 119:3921aeca8633 561 }
mbed_official 119:3921aeca8633 562
mbed_official 119:3921aeca8633 563 /* Interrupt-related */
mbed_official 119:3921aeca8633 564 if (p_recv_cb_fnc != NULL) {
mbed_official 119:3921aeca8633 565 ETHEREESR0 |= 0xFF7F009F; /* Clear all status (by writing 1) */
mbed_official 119:3921aeca8633 566 ETHEREESIPR0 |= 0x00040000; /* FR Frame Reception (1) */
mbed_official 119:3921aeca8633 567 ETHERECSR0 |= 0x00000011; /* Clear all status (clear by writing 1) */
mbed_official 119:3921aeca8633 568 ETHERECSIPR0 &= ~0x00000011; /* PFROIP Disable, ICDIP Disable */
mbed_official 119:3921aeca8633 569 InterruptHandlerRegister(ETHERI_IRQn, INT_Ether); /* Ethernet interrupt handler registration */
mbed_official 119:3921aeca8633 570 GIC_SetPriority(ETHERI_IRQn, Interrupt_priority); /* Ethernet interrupt priority */
mbed_official 119:3921aeca8633 571 GIC_EnableIRQ(ETHERI_IRQn); /* Enables the E-DMAC interrupt */
mbed_official 119:3921aeca8633 572 }
mbed_official 119:3921aeca8633 573
mbed_official 119:3921aeca8633 574 ETHERECMR0 |= 0x00000060; /* RE Enable, TE Enable */
mbed_official 119:3921aeca8633 575
mbed_official 119:3921aeca8633 576 /* Enable transmission/reception */
mbed_official 119:3921aeca8633 577 if ((start_stop == 1) && ((ETHEREDRRR0 & 0x00000001) == 0)) {
mbed_official 119:3921aeca8633 578 ETHEREDRRR0 |= 0x00000001; /* RR */
mbed_official 119:3921aeca8633 579 }
mbed_official 119:3921aeca8633 580 }
mbed_official 119:3921aeca8633 581
mbed_official 119:3921aeca8633 582 static uint16_t phy_reg_read(uint16_t reg_addr) {
mbed_official 119:3921aeca8633 583 uint16_t data;
mbed_official 119:3921aeca8633 584
mbed_official 119:3921aeca8633 585 mii_preamble();
mbed_official 119:3921aeca8633 586 mii_cmd(reg_addr, PHY_READ);
mbed_official 119:3921aeca8633 587 mii_z();
mbed_official 119:3921aeca8633 588 mii_reg_read(&data);
mbed_official 119:3921aeca8633 589 mii_z();
mbed_official 119:3921aeca8633 590
mbed_official 119:3921aeca8633 591 return data;
mbed_official 119:3921aeca8633 592 }
mbed_official 119:3921aeca8633 593
mbed_official 119:3921aeca8633 594 static void phy_reg_write(uint16_t reg_addr, uint16_t data) {
mbed_official 119:3921aeca8633 595 mii_preamble();
mbed_official 119:3921aeca8633 596 mii_cmd(reg_addr, PHY_WRITE);
mbed_official 119:3921aeca8633 597 mii_write_1();
mbed_official 119:3921aeca8633 598 mii_write_0();
mbed_official 119:3921aeca8633 599 mii_reg_write(data);
mbed_official 119:3921aeca8633 600 mii_z();
mbed_official 119:3921aeca8633 601 }
mbed_official 119:3921aeca8633 602
mbed_official 119:3921aeca8633 603 static void mii_preamble(void) {
mbed_official 119:3921aeca8633 604 int32_t i = 32;
mbed_official 119:3921aeca8633 605
mbed_official 119:3921aeca8633 606 for (i = 32; i > 0; i--) {
mbed_official 119:3921aeca8633 607 /* 1 is output via the MII (Media Independent Interface) block. */
mbed_official 119:3921aeca8633 608 mii_write_1();
mbed_official 119:3921aeca8633 609 }
mbed_official 119:3921aeca8633 610 }
mbed_official 119:3921aeca8633 611
mbed_official 119:3921aeca8633 612 static void mii_cmd(uint16_t reg_addr, uint32_t option) {
mbed_official 119:3921aeca8633 613 int32_t i;
mbed_official 119:3921aeca8633 614 uint16_t data = 0;
mbed_official 119:3921aeca8633 615
mbed_official 119:3921aeca8633 616 data |= (PHY_ST << 14); /* ST code */
mbed_official 119:3921aeca8633 617 data |= (option << 12); /* OP code */
mbed_official 119:3921aeca8633 618 data |= (PHY_ADDR << 7); /* PHY Address */
mbed_official 119:3921aeca8633 619 data |= (uint16_t)(reg_addr << 2); /* Reg Address */
mbed_official 119:3921aeca8633 620 for (i = 14; i > 0; i--) {
mbed_official 119:3921aeca8633 621 if ((data & 0x8000) == 0) {
mbed_official 119:3921aeca8633 622 mii_write_0();
mbed_official 119:3921aeca8633 623 } else {
mbed_official 119:3921aeca8633 624 mii_write_1();
mbed_official 119:3921aeca8633 625 }
mbed_official 119:3921aeca8633 626 data <<= 1;
mbed_official 119:3921aeca8633 627 }
mbed_official 119:3921aeca8633 628 }
mbed_official 119:3921aeca8633 629
mbed_official 119:3921aeca8633 630 static void mii_reg_read(uint16_t *data) {
mbed_official 119:3921aeca8633 631 int32_t i;
mbed_official 119:3921aeca8633 632 uint16_t reg_data = 0;
mbed_official 119:3921aeca8633 633
mbed_official 119:3921aeca8633 634 /* Data are read in one bit at a time */
mbed_official 119:3921aeca8633 635 for (i = 16; i > 0; i--) {
mbed_official 119:3921aeca8633 636 set_ether_pir(PIR0_MDC_LOW);
mbed_official 119:3921aeca8633 637 set_ether_pir(PIR0_MDC_HIGH);
mbed_official 119:3921aeca8633 638 reg_data <<= 1;
mbed_official 119:3921aeca8633 639 reg_data |= (uint16_t)((ETHERPIR0 & PIR0_MDI) >> 3); /* MDI read */
mbed_official 119:3921aeca8633 640 set_ether_pir(PIR0_MDC_HIGH);
mbed_official 119:3921aeca8633 641 set_ether_pir(PIR0_MDC_LOW);
mbed_official 119:3921aeca8633 642 }
mbed_official 119:3921aeca8633 643 *data = reg_data;
mbed_official 119:3921aeca8633 644 }
mbed_official 119:3921aeca8633 645
mbed_official 119:3921aeca8633 646 static void mii_reg_write(uint16_t data) {
mbed_official 119:3921aeca8633 647 int32_t i;
mbed_official 119:3921aeca8633 648
mbed_official 119:3921aeca8633 649 /* Data are written one bit at a time */
mbed_official 119:3921aeca8633 650 for (i = 16; i > 0; i--) {
mbed_official 119:3921aeca8633 651 if ((data & 0x8000) == 0) {
mbed_official 119:3921aeca8633 652 mii_write_0();
mbed_official 119:3921aeca8633 653 } else {
mbed_official 119:3921aeca8633 654 mii_write_1();
mbed_official 119:3921aeca8633 655 }
mbed_official 119:3921aeca8633 656 data <<= 1;
mbed_official 119:3921aeca8633 657 }
mbed_official 119:3921aeca8633 658 }
mbed_official 119:3921aeca8633 659
mbed_official 119:3921aeca8633 660 static void mii_z(void) {
mbed_official 119:3921aeca8633 661 set_ether_pir(PIR0_MDC_LOW);
mbed_official 119:3921aeca8633 662 set_ether_pir(PIR0_MDC_HIGH);
mbed_official 119:3921aeca8633 663 set_ether_pir(PIR0_MDC_HIGH);
mbed_official 119:3921aeca8633 664 set_ether_pir(PIR0_MDC_LOW);
mbed_official 119:3921aeca8633 665 }
mbed_official 119:3921aeca8633 666
mbed_official 119:3921aeca8633 667 static void mii_write_1(void) {
mbed_official 119:3921aeca8633 668 set_ether_pir(PIR0_MDO | PIR0_MMD);
mbed_official 119:3921aeca8633 669 set_ether_pir(PIR0_MDO | PIR0_MMD | PIR0_MDC);
mbed_official 119:3921aeca8633 670 set_ether_pir(PIR0_MDO | PIR0_MMD | PIR0_MDC);
mbed_official 119:3921aeca8633 671 set_ether_pir(PIR0_MDO | PIR0_MMD);
mbed_official 119:3921aeca8633 672 }
mbed_official 119:3921aeca8633 673
mbed_official 119:3921aeca8633 674 static void mii_write_0(void) {
mbed_official 119:3921aeca8633 675 set_ether_pir(PIR0_MMD);
mbed_official 119:3921aeca8633 676 set_ether_pir(PIR0_MMD | PIR0_MDC);
mbed_official 119:3921aeca8633 677 set_ether_pir(PIR0_MMD | PIR0_MDC);
mbed_official 119:3921aeca8633 678 set_ether_pir(PIR0_MMD);
mbed_official 119:3921aeca8633 679 }
mbed_official 119:3921aeca8633 680
mbed_official 119:3921aeca8633 681 static void set_ether_pir(uint32_t set_data) {
mbed_official 119:3921aeca8633 682 int32_t i;
mbed_official 119:3921aeca8633 683
mbed_official 119:3921aeca8633 684 for (i = MDC_WAIT; i > 0; i--) {
mbed_official 119:3921aeca8633 685 ETHERPIR0 = set_data;
mbed_official 119:3921aeca8633 686 }
mbed_official 119:3921aeca8633 687 }
mbed_official 119:3921aeca8633 688
mbed_official 119:3921aeca8633 689 static void wait_100us(int32_t wait_cnt) {
mbed_official 119:3921aeca8633 690 volatile int32_t j = LOOP_100us * wait_cnt;
mbed_official 119:3921aeca8633 691
mbed_official 119:3921aeca8633 692 while (--j) {
mbed_official 119:3921aeca8633 693 /* Do Nothing */
mbed_official 119:3921aeca8633 694 }
mbed_official 119:3921aeca8633 695 }