Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/us_ticker.c@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2013 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16 #include <stddef.h>
<> 144:ef7eb2e8f9f7 17 #include "us_ticker_api.h"
<> 144:ef7eb2e8f9f7 18 #include "PeripheralNames.h"
<> 144:ef7eb2e8f9f7 19 #include "ostm_iodefine.h"
<> 144:ef7eb2e8f9f7 20
<> 144:ef7eb2e8f9f7 21 #include "RZ_A1_Init.h"
<> 144:ef7eb2e8f9f7 22 #include "MBRZA1H.h"
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 #define US_TICKER_TIMER_IRQn (OSTMI1TINT_IRQn)
<> 144:ef7eb2e8f9f7 25 #define CPG_STBCR5_BIT_MSTP50 (0x01u) /* OSTM1 */
<> 144:ef7eb2e8f9f7 26
<> 144:ef7eb2e8f9f7 27 #define US_TICKER_CLOCK_US_DEV (1000000)
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 int us_ticker_inited = 0;
<> 144:ef7eb2e8f9f7 30 static double count_clock = 0;
<> 144:ef7eb2e8f9f7 31 static uint32_t last_read = 0;
<> 144:ef7eb2e8f9f7 32 static uint32_t wrap_arround = 0;
<> 144:ef7eb2e8f9f7 33 static uint64_t ticker_us_last64 = 0;
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 void us_ticker_interrupt(void) {
<> 144:ef7eb2e8f9f7 36 us_ticker_irq_handler();
<> 144:ef7eb2e8f9f7 37 }
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 void us_ticker_init(void) {
<> 144:ef7eb2e8f9f7 40 if (us_ticker_inited) return;
<> 144:ef7eb2e8f9f7 41 us_ticker_inited = 1;
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /* set Counter Clock(us) */
<> 144:ef7eb2e8f9f7 44 if (false == RZ_A1_IsClockMode0()) {
<> 144:ef7eb2e8f9f7 45 count_clock = ((double)CM1_RENESAS_RZ_A1_P0_CLK / (double)US_TICKER_CLOCK_US_DEV);
<> 144:ef7eb2e8f9f7 46 } else {
<> 144:ef7eb2e8f9f7 47 count_clock = ((double)CM0_RENESAS_RZ_A1_P0_CLK / (double)US_TICKER_CLOCK_US_DEV);
<> 144:ef7eb2e8f9f7 48 }
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 /* Power Control for Peripherals */
<> 144:ef7eb2e8f9f7 51 CPGSTBCR5 &= ~(CPG_STBCR5_BIT_MSTP50); /* enable OSTM1 clock */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 // timer settings
<> 144:ef7eb2e8f9f7 54 OSTM1TT = 0x01; /* Stop the counter and clears the OSTM1TE bit. */
<> 144:ef7eb2e8f9f7 55 OSTM1CTL = 0x02; /* Free running timer mode. Interrupt disabled when star counter */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 OSTM1TS = 0x1; /* Start the counter and sets the OSTM0TE bit. */
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 // INTC settings
<> 144:ef7eb2e8f9f7 60 InterruptHandlerRegister(US_TICKER_TIMER_IRQn, (void (*)(uint32_t))us_ticker_interrupt);
<> 144:ef7eb2e8f9f7 61 GIC_SetPriority(US_TICKER_TIMER_IRQn, 5);
<> 144:ef7eb2e8f9f7 62 GIC_EnableIRQ(US_TICKER_TIMER_IRQn);
<> 144:ef7eb2e8f9f7 63 }
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 static uint64_t ticker_read_counter64(void) {
<> 144:ef7eb2e8f9f7 66 uint32_t cnt_val;
<> 144:ef7eb2e8f9f7 67 uint64_t cnt_val64;
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 if (!us_ticker_inited)
<> 144:ef7eb2e8f9f7 70 us_ticker_init();
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 /* read counter */
<> 144:ef7eb2e8f9f7 73 cnt_val = OSTM1CNT;
<> 144:ef7eb2e8f9f7 74 if (last_read > cnt_val) {
<> 144:ef7eb2e8f9f7 75 wrap_arround++;
<> 144:ef7eb2e8f9f7 76 }
<> 144:ef7eb2e8f9f7 77 last_read = cnt_val;
<> 144:ef7eb2e8f9f7 78 cnt_val64 = ((uint64_t)wrap_arround << 32) + cnt_val;
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 return cnt_val64;
<> 144:ef7eb2e8f9f7 81 }
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 uint32_t us_ticker_read() {
<> 144:ef7eb2e8f9f7 84 uint64_t cnt_val64;
<> 144:ef7eb2e8f9f7 85 uint64_t us_val64;
<> 144:ef7eb2e8f9f7 86 int check_irq_masked;
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 #if defined ( __ICCARM__)
<> 144:ef7eb2e8f9f7 89 check_irq_masked = __disable_irq_iar();
<> 144:ef7eb2e8f9f7 90 #else
<> 144:ef7eb2e8f9f7 91 check_irq_masked = __disable_irq();
<> 144:ef7eb2e8f9f7 92 #endif /* __ICCARM__ */
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 cnt_val64 = ticker_read_counter64();
<> 144:ef7eb2e8f9f7 95 us_val64 = (cnt_val64 / count_clock);
<> 144:ef7eb2e8f9f7 96 ticker_us_last64 = us_val64;
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 if (!check_irq_masked) {
<> 144:ef7eb2e8f9f7 99 __enable_irq();
<> 144:ef7eb2e8f9f7 100 }
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 /* clock to us */
<> 144:ef7eb2e8f9f7 103 return (uint32_t)us_val64;
<> 144:ef7eb2e8f9f7 104 }
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 void us_ticker_set_interrupt(timestamp_t timestamp) {
<> 144:ef7eb2e8f9f7 107 // set match value
<> 144:ef7eb2e8f9f7 108 uint64_t timestamp64;
<> 144:ef7eb2e8f9f7 109 uint64_t set_cmp_val64;
<> 144:ef7eb2e8f9f7 110 volatile uint32_t set_cmp_val;
<> 144:ef7eb2e8f9f7 111 uint64_t count_val_64;
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 /* calc compare mach timestamp */
<> 144:ef7eb2e8f9f7 114 timestamp64 = (ticker_us_last64 & 0xFFFFFFFF00000000) + timestamp;
<> 144:ef7eb2e8f9f7 115 if (timestamp < (ticker_us_last64 & 0x00000000FFFFFFFF)) {
<> 144:ef7eb2e8f9f7 116 /* This event is wrap arround */
<> 144:ef7eb2e8f9f7 117 timestamp64 += 0x100000000;
<> 144:ef7eb2e8f9f7 118 }
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 /* calc compare mach timestamp */
<> 144:ef7eb2e8f9f7 121 set_cmp_val64 = timestamp64 * count_clock;
<> 144:ef7eb2e8f9f7 122 set_cmp_val = (uint32_t)(set_cmp_val64 & 0x00000000FFFFFFFF);
<> 144:ef7eb2e8f9f7 123 count_val_64 = ticker_read_counter64();
<> 144:ef7eb2e8f9f7 124 if (set_cmp_val64 <= (count_val_64 + 500)) {
<> 144:ef7eb2e8f9f7 125 GIC_SetPendingIRQ(US_TICKER_TIMER_IRQn);
<> 144:ef7eb2e8f9f7 126 GIC_EnableIRQ(US_TICKER_TIMER_IRQn);
<> 144:ef7eb2e8f9f7 127 return;
<> 144:ef7eb2e8f9f7 128 }
<> 144:ef7eb2e8f9f7 129 OSTM1CMP = set_cmp_val;
<> 144:ef7eb2e8f9f7 130 GIC_EnableIRQ(US_TICKER_TIMER_IRQn);
<> 144:ef7eb2e8f9f7 131 }
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 void us_ticker_disable_interrupt(void) {
<> 144:ef7eb2e8f9f7 134 GIC_DisableIRQ(US_TICKER_TIMER_IRQn);
<> 144:ef7eb2e8f9f7 135 }
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 void us_ticker_clear_interrupt(void) {
<> 144:ef7eb2e8f9f7 138 GIC_ClearPendingIRQ(US_TICKER_TIMER_IRQn);
<> 144:ef7eb2e8f9f7 139 }