Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_NXP/TARGET_LPC43XX/spi_api.c@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2013 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 *
<> 144:ef7eb2e8f9f7 16 * Ported to NXP LPC43XX by Micromint USA <support@micromint.com>
<> 144:ef7eb2e8f9f7 17 */
<> 144:ef7eb2e8f9f7 18 #include "mbed_assert.h"
<> 144:ef7eb2e8f9f7 19 #include <math.h>
<> 144:ef7eb2e8f9f7 20
<> 144:ef7eb2e8f9f7 21 #include "spi_api.h"
<> 144:ef7eb2e8f9f7 22 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 23 #include "pinmap.h"
<> 144:ef7eb2e8f9f7 24 #include "mbed_error.h"
<> 144:ef7eb2e8f9f7 25
<> 144:ef7eb2e8f9f7 26 // SCU mode for SPI pins
<> 144:ef7eb2e8f9f7 27 #define SCU_PINIO_SPI SCU_PINIO_FAST
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 static const PinMap PinMap_SPI_SCLK[] = {
<> 144:ef7eb2e8f9f7 30 {P1_19, SPI_1, (SCU_PINIO_SPI | 1)},
<> 144:ef7eb2e8f9f7 31 {P3_0, SPI_0, (SCU_PINIO_SPI | 4)},
<> 144:ef7eb2e8f9f7 32 {P3_3, SPI_0, (SCU_PINIO_SPI | 2)},
<> 144:ef7eb2e8f9f7 33 {PF_0, SPI_0, (SCU_PINIO_SPI | 0)},
<> 144:ef7eb2e8f9f7 34 {PF_4, SPI_1, (SCU_PINIO_SPI | 0)},
<> 144:ef7eb2e8f9f7 35 {NC, NC, 0}
<> 144:ef7eb2e8f9f7 36 };
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 static const PinMap PinMap_SPI_MOSI[] = {
<> 144:ef7eb2e8f9f7 39 {P0_1, SPI_1, (SCU_PINIO_SPI | 1)},
<> 144:ef7eb2e8f9f7 40 {P1_2, SPI_0, (SCU_PINIO_SPI | 5)},
<> 144:ef7eb2e8f9f7 41 {P1_4, SPI_1, (SCU_PINIO_SPI | 5)},
<> 144:ef7eb2e8f9f7 42 {P3_7, SPI_0, (SCU_PINIO_SPI | 5)},
<> 144:ef7eb2e8f9f7 43 {P3_8, SPI_0, (SCU_PINIO_SPI | 2)},
<> 144:ef7eb2e8f9f7 44 {P9_2, SPI_0, (SCU_PINIO_SPI | 7)},
<> 144:ef7eb2e8f9f7 45 {PF_3, SPI_0, (SCU_PINIO_SPI | 2)},
<> 144:ef7eb2e8f9f7 46 {PF_7, SPI_1, (SCU_PINIO_SPI | 2)},
<> 144:ef7eb2e8f9f7 47 {NC, NC, 0}
<> 144:ef7eb2e8f9f7 48 };
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 static const PinMap PinMap_SPI_MISO[] = {
<> 144:ef7eb2e8f9f7 51 {P0_0, SPI_1, (SCU_PINIO_SPI | 1)},
<> 144:ef7eb2e8f9f7 52 {P1_1, SPI_0, (SCU_PINIO_SPI | 5)},
<> 144:ef7eb2e8f9f7 53 {P1_3, SPI_1, (SCU_PINIO_SPI | 5)},
<> 144:ef7eb2e8f9f7 54 {P3_6, SPI_0, (SCU_PINIO_SPI | 5)},
<> 144:ef7eb2e8f9f7 55 {P3_7, SPI_0, (SCU_PINIO_SPI | 2)},
<> 144:ef7eb2e8f9f7 56 {P9_1, SPI_0, (SCU_PINIO_SPI | 7)},
<> 144:ef7eb2e8f9f7 57 {PF_2, SPI_0, (SCU_PINIO_SPI | 2)},
<> 144:ef7eb2e8f9f7 58 {PF_6, SPI_1, (SCU_PINIO_SPI | 2)},
<> 144:ef7eb2e8f9f7 59 {NC, NC, 0}
<> 144:ef7eb2e8f9f7 60 };
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 static const PinMap PinMap_SPI_SSEL[] = {
<> 144:ef7eb2e8f9f7 63 {P1_0, SPI_0, (SCU_PINIO_SPI | 5)},
<> 144:ef7eb2e8f9f7 64 {P1_5, SPI_1, (SCU_PINIO_SPI | 5)},
<> 144:ef7eb2e8f9f7 65 {P1_20, SPI_1, (SCU_PINIO_SPI | 2)},
<> 144:ef7eb2e8f9f7 66 {P3_6, SPI_0, (SCU_PINIO_SPI | 2)},
<> 144:ef7eb2e8f9f7 67 {P3_8, SPI_0, (SCU_PINIO_SPI | 5)},
<> 144:ef7eb2e8f9f7 68 {P9_0, SPI_0, (SCU_PINIO_SPI | 7)},
<> 144:ef7eb2e8f9f7 69 {PF_1, SPI_0, (SCU_PINIO_SPI | 2)},
<> 144:ef7eb2e8f9f7 70 {PF_5, SPI_1, (SCU_PINIO_SPI | 2)},
<> 144:ef7eb2e8f9f7 71 {NC, NC, 0}
<> 144:ef7eb2e8f9f7 72 };
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 static inline int ssp_disable(spi_t *obj);
<> 144:ef7eb2e8f9f7 75 static inline int ssp_enable(spi_t *obj);
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
<> 144:ef7eb2e8f9f7 78 // determine the SPI to use
<> 144:ef7eb2e8f9f7 79 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
<> 144:ef7eb2e8f9f7 80 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
<> 144:ef7eb2e8f9f7 81 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
<> 144:ef7eb2e8f9f7 82 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
<> 144:ef7eb2e8f9f7 83 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
<> 144:ef7eb2e8f9f7 84 SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 obj->spi = (LPC_SSP_T*)pinmap_merge(spi_data, spi_cntl);
<> 144:ef7eb2e8f9f7 87 MBED_ASSERT((int)obj->spi != NC);
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 // enable clocking
<> 144:ef7eb2e8f9f7 90 switch ((int)obj->spi) {
<> 144:ef7eb2e8f9f7 91 case SPI_0: LPC_CGU->BASE_CLK[CLK_BASE_SSP0] = (1 << 11) | (CLKIN_MAINPLL << 24); break;
<> 144:ef7eb2e8f9f7 92 case SPI_1: LPC_CGU->BASE_CLK[CLK_BASE_SSP1] = (1 << 11) | (CLKIN_MAINPLL << 24); break;
<> 144:ef7eb2e8f9f7 93 }
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 // pin out the spi pins
<> 144:ef7eb2e8f9f7 96 pinmap_pinout(mosi, PinMap_SPI_MOSI);
<> 144:ef7eb2e8f9f7 97 pinmap_pinout(miso, PinMap_SPI_MISO);
<> 144:ef7eb2e8f9f7 98 pinmap_pinout(sclk, PinMap_SPI_SCLK);
<> 144:ef7eb2e8f9f7 99 if (ssel != NC) {
<> 144:ef7eb2e8f9f7 100 pinmap_pinout(ssel, PinMap_SPI_SSEL);
<> 144:ef7eb2e8f9f7 101 }
<> 144:ef7eb2e8f9f7 102 }
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 void spi_free(spi_t *obj) {}
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 void spi_format(spi_t *obj, int bits, int mode, int slave) {
<> 144:ef7eb2e8f9f7 107 MBED_ASSERT(((bits >= 4) && (bits <= 16)) || ((mode >= 0) && (mode <= 3)));
<> 144:ef7eb2e8f9f7 108 ssp_disable(obj);
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 int polarity = (mode & 0x2) ? 1 : 0;
<> 144:ef7eb2e8f9f7 111 int phase = (mode & 0x1) ? 1 : 0;
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 // set it up
<> 144:ef7eb2e8f9f7 114 int DSS = bits - 1; // DSS (data select size)
<> 144:ef7eb2e8f9f7 115 int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity
<> 144:ef7eb2e8f9f7 116 int SPH = (phase) ? 1 : 0; // SPH - clock out phase
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 int FRF = 0; // FRF (frame format) = SPI
<> 144:ef7eb2e8f9f7 119 uint32_t tmp = obj->spi->CR0;
<> 144:ef7eb2e8f9f7 120 tmp &= ~(0xFFFF);
<> 144:ef7eb2e8f9f7 121 tmp |= DSS << 0
<> 144:ef7eb2e8f9f7 122 | FRF << 4
<> 144:ef7eb2e8f9f7 123 | SPO << 6
<> 144:ef7eb2e8f9f7 124 | SPH << 7;
<> 144:ef7eb2e8f9f7 125 obj->spi->CR0 = tmp;
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 tmp = obj->spi->CR1;
<> 144:ef7eb2e8f9f7 128 tmp &= ~(0xD);
<> 144:ef7eb2e8f9f7 129 tmp |= 0 << 0 // LBM - loop back mode - off
<> 144:ef7eb2e8f9f7 130 | ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave
<> 144:ef7eb2e8f9f7 131 | 0 << 3; // SOD - slave output disable - na
<> 144:ef7eb2e8f9f7 132 obj->spi->CR1 = tmp;
<> 144:ef7eb2e8f9f7 133 ssp_enable(obj);
<> 144:ef7eb2e8f9f7 134 }
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 void spi_frequency(spi_t *obj, int hz) {
<> 144:ef7eb2e8f9f7 137 ssp_disable(obj);
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 uint32_t PCLK = SystemCoreClock;
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 int prescaler;
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 for (prescaler = 2; prescaler <= 254; prescaler += 2) {
<> 144:ef7eb2e8f9f7 144 int prescale_hz = PCLK / prescaler;
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 // calculate the divider
<> 144:ef7eb2e8f9f7 147 int divider = floor(((float)prescale_hz / (float)hz) + 0.5f);
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 // check we can support the divider
<> 144:ef7eb2e8f9f7 150 if (divider < 256) {
<> 144:ef7eb2e8f9f7 151 // prescaler
<> 144:ef7eb2e8f9f7 152 obj->spi->CPSR = prescaler;
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 // divider
<> 144:ef7eb2e8f9f7 155 obj->spi->CR0 &= ~(0xFFFF << 8);
<> 144:ef7eb2e8f9f7 156 obj->spi->CR0 |= (divider - 1) << 8;
<> 144:ef7eb2e8f9f7 157 ssp_enable(obj);
<> 144:ef7eb2e8f9f7 158 return;
<> 144:ef7eb2e8f9f7 159 }
<> 144:ef7eb2e8f9f7 160 }
<> 144:ef7eb2e8f9f7 161 error("Couldn't setup requested SPI frequency");
<> 144:ef7eb2e8f9f7 162 }
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 static inline int ssp_disable(spi_t *obj) {
<> 144:ef7eb2e8f9f7 165 return obj->spi->CR1 &= ~(1 << 1);
<> 144:ef7eb2e8f9f7 166 }
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 static inline int ssp_enable(spi_t *obj) {
<> 144:ef7eb2e8f9f7 169 return obj->spi->CR1 |= (1 << 1);
<> 144:ef7eb2e8f9f7 170 }
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 static inline int ssp_readable(spi_t *obj) {
<> 144:ef7eb2e8f9f7 173 return obj->spi->SR & (1 << 2);
<> 144:ef7eb2e8f9f7 174 }
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 static inline int ssp_writeable(spi_t *obj) {
<> 144:ef7eb2e8f9f7 177 return obj->spi->SR & (1 << 1);
<> 144:ef7eb2e8f9f7 178 }
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 static inline void ssp_write(spi_t *obj, int value) {
<> 144:ef7eb2e8f9f7 181 while (!ssp_writeable(obj));
<> 144:ef7eb2e8f9f7 182 obj->spi->DR = value;
<> 144:ef7eb2e8f9f7 183 }
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 static inline int ssp_read(spi_t *obj) {
<> 144:ef7eb2e8f9f7 186 while (!ssp_readable(obj));
<> 144:ef7eb2e8f9f7 187 return obj->spi->DR;
<> 144:ef7eb2e8f9f7 188 }
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 static inline int ssp_busy(spi_t *obj) {
<> 144:ef7eb2e8f9f7 191 return (obj->spi->SR & (1 << 4)) ? (1) : (0);
<> 144:ef7eb2e8f9f7 192 }
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 int spi_master_write(spi_t *obj, int value) {
<> 144:ef7eb2e8f9f7 195 ssp_write(obj, value);
<> 144:ef7eb2e8f9f7 196 return ssp_read(obj);
<> 144:ef7eb2e8f9f7 197 }
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 int spi_slave_receive(spi_t *obj) {
<> 144:ef7eb2e8f9f7 200 return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
<> 144:ef7eb2e8f9f7 201 }
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 int spi_slave_read(spi_t *obj) {
<> 144:ef7eb2e8f9f7 204 return obj->spi->DR;
<> 144:ef7eb2e8f9f7 205 }
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 void spi_slave_write(spi_t *obj, int value) {
<> 144:ef7eb2e8f9f7 208 while (ssp_writeable(obj) == 0) ;
<> 144:ef7eb2e8f9f7 209 obj->spi->DR = value;
<> 144:ef7eb2e8f9f7 210 }
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 int spi_busy(spi_t *obj) {
<> 144:ef7eb2e8f9f7 213 return ssp_busy(obj);
<> 144:ef7eb2e8f9f7 214 }