Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_NXP/TARGET_LPC2460/gpio_irq_api.c@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2015 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16 #include "gpio_irq_api.h"
<> 144:ef7eb2e8f9f7 17 #include "mbed_error.h"
<> 144:ef7eb2e8f9f7 18 #include <stddef.h>
<> 144:ef7eb2e8f9f7 19 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 20
<> 144:ef7eb2e8f9f7 21 #define CHANNEL_NUM 48
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 static uint32_t channel_ids[CHANNEL_NUM] = {0};
<> 144:ef7eb2e8f9f7 24 static gpio_irq_handler irq_handler;
<> 144:ef7eb2e8f9f7 25
<> 144:ef7eb2e8f9f7 26 static void handle_interrupt_in(void) {
<> 144:ef7eb2e8f9f7 27 // Read in all current interrupt registers. We do this once as the
<> 144:ef7eb2e8f9f7 28 // GPIO interrupt registers are on the APB bus, and this is slow.
<> 144:ef7eb2e8f9f7 29 uint32_t rise0 = LPC_GPIOINT->IO0IntStatR;
<> 144:ef7eb2e8f9f7 30 uint32_t fall0 = LPC_GPIOINT->IO0IntStatF;
<> 144:ef7eb2e8f9f7 31 uint32_t rise2 = LPC_GPIOINT->IO2IntStatR;
<> 144:ef7eb2e8f9f7 32 uint32_t fall2 = LPC_GPIOINT->IO2IntStatF;
<> 144:ef7eb2e8f9f7 33 uint32_t mask0 = 0;
<> 144:ef7eb2e8f9f7 34 uint32_t mask2 = 0;
<> 144:ef7eb2e8f9f7 35 int i;
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 // P0.0-0.31
<> 144:ef7eb2e8f9f7 38 for (i = 0; i < 32; i++) {
<> 144:ef7eb2e8f9f7 39 uint32_t pmask = (1 << i);
<> 144:ef7eb2e8f9f7 40 if (rise0 & pmask) {
<> 144:ef7eb2e8f9f7 41 mask0 |= pmask;
<> 144:ef7eb2e8f9f7 42 if (channel_ids[i] != 0)
<> 144:ef7eb2e8f9f7 43 irq_handler(channel_ids[i], IRQ_RISE);
<> 144:ef7eb2e8f9f7 44 }
<> 144:ef7eb2e8f9f7 45 if (fall0 & pmask) {
<> 144:ef7eb2e8f9f7 46 mask0 |= pmask;
<> 144:ef7eb2e8f9f7 47 if (channel_ids[i] != 0)
<> 144:ef7eb2e8f9f7 48 irq_handler(channel_ids[i], IRQ_FALL);
<> 144:ef7eb2e8f9f7 49 }
<> 144:ef7eb2e8f9f7 50 }
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 // P2.0-2.15
<> 144:ef7eb2e8f9f7 53 for (i = 0; i < 16; i++) {
<> 144:ef7eb2e8f9f7 54 uint32_t pmask = (1 << i);
<> 144:ef7eb2e8f9f7 55 int channel_index = i + 32;
<> 144:ef7eb2e8f9f7 56 if (rise2 & pmask) {
<> 144:ef7eb2e8f9f7 57 mask2 |= pmask;
<> 144:ef7eb2e8f9f7 58 if (channel_ids[channel_index] != 0)
<> 144:ef7eb2e8f9f7 59 irq_handler(channel_ids[channel_index], IRQ_RISE);
<> 144:ef7eb2e8f9f7 60 }
<> 144:ef7eb2e8f9f7 61 if (fall2 & pmask) {
<> 144:ef7eb2e8f9f7 62 mask2 |= pmask;
<> 144:ef7eb2e8f9f7 63 if (channel_ids[channel_index] != 0)
<> 144:ef7eb2e8f9f7 64 irq_handler(channel_ids[channel_index], IRQ_FALL);
<> 144:ef7eb2e8f9f7 65 }
<> 144:ef7eb2e8f9f7 66 }
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 // Clear the interrupts we just handled
<> 144:ef7eb2e8f9f7 69 LPC_GPIOINT->IO0IntClr = mask0;
<> 144:ef7eb2e8f9f7 70 LPC_GPIOINT->IO2IntClr = mask2;
<> 144:ef7eb2e8f9f7 71 }
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
<> 144:ef7eb2e8f9f7 74 if (pin == NC) return -1;
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 irq_handler = handler;
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 obj->port = (int)pin & ~0x1F;
<> 144:ef7eb2e8f9f7 79 obj->pin = (int)pin & 0x1F;
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 // Interrupts available only on GPIO0 and GPIO2
<> 144:ef7eb2e8f9f7 82 if (obj->port != LPC_GPIO0_BASE && obj->port != LPC_GPIO2_BASE) {
<> 144:ef7eb2e8f9f7 83 error("pins on this port cannot generate interrupts");
<> 144:ef7eb2e8f9f7 84 }
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 // put us in the interrupt table
<> 144:ef7eb2e8f9f7 87 int index = (obj->port == LPC_GPIO0_BASE) ? obj->pin : obj->pin + 32;
<> 144:ef7eb2e8f9f7 88 channel_ids[index] = id;
<> 144:ef7eb2e8f9f7 89 obj->ch = index;
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 NVIC_SetVector(EINT3_IRQn, (uint32_t)handle_interrupt_in);
<> 144:ef7eb2e8f9f7 92 NVIC_EnableIRQ(EINT3_IRQn);
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 return 0;
<> 144:ef7eb2e8f9f7 95 }
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 void gpio_irq_free(gpio_irq_t *obj) {
<> 144:ef7eb2e8f9f7 98 channel_ids[obj->ch] = 0;
<> 144:ef7eb2e8f9f7 99 }
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
<> 144:ef7eb2e8f9f7 102 // ensure nothing is pending
<> 144:ef7eb2e8f9f7 103 switch (obj->port) {
<> 144:ef7eb2e8f9f7 104 case LPC_GPIO0_BASE: LPC_GPIOINT->IO0IntClr = 1 << obj->pin; break;
<> 144:ef7eb2e8f9f7 105 case LPC_GPIO2_BASE: LPC_GPIOINT->IO2IntClr = 1 << obj->pin; break;
<> 144:ef7eb2e8f9f7 106 }
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 // enable the pin interrupt
<> 144:ef7eb2e8f9f7 109 if (event == IRQ_RISE) {
<> 144:ef7eb2e8f9f7 110 switch (obj->port) {
<> 144:ef7eb2e8f9f7 111 case LPC_GPIO0_BASE:
<> 144:ef7eb2e8f9f7 112 if (enable) {
<> 144:ef7eb2e8f9f7 113 LPC_GPIOINT->IO0IntEnR |= 1 << obj->pin;
<> 144:ef7eb2e8f9f7 114 } else {
<> 144:ef7eb2e8f9f7 115 LPC_GPIOINT->IO0IntEnR &= ~(1 << obj->pin);
<> 144:ef7eb2e8f9f7 116 }
<> 144:ef7eb2e8f9f7 117 break;
<> 144:ef7eb2e8f9f7 118 case LPC_GPIO2_BASE:
<> 144:ef7eb2e8f9f7 119 if (enable) {
<> 144:ef7eb2e8f9f7 120 LPC_GPIOINT->IO2IntEnR |= 1 << obj->pin;
<> 144:ef7eb2e8f9f7 121 } else {
<> 144:ef7eb2e8f9f7 122 LPC_GPIOINT->IO2IntEnR &= ~(1 << obj->pin);
<> 144:ef7eb2e8f9f7 123 }
<> 144:ef7eb2e8f9f7 124 break;
<> 144:ef7eb2e8f9f7 125 }
<> 144:ef7eb2e8f9f7 126 } else {
<> 144:ef7eb2e8f9f7 127 switch (obj->port) {
<> 144:ef7eb2e8f9f7 128 case LPC_GPIO0_BASE:
<> 144:ef7eb2e8f9f7 129 if (enable) {
<> 144:ef7eb2e8f9f7 130 LPC_GPIOINT->IO0IntEnF |= 1 << obj->pin;
<> 144:ef7eb2e8f9f7 131 } else {
<> 144:ef7eb2e8f9f7 132 LPC_GPIOINT->IO0IntEnF &= ~(1 << obj->pin);
<> 144:ef7eb2e8f9f7 133 }
<> 144:ef7eb2e8f9f7 134 break;
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 case LPC_GPIO2_BASE:
<> 144:ef7eb2e8f9f7 137 if (enable) {
<> 144:ef7eb2e8f9f7 138 LPC_GPIOINT->IO2IntEnF |= 1 << obj->pin;
<> 144:ef7eb2e8f9f7 139 } else {
<> 144:ef7eb2e8f9f7 140 LPC_GPIOINT->IO2IntEnF &= ~(1 << obj->pin);
<> 144:ef7eb2e8f9f7 141 }
<> 144:ef7eb2e8f9f7 142 break;
<> 144:ef7eb2e8f9f7 143 }
<> 144:ef7eb2e8f9f7 144 }
<> 144:ef7eb2e8f9f7 145 }
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 void gpio_irq_enable(gpio_irq_t *obj) {
<> 144:ef7eb2e8f9f7 148 NVIC_EnableIRQ(EINT3_IRQn);
<> 144:ef7eb2e8f9f7 149 }
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 void gpio_irq_disable(gpio_irq_t *obj) {
<> 144:ef7eb2e8f9f7 152 NVIC_DisableIRQ(EINT3_IRQn);
<> 144:ef7eb2e8f9f7 153 }
<> 144:ef7eb2e8f9f7 154