added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015-2016 Nuvoton
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16
<> 144:ef7eb2e8f9f7 17 #include "pwmout_api.h"
<> 144:ef7eb2e8f9f7 18
<> 144:ef7eb2e8f9f7 19 #if DEVICE_PWMOUT
<> 144:ef7eb2e8f9f7 20
<> 144:ef7eb2e8f9f7 21 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 22 #include "pinmap.h"
<> 144:ef7eb2e8f9f7 23 #include "PeripheralPins.h"
<> 144:ef7eb2e8f9f7 24 #include "nu_modutil.h"
<> 144:ef7eb2e8f9f7 25 #include "nu_miscutil.h"
<> 144:ef7eb2e8f9f7 26 #include "nu_bitutil.h"
<> 144:ef7eb2e8f9f7 27
<> 144:ef7eb2e8f9f7 28 struct nu_pwm_var {
<> 144:ef7eb2e8f9f7 29 uint32_t en_msk;
<> 144:ef7eb2e8f9f7 30 };
<> 144:ef7eb2e8f9f7 31
<> 144:ef7eb2e8f9f7 32 static struct nu_pwm_var pwm0_var = {
<> 144:ef7eb2e8f9f7 33 .en_msk = 0
<> 144:ef7eb2e8f9f7 34 };
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 static struct nu_pwm_var pwm1_var = {
<> 144:ef7eb2e8f9f7 37 .en_msk = 0
<> 144:ef7eb2e8f9f7 38 };
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 static uint32_t pwm_modinit_mask = 0;
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 // FIXME: PWM1 2/3 channels fail. PWM registers cannot write after their respective clocks are enabled.
<> 144:ef7eb2e8f9f7 43 static const struct nu_modinit_s pwm_modinit_tab[] = {
<> 144:ef7eb2e8f9f7 44 {PWM_0_0, PWM0CH01_MODULE, CLK_CLKSEL2_PWM0CH01SEL_HIRC, 0, PWM0_RST, PWM0CH0_IRQn, &pwm0_var},
<> 144:ef7eb2e8f9f7 45 {PWM_0_1, PWM0CH01_MODULE, CLK_CLKSEL2_PWM0CH01SEL_HIRC, 0, PWM0_RST, PWM0CH1_IRQn, &pwm0_var},
<> 144:ef7eb2e8f9f7 46 {PWM_0_2, PWM0CH23_MODULE, CLK_CLKSEL2_PWM0CH23SEL_HIRC, 0, PWM0_RST, PWM0CH2_IRQn, &pwm0_var},
<> 144:ef7eb2e8f9f7 47 {PWM_0_3, PWM0CH23_MODULE, CLK_CLKSEL2_PWM0CH23SEL_HIRC, 0, PWM0_RST, PWM0CH3_IRQn, &pwm0_var},
<> 144:ef7eb2e8f9f7 48 {PWM_0_4, PWM0CH45_MODULE, CLK_CLKSEL2_PWM0CH45SEL_HIRC, 0, PWM0_RST, PWM0CH4_IRQn, &pwm0_var},
<> 144:ef7eb2e8f9f7 49 {PWM_0_5, PWM0CH45_MODULE, CLK_CLKSEL2_PWM0CH45SEL_HIRC, 0, PWM0_RST, PWM0CH5_IRQn, &pwm0_var},
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 {PWM_1_0, PWM1CH01_MODULE, CLK_CLKSEL2_PWM1CH01SEL_HIRC, 0, PWM1_RST, PWM1CH0_IRQn, &pwm1_var},
<> 144:ef7eb2e8f9f7 52 {PWM_1_1, PWM1CH01_MODULE, CLK_CLKSEL2_PWM1CH01SEL_HIRC, 0, PWM1_RST, PWM1CH1_IRQn, &pwm1_var},
<> 144:ef7eb2e8f9f7 53 {PWM_1_2, PWM1CH23_MODULE, CLK_CLKSEL2_PWM1CH23SEL_HIRC, 0, PWM1_RST, PWM1CH2_IRQn, &pwm1_var},
<> 144:ef7eb2e8f9f7 54 {PWM_1_3, PWM1CH23_MODULE, CLK_CLKSEL2_PWM1CH23SEL_HIRC, 0, PWM1_RST, PWM1CH3_IRQn, &pwm1_var},
<> 144:ef7eb2e8f9f7 55 {PWM_1_4, PWM1CH45_MODULE, CLK_CLKSEL2_PWM1CH45SEL_HIRC, 0, PWM1_RST, PWM1CH4_IRQn, &pwm1_var},
<> 144:ef7eb2e8f9f7 56 {PWM_1_5, PWM1CH45_MODULE, CLK_CLKSEL2_PWM1CH45SEL_HIRC, 0, PWM1_RST, PWM1CH5_IRQn, &pwm1_var},
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
<> 144:ef7eb2e8f9f7 59 };
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 static void pwmout_config(pwmout_t* obj);
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 void pwmout_init(pwmout_t* obj, PinName pin)
<> 144:ef7eb2e8f9f7 64 {
<> 144:ef7eb2e8f9f7 65 obj->pwm = (PWMName) pinmap_peripheral(pin, PinMap_PWM);
<> 144:ef7eb2e8f9f7 66 MBED_ASSERT((int) obj->pwm != NC);
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 const struct nu_modinit_s *modinit = get_modinit(obj->pwm, pwm_modinit_tab);
<> 144:ef7eb2e8f9f7 69 MBED_ASSERT(modinit != NULL);
<> 144:ef7eb2e8f9f7 70 MBED_ASSERT(modinit->modname == obj->pwm);
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 // NOTE: All channels (identified by PWMName) share a PWM module. This reset will also affect other channels of the same PWM module.
<> 144:ef7eb2e8f9f7 73 if (! ((struct nu_pwm_var *) modinit->var)->en_msk) {
<> 144:ef7eb2e8f9f7 74 // Reset this module if no channel enabled
<> 144:ef7eb2e8f9f7 75 SYS_ResetModule(modinit->rsetidx);
<> 144:ef7eb2e8f9f7 76 }
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 PWM_T *pwm_base = (PWM_T *) NU_MODBASE(obj->pwm);
<> 144:ef7eb2e8f9f7 79 uint32_t chn = NU_MODSUBINDEX(obj->pwm);
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 // NOTE: Channels 0/1, 2/3, and 4/5 share a clock source.
<> 144:ef7eb2e8f9f7 82 if ((((struct nu_pwm_var *) modinit->var)->en_msk & (0x3 << (chn / 2 * 2))) == 0) {
<> 144:ef7eb2e8f9f7 83 // Select clock source of paired channels
<> 144:ef7eb2e8f9f7 84 CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
<> 144:ef7eb2e8f9f7 85 // Enable clock of paired channels
<> 144:ef7eb2e8f9f7 86 CLK_EnableModuleClock(modinit->clkidx);
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 // FIXME: PWM_1_2/3 design bug. PWM_1_2/3 also require PWM_1_0/1 clock enabled.
<> 144:ef7eb2e8f9f7 89 if (obj->pwm == PWM_1_2 || obj->pwm == PWM_1_3) {
<> 144:ef7eb2e8f9f7 90 CLK_EnableModuleClock(PWM1CH01_MODULE);
<> 144:ef7eb2e8f9f7 91 }
<> 144:ef7eb2e8f9f7 92 }
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 // Wire pinout
<> 144:ef7eb2e8f9f7 95 pinmap_pinout(pin, PinMap_PWM);
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 // Default: period = 10 ms, pulse width = 0 ms
<> 144:ef7eb2e8f9f7 98 obj->period_us = 1000 * 10;
<> 144:ef7eb2e8f9f7 99 obj->pulsewidth_us = 0;
<> 144:ef7eb2e8f9f7 100 pwmout_config(obj);
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 // Enable output of the specified PWM channel
<> 144:ef7eb2e8f9f7 103 PWM_EnableOutput(pwm_base, 1 << chn);
<> 144:ef7eb2e8f9f7 104 PWM_Start(pwm_base, 1 << chn);
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 ((struct nu_pwm_var *) modinit->var)->en_msk |= 1 << chn;
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 // Mark this module to be inited.
<> 144:ef7eb2e8f9f7 109 int i = modinit - pwm_modinit_tab;
<> 144:ef7eb2e8f9f7 110 pwm_modinit_mask |= 1 << i;
<> 144:ef7eb2e8f9f7 111 }
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 void pwmout_free(pwmout_t* obj)
<> 144:ef7eb2e8f9f7 114 {
<> 144:ef7eb2e8f9f7 115 PWM_T *pwm_base = (PWM_T *) NU_MODBASE(obj->pwm);
<> 144:ef7eb2e8f9f7 116 uint32_t chn = NU_MODSUBINDEX(obj->pwm);
<> 144:ef7eb2e8f9f7 117 PWM_ForceStop(pwm_base, 1 << chn);
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 const struct nu_modinit_s *modinit = get_modinit(obj->pwm, pwm_modinit_tab);
<> 144:ef7eb2e8f9f7 120 MBED_ASSERT(modinit != NULL);
<> 144:ef7eb2e8f9f7 121 MBED_ASSERT(modinit->modname == obj->pwm);
<> 144:ef7eb2e8f9f7 122 ((struct nu_pwm_var *) modinit->var)->en_msk &= ~(1 << chn);
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 if ((((struct nu_pwm_var *) modinit->var)->en_msk & (0x3 << (chn / 2 * 2))) == 0) {
<> 144:ef7eb2e8f9f7 126 // FIXME: PWM_1_2/3 design bug. PWM_1_2/3 also require PWM_1_0/1 clock enabled.
<> 144:ef7eb2e8f9f7 127 switch (obj->pwm) {
<> 144:ef7eb2e8f9f7 128 case PWM_1_0:
<> 144:ef7eb2e8f9f7 129 case PWM_1_1:
<> 144:ef7eb2e8f9f7 130 if (pwm1_var.en_msk & 0xC) {
<> 144:ef7eb2e8f9f7 131 break;
<> 144:ef7eb2e8f9f7 132 }
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 case PWM_1_2:
<> 144:ef7eb2e8f9f7 135 case PWM_1_3:
<> 144:ef7eb2e8f9f7 136 if (! (pwm1_var.en_msk & 0x3)) {
<> 144:ef7eb2e8f9f7 137 CLK_DisableModuleClock(PWM1CH01_MODULE);
<> 144:ef7eb2e8f9f7 138 }
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 default:
<> 144:ef7eb2e8f9f7 141 // Disable clock of paired channels
<> 144:ef7eb2e8f9f7 142 CLK_DisableModuleClock(modinit->clkidx);
<> 144:ef7eb2e8f9f7 143 }
<> 144:ef7eb2e8f9f7 144 }
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 // Mark this module to be deinited.
<> 144:ef7eb2e8f9f7 147 int i = modinit - pwm_modinit_tab;
<> 144:ef7eb2e8f9f7 148 pwm_modinit_mask &= ~(1 << i);
<> 144:ef7eb2e8f9f7 149 }
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 void pwmout_write(pwmout_t* obj, float value)
<> 144:ef7eb2e8f9f7 152 {
<> 144:ef7eb2e8f9f7 153 obj->pulsewidth_us = NU_CLAMP((uint32_t) (value * obj->period_us), 0, obj->period_us);
<> 144:ef7eb2e8f9f7 154 pwmout_config(obj);
<> 144:ef7eb2e8f9f7 155 }
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 float pwmout_read(pwmout_t* obj)
<> 144:ef7eb2e8f9f7 158 {
<> 144:ef7eb2e8f9f7 159 return NU_CLAMP((((float) obj->pulsewidth_us) / obj->period_us), 0.0f, 1.0f);
<> 144:ef7eb2e8f9f7 160 }
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 void pwmout_period(pwmout_t* obj, float seconds)
<> 144:ef7eb2e8f9f7 163 {
<> 144:ef7eb2e8f9f7 164 pwmout_period_us(obj, seconds * 1000000.0f);
<> 144:ef7eb2e8f9f7 165 }
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 void pwmout_period_ms(pwmout_t* obj, int ms)
<> 144:ef7eb2e8f9f7 168 {
<> 144:ef7eb2e8f9f7 169 pwmout_period_us(obj, ms * 1000);
<> 144:ef7eb2e8f9f7 170 }
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 // Set the PWM period, keeping the duty cycle the same.
<> 144:ef7eb2e8f9f7 173 void pwmout_period_us(pwmout_t* obj, int us)
<> 144:ef7eb2e8f9f7 174 {
<> 144:ef7eb2e8f9f7 175 uint32_t period_us_old = obj->period_us;
<> 144:ef7eb2e8f9f7 176 uint32_t pulsewidth_us_old = obj->pulsewidth_us;
<> 144:ef7eb2e8f9f7 177 obj->period_us = us;
<> 144:ef7eb2e8f9f7 178 obj->pulsewidth_us = NU_CLAMP(obj->period_us * pulsewidth_us_old / period_us_old, 0, obj->period_us);
<> 144:ef7eb2e8f9f7 179 pwmout_config(obj);
<> 144:ef7eb2e8f9f7 180 }
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 void pwmout_pulsewidth(pwmout_t* obj, float seconds)
<> 144:ef7eb2e8f9f7 183 {
<> 144:ef7eb2e8f9f7 184 pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
<> 144:ef7eb2e8f9f7 185 }
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 void pwmout_pulsewidth_ms(pwmout_t* obj, int ms)
<> 144:ef7eb2e8f9f7 188 {
<> 144:ef7eb2e8f9f7 189 pwmout_pulsewidth_us(obj, ms * 1000);
<> 144:ef7eb2e8f9f7 190 }
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 void pwmout_pulsewidth_us(pwmout_t* obj, int us)
<> 144:ef7eb2e8f9f7 193 {
<> 144:ef7eb2e8f9f7 194 obj->pulsewidth_us = NU_CLAMP(us, 0, obj->period_us);
<> 144:ef7eb2e8f9f7 195 pwmout_config(obj);
<> 144:ef7eb2e8f9f7 196 }
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 int pwmout_allow_powerdown(void)
<> 144:ef7eb2e8f9f7 199 {
<> 144:ef7eb2e8f9f7 200 uint32_t modinit_mask = pwm_modinit_mask;
<> 144:ef7eb2e8f9f7 201 while (modinit_mask) {
<> 144:ef7eb2e8f9f7 202 int pwm_idx = nu_ctz(modinit_mask);
<> 144:ef7eb2e8f9f7 203 const struct nu_modinit_s *modinit = pwm_modinit_tab + pwm_idx;
<> 144:ef7eb2e8f9f7 204 if (modinit->modname != NC) {
<> 144:ef7eb2e8f9f7 205 PWM_T *pwm_base = (PWM_T *) NU_MODBASE(modinit->modname);
<> 144:ef7eb2e8f9f7 206 uint32_t chn = NU_MODSUBINDEX(modinit->modname);
<> 144:ef7eb2e8f9f7 207 // Disallow entering power-down mode if PWM counter is enabled.
<> 144:ef7eb2e8f9f7 208 if ((pwm_base->CNTEN & (1 << chn)) && pwm_base->CMPDAT[chn]) {
<> 144:ef7eb2e8f9f7 209 return 0;
<> 144:ef7eb2e8f9f7 210 }
<> 144:ef7eb2e8f9f7 211 }
<> 144:ef7eb2e8f9f7 212 modinit_mask &= ~(1 << pwm_idx);
<> 144:ef7eb2e8f9f7 213 }
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 return 1;
<> 144:ef7eb2e8f9f7 216 }
<> 144:ef7eb2e8f9f7 217
<> 144:ef7eb2e8f9f7 218 static void pwmout_config(pwmout_t* obj)
<> 144:ef7eb2e8f9f7 219 {
<> 144:ef7eb2e8f9f7 220 PWM_T *pwm_base = (PWM_T *) NU_MODBASE(obj->pwm);
<> 144:ef7eb2e8f9f7 221 uint32_t chn = NU_MODSUBINDEX(obj->pwm);
<> 144:ef7eb2e8f9f7 222 // NOTE: Support period < 1s
<> 144:ef7eb2e8f9f7 223 //PWM_ConfigOutputChannel(pwm_base, chn, 1000 * 1000 / obj->period_us, obj->pulsewidth_us * 100 / obj->period_us);
<> 144:ef7eb2e8f9f7 224 PWM_ConfigOutputChannel2(pwm_base, chn, 1000 * 1000, obj->pulsewidth_us * 100 / obj->period_us, obj->period_us);
<> 144:ef7eb2e8f9f7 225 }
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 #endif