Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/mbed_overrides.c@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015-2016 Nuvoton
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16
<> 144:ef7eb2e8f9f7 17 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 18 #include "analogin_api.h"
<> 144:ef7eb2e8f9f7 19
<> 144:ef7eb2e8f9f7 20 // NOTE: Ensurce mbed_sdk_init() will get called before C++ global object constructor.
<> 144:ef7eb2e8f9f7 21 #if defined(__CC_ARM) || defined(__GNUC__)
<> 144:ef7eb2e8f9f7 22 void mbed_sdk_init_forced(void) __attribute__((constructor(101)));
<> 144:ef7eb2e8f9f7 23 #elif defined(__ICCARM__)
<> 144:ef7eb2e8f9f7 24 // FIXME: How to achieve it in IAR?
<> 144:ef7eb2e8f9f7 25 #endif
<> 144:ef7eb2e8f9f7 26
<> 144:ef7eb2e8f9f7 27 void mbed_sdk_init(void)
<> 144:ef7eb2e8f9f7 28 {
<> 144:ef7eb2e8f9f7 29 // NOTE: Support singleton semantics to be called from other init functions
<> 144:ef7eb2e8f9f7 30 static int inited = 0;
<> 144:ef7eb2e8f9f7 31 if (inited) {
<> 144:ef7eb2e8f9f7 32 return;
<> 144:ef7eb2e8f9f7 33 }
<> 144:ef7eb2e8f9f7 34 inited = 1;
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 /*---------------------------------------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 37 /* Init System Clock */
<> 144:ef7eb2e8f9f7 38 /*---------------------------------------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 39 /* Unlock protected registers */
<> 144:ef7eb2e8f9f7 40 SYS_UnlockReg();
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 /* Enable External XTAL (4~24 MHz) */
<> 144:ef7eb2e8f9f7 43 CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
<> 144:ef7eb2e8f9f7 44 /* Enable LIRC for lp_ticker */
<> 144:ef7eb2e8f9f7 45 CLK_EnableXtalRC(CLK_PWRCTL_LIRCEN_Msk);
<> 144:ef7eb2e8f9f7 46 /* Enable LXT for RTC */
<> 144:ef7eb2e8f9f7 47 CLK_EnableXtalRC(CLK_PWRCTL_LXTEN_Msk);
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /* Waiting for External XTAL (4~24 MHz) ready */
<> 144:ef7eb2e8f9f7 50 CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
<> 144:ef7eb2e8f9f7 51 /* Waiting for LIRC ready */
<> 144:ef7eb2e8f9f7 52 CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk);
<> 144:ef7eb2e8f9f7 53 /* Waiting for LXT ready */
<> 144:ef7eb2e8f9f7 54 CLK_WaitClockReady(CLK_STATUS_LXTSTB_Msk);
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 /* Switch HCLK clock source to HXT */
<> 144:ef7eb2e8f9f7 57 CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HXT,CLK_CLKDIV0_HCLK(1));
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /* Set PLL to power down mode and PLLSTB bit in CLKSTATUS register will be cleared by hardware.*/
<> 144:ef7eb2e8f9f7 60 CLK->PLLCTL|= CLK_PLLCTL_PD_Msk;
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /* Set PLL frequency */
<> 144:ef7eb2e8f9f7 63 CLK->PLLCTL = CLK_PLLCTL_84MHz_HXT;
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 /* Waiting for clock ready */
<> 144:ef7eb2e8f9f7 66 CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 /* Switch HCLK clock source to PLL */
<> 144:ef7eb2e8f9f7 69 CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL,CLK_CLKDIV0_HCLK(1));
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 /* Enable IP clock */
<> 144:ef7eb2e8f9f7 72 //CLK_EnableModuleClock(UART0_MODULE);
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 /* Select IP clock source */
<> 144:ef7eb2e8f9f7 75 //CLK_SetModuleClock(UART0_MODULE,CLK_CLKSEL1_UARTSEL_HXT,CLK_CLKDIV0_UART(1));
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 #if DEVICE_ANALOGIN
<> 144:ef7eb2e8f9f7 78 /* Vref connect to AVDD */
<> 144:ef7eb2e8f9f7 79 SYS->VREFCTL = (SYS->VREFCTL & ~SYS_VREFCTL_VREFCTL_Msk) | SYS_VREFCTL_VREF_AVDD;
<> 144:ef7eb2e8f9f7 80 #endif
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 /* Update System Core Clock */
<> 144:ef7eb2e8f9f7 83 /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */
<> 144:ef7eb2e8f9f7 84 SystemCoreClockUpdate();
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 /* Lock protected registers */
<> 144:ef7eb2e8f9f7 87 SYS_LockReg();
<> 144:ef7eb2e8f9f7 88 }
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 void mbed_sdk_init_forced(void)
<> 144:ef7eb2e8f9f7 91 {
<> 144:ef7eb2e8f9f7 92 mbed_sdk_init();
<> 144:ef7eb2e8f9f7 93 }