Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Maxim/TARGET_MAX32620/sleep.c@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*******************************************************************************
<> 144:ef7eb2e8f9f7 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 144:ef7eb2e8f9f7 5 * copy of this software and associated documentation files (the "Software"),
<> 144:ef7eb2e8f9f7 6 * to deal in the Software without restriction, including without limitation
<> 144:ef7eb2e8f9f7 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 144:ef7eb2e8f9f7 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 144:ef7eb2e8f9f7 9 * Software is furnished to do so, subject to the following conditions:
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * The above copyright notice and this permission notice shall be included
<> 144:ef7eb2e8f9f7 12 * in all copies or substantial portions of the Software.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 144:ef7eb2e8f9f7 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 144:ef7eb2e8f9f7 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 144:ef7eb2e8f9f7 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 144:ef7eb2e8f9f7 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 144:ef7eb2e8f9f7 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * Except as contained in this notice, the name of Maxim Integrated
<> 144:ef7eb2e8f9f7 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 144:ef7eb2e8f9f7 24 * Products, Inc. Branding Policy.
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * The mere transfer of this software does not imply any licenses
<> 144:ef7eb2e8f9f7 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 144:ef7eb2e8f9f7 28 * trademarks, maskwork rights, or any other form of intellectual
<> 144:ef7eb2e8f9f7 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 144:ef7eb2e8f9f7 30 * ownership rights.
<> 144:ef7eb2e8f9f7 31 *******************************************************************************
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #include "sleep_api.h"
<> 144:ef7eb2e8f9f7 35 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 36 #include "pwrman_regs.h"
<> 144:ef7eb2e8f9f7 37 #include "pwrseq_regs.h"
<> 144:ef7eb2e8f9f7 38 #include "clkman_regs.h"
<> 144:ef7eb2e8f9f7 39 #include "ioman_regs.h"
<> 144:ef7eb2e8f9f7 40 #include "rtc_regs.h"
<> 144:ef7eb2e8f9f7 41 #include "usb_regs.h"
<> 144:ef7eb2e8f9f7 42 #include "wait_api.h"
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 #define REVISION_A3 2
<> 144:ef7eb2e8f9f7 45 #define REVISION_A4 3
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 // USB state to be restored upon wakeup
<> 144:ef7eb2e8f9f7 48 typedef struct {
<> 144:ef7eb2e8f9f7 49 uint32_t dev_cn;
<> 144:ef7eb2e8f9f7 50 uint32_t dev_inten;
<> 144:ef7eb2e8f9f7 51 uint32_t ep_base;
<> 144:ef7eb2e8f9f7 52 uint32_t ep[MXC_USB_NUM_EP];
<> 144:ef7eb2e8f9f7 53 } usb_state_t;
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 static mxc_uart_regs_t *stdio_uart = (mxc_uart_regs_t*)STDIO_UART;
<> 144:ef7eb2e8f9f7 56 static int restore_usb;
<> 144:ef7eb2e8f9f7 57 static usb_state_t usb_state;
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 void sleep(void)
<> 144:ef7eb2e8f9f7 60 {
<> 144:ef7eb2e8f9f7 61 // Normal sleep mode for ARM core
<> 144:ef7eb2e8f9f7 62 SCB->SCR = 0;
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 __DSB();
<> 144:ef7eb2e8f9f7 65 __WFI();
<> 144:ef7eb2e8f9f7 66 }
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 static void usb_sleep(void)
<> 144:ef7eb2e8f9f7 69 {
<> 144:ef7eb2e8f9f7 70 int i;
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 if (MXC_USB->cn & MXC_F_USB_CN_USB_EN) {
<> 144:ef7eb2e8f9f7 73 // The USB module will not survive Deep Sleep.
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 // Save the USB state to restore it upon wakeup
<> 144:ef7eb2e8f9f7 76 usb_state.dev_cn = MXC_USB->dev_cn;
<> 144:ef7eb2e8f9f7 77 usb_state.dev_inten = MXC_USB->dev_inten;
<> 144:ef7eb2e8f9f7 78 usb_state.ep_base = MXC_USB->ep_base;
<> 144:ef7eb2e8f9f7 79 for (i = 0; i < MXC_USB_NUM_EP; i++) {
<> 144:ef7eb2e8f9f7 80 usb_state.ep[i] = MXC_USB->ep[i] & (MXC_F_USB_EP_DIR | MXC_F_USB_EP_BUF2 | MXC_F_USB_EP_INT_EN | MXC_F_USB_EP_NAK_EN);
<> 144:ef7eb2e8f9f7 81 }
<> 144:ef7eb2e8f9f7 82 restore_usb = 1;
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 // Shut down the USB module.
<> 144:ef7eb2e8f9f7 85 MXC_USB->dev_inten = 0;
<> 144:ef7eb2e8f9f7 86 MXC_USB->dev_cn = 0;
<> 144:ef7eb2e8f9f7 87 MXC_USB->cn = 0;
<> 144:ef7eb2e8f9f7 88 restore_usb = 1; // USB should be restored upon wakeup
<> 144:ef7eb2e8f9f7 89 }
<> 144:ef7eb2e8f9f7 90 else {
<> 144:ef7eb2e8f9f7 91 restore_usb = 0;
<> 144:ef7eb2e8f9f7 92 }
<> 144:ef7eb2e8f9f7 93 }
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 // Restore the USB module state.
<> 144:ef7eb2e8f9f7 96 static void usb_wakeup(void)
<> 144:ef7eb2e8f9f7 97 {
<> 144:ef7eb2e8f9f7 98 int i;
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 if (restore_usb) {
<> 144:ef7eb2e8f9f7 101 MXC_USB->cn = MXC_F_USB_CN_USB_EN;
<> 144:ef7eb2e8f9f7 102 MXC_USB->dev_cn = MXC_F_USB_DEV_CN_URST;
<> 144:ef7eb2e8f9f7 103 MXC_USB->dev_cn = 0;
<> 144:ef7eb2e8f9f7 104 for (i = 0; i < MXC_USB_NUM_EP; i++) {
<> 144:ef7eb2e8f9f7 105 MXC_USB->ep[i] = usb_state.ep[i];
<> 144:ef7eb2e8f9f7 106 }
<> 144:ef7eb2e8f9f7 107 MXC_USB->ep_base = usb_state.ep_base;
<> 144:ef7eb2e8f9f7 108 MXC_USB->dev_cn = usb_state.dev_cn;
<> 144:ef7eb2e8f9f7 109 MXC_USB->dev_inten = usb_state.dev_inten;
<> 144:ef7eb2e8f9f7 110 restore_usb = 0;
<> 144:ef7eb2e8f9f7 111 }
<> 144:ef7eb2e8f9f7 112 }
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 // Low-power stop mode
<> 144:ef7eb2e8f9f7 115 void deepsleep(void)
<> 144:ef7eb2e8f9f7 116 {
<> 144:ef7eb2e8f9f7 117 unsigned int part_rev = MXC_PWRMAN->mask_id0 & MXC_F_PWRMAN_MASK_ID0_REVISION_ID;
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 // Deep Sleep is not working properly on Revisions A3 and earlier
<> 144:ef7eb2e8f9f7 120 if (part_rev <= REVISION_A3) {
<> 144:ef7eb2e8f9f7 121 sleep();
<> 144:ef7eb2e8f9f7 122 return;
<> 144:ef7eb2e8f9f7 123 }
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 // Wait for all STDIO characters to be sent. The UART clock will stop.
<> 144:ef7eb2e8f9f7 126 while ((stdio_uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY) ||
<> 144:ef7eb2e8f9f7 127 !(stdio_uart->intfl & MXC_F_UART_INTFL_TX_DONE));
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 __disable_irq();
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 // Do not enter Deep Sleep if connected to VBUS
<> 144:ef7eb2e8f9f7 132 if (MXC_USB->dev_intfl & MXC_F_USB_DEV_INTFL_VBUS_ST) {
<> 144:ef7eb2e8f9f7 133 __enable_irq();
<> 144:ef7eb2e8f9f7 134 sleep();
<> 144:ef7eb2e8f9f7 135 return;
<> 144:ef7eb2e8f9f7 136 }
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 // The USB module will not survive Deep Sleep. Shut it down.
<> 144:ef7eb2e8f9f7 139 usb_sleep();
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 // Make sure RTC is not pending before sleeping, if its still synchronizing
<> 144:ef7eb2e8f9f7 142 // we might not wake up.
<> 144:ef7eb2e8f9f7 143 while (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 // Clear any active GPIO Wake Up Events
<> 144:ef7eb2e8f9f7 146 if (MXC_PWRSEQ->flags & MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP) {
<> 144:ef7eb2e8f9f7 147 // NOTE: These must be cleared before clearing IOWAKEUP
<> 144:ef7eb2e8f9f7 148 MXC_PWRSEQ->reg1 |= MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH;
<> 144:ef7eb2e8f9f7 149 MXC_PWRSEQ->reg1 &= ~MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH;
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 MXC_PWRSEQ->flags |= MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP;
<> 144:ef7eb2e8f9f7 152 }
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 // Set the LP1 select bit so CPU goes to LP1 during SLEEPDEEP
<> 144:ef7eb2e8f9f7 155 if (part_rev == REVISION_A4) {
<> 144:ef7eb2e8f9f7 156 MXC_PWRSEQ->reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_LP1; // A4 requires part to go to pseudo LP0
<> 144:ef7eb2e8f9f7 157 } else {
<> 144:ef7eb2e8f9f7 158 MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_LP1;
<> 144:ef7eb2e8f9f7 159 }
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 // The SLEEPDEEP bit will cause a WFE() to trigger LP0/LP1 (depending on ..._REG0_PWR_LP1 state)
<> 144:ef7eb2e8f9f7 162 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 if (part_rev == REVISION_A4) {
<> 144:ef7eb2e8f9f7 165 // WORKAROUND: Toggle SVM bits, which send extra clocks to the power sequencer to fix retention controller
<> 144:ef7eb2e8f9f7 166 MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD;
<> 144:ef7eb2e8f9f7 167 MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN);
<> 144:ef7eb2e8f9f7 168 MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN;
<> 144:ef7eb2e8f9f7 169 MXC_PWRSEQ->msk_flags &= ~MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD;
<> 144:ef7eb2e8f9f7 170 }
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 // Enable Retention controller
<> 144:ef7eb2e8f9f7 173 MXC_PWRSEQ->retn_ctrl0 |= MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN;
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 // Clear the firstboot bit, which is generated by a POR event and locks out LPx modes
<> 144:ef7eb2e8f9f7 176 MXC_PWRSEQ->reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT;
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 // Freeze GPIO using MBUS so that it doesn't flail while digital core is asleep
<> 144:ef7eb2e8f9f7 179 MXC_PWRSEQ->reg1 |= MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE;
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 // Dummy read to make sure SSB writes are complete
<> 144:ef7eb2e8f9f7 182 MXC_PWRSEQ->reg0;
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 if (part_rev == REVISION_A4) {
<> 144:ef7eb2e8f9f7 185 // Note: ARM deep-sleep requires a specific sequence to clear event latches,
<> 144:ef7eb2e8f9f7 186 // otherwise the CPU will not enter sleep.
<> 144:ef7eb2e8f9f7 187 __SEV();
<> 144:ef7eb2e8f9f7 188 __WFE();
<> 144:ef7eb2e8f9f7 189 __WFI();
<> 144:ef7eb2e8f9f7 190 }
<> 144:ef7eb2e8f9f7 191 else {
<> 144:ef7eb2e8f9f7 192 // Note: ARM deep-sleep requires a specific sequence to clear event latches,
<> 144:ef7eb2e8f9f7 193 // otherwise the CPU will not enter sleep.
<> 144:ef7eb2e8f9f7 194 __SEV();
<> 144:ef7eb2e8f9f7 195 __WFE();
<> 144:ef7eb2e8f9f7 196 __WFE();
<> 144:ef7eb2e8f9f7 197 }
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 // We'll wakeup here ...
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 // Unfreeze the GPIO by clearing MBUS_GATE
<> 144:ef7eb2e8f9f7 202 MXC_PWRSEQ->reg1 &= ~MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE;
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 usb_wakeup();
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 // Clear power sequencer event flags (write-1-to-clear)
<> 144:ef7eb2e8f9f7 207 // RTC and GPIO flags are cleared in their interrupts handlers
<> 144:ef7eb2e8f9f7 208 // NOTE: We are ignoring all of these potential wake up types
<> 144:ef7eb2e8f9f7 209 MXC_PWRSEQ->flags = (MXC_F_PWRSEQ_FLAGS_PWR_POWER_FAIL |
<> 144:ef7eb2e8f9f7 210 MXC_F_PWRSEQ_FLAGS_PWR_BOOT_FAIL |
<> 144:ef7eb2e8f9f7 211 MXC_F_PWRSEQ_FLAGS_PWR_FLASH_DISCHARGE |
<> 144:ef7eb2e8f9f7 212 MXC_F_PWRSEQ_FLAGS_PWR_VDD12_RST_BAD |
<> 144:ef7eb2e8f9f7 213 MXC_F_PWRSEQ_FLAGS_PWR_VDD18_RST_BAD |
<> 144:ef7eb2e8f9f7 214 MXC_F_PWRSEQ_FLAGS_PWR_VRTC_RST_BAD |
<> 144:ef7eb2e8f9f7 215 MXC_F_PWRSEQ_FLAGS_PWR_VDDB_RST_BAD |
<> 144:ef7eb2e8f9f7 216 MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_RST_BAD |
<> 144:ef7eb2e8f9f7 217 MXC_F_PWRSEQ_FLAGS_PWR_POR18Z_FAIL_LATCH |
<> 144:ef7eb2e8f9f7 218 MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP |
<> 144:ef7eb2e8f9f7 219 MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP |
<> 144:ef7eb2e8f9f7 220 MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_BAD);
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 __enable_irq();
<> 144:ef7eb2e8f9f7 223 }