Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Maxim/TARGET_MAX32620/gpio_irq_api.c@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*******************************************************************************
<> 144:ef7eb2e8f9f7 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 144:ef7eb2e8f9f7 5 * copy of this software and associated documentation files (the "Software"),
<> 144:ef7eb2e8f9f7 6 * to deal in the Software without restriction, including without limitation
<> 144:ef7eb2e8f9f7 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 144:ef7eb2e8f9f7 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 144:ef7eb2e8f9f7 9 * Software is furnished to do so, subject to the following conditions:
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * The above copyright notice and this permission notice shall be included
<> 144:ef7eb2e8f9f7 12 * in all copies or substantial portions of the Software.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 144:ef7eb2e8f9f7 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 144:ef7eb2e8f9f7 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 144:ef7eb2e8f9f7 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 144:ef7eb2e8f9f7 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 144:ef7eb2e8f9f7 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * Except as contained in this notice, the name of Maxim Integrated
<> 144:ef7eb2e8f9f7 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 144:ef7eb2e8f9f7 24 * Products, Inc. Branding Policy.
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * The mere transfer of this software does not imply any licenses
<> 144:ef7eb2e8f9f7 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 144:ef7eb2e8f9f7 28 * trademarks, maskwork rights, or any other form of intellectual
<> 144:ef7eb2e8f9f7 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 144:ef7eb2e8f9f7 30 * ownership rights.
<> 144:ef7eb2e8f9f7 31 *******************************************************************************
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #include <stddef.h>
<> 144:ef7eb2e8f9f7 35 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 36 #include "gpio_irq_api.h"
<> 144:ef7eb2e8f9f7 37 #include "mbed_error.h"
<> 144:ef7eb2e8f9f7 38 #include "ioman_regs.h"
<> 144:ef7eb2e8f9f7 39 #include "pwrman_regs.h"
<> 144:ef7eb2e8f9f7 40 #include "pwrseq_regs.h"
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 static gpio_irq_t *objs[MXC_GPIO_NUM_PORTS][MXC_GPIO_MAX_PINS_PER_PORT] = {{0}};
<> 144:ef7eb2e8f9f7 43 static gpio_irq_handler irq_handler;
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 static void gpio_irq_wud_req(gpio_irq_t *obj)
<> 144:ef7eb2e8f9f7 46 {
<> 144:ef7eb2e8f9f7 47 unsigned int port = obj->port;
<> 144:ef7eb2e8f9f7 48 unsigned int pin = obj->pin;
<> 144:ef7eb2e8f9f7 49 uint32_t pin_mask = 1 << pin;
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 /* Ports 0-3 are controlled by wud_req0, while 4-7 are controlled by wud_req1 */
<> 144:ef7eb2e8f9f7 52 /* During the time the WUD IOMAN requests are asserted (1), the GPIO Pad */
<> 144:ef7eb2e8f9f7 53 /* is in HIGH Z mode, regardless of GPIO setting. This may cause bogus interrupts. */
<> 144:ef7eb2e8f9f7 54 if (port < 4) {
<> 144:ef7eb2e8f9f7 55 uint32_t mask = pin_mask << (port << 3);
<> 144:ef7eb2e8f9f7 56 if (!(MXC_IOMAN->wud_ack0 & mask)) {
<> 144:ef7eb2e8f9f7 57 MXC_IOMAN->wud_req0 |= mask;
<> 144:ef7eb2e8f9f7 58 while(!(MXC_IOMAN->wud_ack0 & mask));
<> 144:ef7eb2e8f9f7 59 }
<> 144:ef7eb2e8f9f7 60 } else if (port < 8) {
<> 144:ef7eb2e8f9f7 61 uint32_t mask = pin_mask << ((port-4) << 3);
<> 144:ef7eb2e8f9f7 62 if (!(MXC_IOMAN->wud_ack1 & mask)) {
<> 144:ef7eb2e8f9f7 63 MXC_IOMAN->wud_req1 |= mask;
<> 144:ef7eb2e8f9f7 64 while(!(MXC_IOMAN->wud_ack1 & mask));
<> 144:ef7eb2e8f9f7 65 }
<> 144:ef7eb2e8f9f7 66 }
<> 144:ef7eb2e8f9f7 67 }
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 /* Clear the selected pin from wake-up detect */
<> 144:ef7eb2e8f9f7 70 static void gpio_irq_wud_clear(gpio_irq_t *obj)
<> 144:ef7eb2e8f9f7 71 {
<> 144:ef7eb2e8f9f7 72 unsigned int port = obj->port;
<> 144:ef7eb2e8f9f7 73 unsigned int pin = obj->pin;
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 /* Enable modifications to WUD configuration */
<> 144:ef7eb2e8f9f7 76 MXC_PWRMAN->wud_ctrl = MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE;
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 /* Select pad in WUD control */
<> 144:ef7eb2e8f9f7 79 /* Note: Pads are numbered from 0-48; {0-7} => {P0.0-P0.7}, {8-15} => {P1.0-P1.7}, etc. */
<> 144:ef7eb2e8f9f7 80 MXC_PWRMAN->wud_ctrl |= (port * 8) + pin;
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 /* Clear any existing WUD configuration for this pad */
<> 144:ef7eb2e8f9f7 83 MXC_PWRMAN->wud_ctrl &= ~(MXC_F_PWRMAN_WUD_CTRL_PAD_MODE);
<> 144:ef7eb2e8f9f7 84 MXC_PWRMAN->wud_ctrl |= (MXC_E_PWRMAN_PAD_MODE_CLEAR_SET << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS);
<> 144:ef7eb2e8f9f7 85 /* Clear with PULSE0; PULSE1 enables WUD */
<> 144:ef7eb2e8f9f7 86 MXC_PWRMAN->wud_pulse0 = 1;
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 /* Disable configuration */
<> 144:ef7eb2e8f9f7 89 MXC_PWRMAN->wud_ctrl = 0;
<> 144:ef7eb2e8f9f7 90 MXC_IOMAN->wud_req0 = 0;
<> 144:ef7eb2e8f9f7 91 MXC_IOMAN->wud_req1 = 0;
<> 144:ef7eb2e8f9f7 92 }
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 /* Configure the selected pin for wake-up detect */
<> 144:ef7eb2e8f9f7 95 static void gpio_irq_wud_config(gpio_irq_t *obj)
<> 144:ef7eb2e8f9f7 96 {
<> 144:ef7eb2e8f9f7 97 unsigned int port = obj->port;
<> 144:ef7eb2e8f9f7 98 unsigned int pin = obj->pin;
<> 144:ef7eb2e8f9f7 99 uint32_t pin_mask = 1 << pin;
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 /* Enable modifications to WUD configuration */
<> 144:ef7eb2e8f9f7 102 MXC_PWRMAN->wud_ctrl = MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE;
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 /* Select pad in WUD control */
<> 144:ef7eb2e8f9f7 105 /* Note: Pads are numbered from 0-48; {0-7} => {P0.0-P0.7}, {8-15} => {P1.0-P1.7}, etc. */
<> 144:ef7eb2e8f9f7 106 MXC_PWRMAN->wud_ctrl |= (port * 8) + pin;
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 /* First clear any existing WUD configuration for this pad */
<> 144:ef7eb2e8f9f7 109 MXC_PWRMAN->wud_ctrl &= ~(MXC_F_PWRMAN_WUD_CTRL_PAD_MODE);
<> 144:ef7eb2e8f9f7 110 MXC_PWRMAN->wud_ctrl |= (MXC_E_PWRMAN_PAD_MODE_CLEAR_SET << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS);
<> 144:ef7eb2e8f9f7 111 /* Clear with PULSE0; PULSE1 enables WUD */
<> 144:ef7eb2e8f9f7 112 MXC_PWRMAN->wud_pulse0 = 1;
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 if (obj->fall_en || obj->rise_en) {
<> 144:ef7eb2e8f9f7 115 /* Configure sense level on this pad */
<> 144:ef7eb2e8f9f7 116 MXC_PWRMAN->wud_ctrl &= ~(MXC_F_PWRMAN_WUD_CTRL_PAD_MODE);
<> 144:ef7eb2e8f9f7 117 MXC_PWRMAN->wud_ctrl |= (MXC_E_PWRMAN_PAD_MODE_ACT_HI_LO << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS);
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 uint32_t in_val = MXC_GPIO->in_val[port] & pin_mask;
<> 144:ef7eb2e8f9f7 120 do {
<> 144:ef7eb2e8f9f7 121 if (in_val) {
<> 144:ef7eb2e8f9f7 122 /* Select active low with PULSE1 (backwards from what you'd expect) */
<> 144:ef7eb2e8f9f7 123 MXC_PWRMAN->wud_pulse1 = 1;
<> 144:ef7eb2e8f9f7 124 } else {
<> 144:ef7eb2e8f9f7 125 /* Select active high with PULSE0 (backwards from what you'd expect) */
<> 144:ef7eb2e8f9f7 126 MXC_PWRMAN->wud_pulse0 = 1;
<> 144:ef7eb2e8f9f7 127 }
<> 144:ef7eb2e8f9f7 128 } while ((MXC_GPIO->in_val[port] & pin_mask) != in_val);
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 /* Select this pad to have the wake-up function enabled */
<> 144:ef7eb2e8f9f7 131 MXC_PWRMAN->wud_ctrl &= ~(MXC_F_PWRMAN_WUD_CTRL_PAD_MODE);
<> 144:ef7eb2e8f9f7 132 MXC_PWRMAN->wud_ctrl |= (MXC_E_PWRMAN_PAD_MODE_CLEAR_SET << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS);
<> 144:ef7eb2e8f9f7 133 /* Activate with PULSE1 */
<> 144:ef7eb2e8f9f7 134 MXC_PWRMAN->wud_pulse1 = 1;
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 // NOTE: Low Power Pullup/down is not normally needed in addition to
<> 144:ef7eb2e8f9f7 137 // standard GPIO Pullup/downs.
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 /* Enable IOWakeup, as there is at least 1 GPIO pin configured as a wake source */
<> 144:ef7eb2e8f9f7 140 MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP;
<> 144:ef7eb2e8f9f7 141 }
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 /* Disable configuration */
<> 144:ef7eb2e8f9f7 144 MXC_PWRMAN->wud_ctrl = 0;
<> 144:ef7eb2e8f9f7 145 MXC_IOMAN->wud_req0 = 0;
<> 144:ef7eb2e8f9f7 146 MXC_IOMAN->wud_req1 = 0;
<> 144:ef7eb2e8f9f7 147 }
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 static void handle_irq(unsigned int port)
<> 144:ef7eb2e8f9f7 150 {
<> 144:ef7eb2e8f9f7 151 uint32_t intfl, in_val;
<> 144:ef7eb2e8f9f7 152 uint32_t mask;
<> 144:ef7eb2e8f9f7 153 unsigned int pin;
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 /* Read pin state */
<> 144:ef7eb2e8f9f7 156 in_val = MXC_GPIO->in_val[port];
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 /* Read interrupts */
<> 144:ef7eb2e8f9f7 159 intfl = MXC_GPIO->intfl[port] & MXC_GPIO->inten[port];
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 mask = 1;
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 for (pin = 0; pin < MXC_GPIO_MAX_PINS_PER_PORT; pin++) {
<> 144:ef7eb2e8f9f7 164 if (intfl & mask) {
<> 144:ef7eb2e8f9f7 165 MXC_GPIO->intfl[port] = mask; /* clear interrupt */
<> 144:ef7eb2e8f9f7 166 gpio_irq_event event = (in_val & mask) ? IRQ_RISE : IRQ_FALL;
<> 144:ef7eb2e8f9f7 167 gpio_irq_t *obj = objs[port][pin];
<> 144:ef7eb2e8f9f7 168 if (obj && obj->id) {
<> 144:ef7eb2e8f9f7 169 if ((event == IRQ_RISE) && obj->rise_en) {
<> 144:ef7eb2e8f9f7 170 irq_handler(obj->id, IRQ_RISE);
<> 144:ef7eb2e8f9f7 171 } else if ((event == IRQ_FALL) && obj->fall_en) {
<> 144:ef7eb2e8f9f7 172 irq_handler(obj->id, IRQ_FALL);
<> 144:ef7eb2e8f9f7 173 }
<> 144:ef7eb2e8f9f7 174 }
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 gpio_irq_wud_config(obj);
<> 144:ef7eb2e8f9f7 177 }
<> 144:ef7eb2e8f9f7 178 mask <<= 1;
<> 144:ef7eb2e8f9f7 179 }
<> 144:ef7eb2e8f9f7 180 }
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 void gpio_irq_0(void) { handle_irq(0); }
<> 144:ef7eb2e8f9f7 183 void gpio_irq_1(void) { handle_irq(1); }
<> 144:ef7eb2e8f9f7 184 void gpio_irq_2(void) { handle_irq(2); }
<> 144:ef7eb2e8f9f7 185 void gpio_irq_3(void) { handle_irq(3); }
<> 144:ef7eb2e8f9f7 186 void gpio_irq_4(void) { handle_irq(4); }
<> 144:ef7eb2e8f9f7 187 void gpio_irq_5(void) { handle_irq(5); }
<> 144:ef7eb2e8f9f7 188 void gpio_irq_6(void) { handle_irq(6); }
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 int gpio_irq_init(gpio_irq_t *obj, PinName name, gpio_irq_handler handler, uint32_t id)
<> 144:ef7eb2e8f9f7 191 {
<> 144:ef7eb2e8f9f7 192 if (name == NC) {
<> 144:ef7eb2e8f9f7 193 return -1;
<> 144:ef7eb2e8f9f7 194 }
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 uint8_t port = PINNAME_TO_PORT(name);
<> 144:ef7eb2e8f9f7 197 uint8_t pin = PINNAME_TO_PIN(name);
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 if ((port > MXC_GPIO_NUM_PORTS) || (pin > MXC_GPIO_MAX_PINS_PER_PORT)) {
<> 144:ef7eb2e8f9f7 200 return 1;
<> 144:ef7eb2e8f9f7 201 }
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 obj->port = port;
<> 144:ef7eb2e8f9f7 204 obj->pin = pin;
<> 144:ef7eb2e8f9f7 205 obj->id = id;
<> 144:ef7eb2e8f9f7 206 objs[port][pin] = obj;
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 /* register handlers */
<> 144:ef7eb2e8f9f7 209 irq_handler = handler;
<> 144:ef7eb2e8f9f7 210 NVIC_SetVector(GPIO_P0_IRQn, (uint32_t)gpio_irq_0);
<> 144:ef7eb2e8f9f7 211 NVIC_SetVector(GPIO_P1_IRQn, (uint32_t)gpio_irq_1);
<> 144:ef7eb2e8f9f7 212 NVIC_SetVector(GPIO_P2_IRQn, (uint32_t)gpio_irq_2);
<> 144:ef7eb2e8f9f7 213 NVIC_SetVector(GPIO_P3_IRQn, (uint32_t)gpio_irq_3);
<> 144:ef7eb2e8f9f7 214 NVIC_SetVector(GPIO_P4_IRQn, (uint32_t)gpio_irq_4);
<> 144:ef7eb2e8f9f7 215 NVIC_SetVector(GPIO_P5_IRQn, (uint32_t)gpio_irq_5);
<> 144:ef7eb2e8f9f7 216 NVIC_SetVector(GPIO_P6_IRQn, (uint32_t)gpio_irq_6);
<> 144:ef7eb2e8f9f7 217
<> 144:ef7eb2e8f9f7 218 /* request WUD in case the application is going to sleep */
<> 144:ef7eb2e8f9f7 219 gpio_irq_wud_req(obj);
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 /* disable the interrupt locally */
<> 144:ef7eb2e8f9f7 222 MXC_GPIO->int_mode[port] &= ~(0xF << (pin*4));
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 /* clear a pending request */
<> 144:ef7eb2e8f9f7 225 MXC_GPIO->intfl[port] = 1 << pin;
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 /* enable the requested interrupt */
<> 144:ef7eb2e8f9f7 228 MXC_GPIO->inten[port] |= (1 << pin);
<> 144:ef7eb2e8f9f7 229 NVIC_EnableIRQ((IRQn_Type)((uint32_t)GPIO_P0_IRQn + port));
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 return 0;
<> 144:ef7eb2e8f9f7 232 }
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 void gpio_irq_free(gpio_irq_t *obj)
<> 144:ef7eb2e8f9f7 235 {
<> 144:ef7eb2e8f9f7 236 /* disable interrupt */
<> 144:ef7eb2e8f9f7 237 MXC_GPIO->inten[obj->port] &= ~(1 << obj->pin);
<> 144:ef7eb2e8f9f7 238 MXC_GPIO->int_mode[obj->port] &= ~(MXC_V_GPIO_INT_MODE_ANY_EDGE << (obj->pin*4));
<> 144:ef7eb2e8f9f7 239 objs[obj->port][obj->pin] = NULL;
<> 144:ef7eb2e8f9f7 240 gpio_irq_wud_clear(obj);
<> 144:ef7eb2e8f9f7 241 }
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
<> 144:ef7eb2e8f9f7 244 {
<> 144:ef7eb2e8f9f7 245 if (event == IRQ_FALL) {
<> 144:ef7eb2e8f9f7 246 obj->fall_en = enable;
<> 144:ef7eb2e8f9f7 247 } else if (event == IRQ_RISE) {
<> 144:ef7eb2e8f9f7 248 obj->rise_en = enable;
<> 144:ef7eb2e8f9f7 249 }
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 if (obj->fall_en || obj->rise_en) {
<> 144:ef7eb2e8f9f7 252 MXC_GPIO->int_mode[obj->port] |= (MXC_V_GPIO_INT_MODE_ANY_EDGE << (obj->pin*4));
<> 144:ef7eb2e8f9f7 253 gpio_irq_wud_config(obj); /* enable WUD for this pin so we may wake from deepsleep as well */
<> 144:ef7eb2e8f9f7 254 } else {
<> 144:ef7eb2e8f9f7 255 MXC_GPIO->int_mode[obj->port] &= (MXC_V_GPIO_INT_MODE_ANY_EDGE << (obj->pin*4));
<> 144:ef7eb2e8f9f7 256 gpio_irq_wud_clear(obj);
<> 144:ef7eb2e8f9f7 257 }
<> 144:ef7eb2e8f9f7 258 }
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 void gpio_irq_enable(gpio_irq_t *obj)
<> 144:ef7eb2e8f9f7 261 {
<> 144:ef7eb2e8f9f7 262 MXC_GPIO->inten[obj->port] |= (1 << obj->pin);
<> 144:ef7eb2e8f9f7 263 gpio_irq_wud_config(obj);
<> 144:ef7eb2e8f9f7 264 }
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 void gpio_irq_disable(gpio_irq_t *obj)
<> 144:ef7eb2e8f9f7 267 {
<> 144:ef7eb2e8f9f7 268 MXC_GPIO->inten[obj->port] &= ~(1 << obj->pin);
<> 144:ef7eb2e8f9f7 269 gpio_irq_wud_clear(obj);
<> 144:ef7eb2e8f9f7 270 }
<> 144:ef7eb2e8f9f7 271
<> 144:ef7eb2e8f9f7 272 gpio_irq_t *gpio_irq_get_obj(PinName name)
<> 144:ef7eb2e8f9f7 273 {
<> 144:ef7eb2e8f9f7 274 if (name == NC) {
<> 144:ef7eb2e8f9f7 275 return NULL;
<> 144:ef7eb2e8f9f7 276 }
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 unsigned int port = PINNAME_TO_PORT(name);
<> 144:ef7eb2e8f9f7 279 unsigned int pin = PINNAME_TO_PIN(name);
<> 144:ef7eb2e8f9f7 280
<> 144:ef7eb2e8f9f7 281 if ((port > MXC_GPIO_NUM_PORTS) || (pin > MXC_GPIO_MAX_PINS_PER_PORT)) {
<> 144:ef7eb2e8f9f7 282 return NULL;
<> 144:ef7eb2e8f9f7 283 }
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 return objs[port][pin];
<> 144:ef7eb2e8f9f7 286 }