Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Maxim/TARGET_MAX32610/sleep.c@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*******************************************************************************
<> 144:ef7eb2e8f9f7 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 144:ef7eb2e8f9f7 5 * copy of this software and associated documentation files (the "Software"),
<> 144:ef7eb2e8f9f7 6 * to deal in the Software without restriction, including without limitation
<> 144:ef7eb2e8f9f7 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 144:ef7eb2e8f9f7 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 144:ef7eb2e8f9f7 9 * Software is furnished to do so, subject to the following conditions:
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * The above copyright notice and this permission notice shall be included
<> 144:ef7eb2e8f9f7 12 * in all copies or substantial portions of the Software.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 144:ef7eb2e8f9f7 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 144:ef7eb2e8f9f7 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 144:ef7eb2e8f9f7 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 144:ef7eb2e8f9f7 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 144:ef7eb2e8f9f7 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * Except as contained in this notice, the name of Maxim Integrated
<> 144:ef7eb2e8f9f7 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 144:ef7eb2e8f9f7 24 * Products, Inc. Branding Policy.
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * The mere transfer of this software does not imply any licenses
<> 144:ef7eb2e8f9f7 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 144:ef7eb2e8f9f7 28 * trademarks, maskwork rights, or any other form of intellectual
<> 144:ef7eb2e8f9f7 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 144:ef7eb2e8f9f7 30 * ownership rights.
<> 144:ef7eb2e8f9f7 31 *******************************************************************************
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #include "sleep_api.h"
<> 144:ef7eb2e8f9f7 35 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 36 #include "pwrman_regs.h"
<> 144:ef7eb2e8f9f7 37 #include "pwrseq_regs.h"
<> 144:ef7eb2e8f9f7 38 #include "ioman_regs.h"
<> 144:ef7eb2e8f9f7 39 #include "rtc_regs.h"
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 static mxc_uart_regs_t *stdio_uart = (mxc_uart_regs_t*)STDIO_UART;
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 // Normal wait mode
<> 144:ef7eb2e8f9f7 44 void sleep(void)
<> 144:ef7eb2e8f9f7 45 {
<> 144:ef7eb2e8f9f7 46 // Normal sleep mode for ARM core
<> 144:ef7eb2e8f9f7 47 SCB->SCR = 0;
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 __DSB();
<> 144:ef7eb2e8f9f7 50 __WFI();
<> 144:ef7eb2e8f9f7 51 }
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 // Work-around for issue of clearing power sequencer I/O flag
<> 144:ef7eb2e8f9f7 54 static void clearAllGPIOWUD(void)
<> 144:ef7eb2e8f9f7 55 {
<> 144:ef7eb2e8f9f7 56 uint32_t wud_req0 = MXC_IOMAN->wud_req0;
<> 144:ef7eb2e8f9f7 57 uint32_t wud_req1 = MXC_IOMAN->wud_req1;
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 // I/O must be a wakeup detect to clear
<> 144:ef7eb2e8f9f7 60 MXC_IOMAN->wud_req0 = 0xffffffff;
<> 144:ef7eb2e8f9f7 61 MXC_IOMAN->wud_req1 = 0xffffffff;
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 // Clear all WUDs
<> 144:ef7eb2e8f9f7 64 MXC_PWRMAN->wud_ctrl = (MXC_E_PWRMAN_PAD_MODE_CLEAR_SET << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS) | MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL;
<> 144:ef7eb2e8f9f7 65 MXC_PWRMAN->wud_pulse0 = 1;
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 // Restore WUD requests
<> 144:ef7eb2e8f9f7 68 MXC_IOMAN->wud_req0 = wud_req0;
<> 144:ef7eb2e8f9f7 69 MXC_IOMAN->wud_req1 = wud_req1;
<> 144:ef7eb2e8f9f7 70 }
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 // Low-power stop mode
<> 144:ef7eb2e8f9f7 73 void deepsleep(void)
<> 144:ef7eb2e8f9f7 74 {
<> 144:ef7eb2e8f9f7 75 __disable_irq();
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 // Wait for all STDIO characters to be sent. The UART clock will stop.
<> 144:ef7eb2e8f9f7 78 while (stdio_uart->status & MXC_F_UART_STATUS_TX_BUSY);
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 // Prepare for LP1
<> 144:ef7eb2e8f9f7 81 uint32_t reg0 = MXC_PWRSEQ->reg0;
<> 144:ef7eb2e8f9f7 82 reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP; // disable VDD3 SVM during sleep mode
<> 144:ef7eb2e8f9f7 83 reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP; // disable VREG18 SVM during sleep mode
<> 144:ef7eb2e8f9f7 84 if (reg0 & MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN) { // if real-time clock enabled during run
<> 144:ef7eb2e8f9f7 85 reg0 |= MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP; // enable real-time clock during sleep mode
<> 144:ef7eb2e8f9f7 86 } else {
<> 144:ef7eb2e8f9f7 87 reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP; // disable real-time clock during sleep mode
<> 144:ef7eb2e8f9f7 88 }
<> 144:ef7eb2e8f9f7 89 reg0 |= MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP; // enable CHZY regulator during sleep mode
<> 144:ef7eb2e8f9f7 90 reg0 |= MXC_F_PWRSEQ_REG0_PWR_LP1; // go into LP1
<> 144:ef7eb2e8f9f7 91 reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT; // clear first boot flag
<> 144:ef7eb2e8f9f7 92 MXC_PWRSEQ->reg0 = reg0;
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 MXC_PWRSEQ->reg3 = (MXC_PWRSEQ->reg3 & ~MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK) | (3 << MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK_POS);
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 // Deep sleep for ARM core
<> 144:ef7eb2e8f9f7 97 SCB->SCR = SCB_SCR_SLEEPDEEP_Msk;
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 // clear latches for wakeup detect
<> 144:ef7eb2e8f9f7 100 MXC_PWRSEQ->flags = MXC_PWRSEQ->flags;
<> 144:ef7eb2e8f9f7 101 if (MXC_PWRSEQ->flags & MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP) {
<> 144:ef7eb2e8f9f7 102 // attempt work-around for I/O flag clearing issue
<> 144:ef7eb2e8f9f7 103 clearAllGPIOWUD();
<> 144:ef7eb2e8f9f7 104 MXC_PWRSEQ->flags = MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP;
<> 144:ef7eb2e8f9f7 105 }
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 // Wait for pending RTC transaction
<> 144:ef7eb2e8f9f7 108 while (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 // Ensure that the event register is clear
<> 144:ef7eb2e8f9f7 111 __SEV(); // set event
<> 144:ef7eb2e8f9f7 112 __WFE(); // clear event
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 // Enter LP1
<> 144:ef7eb2e8f9f7 115 __WFE();
<> 144:ef7eb2e8f9f7 116 // Woke up from LP1
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 // The RTC timer does not update until the next tick
<> 144:ef7eb2e8f9f7 119 uint32_t temp = MXC_RTCTMR->timer;
<> 144:ef7eb2e8f9f7 120 while (MXC_RTCTMR->timer == temp);
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 __enable_irq();
<> 144:ef7eb2e8f9f7 123 }